projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ramips: rt305x: nuke built-in MTD partition maps
[openwrt.git] / target / linux / generic / patches-3.0 / 020-ssb_update.patch
1 --- a/drivers/ssb/b43_pci_bridge.c
2 +++ b/drivers/ssb/b43_pci_bridge.c
3 @@ -5,12 +5,13 @@
4 * because of its small size we include it in the SSB core
5 * instead of creating a standalone module.
6 *
7 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2007 Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12
13 #include <linux/pci.h>
14 +#include <linux/module.h>
15 #include <linux/ssb/ssb.h>
16
17 #include "ssb_private.h"
18 --- a/drivers/ssb/driver_chipcommon.c
19 +++ b/drivers/ssb/driver_chipcommon.c
20 @@ -3,7 +3,7 @@
21 * Broadcom ChipCommon core driver
22 *
23 * Copyright 2005, Broadcom Corporation
24 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
25 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
26 *
27 * Licensed under the GNU/GPL. See COPYING for details.
28 */
29 --- a/drivers/ssb/driver_chipcommon_pmu.c
30 +++ b/drivers/ssb/driver_chipcommon_pmu.c
31 @@ -2,7 +2,7 @@
32 * Sonics Silicon Backplane
33 * Broadcom ChipCommon Power Management Unit driver
34 *
35 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
36 + * Copyright 2009, Michael Buesch <m@bues.ch>
37 * Copyright 2007, Broadcom Corporation
38 *
39 * Licensed under the GNU/GPL. See COPYING for details.
40 @@ -417,9 +417,9 @@ static void ssb_pmu_resources_init(struc
41 u32 min_msk = 0, max_msk = 0;
42 unsigned int i;
43 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
44 - unsigned int updown_tab_size;
45 + unsigned int updown_tab_size = 0;
46 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
47 - unsigned int depend_tab_size;
48 + unsigned int depend_tab_size = 0;
49
50 switch (bus->chip_id) {
51 case 0x4312:
52 --- a/drivers/ssb/driver_extif.c
53 +++ b/drivers/ssb/driver_extif.c
54 @@ -3,7 +3,7 @@
55 * Broadcom EXTIF core driver
56 *
57 * Copyright 2005, Broadcom Corporation
58 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
59 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
60 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
61 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
62 *
63 --- a/drivers/ssb/driver_gige.c
64 +++ b/drivers/ssb/driver_gige.c
65 @@ -3,7 +3,7 @@
66 * Broadcom Gigabit Ethernet core driver
67 *
68 * Copyright 2008, Broadcom Corporation
69 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
70 + * Copyright 2008, Michael Buesch <m@bues.ch>
71 *
72 * Licensed under the GNU/GPL. See COPYING for details.
73 */
74 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
75 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
76 }
77
78 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
79 - int reg, int size, u32 *val)
80 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
81 + unsigned int devfn, int reg,
82 + int size, u32 *val)
83 {
84 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
85 unsigned long flags;
86 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
87 return PCIBIOS_SUCCESSFUL;
88 }
89
90 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
91 - int reg, int size, u32 val)
92 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
93 + unsigned int devfn, int reg,
94 + int size, u32 val)
95 {
96 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
97 unsigned long flags;
98 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
99 return PCIBIOS_SUCCESSFUL;
100 }
101
102 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
103 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
104 + const struct ssb_device_id *id)
105 {
106 struct ssb_gige *dev;
107 u32 base, tmslow, tmshigh;
108 --- a/drivers/ssb/driver_mipscore.c
109 +++ b/drivers/ssb/driver_mipscore.c
110 @@ -3,7 +3,7 @@
111 * Broadcom MIPS core driver
112 *
113 * Copyright 2005, Broadcom Corporation
114 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
115 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
116 *
117 * Licensed under the GNU/GPL. See COPYING for details.
118 */
119 --- a/drivers/ssb/driver_pcicore.c
120 +++ b/drivers/ssb/driver_pcicore.c
121 @@ -3,7 +3,7 @@
122 * Broadcom PCI-core driver
123 *
124 * Copyright 2005, Broadcom Corporation
125 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
126 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
127 *
128 * Licensed under the GNU/GPL. See COPYING for details.
129 */
130 @@ -314,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
131 return ssb_mips_irq(extpci_core->dev) + 2;
132 }
133
134 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
135 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
136 {
137 u32 val;
138
139 @@ -379,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
140 register_pci_controller(&ssb_pcicore_controller);
141 }
142
143 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
144 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
145 {
146 struct ssb_bus *bus = pc->dev->bus;
147 u16 chipid_top;
148 @@ -412,7 +412,7 @@ static int pcicore_is_in_hostmode(struct
149 * Workarounds.
150 **************************************************/
151
152 -static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
153 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
154 {
155 u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
156 if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
157 @@ -514,7 +514,7 @@ static void ssb_pcicore_pcie_setup_worka
158 * Generic and Clientmode operation code.
159 **************************************************/
160
161 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
162 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
163 {
164 struct ssb_device *pdev = pc->dev;
165 struct ssb_bus *bus = pdev->bus;
166 --- a/drivers/ssb/embedded.c
167 +++ b/drivers/ssb/embedded.c
168 @@ -3,7 +3,7 @@
169 * Embedded systems support code
170 *
171 * Copyright 2005-2008, Broadcom Corporation
172 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
173 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
174 *
175 * Licensed under the GNU/GPL. See COPYING for details.
176 */
177 --- a/drivers/ssb/main.c
178 +++ b/drivers/ssb/main.c
179 @@ -3,7 +3,7 @@
180 * Subsystem core
181 *
182 * Copyright 2005, Broadcom Corporation
183 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
184 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
185 *
186 * Licensed under the GNU/GPL. See COPYING for details.
187 */
188 @@ -12,6 +12,7 @@
189
190 #include <linux/delay.h>
191 #include <linux/io.h>
192 +#include <linux/module.h>
193 #include <linux/ssb/ssb.h>
194 #include <linux/ssb/ssb_regs.h>
195 #include <linux/ssb/ssb_driver_gige.h>
196 @@ -557,7 +558,7 @@ error:
197 }
198
199 /* Needs ssb_buses_lock() */
200 -static int ssb_attach_queued_buses(void)
201 +static int __devinit ssb_attach_queued_buses(void)
202 {
203 struct ssb_bus *bus, *n;
204 int err = 0;
205 @@ -768,9 +769,9 @@ out:
206 return err;
207 }
208
209 -static int ssb_bus_register(struct ssb_bus *bus,
210 - ssb_invariants_func_t get_invariants,
211 - unsigned long baseaddr)
212 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
213 + ssb_invariants_func_t get_invariants,
214 + unsigned long baseaddr)
215 {
216 int err;
217
218 @@ -851,8 +852,8 @@ err_disable_xtal:
219 }
220
221 #ifdef CONFIG_SSB_PCIHOST
222 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
223 - struct pci_dev *host_pci)
224 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
225 + struct pci_dev *host_pci)
226 {
227 int err;
228
229 @@ -875,9 +876,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
230 #endif /* CONFIG_SSB_PCIHOST */
231
232 #ifdef CONFIG_SSB_PCMCIAHOST
233 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
234 - struct pcmcia_device *pcmcia_dev,
235 - unsigned long baseaddr)
236 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
237 + struct pcmcia_device *pcmcia_dev,
238 + unsigned long baseaddr)
239 {
240 int err;
241
242 @@ -897,8 +898,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
243 #endif /* CONFIG_SSB_PCMCIAHOST */
244
245 #ifdef CONFIG_SSB_SDIOHOST
246 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
247 - unsigned int quirks)
248 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
249 + struct sdio_func *func,
250 + unsigned int quirks)
251 {
252 int err;
253
254 @@ -918,9 +920,9 @@ int ssb_bus_sdiobus_register(struct ssb_
255 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
256 #endif /* CONFIG_SSB_PCMCIAHOST */
257
258 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
259 - unsigned long baseaddr,
260 - ssb_invariants_func_t get_invariants)
261 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
262 + unsigned long baseaddr,
263 + ssb_invariants_func_t get_invariants)
264 {
265 int err;
266
267 @@ -1001,8 +1003,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
268 switch (plltype) {
269 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
270 if (m & SSB_CHIPCO_CLK_T6_MMASK)
271 - return SSB_CHIPCO_CLK_T6_M0;
272 - return SSB_CHIPCO_CLK_T6_M1;
273 + return SSB_CHIPCO_CLK_T6_M1;
274 + return SSB_CHIPCO_CLK_T6_M0;
275 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
276 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
277 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
278 @@ -1259,13 +1261,34 @@ void ssb_device_disable(struct ssb_devic
279 }
280 EXPORT_SYMBOL(ssb_device_disable);
281
282 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
283 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
284 +{
285 + u16 chip_id = dev->bus->chip_id;
286 +
287 + if (dev->id.coreid == SSB_DEV_80211) {
288 + return (chip_id == 0x4322 || chip_id == 43221 ||
289 + chip_id == 43231 || chip_id == 43222);
290 + }
291 +
292 + return 0;
293 +}
294 +
295 u32 ssb_dma_translation(struct ssb_device *dev)
296 {
297 switch (dev->bus->bustype) {
298 case SSB_BUSTYPE_SSB:
299 return 0;
300 case SSB_BUSTYPE_PCI:
301 - return SSB_PCI_DMA;
302 + if (pci_is_pcie(dev->bus->host_pci) &&
303 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
304 + return SSB_PCIE_DMA_H32;
305 + } else {
306 + if (ssb_dma_translation_special_bit(dev))
307 + return SSB_PCIE_DMA_H32;
308 + else
309 + return SSB_PCI_DMA;
310 + }
311 default:
312 __ssb_dma_not_implemented(dev);
313 }
314 --- a/drivers/ssb/pci.c
315 +++ b/drivers/ssb/pci.c
316 @@ -1,7 +1,7 @@
317 /*
318 * Sonics Silicon Backplane PCI-Hostbus related functions.
319 *
320 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
321 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
322 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
323 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
324 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
325 @@ -523,7 +523,13 @@ static void sprom_extract_r45(struct ssb
326 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
327 {
328 int i;
329 - u16 v;
330 + u16 v, o;
331 + u16 pwr_info_offset[] = {
332 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
333 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
334 + };
335 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
336 + ARRAY_SIZE(out->core_pwr_info));
337
338 /* extract the MAC address */
339 for (i = 0; i < 3; i++) {
340 @@ -607,6 +613,61 @@ static void sprom_extract_r8(struct ssb_
341 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
342 sizeof(out->antenna_gain.ghz5));
343
344 + /* Extract cores power info info */
345 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
346 + o = pwr_info_offset[i];
347 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
348 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
349 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
350 + SSB_SPROM8_2G_MAXP, 0);
351 +
352 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
353 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
354 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
355 +
356 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
357 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
358 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
359 + SSB_SPROM8_5G_MAXP, 0);
360 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
361 + SSB_SPROM8_5GH_MAXP, 0);
362 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
363 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
364 +
365 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
366 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
367 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
368 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
369 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
370 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
371 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
372 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
373 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
374 + }
375 +
376 + /* Extract FEM info */
377 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
378 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
379 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
380 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
381 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
382 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
383 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
384 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
385 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
386 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
387 +
388 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
389 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
390 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
391 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
392 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
393 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
394 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
395 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
396 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
397 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
398 +
399 sprom_extract_r458(out, in);
400
401 /* TODO - get remaining rev 8 stuff needed */
402 @@ -734,12 +795,9 @@ out_free:
403 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
404 struct ssb_boardinfo *bi)
405 {
406 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
407 - &bi->vendor);
408 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
409 - &bi->type);
410 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
411 - &bi->rev);
412 + bi->vendor = bus->host_pci->subsystem_vendor;
413 + bi->type = bus->host_pci->subsystem_device;
414 + bi->rev = bus->host_pci->revision;
415 }
416
417 int ssb_pci_get_invariants(struct ssb_bus *bus,
418 --- a/drivers/ssb/pcihost_wrapper.c
419 +++ b/drivers/ssb/pcihost_wrapper.c
420 @@ -6,7 +6,7 @@
421 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
422 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
423 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
424 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
425 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
426 *
427 * Licensed under the GNU/GPL. See COPYING for details.
428 */
429 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
430 # define ssb_pcihost_resume NULL
431 #endif /* CONFIG_PM */
432
433 -static int ssb_pcihost_probe(struct pci_dev *dev,
434 - const struct pci_device_id *id)
435 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
436 + const struct pci_device_id *id)
437 {
438 struct ssb_bus *ssb;
439 int err = -ENOMEM;
440 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
441 pci_set_drvdata(dev, NULL);
442 }
443
444 -int ssb_pcihost_register(struct pci_driver *driver)
445 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
446 {
447 driver->probe = ssb_pcihost_probe;
448 driver->remove = ssb_pcihost_remove;
449 --- a/drivers/ssb/pcmcia.c
450 +++ b/drivers/ssb/pcmcia.c
451 @@ -3,7 +3,7 @@
452 * PCMCIA-Hostbus related functions
453 *
454 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
455 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
456 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
457 *
458 * Licensed under the GNU/GPL. See COPYING for details.
459 */
460 --- a/drivers/ssb/scan.c
461 +++ b/drivers/ssb/scan.c
462 @@ -2,7 +2,7 @@
463 * Sonics Silicon Backplane
464 * Bus scanning
465 *
466 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
467 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
468 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
469 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
470 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
471 @@ -310,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
472 } else {
473 if (bus->bustype == SSB_BUSTYPE_PCI) {
474 bus->chip_id = pcidev_to_chipid(bus->host_pci);
475 - pci_read_config_byte(bus->host_pci, PCI_REVISION_ID,
476 - &bus->chip_rev);
477 + bus->chip_rev = bus->host_pci->revision;
478 bus->chip_package = 0;
479 } else {
480 bus->chip_id = 0x4710;
481 --- a/drivers/ssb/sdio.c
482 +++ b/drivers/ssb/sdio.c
483 @@ -6,7 +6,7 @@
484 *
485 * Based on drivers/ssb/pcmcia.c
486 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
487 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
488 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
489 *
490 * Licensed under the GNU/GPL. See COPYING for details.
491 *
492 --- a/drivers/ssb/sprom.c
493 +++ b/drivers/ssb/sprom.c
494 @@ -2,7 +2,7 @@
495 * Sonics Silicon Backplane
496 * Common SPROM support routines
497 *
498 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
499 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
500 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
501 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
502 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
503 --- a/include/linux/ssb/ssb.h
504 +++ b/include/linux/ssb/ssb.h
505 @@ -16,6 +16,12 @@ struct pcmcia_device;
506 struct ssb_bus;
507 struct ssb_driver;
508
509 +struct ssb_sprom_core_pwr_info {
510 + u8 itssi_2g, itssi_5g;
511 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
512 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
513 +};
514 +
515 struct ssb_sprom {
516 u8 revision;
517 u8 il0mac[6]; /* MAC address for 802.11b/g */
518 @@ -25,8 +31,10 @@ struct ssb_sprom {
519 u8 et1phyaddr; /* MII address for enet1 */
520 u8 et0mdcport; /* MDIO for enet0 */
521 u8 et1mdcport; /* MDIO for enet1 */
522 - u8 board_rev; /* Board revision number from SPROM. */
523 + u16 board_rev; /* Board revision number from SPROM. */
524 u8 country_code; /* Country Code */
525 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
526 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
527 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
528 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
529 u16 pa0b0;
530 @@ -80,6 +88,8 @@ struct ssb_sprom {
531 u16 boardflags2_hi; /* Board flags (bits 48-63) */
532 /* TODO store board flags in a single u64 */
533
534 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
535 +
536 /* Antenna gain values for up to 4 antennas
537 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
538 * loss in the connectors is bigger than the gain. */
539 @@ -92,6 +102,15 @@ struct ssb_sprom {
540 } ghz5; /* 5GHz band */
541 } antenna_gain;
542
543 + struct {
544 + struct {
545 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
546 + } ghz2;
547 + struct {
548 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
549 + } ghz5;
550 + } fem;
551 +
552 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
553 };
554
555 @@ -99,7 +118,7 @@ struct ssb_sprom {
556 struct ssb_boardinfo {
557 u16 vendor;
558 u16 type;
559 - u16 rev;
560 + u8 rev;
561 };
562
563
564 @@ -229,10 +248,9 @@ struct ssb_driver {
565 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
566
567 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
568 -static inline int ssb_driver_register(struct ssb_driver *drv)
569 -{
570 - return __ssb_driver_register(drv, THIS_MODULE);
571 -}
572 +#define ssb_driver_register(drv) \
573 + __ssb_driver_register(drv, THIS_MODULE)
574 +
575 extern void ssb_driver_unregister(struct ssb_driver *drv);
576
577
578 --- a/include/linux/ssb/ssb_driver_chipcommon.h
579 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
580 @@ -8,7 +8,7 @@
581 * gpio interface, extbus, and support for serial and parallel flashes.
582 *
583 * Copyright 2005, Broadcom Corporation
584 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
585 + * Copyright 2006, Michael Buesch <m@bues.ch>
586 *
587 * Licensed under the GPL version 2. See COPYING for details.
588 */
589 --- a/include/linux/ssb/ssb_regs.h
590 +++ b/include/linux/ssb/ssb_regs.h
591 @@ -432,6 +432,56 @@
592 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
593 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
594 #define SSB_SPROM8_RXPO5G_SHIFT 8
595 +#define SSB_SPROM8_FEM2G 0x00AE
596 +#define SSB_SPROM8_FEM5G 0x00B0
597 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
598 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
599 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
600 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
601 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
602 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
603 +#define SSB_SROM8_FEM_TR_ISO 0x0700
604 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
605 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
606 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
607 +#define SSB_SPROM8_THERMAL 0x00B2
608 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
609 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
610 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
611 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
612 +
613 +/* There are 4 blocks with power info sharing the same layout */
614 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
615 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
616 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
617 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
618 +
619 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
620 +#define SSB_SPROM8_2G_MAXP 0x00FF
621 +#define SSB_SPROM8_2G_ITSSI 0xFF00
622 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
623 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
624 +#define SSB_SROM8_2G_PA_1 0x04
625 +#define SSB_SROM8_2G_PA_2 0x06
626 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
627 +#define SSB_SPROM8_5G_MAXP 0x00FF
628 +#define SSB_SPROM8_5G_ITSSI 0xFF00
629 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
630 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
631 +#define SSB_SPROM8_5GH_MAXP 0x00FF
632 +#define SSB_SPROM8_5GL_MAXP 0xFF00
633 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
634 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
635 +#define SSB_SROM8_5G_PA_1 0x0E
636 +#define SSB_SROM8_5G_PA_2 0x10
637 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
638 +#define SSB_SROM8_5GL_PA_1 0x14
639 +#define SSB_SROM8_5GL_PA_2 0x16
640 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
641 +#define SSB_SROM8_5GH_PA_1 0x1A
642 +#define SSB_SROM8_5GH_PA_2 0x1C
643 +
644 +/* TODO: Make it deprecated */
645 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
646 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
647 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
648 @@ -456,12 +506,53 @@
649 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
650 #define SSB_SPROM8_PA1HIB1 0x00DA
651 #define SSB_SPROM8_PA1HIB2 0x00DC
652 +
653 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
654 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
655 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
656 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
657 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
658
659 +/* Values for boardflags_lo read from SPROM */
660 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
661 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
662 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
663 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
664 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
665 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
666 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
667 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
668 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
669 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
670 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
671 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
672 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
673 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
674 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
675 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
676 +
677 +/* Values for boardflags_hi read from SPROM */
678 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
679 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
680 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
681 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
682 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
683 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
684 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
685 +
686 +/* Values for boardflags2_lo read from SPROM */
687 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
688 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
689 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
690 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
691 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
692 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
693 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
694 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
695 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
696 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
697 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
698 +
699 /* Values for SSB_SPROM1_BINF_CCODE */
700 enum {
701 SSB_SPROM1CCODE_WORLD = 0,
Personal OpenWRT clone
This page took 0.069349 seconds and 5 git commands to generate.