1 diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
2 index 18f9588..fff94e6 100644
3 --- a/arch/arm/plat-s3c/include/plat/nand.h
4 +++ b/arch/arm/plat-s3c/include/plat/nand.h
5 @@ -33,6 +33,8 @@ struct s3c2410_nand_set {
10 +#define S3C2410_NAND_BBT 0x0001
13 struct mtd_partition *partitions;
14 @@ -51,6 +53,9 @@ struct s3c2410_platform_nand {
16 struct s3c2410_nand_set *sets;
18 + /* force software_ecc at runtime */
21 void (*select_chip)(struct s3c2410_nand_set *,
24 diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
25 index 11dc7e6..59637ac 100644
26 --- a/drivers/mtd/nand/s3c2410.c
27 +++ b/drivers/mtd/nand/s3c2410.c
28 @@ -491,7 +491,7 @@ static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
29 if ((diff0 & ~(1<<fls(diff0))) == 0)
37 @@ -774,9 +783,13 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
38 chip->select_chip = s3c2410_nand_select_chip;
39 chip->chip_delay = 50;
42 chip->controller = &info->controller;
44 + if (set->flags & S3C2410_NAND_BBT)
45 + chip->options = NAND_USE_FLASH_BBT;
49 switch (info->cpu_type) {
51 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
52 @@ -816,7 +829,7 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
53 nmtd->mtd.owner = THIS_MODULE;
57 + if (!info->platform->software_ecc && hardware_ecc) {
58 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
59 chip->ecc.correct = s3c2410_nand_correct_data;
60 chip->ecc.mode = NAND_ECC_HW;