target/linux/xburst/patches-2.6.35/053-adc.patch

   1 From ae6e941c5d58262c0a09c355ae384b7109977053 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Mon, 12 Jul 2010 03:48:08 +0200
   4 Subject: [PATCH] mfd: Add JZ4740 ADC driver
   5
   6 This patch adds a MFD driver for the JZ4740 ADC unit. The driver is used to
   7 demultiplex IRQs and synchronize access to shared registers between the
   8 battery, hwmon and (future) touchscreen driver.
   9
  10 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
  11 Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
  12 ---
  13  drivers/mfd/Kconfig        |    8 +
  14  drivers/mfd/Makefile       |    1 +
  15  drivers/mfd/jz4740-adc.c   |  394 ++++++++++++++++++++++++++++++++++++++++++++
  16  include/linux/jz4740-adc.h |   32 ++++
  17  4 files changed, 435 insertions(+), 0 deletions(-)
  18  create mode 100644 drivers/mfd/jz4740-adc.c
  19  create mode 100644 include/linux/jz4740-adc.h
  20
  21 --- a/drivers/mfd/Kconfig
  22 +++ b/drivers/mfd/Kconfig
  23 @@ -482,6 +482,14 @@ config MFD_JANZ_CMODIO
  24           host many different types of MODULbus daughterboards, including
  25           CAN and GPIO controllers.
  26
  27 +config MFD_JZ4740_ADC
  28 +       tristate "Support for the JZ4740 SoC ADC core"
  29 +       select MFD_CORE
  30 +       depends on MACH_JZ4740
  31 +       help
  32 +         Say yes here if you want support for the ADC unit in the JZ4740 SoC.
  33 +         This driver is necessary for jz4740-battery and jz4740-hwmon driver.
  34 +
  35  endif # MFD_SUPPORT
  36
  37  menu "Multimedia Capabilities Port drivers"
  38 --- a/drivers/mfd/Makefile
  39 +++ b/drivers/mfd/Makefile
  40 @@ -71,3 +71,4 @@ obj-$(CONFIG_PMIC_ADP5520)    += adp5520.o
  41  obj-$(CONFIG_LPC_SCH)          += lpc_sch.o
  42  obj-$(CONFIG_MFD_RDC321X)      += rdc321x-southbridge.o
  43  obj-$(CONFIG_MFD_JANZ_CMODIO)  += janz-cmodio.o
  44 +obj-$(CONFIG_MFD_JZ4740_ADC)   += jz4740-adc.o
  45 --- /dev/null
  46 +++ b/drivers/mfd/jz4740-adc.c
  47 @@ -0,0 +1,394 @@
  48 +/*
  49 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
  50 + * JZ4740 SoC ADC driver
  51 + *
  52 + * This program is free software; you can redistribute it and/or modify it
  53 + * under  the terms of the GNU General  Public License as published by the
  54 + * Free Software Foundation;  either version 2 of the License, or (at your
  55 + * option) any later version.
  56 + *
  57 + * You should have received a copy of the GNU General Public License along
  58 + * with this program; if not, write to the Free Software Foundation, Inc.,
  59 + * 675 Mass Ave, Cambridge, MA 02139, USA.
  60 + *
  61 + * This driver synchronizes access to the JZ4740 ADC core between the
  62 + * JZ4740 battery and hwmon drivers.
  63 + */
  64 +
  65 +#include <linux/err.h>
  66 +#include <linux/irq.h>
  67 +#include <linux/interrupt.h>
  68 +#include <linux/kernel.h>
  69 +#include <linux/module.h>
  70 +#include <linux/platform_device.h>
  71 +#include <linux/slab.h>
  72 +#include <linux/spinlock.h>
  73 +
  74 +#include <linux/clk.h>
  75 +#include <linux/mfd/core.h>
  76 +
  77 +#include <linux/jz4740-adc.h>
  78 +
  79 +
  80 +#define JZ_REG_ADC_ENABLE      0x00
  81 +#define JZ_REG_ADC_CFG         0x04
  82 +#define JZ_REG_ADC_CTRL                0x08
  83 +#define JZ_REG_ADC_STATUS      0x0c
  84 +
  85 +#define JZ_REG_ADC_TOUCHSCREEN_BASE    0x10
  86 +#define JZ_REG_ADC_BATTERY_BASE        0x1c
  87 +#define JZ_REG_ADC_HWMON_BASE  0x20
  88 +
  89 +#define JZ_ADC_ENABLE_TOUCH    BIT(2)
  90 +#define JZ_ADC_ENABLE_BATTERY  BIT(1)
  91 +#define JZ_ADC_ENABLE_ADCIN    BIT(0)
  92 +
  93 +enum {
  94 +       JZ_ADC_IRQ_ADCIN = 0,
  95 +       JZ_ADC_IRQ_BATTERY,
  96 +       JZ_ADC_IRQ_TOUCH,
  97 +       JZ_ADC_IRQ_PENUP,
  98 +       JZ_ADC_IRQ_PENDOWN,
  99 +};
 100 +
 101 +struct jz4740_adc {
 102 +       struct resource *mem;
 103 +       void __iomem *base;
 104 +
 105 +       int irq;
 106 +       int irq_base;
 107 +
 108 +       struct clk *clk;
 109 +       atomic_t clk_ref;
 110 +
 111 +       spinlock_t lock;
 112 +};
 113 +
 114 +static inline void jz4740_adc_irq_set_masked(struct jz4740_adc *adc, int irq,
 115 +       bool masked)
 116 +{
 117 +       unsigned long flags;
 118 +       uint8_t val;
 119 +
 120 +       irq -= adc->irq_base;
 121 +
 122 +       spin_lock_irqsave(&adc->lock, flags);
 123 +
 124 +       val = readb(adc->base + JZ_REG_ADC_CTRL);
 125 +       if (masked)
 126 +               val |= BIT(irq);
 127 +       else
 128 +               val &= ~BIT(irq);
 129 +       writeb(val, adc->base + JZ_REG_ADC_CTRL);
 130 +
 131 +       spin_unlock_irqrestore(&adc->lock, flags);
 132 +}
 133 +
 134 +static void jz4740_adc_irq_mask(unsigned int irq)
 135 +{
 136 +       struct jz4740_adc *adc = get_irq_chip_data(irq);
 137 +       jz4740_adc_irq_set_masked(adc, irq, true);
 138 +}
 139 +
 140 +static void jz4740_adc_irq_unmask(unsigned int irq)
 141 +{
 142 +       struct jz4740_adc *adc = get_irq_chip_data(irq);
 143 +       jz4740_adc_irq_set_masked(adc, irq, false);
 144 +}
 145 +
 146 +static void jz4740_adc_irq_ack(unsigned int irq)
 147 +{
 148 +       struct jz4740_adc *adc = get_irq_chip_data(irq);
 149 +
 150 +       irq -= adc->irq_base;
 151 +       writeb(BIT(irq), adc->base + JZ_REG_ADC_STATUS);
 152 +}
 153 +
 154 +static struct irq_chip jz4740_adc_irq_chip = {
 155 +       .name = "jz4740-adc",
 156 +       .mask = jz4740_adc_irq_mask,
 157 +       .unmask = jz4740_adc_irq_unmask,
 158 +       .ack = jz4740_adc_irq_ack,
 159 +};
 160 +
 161 +static void jz4740_adc_irq_demux(unsigned int irq, struct irq_desc *desc)
 162 +{
 163 +       struct jz4740_adc *adc = get_irq_desc_data(desc);
 164 +       uint8_t status;
 165 +       unsigned int i;
 166 +
 167 +       status = readb(adc->base + JZ_REG_ADC_STATUS);
 168 +
 169 +       for (i = 0; i < 5; ++i) {
 170 +               if (status & BIT(i))
 171 +                       generic_handle_irq(adc->irq_base + i);
 172 +       }
 173 +}
 174 +
 175 +
 176 +/* Refcounting for the ADC clock is done in here instead of in the clock
 177 + * framework, because it is the only clock which is shared between multiple
 178 + * devices and thus is the only clock which needs refcounting */
 179 +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
 180 +{
 181 +       if (atomic_inc_return(&adc->clk_ref) == 1)
 182 +               clk_enable(adc->clk);
 183 +}
 184 +
 185 +static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
 186 +{
 187 +       if (atomic_dec_return(&adc->clk_ref) == 0)
 188 +               clk_disable(adc->clk);
 189 +}
 190 +
 191 +static inline void jz4740_adc_set_enabled(struct jz4740_adc *adc, int engine,
 192 +       bool enabled)
 193 +{
 194 +       unsigned long flags;
 195 +       uint8_t val;
 196 +
 197 +       spin_lock_irqsave(&adc->lock, flags);
 198 +
 199 +       val = readb(adc->base + JZ_REG_ADC_ENABLE);
 200 +       if (enabled)
 201 +               val |= BIT(engine);
 202 +       else
 203 +               val &= BIT(engine);
 204 +       writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 205 +
 206 +       spin_unlock_irqrestore(&adc->lock, flags);
 207 +}
 208 +
 209 +static int jz4740_adc_cell_enable(struct platform_device *pdev)
 210 +{
 211 +       struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
 212 +
 213 +       jz4740_adc_clk_enable(adc);
 214 +       jz4740_adc_set_enabled(adc, pdev->id, true);
 215 +
 216 +       return 0;
 217 +}
 218 +
 219 +static int jz4740_adc_cell_disable(struct platform_device *pdev)
 220 +{
 221 +       struct jz4740_adc *adc = dev_get_drvdata(pdev->dev.parent);
 222 +
 223 +       jz4740_adc_set_enabled(adc, pdev->id, false);
 224 +       jz4740_adc_clk_disable(adc);
 225 +
 226 +       return 0;
 227 +}
 228 +
 229 +int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val)
 230 +{
 231 +       struct jz4740_adc *adc = dev_get_drvdata(dev);
 232 +       unsigned long flags;
 233 +       uint32_t cfg;
 234 +
 235 +       if (!adc)
 236 +               return -ENODEV;
 237 +
 238 +       spin_lock_irqsave(&adc->lock, flags);
 239 +
 240 +       cfg = readl(adc->base + JZ_REG_ADC_CFG);
 241 +
 242 +       cfg &= ~mask;
 243 +       cfg |= val;
 244 +
 245 +       writel(cfg, adc->base + JZ_REG_ADC_CFG);
 246 +
 247 +       spin_unlock_irqrestore(&adc->lock, flags);
 248 +
 249 +       return 0;
 250 +}
 251 +EXPORT_SYMBOL_GPL(jz4740_adc_set_config);
 252 +
 253 +static struct resource jz4740_hwmon_resources[] = {
 254 +       {
 255 +               .start = JZ_ADC_IRQ_ADCIN,
 256 +               .flags = IORESOURCE_IRQ,
 257 +       },
 258 +       {
 259 +               .start  = JZ_REG_ADC_HWMON_BASE,
 260 +               .end    = JZ_REG_ADC_HWMON_BASE + 3,
 261 +               .flags  = IORESOURCE_MEM,
 262 +       },
 263 +};
 264 +
 265 +static struct resource jz4740_battery_resources[] = {
 266 +       {
 267 +               .start = JZ_ADC_IRQ_BATTERY,
 268 +               .flags = IORESOURCE_IRQ,
 269 +       },
 270 +       {
 271 +               .start  = JZ_REG_ADC_BATTERY_BASE,
 272 +               .end    = JZ_REG_ADC_BATTERY_BASE + 3,
 273 +               .flags  = IORESOURCE_MEM,
 274 +       },
 275 +};
 276 +
 277 +const struct mfd_cell jz4740_adc_cells[] = {
 278 +       {
 279 +               .id = 0,
 280 +               .name = "jz4740-hwmon",
 281 +               .num_resources = ARRAY_SIZE(jz4740_hwmon_resources),
 282 +               .resources = jz4740_hwmon_resources,
 283 +               .platform_data = (void *)&jz4740_adc_cells[0],
 284 +               .data_size = sizeof(struct mfd_cell),
 285 +
 286 +               .enable = jz4740_adc_cell_enable,
 287 +               .disable = jz4740_adc_cell_disable,
 288 +       },
 289 +       {
 290 +               .id = 1,
 291 +               .name = "jz4740-battery",
 292 +               .num_resources = ARRAY_SIZE(jz4740_battery_resources),
 293 +               .resources = jz4740_battery_resources,
 294 +               .platform_data = (void *)&jz4740_adc_cells[1],
 295 +               .data_size = sizeof(struct mfd_cell),
 296 +
 297 +               .enable = jz4740_adc_cell_enable,
 298 +               .disable = jz4740_adc_cell_disable,
 299 +       },
 300 +};
 301 +
 302 +static int __devinit jz4740_adc_probe(struct platform_device *pdev)
 303 +{
 304 +       int ret;
 305 +       struct jz4740_adc *adc;
 306 +       struct resource *mem_base;
 307 +       int irq;
 308 +
 309 +       adc = kmalloc(sizeof(*adc), GFP_KERNEL);
 310 +       if (!adc) {
 311 +               dev_err(&pdev->dev, "Failed to allocate driver structure\n");
 312 +               return -ENOMEM;
 313 +       }
 314 +
 315 +       adc->irq = platform_get_irq(pdev, 0);
 316 +       if (adc->irq < 0) {
 317 +               ret = adc->irq;
 318 +               dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 319 +               goto err_free;
 320 +       }
 321 +
 322 +       adc->irq_base = platform_get_irq(pdev, 1);
 323 +       if (adc->irq_base < 0) {
 324 +               ret = adc->irq_base;
 325 +               dev_err(&pdev->dev, "Failed to get irq base: %d\n", ret);
 326 +               goto err_free;
 327 +       }
 328 +
 329 +       mem_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 330 +       if (!mem_base) {
 331 +               ret = -ENOENT;
 332 +               dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
 333 +               goto err_free;
 334 +       }
 335 +
 336 +       /* Only request the shared registers for the MFD driver */
 337 +       adc->mem = request_mem_region(mem_base->start, JZ_REG_ADC_STATUS,
 338 +                                       pdev->name);
 339 +       if (!adc->mem) {
 340 +               ret = -EBUSY;
 341 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 342 +               goto err_free;
 343 +       }
 344 +
 345 +       adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
 346 +       if (!adc->base) {
 347 +               ret = -EBUSY;
 348 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 349 +               goto err_release_mem_region;
 350 +       }
 351 +
 352 +       adc->clk = clk_get(&pdev->dev, "adc");
 353 +       if (IS_ERR(adc->clk)) {
 354 +               ret = PTR_ERR(adc->clk);
 355 +               dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
 356 +               goto err_iounmap;
 357 +       }
 358 +
 359 +       spin_lock_init(&adc->lock);
 360 +       atomic_set(&adc->clk_ref, 0);
 361 +
 362 +       platform_set_drvdata(pdev, adc);
 363 +
 364 +       for (irq = adc->irq_base; irq < adc->irq_base + 5; ++irq) {
 365 +               set_irq_chip_data(irq, adc);
 366 +               set_irq_chip_and_handler(irq, &jz4740_adc_irq_chip,
 367 +                   handle_level_irq);
 368 +       }
 369 +
 370 +       set_irq_data(adc->irq, adc);
 371 +       set_irq_chained_handler(adc->irq, jz4740_adc_irq_demux);
 372 +
 373 +       writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
 374 +       writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
 375 +
 376 +       ret = mfd_add_devices(&pdev->dev, 0, jz4740_adc_cells,
 377 +               ARRAY_SIZE(jz4740_adc_cells), mem_base, adc->irq_base);
 378 +       if (ret < 0)
 379 +               goto err_clk_put;
 380 +
 381 +       return 0;
 382 +
 383 +err_clk_put:
 384 +       clk_put(adc->clk);
 385 +err_iounmap:
 386 +       platform_set_drvdata(pdev, NULL);
 387 +       iounmap(adc->base);
 388 +err_release_mem_region:
 389 +       release_mem_region(adc->mem->start, resource_size(adc->mem));
 390 +err_free:
 391 +       kfree(adc);
 392 +
 393 +       return ret;
 394 +}
 395 +
 396 +static int __devexit jz4740_adc_remove(struct platform_device *pdev)
 397 +{
 398 +       struct jz4740_adc *adc = platform_get_drvdata(pdev);
 399 +
 400 +       mfd_remove_devices(&pdev->dev);
 401 +
 402 +       set_irq_data(adc->irq, NULL);
 403 +       set_irq_chained_handler(adc->irq, NULL);
 404 +
 405 +       iounmap(adc->base);
 406 +       release_mem_region(adc->mem->start, resource_size(adc->mem));
 407 +
 408 +       clk_put(adc->clk);
 409 +
 410 +       platform_set_drvdata(pdev, NULL);
 411 +
 412 +       kfree(adc);
 413 +
 414 +       return 0;
 415 +}
 416 +
 417 +struct platform_driver jz4740_adc_driver = {
 418 +       .probe  = jz4740_adc_probe,
 419 +       .remove = __devexit_p(jz4740_adc_remove),
 420 +       .driver = {
 421 +               .name = "jz4740-adc",
 422 +               .owner = THIS_MODULE,
 423 +       },
 424 +};
 425 +
 426 +static int __init jz4740_adc_init(void)
 427 +{
 428 +       return platform_driver_register(&jz4740_adc_driver);
 429 +}
 430 +module_init(jz4740_adc_init);
 431 +
 432 +static void __exit jz4740_adc_exit(void)
 433 +{
 434 +       platform_driver_unregister(&jz4740_adc_driver);
 435 +}
 436 +module_exit(jz4740_adc_exit);
 437 +
 438 +MODULE_DESCRIPTION("JZ4740 SoC ADC driver");
 439 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 440 +MODULE_LICENSE("GPL");
 441 +MODULE_ALIAS("platform:jz4740-adc");
 442 --- /dev/null
 443 +++ b/include/linux/jz4740-adc.h
 444 @@ -0,0 +1,32 @@
 445 +
 446 +#ifndef __LINUX_JZ4740_ADC
 447 +#define __LINUX_JZ4740_ADC
 448 +
 449 +#include <linux/device.h>
 450 +
 451 +/*
 452 + * jz4740_adc_set_config - Configure a JZ4740 adc device
 453 + * @dev: Pointer to a jz4740-adc device
 454 + * @mask: Mask for the config value to be set
 455 + * @val: Value to be set
 456 + *
 457 + * This function can be used by the JZ4740 ADC mfd cells to configure their
 458 + * options in the shared config register.
 459 +*/
 460 +int jz4740_adc_set_config(struct device *dev, uint32_t mask, uint32_t val);
 461 +
 462 +#define JZ_ADC_CONFIG_SPZZ             BIT(31)
 463 +#define JZ_ADC_CONFIG_EX_IN            BIT(30)
 464 +#define JZ_ADC_CONFIG_DNUM_MASK                (0x7 << 16)
 465 +#define JZ_ADC_CONFIG_DMA_ENABLE       BIT(15)
 466 +#define JZ_ADC_CONFIG_XYZ_MASK         (0x2 << 13)
 467 +#define JZ_ADC_CONFIG_SAMPLE_NUM_MASK  (0x7 << 10)
 468 +#define JZ_ADC_CONFIG_CLKDIV_MASK      (0xf << 5)
 469 +#define JZ_ADC_CONFIG_BAT_MB           BIT(4)
 470 +
 471 +#define JZ_ADC_CONFIG_DNUM(dnum)       ((dnum) << 16)
 472 +#define JZ_ADC_CONFIG_XYZ_OFFSET(dnum) ((xyz) << 13)
 473 +#define JZ_ADC_CONFIG_SAMPLE_NUM(x)    ((x) << 10)
 474 +#define JZ_ADC_CONFIG_CLKDIV(div)      ((div) << 5)
 475 +
 476 +#endif