target/linux/adm5120-2.6/files/arch/mips/adm5120/mipsIRQ.S

   1 /*
   2  * Carsten Langgaard, carstenl@mips.com
   3  * Copyright (C) 1999, 2000 MIPS Technologies, Inc.  All rights reserved.
   4  *
   5  * ########################################################################
   6  *
   7  *  This program is free software; you can distribute it and/or modify it
   8  *  under the terms of the GNU General Public License (Version 2) as
   9  *  published by the Free Software Foundation.
  10  *
  11  *  This program is distributed in the hope it will be useful, but WITHOUT
  12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  *  for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License along
  17  *  with this program; if not, write to the Free Software Foundation, Inc.,
  18  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  19  *
  20  * ########################################################################
  21  *
  22  * Interrupt exception dispatch code.
  23  *
  24  */
  25 #include <linux/autoconf.h>
  26
  27 #include <asm/asm.h>
  28 #include <asm/mipsregs.h>
  29 #include <asm/regdef.h>
  30 #include <asm/stackframe.h>
  31
  32 #define STATUS_IE       0x00000001
  33
  34 /* A lot of complication here is taken away because:
  35  *
  36  * 1) We handle one interrupt and return, sitting in a loop and moving across
  37  *    all the pending IRQ bits in the cause register is _NOT_ the answer, the
  38  *    common case is one pending IRQ so optimize in that direction.
  39  *
  40  * 2) We need not check against bits in the status register IRQ mask, that
  41  *    would make this routine slow as hell.
  42  *
  43  * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
  44  *    between like BSD spl() brain-damage.
  45  *
  46  * Furthermore, the IRQs on the MIPS board look basically (barring software
  47  * IRQs which we don't use at all and all external interrupt sources are
  48  * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
  49  *
  50  *      MIPS IRQ        Source
  51  *      --------        ------
  52  *             0        Software (ignored)
  53  *             1        Software (ignored)
  54  *             2        Combined hardware interrupt (hw0)
  55  *             3        Hardware (ignored)
  56  *             4        Hardware (ignored)
  57  *             5        Hardware (ignored)
  58  *             6        Hardware (ignored)
  59  *             7        R4k timer (what we use)
  60  *
  61  * Note: On the SEAD board thing are a little bit different.
  62  *       Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
  63  *       wired to UART1.
  64  *
  65  * We handle the IRQ according to _our_ priority which is:
  66  *
  67  * Highest ----     R4k Timer
  68  * Lowest  ----     Combined hardware interrupt
  69  *
  70  * then we just return, if multiple IRQs are pending then we will just take
  71  * another exception, big deal.
  72  */
  73
  74         .text
  75         .set    noreorder
  76         .set    noat
  77         .align  5
  78
  79 NESTED(mipsIRQ, PT_SIZE, sp)
  80         SAVE_ALL
  81         CLI
  82         .set    at
  83
  84         mfc0    s0, CP0_CAUSE
  85         mfc0    s1, CP0_STATUS
  86         and     s0, s0, s1
  87
  88         /* First we check for r4k counter/timer IRQ. */
  89         andi    a0, s0, CAUSEF_IP7
  90         beq             a0, zero, 1f
  91         nop
  92
  93         move    a0, sp
  94         jal             mips_timer_interrupt
  95         nop
  96
  97         j               ret_from_irq
  98         nop
  99
 100 1:
 101         andi    a0, s0, CAUSEF_IP2
 102         beq             a0, zero, 1f
 103         nop
 104
 105         move    a0, sp
 106         jal             adm5120_hw0_irqdispatch
 107         nop
 108 1:
 109         j               ret_from_irq
 110         nop
 111
 112 END(mipsIRQ)
 113
 114
 115 LEAF(mips_int_lock)
 116         .set noreorder
 117         mfc0    v0, CP0_STATUS
 118         li              v1, ~STATUS_IE
 119         and             v1, v1, v0
 120         mtc0    v1, CP0_STATUS
 121         j               ra
 122         and             v0, v0, STATUS_IE
 123         .set reorder
 124 END(mips_int_lock)
 125
 126
 127 LEAF(mips_int_unlock)
 128         mfc0    v0, CP0_STATUS
 129         and             a0, a0, STATUS_IE
 130         or              v0, v0, a0
 131         mtc0    v0, CP0_STATUS
 132         j               ra
 133         nop
 134 END(mips_int_unlock)
 135