package/uboot-lantiq/files/board/arcadyan/lowlevel_bootstrap_init.S

   1 /*
   2  *  Memory sub-system initialization code for Danube board.
   3  *  Andre Messerschmidt
   4  *  Copyright (c) 2005  Infineon Technologies AG
   5  *
   6  *  Based on Inca-IP code
   7  *  Copyright (c) 2003  Wolfgang Denk <wd@denx.de>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27 /* History:
  28       peng liu May 25, 2006, for PLL setting after reset, 05252006
  29  */
  30 #include <config.h>
  31 #include <version.h>
  32 #include <asm/regdef.h>
  33
  34 #if defined(CONFIG_USE_DDR_PSC_32)
  35 #include "ddr_settings_psc_32.h"
  36 #define DDR166
  37 #elif defined(CONFIG_USE_DDR_PSC_64)
  38 #include "ddr_settings_psc_64.h"
  39 #define DDR166
  40 #else
  41 #error "missing definition for RAM"
  42 #endif
  43
  44 #define EBU_MODUL_BASE          0xBE105300
  45 #define EBU_CLC(value)          0x0000(value)
  46 #define EBU_CON(value)          0x0010(value)
  47 #define EBU_ADDSEL0(value)      0x0020(value)
  48 #define EBU_ADDSEL1(value)      0x0024(value)
  49 #define EBU_ADDSEL2(value)      0x0028(value)
  50 #define EBU_ADDSEL3(value)      0x002C(value)
  51 #define EBU_BUSCON0(value)      0x0060(value)
  52 #define EBU_BUSCON1(value)      0x0064(value)
  53 #define EBU_BUSCON2(value)      0x0068(value)
  54 #define EBU_BUSCON3(value)      0x006C(value)
  55
  56 #define MC_MODUL_BASE           0xBF800000
  57 #define MC_ERRCAUSE(value)      0x0010(value)
  58 #define MC_ERRADDR(value)       0x0020(value)
  59 #define MC_CON(value)           0x0060(value)
  60
  61 #define MC_SRAM_ENABLE          0x00000004
  62 #define MC_SDRAM_ENABLE         0x00000002
  63 #define MC_DDRRAM_ENABLE        0x00000001
  64
  65 #define MC_SDR_MODUL_BASE       0xBF800200
  66 #define MC_IOGP(value)          0x0000(value)
  67 #define MC_CTRLENA(value)       0x0010(value)
  68 #define MC_MRSCODE(value)       0x0020(value)
  69 #define MC_CFGDW(value)         0x0030(value)
  70 #define MC_CFGPB0(value)        0x0040(value)
  71 #define MC_LATENCY(value)       0x0080(value)
  72 #define MC_TREFRESH(value)      0x0090(value)
  73 #define MC_SELFRFSH(value)      0x00A0(value)
  74
  75 #define MC_DDR_MODUL_BASE       0xBF801000
  76 #define MC_DC00(value)          0x0000(value)
  77 #define MC_DC01(value)          0x0010(value)
  78 #define MC_DC02(value)          0x0020(value)
  79 #define MC_DC03(value)          0x0030(value)
  80 #define MC_DC04(value)          0x0040(value)
  81 #define MC_DC05(value)          0x0050(value)
  82 #define MC_DC06(value)          0x0060(value)
  83 #define MC_DC07(value)          0x0070(value)
  84 #define MC_DC08(value)          0x0080(value)
  85 #define MC_DC09(value)          0x0090(value)
  86 #define MC_DC10(value)          0x00A0(value)
  87 #define MC_DC11(value)          0x00B0(value)
  88 #define MC_DC12(value)          0x00C0(value)
  89 #define MC_DC13(value)          0x00D0(value)
  90 #define MC_DC14(value)          0x00E0(value)
  91 #define MC_DC15(value)          0x00F0(value)
  92 #define MC_DC16(value)          0x0100(value)
  93 #define MC_DC17(value)          0x0110(value)
  94 #define MC_DC18(value)          0x0120(value)
  95 #define MC_DC19(value)          0x0130(value)
  96 #define MC_DC20(value)          0x0140(value)
  97 #define MC_DC21(value)          0x0150(value)
  98 #define MC_DC22(value)          0x0160(value)
  99 #define MC_DC23(value)          0x0170(value)
 100 #define MC_DC24(value)          0x0180(value)
 101 #define MC_DC25(value)          0x0190(value)
 102 #define MC_DC26(value)          0x01A0(value)
 103 #define MC_DC27(value)          0x01B0(value)
 104 #define MC_DC28(value)          0x01C0(value)
 105 #define MC_DC29(value)          0x01D0(value)
 106 #define MC_DC30(value)          0x01E0(value)
 107 #define MC_DC31(value)          0x01F0(value)
 108 #define MC_DC32(value)          0x0200(value)
 109 #define MC_DC33(value)          0x0210(value)
 110 #define MC_DC34(value)          0x0220(value)
 111 #define MC_DC35(value)          0x0230(value)
 112 #define MC_DC36(value)          0x0240(value)
 113 #define MC_DC37(value)          0x0250(value)
 114 #define MC_DC38(value)          0x0260(value)
 115 #define MC_DC39(value)          0x0270(value)
 116 #define MC_DC40(value)          0x0280(value)
 117 #define MC_DC41(value)          0x0290(value)
 118 #define MC_DC42(value)          0x02A0(value)
 119 #define MC_DC43(value)          0x02B0(value)
 120 #define MC_DC44(value)          0x02C0(value)
 121 #define MC_DC45(value)          0x02D0(value)
 122 #define MC_DC46(value)          0x02E0(value)
 123
 124 #define RCU_OFFSET  0xBF203000
 125 #define RCU_RST_REQ      (RCU_OFFSET + 0x0010)
 126 #define RCU_STS          (RCU_OFFSET + 0x0014)
 127
 128 #define CGU_OFFSET  0xBF103000
 129 #define  PLL0_CFG     (CGU_OFFSET + 0x0004)
 130 #define  PLL1_CFG     (CGU_OFFSET + 0x0008)
 131 #define  PLL2_CFG     (CGU_OFFSET + 0x000C)
 132 #define  CGU_SYS      (CGU_OFFSET + 0x0010)
 133 #define  CGU_UPDATE   (CGU_OFFSET + 0x0014)
 134 #define  IF_CLK       (CGU_OFFSET + 0x0018)
 135 #define  CGU_SMD      (CGU_OFFSET + 0x0020)
 136 #define  CGU_CT1SR    (CGU_OFFSET + 0x0028)
 137 #define  CGU_CT2SR    (CGU_OFFSET + 0x002C)
 138 #define  CGU_PCMCR    (CGU_OFFSET + 0x0030)
 139 #define  PCI_CR_PCI   (CGU_OFFSET + 0x0034)
 140 #define  CGU_OSC_CTRL (CGU_OFFSET + 0x001C)
 141 #define  CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038)
 142 #define  CLK_MEASURE  (CGU_OFFSET + 0x003C)
 143
 144 //05252006
 145 #define  pll0_35MHz_CONFIG 0x9D861059
 146 #define  pll1_35MHz_CONFIG 0x1A260CD9
 147 #define  pll2_35MHz_CONFIG 0x8000f1e5
 148 #define  pll0_36MHz_CONFIG 0x1000125D
 149 #define  pll1_36MHz_CONFIG 0x1B1E0C99
 150 #define  pll2_36MHz_CONFIG 0x8002f2a1
 151 //05252006
 152
 153 //06063001-joelin disable the PCI CFRAME mask -start
 154 /*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out.
 155 But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled.
 156
 157 The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus.
 158 The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function.
 159 */
 160 #define PCI_CR_PR_OFFSET  0xBE105400
 161 #define PCI_CR_PCI_MOD_REG          (PCI_CR_PR_OFFSET + 0x0030)
 162 #define PCI_CONFIG_SPACE  0xB7000000
 163 #define CS_CFM          (PCI_CONFIG_SPACE + 0x6C)
 164 //06063001-joelin disable the PCI CFRAME mask -end
 165         .set    noreorder
 166
 167
 168 /*
 169  * void ebu_init(void)
 170  */
 171         .globl  ebu_init
 172         .ent    ebu_init
 173 ebu_init:
 174
 175 #if defined(CONFIG_EBU_ADDSEL0) || defined(CONFIG_EBU_ADDSEL1) || \
 176         defined(CONFIG_EBU_ADDSEL2) || defined(CONFIG_EBU_ADDSEL3) || \
 177         defined(CONFIG_EBU_BUSCON0) || defined(CONFIG_EBU_BUSCON1) || \
 178         defined(CONFIG_EBU_BUSCON2) || defined(CONFIG_EBU_BUSCON3)
 179
 180         li      t1, EBU_MODUL_BASE
 181 #if defined(CONFIG_EBU_ADDSEL0)
 182         li      t2, CONFIG_EBU_ADDSEL0
 183         sw      t2, EBU_ADDSEL0(t1)
 184 #endif
 185 #if defined(CONFIG_EBU_ADDSEL1)
 186         li      t2, CONFIG_EBU_ADDSEL1
 187         sw      t2, EBU_ADDSEL1(t1)
 188 #endif
 189 #if defined(CONFIG_EBU_ADDSEL2)
 190         li      t2, CONFIG_EBU_ADDSEL2
 191         sw      t2, EBU_ADDSEL2(t1)
 192 #endif
 193 #if defined(CONFIG_EBU_ADDSEL3)
 194         li      t2, CONFIG_EBU_ADDSEL3
 195         sw      t2, EBU_ADDSEL3(t1)
 196 #endif
 197
 198 #if defined(CONFIG_EBU_BUSCON0)
 199         li      t2, CONFIG_EBU_BUSCON0
 200         sw      t2, EBU_BUSCON0(t1)
 201 #endif
 202 #if defined(CONFIG_EBU_BUSCON1)
 203         li      t2, CONFIG_EBU_BUSCON1
 204         sw      t2, EBU_BUSCON1(t1)
 205 #endif
 206 #if defined(CONFIG_EBU_BUSCON2)
 207         li      t2, CONFIG_EBU_BUSCON2
 208         sw      t2, EBU_BUSCON2(t1)
 209 #endif
 210 #if defined(CONFIG_EBU_BUSCON3)
 211         li      t2, CONFIG_EBU_BUSCON3
 212         sw      t2, EBU_BUSCON3(t1)
 213 #endif
 214
 215 #endif
 216
 217         j       ra
 218         nop
 219
 220         .end    ebu_init
 221
 222
 223 /*
 224  * void cgu_init(long)
 225  *
 226  * a0 has the clock value
 227  */
 228         .globl  cgu_init
 229         .ent    cgu_init
 230 cgu_init:
 231         li  t2, CGU_SYS
 232         lw  t2,0(t2)
 233         beq t2,a0,freq_up2date
 234         nop
 235
 236         li  t2, RCU_STS
 237         lw  t2, 0(t2)
 238         and t2,0x00020000
 239         beq t2,0x00020000,boot_36MHZ
 240         nop
 241 //05252006
 242         li  t1, PLL0_CFG
 243         li  t2, pll0_35MHz_CONFIG
 244         sw      t2,0(t1)
 245         li  t1, PLL1_CFG
 246         li  t2, pll1_35MHz_CONFIG
 247         sw      t2,0(t1)
 248         li  t1, PLL2_CFG
 249         li  t2, pll2_35MHz_CONFIG
 250         sw      t2,0(t1)
 251         li  t1, CGU_SYS
 252         sw      a0,0(t1)
 253         li  t1, RCU_RST_REQ
 254         li  t2, 0x40000008
 255         sw      t2,0(t1)
 256         b   wait_reset
 257         nop
 258 boot_36MHZ:
 259         li  t1, PLL0_CFG
 260         li  t2, pll0_36MHz_CONFIG
 261         sw      t2,0(t1)
 262         li  t1, PLL1_CFG
 263         li  t2, pll1_36MHz_CONFIG
 264         sw      t2,0(t1)
 265         li  t1, PLL2_CFG
 266         li  t2, pll2_36MHz_CONFIG
 267         sw      t2,0(t1)
 268         li  t1, CGU_SYS
 269         sw      a0,0(t1)
 270         li  t1, RCU_RST_REQ
 271         li  t2, 0x40000008
 272         sw      t2,0(t1)
 273 //05252006
 274
 275 wait_reset:
 276         b   wait_reset
 277         nop
 278 freq_up2date:
 279         j ra
 280         nop
 281
 282         .end    cgu_init
 283
 284 #ifndef CONFIG_USE_DDR_RAM
 285 /*
 286  * void sdram_init(long)
 287  *
 288  * a0 has the clock value
 289  */
 290         .globl  sdram_init
 291         .ent    sdram_init
 292 sdram_init:
 293
 294         /* SDRAM Initialization
 295          */
 296         li      t1, MC_MODUL_BASE
 297
 298         /* Clear Error log registers */
 299         sw      zero, MC_ERRCAUSE(t1)
 300         sw      zero, MC_ERRADDR(t1)
 301
 302         /* Enable SDRAM module in memory controller */
 303         li      t3, MC_SDRAM_ENABLE
 304         lw      t2, MC_CON(t1)
 305         or      t3, t2, t3
 306         sw      t3, MC_CON(t1)
 307
 308         li      t1, MC_SDR_MODUL_BASE
 309
 310         /* disable the controller */
 311         li      t2, 0
 312         sw      t2, MC_CTRLENA(t1)
 313
 314         li      t2, 0x822
 315         sw      t2, MC_IOGP(t1)
 316
 317         li      t2, 0x2
 318         sw      t2, MC_CFGDW(t1)
 319
 320         /* Set CAS Latency */
 321         li      t2, 0x00000020
 322         sw      t2, MC_MRSCODE(t1)
 323
 324         /* Set CS0 to SDRAM parameters */
 325         li      t2, 0x000014d8
 326         sw      t2, MC_CFGPB0(t1)
 327
 328         /* Set SDRAM latency parameters */
 329         li      t2, 0x00036325;   /* BC PC100 */
 330         sw      t2, MC_LATENCY(t1)
 331
 332         /* Set SDRAM refresh rate */
 333         li      t2, 0x00000C30
 334         sw      t2, MC_TREFRESH(t1)
 335
 336         /* Clear Power-down registers */
 337         sw      zero, MC_SELFRFSH(t1)
 338
 339         /* Finally enable the controller */
 340         li      t2, 1
 341         sw      t2, MC_CTRLENA(t1)
 342
 343         j       ra
 344         nop
 345
 346         .end    sdram_init
 347
 348 #endif /* !CONFIG_USE_DDR_RAM */
 349
 350 #ifdef CONFIG_USE_DDR_RAM
 351 /*
 352  * void ddrram_init(long)
 353  *
 354  * a0 has the clock value
 355  */
 356         .globl  ddrram_init
 357         .ent    ddrram_init
 358 ddrram_init:
 359
 360         /* DDR-DRAM Initialization
 361          */
 362         li      t1, MC_MODUL_BASE
 363
 364         /* Clear Error log registers */
 365         sw      zero, MC_ERRCAUSE(t1)
 366         sw      zero, MC_ERRADDR(t1)
 367
 368         /* Enable DDR module in memory controller */
 369         li      t3, MC_DDRRAM_ENABLE
 370         lw      t2, MC_CON(t1)
 371         or      t3, t2, t3
 372         sw      t3, MC_CON(t1)
 373
 374         li      t1, MC_DDR_MODUL_BASE
 375
 376         /* Write configuration to DDR controller registers */
 377         li      t2, MC_DC0_VALUE
 378         sw      t2, MC_DC00(t1)
 379
 380         li      t2, MC_DC1_VALUE
 381         sw      t2, MC_DC01(t1)
 382
 383         li      t2, MC_DC2_VALUE
 384         sw      t2, MC_DC02(t1)
 385
 386         li      t2, MC_DC3_VALUE
 387         sw      t2, MC_DC03(t1)
 388
 389         li      t2, MC_DC4_VALUE
 390         sw      t2, MC_DC04(t1)
 391
 392         li      t2, MC_DC5_VALUE
 393         sw      t2, MC_DC05(t1)
 394
 395         li      t2, MC_DC6_VALUE
 396         sw      t2, MC_DC06(t1)
 397
 398         li      t2, MC_DC7_VALUE
 399         sw      t2, MC_DC07(t1)
 400
 401         li      t2, MC_DC8_VALUE
 402         sw      t2, MC_DC08(t1)
 403
 404         li      t2, MC_DC9_VALUE
 405         sw      t2, MC_DC09(t1)
 406
 407         li      t2, MC_DC10_VALUE
 408         sw      t2, MC_DC10(t1)
 409
 410         li      t2, MC_DC11_VALUE
 411         sw      t2, MC_DC11(t1)
 412
 413         li      t2, MC_DC12_VALUE
 414         sw      t2, MC_DC12(t1)
 415
 416         li      t2, MC_DC13_VALUE
 417         sw      t2, MC_DC13(t1)
 418
 419         li      t2, MC_DC14_VALUE
 420         sw      t2, MC_DC14(t1)
 421
 422         li      t2, MC_DC15_VALUE
 423         sw      t2, MC_DC15(t1)
 424
 425         li      t2, MC_DC16_VALUE
 426         sw      t2, MC_DC16(t1)
 427
 428         li      t2, MC_DC17_VALUE
 429         sw      t2, MC_DC17(t1)
 430
 431         li      t2, MC_DC18_VALUE
 432         sw      t2, MC_DC18(t1)
 433
 434         li      t2, MC_DC19_VALUE
 435         sw      t2, MC_DC19(t1)
 436
 437         li      t2, MC_DC20_VALUE
 438         sw      t2, MC_DC20(t1)
 439
 440         li      t2, MC_DC21_VALUE
 441         sw      t2, MC_DC21(t1)
 442
 443         li      t2, MC_DC22_VALUE
 444         sw      t2, MC_DC22(t1)
 445
 446         li      t2, MC_DC23_VALUE
 447         sw      t2, MC_DC23(t1)
 448
 449         li      t2, MC_DC24_VALUE
 450         sw      t2, MC_DC24(t1)
 451
 452         li      t2, MC_DC25_VALUE
 453         sw      t2, MC_DC25(t1)
 454
 455         li      t2, MC_DC26_VALUE
 456         sw      t2, MC_DC26(t1)
 457
 458         li      t2, MC_DC27_VALUE
 459         sw      t2, MC_DC27(t1)
 460
 461         li      t2, MC_DC28_VALUE
 462         sw      t2, MC_DC28(t1)
 463
 464         li      t2, MC_DC29_VALUE
 465         sw      t2, MC_DC29(t1)
 466
 467         li      t2, MC_DC30_VALUE
 468         sw      t2, MC_DC30(t1)
 469
 470         li      t2, MC_DC31_VALUE
 471         sw      t2, MC_DC31(t1)
 472
 473         li      t2, MC_DC32_VALUE
 474         sw      t2, MC_DC32(t1)
 475
 476         li      t2, MC_DC33_VALUE
 477         sw      t2, MC_DC33(t1)
 478
 479         li      t2, MC_DC34_VALUE
 480         sw      t2, MC_DC34(t1)
 481
 482         li      t2, MC_DC35_VALUE
 483         sw      t2, MC_DC35(t1)
 484
 485         li      t2, MC_DC36_VALUE
 486         sw      t2, MC_DC36(t1)
 487
 488         li      t2, MC_DC37_VALUE
 489         sw      t2, MC_DC37(t1)
 490
 491         li      t2, MC_DC38_VALUE
 492         sw      t2, MC_DC38(t1)
 493
 494         li      t2, MC_DC39_VALUE
 495         sw      t2, MC_DC39(t1)
 496
 497         li      t2, MC_DC40_VALUE
 498         sw      t2, MC_DC40(t1)
 499
 500         li      t2, MC_DC41_VALUE
 501         sw      t2, MC_DC41(t1)
 502
 503         li      t2, MC_DC42_VALUE
 504         sw      t2, MC_DC42(t1)
 505
 506         li      t2, MC_DC43_VALUE
 507         sw      t2, MC_DC43(t1)
 508
 509         li      t2, MC_DC44_VALUE
 510         sw      t2, MC_DC44(t1)
 511
 512         li      t2, MC_DC45_VALUE
 513         sw      t2, MC_DC45(t1)
 514
 515         li      t2, MC_DC46_VALUE
 516         sw      t2, MC_DC46(t1)
 517
 518         li      t2, 0x00000100
 519         sw      t2, MC_DC03(t1)
 520
 521         j       ra
 522         nop
 523
 524         .end    ddrram_init
 525 #endif /* CONFIG_USE_DDR_RAM */
 526
 527         .globl  lowlevel_init
 528         .ent    lowlevel_init
 529 lowlevel_init:
 530         /* EBU, CGU and SDRAM/DDR-RAM Initialization.
 531          */
 532         move    t0, ra
 533         /* We rely on the fact that non of the following ..._init() functions
 534          * modify t0
 535          */
 536 #if defined(DDR166)
 537         /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */
 538         li  a0,0xe8
 539 #elif defined(DDR133)
 540         /* 0xe9 means CPU0/CPU1 333M, DDR 133M, FPI 83M, PPE 240M */
 541         li  a0,0xe9
 542 #else /* defined(DDR111) */
 543         /* 0xea means CPU0/CPU1 333M, DDR 111M, FPI 83M, PPE 240M */
 544         li  a0,0xea
 545 #endif
 546         bal     cgu_init
 547         nop
 548
 549         bal     ebu_init
 550         nop
 551
 552 //06063001-joelin disable the PCI CFRAME mask-start
 553 #ifdef DISABLE_CFRAME
 554         li  t1, PCI_CR_PCI      //mw bf103034 80000000
 555         li  t2, 0x80000000
 556         sw      t2,0(t1)
 557
 558         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 559         li  t2, 0x103
 560         sw  t2,0(t1)
 561
 562         li  t1, CS_CFM                  //mw b700006c 0
 563         li  t2, 0x00
 564         sw  t2, 0(t1)
 565
 566         li  t1, PCI_CR_PCI_MOD_REG      //mw be105430 103
 567         li  t2, 0x1000103
 568         sw  t2, 0(t1)
 569 #endif
 570 //06063001-joelin disable the PCI CFRAME mask-end
 571
 572 #ifdef CONFIG_USE_DDR_RAM
 573         bal     ddrram_init
 574         nop
 575 #else
 576         bal     sdram_init
 577         nop
 578 #endif
 579         move    ra, t0
 580         j       ra
 581         nop
 582
 583         .end    lowlevel_init