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initial attempt at cleaning up the bcm63xx stuff
[openwrt.git] / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.17/arch/mips/aruba/Makefile linux-2.6.17-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.17/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.17-owrt/arch/mips/aruba/Makefile 2006-06-18 12:44:28.000000000 +0200
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/Makefile linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.17/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/Makefile 2006-06-18 12:44:28.000000000 +0200
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.c linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.c 2006-06-18 12:44:28.000000000 +0200
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.17/arch/mips/aruba/nvram/nvram434.h linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.17/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.17-owrt/arch/mips/aruba/nvram/nvram434.h 2006-06-18 12:44:28.000000000 +0200
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.17/arch/mips/aruba/prom.c linux-2.6.17-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.17/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.17-owrt/arch/mips/aruba/prom.c 2006-06-18 12:44:28.000000000 +0200
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.17/arch/mips/aruba/serial.c linux-2.6.17-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.17/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.17-owrt/arch/mips/aruba/serial.c 2006-06-18 12:44:28.000000000 +0200
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.17/arch/mips/aruba/setup.c linux-2.6.17-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.17/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.17-owrt/arch/mips/aruba/setup.c 2006-06-18 12:44:28.000000000 +0200
786 @@ -0,0 +1,134 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + switch (mips_machtype) {
909 + case MACH_ARUBA_AP70:
910 + return "Aruba AP70";
911 + case MACH_ARUBA_AP65:
912 + return "Aruba AP65";
913 + case MACH_ARUBA_AP60:
914 + return "Aruba AP60/AP61";
915 + default:
916 + return "Aruba UNKNOWN";
917 + }
918 +}
919 +
920 +EXPORT_SYMBOL(get_system_type);
921 diff -Nur linux-2.6.17/arch/mips/aruba/time.c linux-2.6.17-owrt/arch/mips/aruba/time.c
922 --- linux-2.6.17/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
923 +++ linux-2.6.17-owrt/arch/mips/aruba/time.c 2006-06-18 12:44:28.000000000 +0200
924 @@ -0,0 +1,110 @@
925 +/**************************************************************************
926 + *
927 + * BRIEF MODULE DESCRIPTION
928 + * timer routines for IDT EB434 boards
929 + *
930 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
931 + *
932 + * This program is free software; you can redistribute it and/or modify it
933 + * under the terms of the GNU General Public License as published by the
934 + * Free Software Foundation; either version 2 of the License, or (at your
935 + * option) any later version.
936 + *
937 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
938 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
939 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
940 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
941 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
942 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
943 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
944 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
945 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
946 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
947 + *
948 + * You should have received a copy of the GNU General Public License along
949 + * with this program; if not, write to the Free Software Foundation, Inc.,
950 + * 675 Mass Ave, Cambridge, MA 02139, USA.
951 + *
952 + *
953 + **************************************************************************
954 + * May 2004 rkt, neb
955 + *
956 + * Initial Release
957 + *
958 + *
959 + *
960 + **************************************************************************
961 + */
962 +
963 +#include <linux/config.h>
964 +#include <linux/init.h>
965 +#include <linux/kernel_stat.h>
966 +#include <linux/sched.h>
967 +#include <linux/spinlock.h>
968 +#include <linux/mc146818rtc.h>
969 +#include <linux/irq.h>
970 +#include <linux/timex.h>
971 +
972 +#include <linux/param.h>
973 +#include <asm/mipsregs.h>
974 +#include <asm/ptrace.h>
975 +#include <asm/time.h>
976 +#include <asm/hardirq.h>
977 +
978 +#include <asm/mipsregs.h>
979 +#include <asm/ptrace.h>
980 +#include <asm/debug.h>
981 +#include <asm/time.h>
982 +
983 +#include <asm/idt-boards/rc32434/rc32434.h>
984 +
985 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
986 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
987 +
988 +extern unsigned int idt_cpu_freq;
989 +
990 +static unsigned long __init cal_r4koff(void)
991 +{
992 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
993 + return (mips_hpt_frequency / HZ);
994 +}
995 +
996 +void __init aruba_time_init(void)
997 +{
998 + unsigned int est_freq, flags;
999 + local_irq_save(flags);
1000 +
1001 + printk("calculating r4koff... ");
1002 + r4k_offset = cal_r4koff();
1003 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
1004 +
1005 + est_freq = 2 * r4k_offset * HZ;
1006 + est_freq += 5000; /* round */
1007 + est_freq -= est_freq % 10000;
1008 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1009 + (est_freq % 1000000) * 100 / 1000000);
1010 + local_irq_restore(flags);
1011 +
1012 +}
1013 +
1014 +void __init aruba_timer_setup(struct irqaction *irq)
1015 +{
1016 + /* we are using the cpu counter for timer interrupts */
1017 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1018 +
1019 + /* to generate the first timer interrupt */
1020 + r4k_cur = (read_c0_count() + r4k_offset);
1021 + write_c0_compare(r4k_cur);
1022 +
1023 +}
1024 +
1025 +asmlinkage void aruba_timer_interrupt(struct pt_regs *regs)
1026 +{
1027 + int irq = MIPS_CPU_TIMER_IRQ;
1028 +
1029 + irq_enter();
1030 + kstat_this_cpu.irqs[irq]++;
1031 +
1032 + timer_interrupt(irq, NULL, regs);
1033 + irq_exit();
1034 +}
1035 diff -Nur linux-2.6.17/arch/mips/Kconfig linux-2.6.17-owrt/arch/mips/Kconfig
1036 --- linux-2.6.17/arch/mips/Kconfig 2006-06-18 03:49:35.000000000 +0200
1037 +++ linux-2.6.17-owrt/arch/mips/Kconfig 2006-06-18 12:44:28.000000000 +0200
1038 @@ -227,6 +227,17 @@
1039 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1040 a kernel for this platform.
1041
1042 +config MACH_ARUBA
1043 + bool "Support for the ARUBA product line"
1044 + select DMA_NONCOHERENT
1045 + select CPU_HAS_PREFETCH
1046 + select HW_HAS_PCI
1047 + select SWAP_IO_SPACE
1048 + select SYS_SUPPORTS_32BIT_KERNEL
1049 + select SYS_HAS_CPU_MIPS32_R1
1050 + select SYS_SUPPORTS_BIG_ENDIAN
1051 +
1052 +
1053 config MACH_JAZZ
1054 bool "Jazz family of machines"
1055 select ARC
1056 diff -Nur linux-2.6.17/arch/mips/Makefile linux-2.6.17-owrt/arch/mips/Makefile
1057 --- linux-2.6.17/arch/mips/Makefile 2006-06-18 03:49:35.000000000 +0200
1058 +++ linux-2.6.17-owrt/arch/mips/Makefile 2006-06-18 12:44:28.000000000 +0200
1059 @@ -145,6 +145,14 @@
1060 #
1061
1062 #
1063 +# Aruba
1064 +#
1065 +
1066 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1067 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1068 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1069 +
1070 +#
1071 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1072 #
1073 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1074 diff -Nur linux-2.6.17/arch/mips/mm/tlbex.c linux-2.6.17-owrt/arch/mips/mm/tlbex.c
1075 --- linux-2.6.17/arch/mips/mm/tlbex.c 2006-06-18 03:49:35.000000000 +0200
1076 +++ linux-2.6.17-owrt/arch/mips/mm/tlbex.c 2006-06-18 12:48:27.000000000 +0200
1077 @@ -876,7 +876,6 @@
1078 case CPU_R10000:
1079 case CPU_R12000:
1080 case CPU_R14000:
1081 - case CPU_4KC:
1082 case CPU_SB1:
1083 case CPU_SB1A:
1084 case CPU_4KSC:
1085 @@ -904,6 +903,7 @@
1086 tlbw(p);
1087 break;
1088
1089 + case CPU_4KC:
1090 case CPU_4KEC:
1091 case CPU_24K:
1092 case CPU_34K:
1093 diff -Nur linux-2.6.17/drivers/net/Kconfig linux-2.6.17-owrt/drivers/net/Kconfig
1094 --- linux-2.6.17/drivers/net/Kconfig 2006-06-18 03:49:35.000000000 +0200
1095 +++ linux-2.6.17-owrt/drivers/net/Kconfig 2006-06-18 12:44:28.000000000 +0200
1096 @@ -187,6 +187,13 @@
1097
1098 source "drivers/net/arm/Kconfig"
1099
1100 +config IDT_RC32434_ETH
1101 + tristate "IDT RC32434 Local Ethernet support"
1102 + depends on NET_ETHERNET
1103 + help
1104 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1105 + To compile this driver as a module, choose M here.
1106 +
1107 config MACE
1108 tristate "MACE (Power Mac ethernet) support"
1109 depends on NET_ETHERNET && PPC_PMAC && PPC32
1110 diff -Nur linux-2.6.17/drivers/net/Makefile linux-2.6.17-owrt/drivers/net/Makefile
1111 --- linux-2.6.17/drivers/net/Makefile 2006-06-18 03:49:35.000000000 +0200
1112 +++ linux-2.6.17-owrt/drivers/net/Makefile 2006-06-18 12:44:28.000000000 +0200
1113 @@ -38,6 +38,7 @@
1114
1115 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1116
1117 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1118 obj-$(CONFIG_DGRS) += dgrs.o
1119 obj-$(CONFIG_VORTEX) += 3c59x.o
1120 obj-$(CONFIG_TYPHOON) += typhoon.o
1121 diff -Nur linux-2.6.17/drivers/net/natsemi.c linux-2.6.17-owrt/drivers/net/natsemi.c
1122 --- linux-2.6.17/drivers/net/natsemi.c 2006-06-18 03:49:35.000000000 +0200
1123 +++ linux-2.6.17-owrt/drivers/net/natsemi.c 2006-06-18 12:44:28.000000000 +0200
1124 @@ -771,6 +771,49 @@
1125 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1126 static struct ethtool_ops ethtool_ops;
1127
1128 +#ifdef CONFIG_MACH_ARUBA
1129 +
1130 +#include <linux/ctype.h>
1131 +
1132 +#ifndef ERR
1133 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1134 +#endif
1135 +
1136 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1137 +{
1138 + int i, j;
1139 + unsigned char result, value;
1140 +
1141 + for (i=0; i<6; i++) {
1142 + result = 0;
1143 + if (i != 5 && *(macstr+2) != ':') {
1144 + ERR("invalid mac address format: %d %c\n",
1145 + i, *(macstr+2));
1146 + return -EINVAL;
1147 + }
1148 + for (j=0; j<2; j++) {
1149 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1150 + toupper(*macstr)-'A'+10) < 16) {
1151 + result = result*16 + value;
1152 + macstr++;
1153 + }
1154 + else {
1155 + ERR("invalid mac address "
1156 + "character: %c\n", *macstr);
1157 + return -EINVAL;
1158 + }
1159 + }
1160 +
1161 + macstr++;
1162 + dev->dev_addr[i] = result;
1163 + }
1164 +
1165 + dev->dev_addr[5]++;
1166 + return 0;
1167 +}
1168 +
1169 +#endif
1170 +
1171 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1172 {
1173 return (void __iomem *) dev->base_addr;
1174 @@ -871,6 +914,7 @@
1175 goto err_ioremap;
1176 }
1177
1178 +#ifndef CONFIG_MACH_ARUBA
1179 /* Work around the dropped serial bit. */
1180 prev_eedata = eeprom_read(ioaddr, 6);
1181 for (i = 0; i < 3; i++) {
1182 @@ -879,6 +923,19 @@
1183 dev->dev_addr[i*2+1] = eedata >> 7;
1184 prev_eedata = eedata;
1185 }
1186 +#else
1187 + {
1188 + char mac[32];
1189 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1190 + extern char *getenv(char *e);
1191 + memset(mac, 0, 32);
1192 + memcpy(mac, getenv("ethaddr"), 17);
1193 + if (parse_mac_addr(dev, mac)){
1194 + printk("%s: MAC address not found\n", __func__);
1195 + memcpy(dev->dev_addr, def_mac, 6);
1196 + }
1197 + }
1198 +#endif
1199
1200 dev->base_addr = (unsigned long __force) ioaddr;
1201 dev->irq = irq;
1202 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.c linux-2.6.17-owrt/drivers/net/rc32434_eth.c
1203 --- linux-2.6.17/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1204 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.c 2006-06-18 12:44:28.000000000 +0200
1205 @@ -0,0 +1,1273 @@
1206 +/**************************************************************************
1207 + *
1208 + * BRIEF MODULE DESCRIPTION
1209 + * Driver for the IDT RC32434 on-chip ethernet controller.
1210 + *
1211 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1212 + *
1213 + * This program is free software; you can redistribute it and/or modify it
1214 + * under the terms of the GNU General Public License as published by the
1215 + * Free Software Foundation; either version 2 of the License, or (at your
1216 + * option) any later version.
1217 + *
1218 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1219 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1220 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1221 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1222 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1223 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1224 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1225 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1226 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1227 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1228 + *
1229 + * You should have received a copy of the GNU General Public License along
1230 + * with this program; if not, write to the Free Software Foundation, Inc.,
1231 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1232 + *
1233 + *
1234 + **************************************************************************
1235 + * May 2004 rkt, neb
1236 + *
1237 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1238 + *
1239 + * Aug 2004 Sadik
1240 + *
1241 + * Added NAPI
1242 + *
1243 + **************************************************************************
1244 + */
1245 +
1246 +#include <linux/config.h>
1247 +#include <linux/version.h>
1248 +#include <linux/module.h>
1249 +#include <linux/kernel.h>
1250 +#include <linux/moduleparam.h>
1251 +#include <linux/sched.h>
1252 +#include <linux/ctype.h>
1253 +#include <linux/types.h>
1254 +#include <linux/fcntl.h>
1255 +#include <linux/interrupt.h>
1256 +#include <linux/ptrace.h>
1257 +#include <linux/init.h>
1258 +#include <linux/ioport.h>
1259 +#include <linux/proc_fs.h>
1260 +#include <linux/in.h>
1261 +#include <linux/slab.h>
1262 +#include <linux/string.h>
1263 +#include <linux/delay.h>
1264 +#include <linux/netdevice.h>
1265 +#include <linux/etherdevice.h>
1266 +#include <linux/skbuff.h>
1267 +#include <linux/errno.h>
1268 +#include <asm/bootinfo.h>
1269 +#include <asm/system.h>
1270 +#include <asm/bitops.h>
1271 +#include <asm/pgtable.h>
1272 +#include <asm/segment.h>
1273 +#include <asm/io.h>
1274 +#include <asm/dma.h>
1275 +
1276 +#include "rc32434_eth.h"
1277 +
1278 +#define DRIVER_VERSION "(mar2904)"
1279 +
1280 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1281 +
1282 +
1283 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1284 + ((dev)->dev_addr[1]))
1285 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1286 + ((dev)->dev_addr[3] << 16) | \
1287 + ((dev)->dev_addr[4] << 8) | \
1288 + ((dev)->dev_addr[5]))
1289 +
1290 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1291 +static char mac0[18] = "08:00:06:05:40:01";
1292 +
1293 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
1294 +module_param_string(mac0, mac0, 18, 0);
1295 +#else
1296 +MODULE_PARM(mac0, "c18");
1297 +#endif
1298 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1299 +
1300 +static struct rc32434_if_t {
1301 + char *name;
1302 + struct net_device *dev;
1303 + char* mac_str;
1304 + int weight;
1305 + u32 iobase;
1306 + u32 rxdmabase;
1307 + u32 txdmabase;
1308 + int rx_dma_irq;
1309 + int tx_dma_irq;
1310 + int rx_ovr_irq;
1311 + int tx_und_irq;
1312 +} rc32434_iflist[] =
1313 +{
1314 + {
1315 + "rc32434_eth0", NULL, mac0,
1316 + 64,
1317 + ETH0_PhysicalAddress,
1318 + ETH0_RX_DMA_ADDR,
1319 + ETH0_TX_DMA_ADDR,
1320 + ETH0_DMA_RX_IRQ,
1321 + ETH0_DMA_TX_IRQ,
1322 + ETH0_RX_OVR_IRQ,
1323 + ETH0_TX_UND_IRQ
1324 + }
1325 +};
1326 +
1327 +
1328 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1329 +{
1330 + int i, j;
1331 + unsigned char result, value;
1332 +
1333 + for (i=0; i<6; i++) {
1334 + result = 0;
1335 + if (i != 5 && *(macstr+2) != ':') {
1336 + ERR("invalid mac address format: %d %c\n",
1337 + i, *(macstr+2));
1338 + return -EINVAL;
1339 + }
1340 + for (j=0; j<2; j++) {
1341 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1342 + toupper(*macstr)-'A'+10) < 16) {
1343 + result = result*16 + value;
1344 + macstr++;
1345 + }
1346 + else {
1347 + ERR("invalid mac address "
1348 + "character: %c\n", *macstr);
1349 + return -EINVAL;
1350 + }
1351 + }
1352 +
1353 + macstr++;
1354 + dev->dev_addr[i] = result;
1355 + }
1356 +
1357 + return 0;
1358 +}
1359 +
1360 +
1361 +
1362 +static inline void rc32434_abort_tx(struct net_device *dev)
1363 +{
1364 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1365 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1366 +
1367 +}
1368 +
1369 +static inline void rc32434_abort_rx(struct net_device *dev)
1370 +{
1371 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1372 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1373 +
1374 +}
1375 +
1376 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1377 +{
1378 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1379 +}
1380 +
1381 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1382 +{
1383 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1384 +}
1385 +
1386 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1387 +{
1388 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1389 +}
1390 +
1391 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1392 +{
1393 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1394 +}
1395 +
1396 +#ifdef RC32434_PROC_DEBUG
1397 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1398 + int length, int *eof, void *data)
1399 +{
1400 + struct net_device *dev = (struct net_device *)data;
1401 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1402 + int len = 0;
1403 +
1404 + /* print out header */
1405 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1406 + len += sprintf (buf + len,
1407 + "DMA halt count = %10d, DMA run count = %10d\n",
1408 + lp->dma_halt_cnt, lp->dma_run_cnt);
1409 +
1410 + if (fpos >= len) {
1411 + *start = buf;
1412 + *eof = 1;
1413 + return 0;
1414 + }
1415 + *start = buf + fpos;
1416 +
1417 + if ((len -= fpos) > length)
1418 + return length;
1419 + *eof = 1;
1420 +
1421 + return len;
1422 +
1423 +}
1424 +#endif
1425 +
1426 +
1427 +/*
1428 + * Restart the RC32434 ethernet controller.
1429 + */
1430 +static int rc32434_restart(struct net_device *dev)
1431 +{
1432 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1433 +
1434 + /*
1435 + * Disable interrupts
1436 + */
1437 + disable_irq(lp->rx_irq);
1438 + disable_irq(lp->tx_irq);
1439 +#ifdef RC32434_REVISION
1440 + disable_irq(lp->ovr_irq);
1441 +#endif
1442 + disable_irq(lp->und_irq);
1443 +
1444 + /* Mask F E bit in Tx DMA */
1445 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1446 + /* Mask D H E bit in Rx DMA */
1447 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1448 +
1449 + rc32434_init(dev);
1450 + rc32434_multicast_list(dev);
1451 +
1452 + enable_irq(lp->und_irq);
1453 +#ifdef RC32434_REVISION
1454 + enable_irq(lp->ovr_irq);
1455 +#endif
1456 + enable_irq(lp->tx_irq);
1457 + enable_irq(lp->rx_irq);
1458 +
1459 + return 0;
1460 +}
1461 +
1462 +int rc32434_init_module(void)
1463 +{
1464 +#ifdef CONFIG_MACH_ARUBA
1465 + if (mips_machtype != MACH_ARUBA_AP70)
1466 + return 1;
1467 +#endif
1468 +
1469 + printk(KERN_INFO DRIVER_NAME " \n");
1470 + return rc32434_probe(0);
1471 +}
1472 +
1473 +static int rc32434_probe(int port_num)
1474 +{
1475 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1476 + struct rc32434_local *lp = NULL;
1477 + struct net_device *dev = NULL;
1478 + int i, retval,err;
1479 +
1480 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1481 + if(!dev) {
1482 + ERR("rc32434_eth: alloc_etherdev failed\n");
1483 + return -1;
1484 + }
1485 +
1486 + SET_MODULE_OWNER(dev);
1487 + bif->dev = dev;
1488 +
1489 +#ifdef CONFIG_MACH_ARUBA
1490 + {
1491 + extern char * getenv(char *e);
1492 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1493 + }
1494 +#endif
1495 +
1496 + printk("mac: %s\n", bif->mac_str);
1497 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1498 + ERR("MAC address parse failed\n");
1499 + free_netdev(dev);
1500 + return -1;
1501 + }
1502 +
1503 +
1504 + /* Initialize the device structure. */
1505 + if (dev->priv == NULL) {
1506 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1507 + memset(lp, 0, sizeof(struct rc32434_local));
1508 + }
1509 + else {
1510 + lp = (struct rc32434_local *)dev->priv;
1511 + }
1512 +
1513 + lp->rx_irq = bif->rx_dma_irq;
1514 + lp->tx_irq = bif->tx_dma_irq;
1515 + lp->ovr_irq = bif->rx_ovr_irq;
1516 + lp->und_irq = bif->tx_und_irq;
1517 +
1518 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1519 +
1520 + if (!lp->eth_regs) {
1521 + ERR("Can't remap eth registers\n");
1522 + retval = -ENXIO;
1523 + goto probe_err_out;
1524 + }
1525 +
1526 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1527 +
1528 + if (!lp->rx_dma_regs) {
1529 + ERR("Can't remap Rx DMA registers\n");
1530 + retval = -ENXIO;
1531 + goto probe_err_out;
1532 + }
1533 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1534 +
1535 + if (!lp->tx_dma_regs) {
1536 + ERR("Can't remap Tx DMA registers\n");
1537 + retval = -ENXIO;
1538 + goto probe_err_out;
1539 + }
1540 +
1541 +#ifdef RC32434_PROC_DEBUG
1542 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1543 + rc32434_read_proc, dev);
1544 +#endif
1545 +
1546 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1547 + if (!lp->td_ring) {
1548 + ERR("Can't allocate descriptors\n");
1549 + retval = -ENOMEM;
1550 + goto probe_err_out;
1551 + }
1552 +
1553 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1554 +
1555 + /* now convert TD_RING pointer to KSEG1 */
1556 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1557 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1558 +
1559 +
1560 + spin_lock_init(&lp->lock);
1561 +
1562 + dev->base_addr = bif->iobase;
1563 + /* just use the rx dma irq */
1564 + dev->irq = bif->rx_dma_irq;
1565 +
1566 + dev->priv = lp;
1567 +
1568 + dev->open = rc32434_open;
1569 + dev->stop = rc32434_close;
1570 + dev->hard_start_xmit = rc32434_send_packet;
1571 + dev->get_stats = rc32434_get_stats;
1572 + dev->set_multicast_list = &rc32434_multicast_list;
1573 + dev->tx_timeout = rc32434_tx_timeout;
1574 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1575 +
1576 +#ifdef CONFIG_IDT_USE_NAPI
1577 + dev->poll = rc32434_poll;
1578 + dev->weight = bif->weight;
1579 + printk("Using NAPI with weight %d\n",dev->weight);
1580 +#else
1581 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1582 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1583 +#endif
1584 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1585 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1586 +
1587 + if ((err = register_netdev(dev))) {
1588 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1589 + free_netdev(dev);
1590 + retval = -EINVAL;
1591 + goto probe_err_out;
1592 + }
1593 +
1594 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1595 + for (i = 0; i < 6; i++) {
1596 + printk("%2.2x", dev->dev_addr[i]);
1597 + if (i<5)
1598 + printk(":");
1599 + }
1600 + printk("\n");
1601 +
1602 + return 0;
1603 +
1604 + probe_err_out:
1605 + rc32434_cleanup_module();
1606 + ERR(" failed. Returns %d\n", retval);
1607 + return retval;
1608 +
1609 +}
1610 +
1611 +
1612 +static void rc32434_cleanup_module(void)
1613 +{
1614 + int i;
1615 +
1616 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1617 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1618 + if (bif->dev != NULL) {
1619 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1620 + if (lp != NULL) {
1621 + if (lp->eth_regs)
1622 + iounmap((void*)lp->eth_regs);
1623 + if (lp->rx_dma_regs)
1624 + iounmap((void*)lp->rx_dma_regs);
1625 + if (lp->tx_dma_regs)
1626 + iounmap((void*)lp->tx_dma_regs);
1627 + if (lp->td_ring)
1628 + kfree((void*)KSEG0ADDR(lp->td_ring));
1629 +
1630 +#ifdef RC32434_PROC_DEBUG
1631 + if (lp->ps) {
1632 + remove_proc_entry(bif->name, proc_net);
1633 + }
1634 +#endif
1635 + kfree(lp);
1636 + }
1637 +
1638 + unregister_netdev(bif->dev);
1639 + free_netdev(bif->dev);
1640 + kfree(bif->dev);
1641 + }
1642 + }
1643 +}
1644 +
1645 +
1646 +
1647 +static int rc32434_open(struct net_device *dev)
1648 +{
1649 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1650 +
1651 + /* Initialize */
1652 + if (rc32434_init(dev)) {
1653 + ERR("Error: cannot open the Ethernet device\n");
1654 + return -EAGAIN;
1655 + }
1656 +
1657 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1658 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1659 + SA_SHIRQ | SA_INTERRUPT,
1660 + "rc32434 ethernet Rx", dev)) {
1661 + ERR(": unable to get Rx DMA IRQ %d\n",
1662 + lp->rx_irq);
1663 + return -EAGAIN;
1664 + }
1665 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1666 + SA_SHIRQ | SA_INTERRUPT,
1667 + "rc32434 ethernet Tx", dev)) {
1668 + ERR(": unable to get Tx DMA IRQ %d\n",
1669 + lp->tx_irq);
1670 + free_irq(lp->rx_irq, dev);
1671 + return -EAGAIN;
1672 + }
1673 +
1674 +#ifdef RC32434_REVISION
1675 + /* Install handler for overrun error. */
1676 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1677 + SA_SHIRQ | SA_INTERRUPT,
1678 + "Ethernet Overflow", dev)) {
1679 + ERR(": unable to get OVR IRQ %d\n",
1680 + lp->ovr_irq);
1681 + free_irq(lp->rx_irq, dev);
1682 + free_irq(lp->tx_irq, dev);
1683 + return -EAGAIN;
1684 + }
1685 +#endif
1686 +
1687 + /* Install handler for underflow error. */
1688 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1689 + SA_SHIRQ | SA_INTERRUPT,
1690 + "Ethernet Underflow", dev)) {
1691 + ERR(": unable to get UND IRQ %d\n",
1692 + lp->und_irq);
1693 + free_irq(lp->rx_irq, dev);
1694 + free_irq(lp->tx_irq, dev);
1695 +#ifdef RC32434_REVISION
1696 + free_irq(lp->ovr_irq, dev);
1697 +#endif
1698 + return -EAGAIN;
1699 + }
1700 +
1701 +
1702 + return 0;
1703 +}
1704 +
1705 +
1706 +
1707 +
1708 +static int rc32434_close(struct net_device *dev)
1709 +{
1710 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1711 + u32 tmp;
1712 +
1713 + /* Disable interrupts */
1714 + disable_irq(lp->rx_irq);
1715 + disable_irq(lp->tx_irq);
1716 +#ifdef RC32434_REVISION
1717 + disable_irq(lp->ovr_irq);
1718 +#endif
1719 + disable_irq(lp->und_irq);
1720 +
1721 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1722 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1723 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1724 +
1725 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1726 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1727 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1728 +
1729 + free_irq(lp->rx_irq, dev);
1730 + free_irq(lp->tx_irq, dev);
1731 +#ifdef RC32434_REVISION
1732 + free_irq(lp->ovr_irq, dev);
1733 +#endif
1734 + free_irq(lp->und_irq, dev);
1735 + return 0;
1736 +}
1737 +
1738 +
1739 +/* transmit packet */
1740 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1741 +{
1742 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1743 + unsigned long flags;
1744 + u32 length;
1745 + DMAD_t td;
1746 +
1747 +
1748 + spin_lock_irqsave(&lp->lock, flags);
1749 +
1750 + td = &lp->td_ring[lp->tx_chain_tail];
1751 +
1752 + /* stop queue when full, drop pkts if queue already full */
1753 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1754 + lp->tx_full = 1;
1755 +
1756 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1757 + netif_stop_queue(dev);
1758 + }
1759 + else {
1760 + lp->stats.tx_dropped++;
1761 + dev_kfree_skb_any(skb);
1762 + spin_unlock_irqrestore(&lp->lock, flags);
1763 + return 1;
1764 + }
1765 + }
1766 +
1767 + lp->tx_count ++;
1768 +
1769 + lp->tx_skb[lp->tx_chain_tail] = skb;
1770 +
1771 + length = skb->len;
1772 +
1773 + /* Setup the transmit descriptor. */
1774 + td->ca = CPHYSADDR(skb->data);
1775 +
1776 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1777 + if( lp->tx_chain_status == empty ) {
1778 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1779 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1780 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1781 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1782 + }
1783 + else {
1784 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1785 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1786 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1787 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1788 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1789 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1790 + lp->tx_chain_status = empty;
1791 + }
1792 + }
1793 + else {
1794 + if( lp->tx_chain_status == empty ) {
1795 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1796 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1797 + lp->tx_chain_status = filled;
1798 + }
1799 + else {
1800 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1801 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1802 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1803 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1804 + }
1805 + }
1806 +
1807 + dev->trans_start = jiffies;
1808 +
1809 + spin_unlock_irqrestore(&lp->lock, flags);
1810 +
1811 + return 0;
1812 +}
1813 +
1814 +
1815 +/* Ethernet MII-PHY Handler */
1816 +static void rc32434_mii_handler(unsigned long data)
1817 +{
1818 + struct net_device *dev = (struct net_device *)data;
1819 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1820 + unsigned long flags;
1821 + unsigned long duplex_status;
1822 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1823 +
1824 + spin_lock_irqsave(&lp->lock, flags);
1825 +
1826 + /* Two ports are using the same MII, the difference is the PHY address */
1827 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1828 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1829 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1830 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1831 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1832 +
1833 + ERR("irq:%x port_addr:%x RDD:%x\n",
1834 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1835 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1836 + if(duplex_status != lp->duplex_mode) {
1837 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1838 + lp->duplex_mode = duplex_status;
1839 + rc32434_restart(dev);
1840 + }
1841 +
1842 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1843 + add_timer(&lp->mii_phy_timer);
1844 +
1845 + spin_unlock_irqrestore(&lp->lock, flags);
1846 +
1847 +}
1848 +
1849 +#ifdef RC32434_REVISION
1850 +/* Ethernet Rx Overflow interrupt */
1851 +static irqreturn_t
1852 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1853 +{
1854 + struct net_device *dev = (struct net_device *)dev_id;
1855 + struct rc32434_local *lp;
1856 + unsigned int ovr;
1857 + irqreturn_t retval = IRQ_NONE;
1858 +
1859 + ASSERT(dev != NULL);
1860 +
1861 + lp = (struct rc32434_local *)dev->priv;
1862 + spin_lock(&lp->lock);
1863 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1864 +
1865 + if(ovr & ETHINTFC_ovr_m) {
1866 + netif_stop_queue(dev);
1867 +
1868 + /* clear OVR bit */
1869 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1870 +
1871 + /* Restart interface */
1872 + rc32434_restart(dev);
1873 + retval = IRQ_HANDLED;
1874 + }
1875 + spin_unlock(&lp->lock);
1876 +
1877 + return retval;
1878 +}
1879 +
1880 +#endif
1881 +
1882 +
1883 +/* Ethernet Tx Underflow interrupt */
1884 +static irqreturn_t
1885 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1886 +{
1887 + struct net_device *dev = (struct net_device *)dev_id;
1888 + struct rc32434_local *lp;
1889 + unsigned int und;
1890 + irqreturn_t retval = IRQ_NONE;
1891 +
1892 + ASSERT(dev != NULL);
1893 +
1894 + lp = (struct rc32434_local *)dev->priv;
1895 +
1896 + spin_lock(&lp->lock);
1897 +
1898 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1899 +
1900 + if(und & ETHINTFC_und_m) {
1901 + netif_stop_queue(dev);
1902 +
1903 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1904 +
1905 + /* Restart interface */
1906 + rc32434_restart(dev);
1907 + retval = IRQ_HANDLED;
1908 + }
1909 +
1910 + spin_unlock(&lp->lock);
1911 +
1912 + return retval;
1913 +}
1914 +
1915 +
1916 +/* Ethernet Rx DMA interrupt */
1917 +static irqreturn_t
1918 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1919 +{
1920 + struct net_device *dev = (struct net_device *)dev_id;
1921 + struct rc32434_local* lp;
1922 + volatile u32 dmas,dmasm;
1923 + irqreturn_t retval;
1924 +
1925 + ASSERT(dev != NULL);
1926 +
1927 + lp = (struct rc32434_local *)dev->priv;
1928 +
1929 + spin_lock(&lp->lock);
1930 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1931 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1932 + /* Mask D H E bit in Rx DMA */
1933 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1934 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1935 +#ifdef CONFIG_IDT_USE_NAPI
1936 + if(netif_rx_schedule_prep(dev))
1937 + __netif_rx_schedule(dev);
1938 +#else
1939 + tasklet_hi_schedule(lp->rx_tasklet);
1940 +#endif
1941 +
1942 + if (dmas & DMAS_e_m)
1943 + ERR(": DMA error\n");
1944 +
1945 + retval = IRQ_HANDLED;
1946 + }
1947 + else
1948 + retval = IRQ_NONE;
1949 +
1950 + spin_unlock(&lp->lock);
1951 + return retval;
1952 +}
1953 +
1954 +#ifdef CONFIG_IDT_USE_NAPI
1955 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1956 +#else
1957 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1958 +#endif
1959 +{
1960 + struct net_device *dev = (struct net_device *)rx_data_dev;
1961 + struct rc32434_local* lp = netdev_priv(dev);
1962 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1963 + struct sk_buff *skb, *skb_new;
1964 + u8* pkt_buf;
1965 + u32 devcs, count, pkt_len, pktuncrc_len;
1966 + volatile u32 dmas;
1967 +#ifdef CONFIG_IDT_USE_NAPI
1968 + u32 received = 0;
1969 + int rx_work_limit = min(*budget,dev->quota);
1970 +#else
1971 + unsigned long flags;
1972 + spin_lock_irqsave(&lp->lock, flags);
1973 +#endif
1974 +
1975 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1976 +#ifdef CONFIG_IDT_USE_NAPI
1977 + if(--rx_work_limit <0)
1978 + {
1979 + break;
1980 + }
1981 +#endif
1982 + /* init the var. used for the later operations within the while loop */
1983 + skb_new = NULL;
1984 + devcs = rd->devcs;
1985 + pkt_len = RCVPKT_LENGTH(devcs);
1986 + skb = lp->rx_skb[lp->rx_next_done];
1987 +
1988 + if (count < 64) {
1989 + lp->stats.rx_errors++;
1990 + lp->stats.rx_dropped++;
1991 + }
1992 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1993 + /* check that this is a whole packet */
1994 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1995 + lp->stats.rx_errors++;
1996 + lp->stats.rx_dropped++;
1997 + }
1998 + else if ( (devcs & ETHRX_rok_m) ) {
1999 +
2000 + {
2001 + /* must be the (first and) last descriptor then */
2002 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
2003 +
2004 + pktuncrc_len = pkt_len - 4;
2005 + /* invalidate the cache */
2006 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
2007 +
2008 + /* Malloc up new buffer. */
2009 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
2010 +
2011 + if (skb_new != NULL){
2012 + /* Make room */
2013 + skb_put(skb, pktuncrc_len);
2014 +
2015 + skb->protocol = eth_type_trans(skb, dev);
2016 +
2017 + /* pass the packet to upper layers */
2018 +#ifdef CONFIG_IDT_USE_NAPI
2019 + netif_receive_skb(skb);
2020 +#else
2021 + netif_rx(skb);
2022 +#endif
2023 +
2024 + dev->last_rx = jiffies;
2025 + lp->stats.rx_packets++;
2026 + lp->stats.rx_bytes += pktuncrc_len;
2027 +
2028 + if (IS_RCV_MP(devcs))
2029 + lp->stats.multicast++;
2030 +
2031 + /* 16 bit align */
2032 + skb_reserve(skb_new, 2);
2033 +
2034 + skb_new->dev = dev;
2035 + lp->rx_skb[lp->rx_next_done] = skb_new;
2036 + }
2037 + else {
2038 + ERR("no memory, dropping rx packet.\n");
2039 + lp->stats.rx_errors++;
2040 + lp->stats.rx_dropped++;
2041 + }
2042 + }
2043 +
2044 + }
2045 + else {
2046 + /* This should only happen if we enable accepting broken packets */
2047 + lp->stats.rx_errors++;
2048 + lp->stats.rx_dropped++;
2049 +
2050 + /* add statistics counters */
2051 + if (IS_RCV_CRC_ERR(devcs)) {
2052 + DBG(2, "RX CRC error\n");
2053 + lp->stats.rx_crc_errors++;
2054 + }
2055 + else if (IS_RCV_LOR_ERR(devcs)) {
2056 + DBG(2, "RX LOR error\n");
2057 + lp->stats.rx_length_errors++;
2058 + }
2059 + else if (IS_RCV_LE_ERR(devcs)) {
2060 + DBG(2, "RX LE error\n");
2061 + lp->stats.rx_length_errors++;
2062 + }
2063 + else if (IS_RCV_OVR_ERR(devcs)) {
2064 + lp->stats.rx_over_errors++;
2065 + }
2066 + else if (IS_RCV_CV_ERR(devcs)) {
2067 + /* code violation */
2068 + DBG(2, "RX CV error\n");
2069 + lp->stats.rx_frame_errors++;
2070 + }
2071 + else if (IS_RCV_CES_ERR(devcs)) {
2072 + DBG(2, "RX Preamble error\n");
2073 + }
2074 + }
2075 +
2076 + rd->devcs = 0;
2077 +
2078 + /* restore descriptor's curr_addr */
2079 + if(skb_new)
2080 + rd->ca = CPHYSADDR(skb_new->data);
2081 + else
2082 + rd->ca = CPHYSADDR(skb->data);
2083 +
2084 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2085 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2086 +
2087 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2088 + rd = &lp->rd_ring[lp->rx_next_done];
2089 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2090 + }
2091 +#ifdef CONFIG_IDT_USE_NAPI
2092 + dev->quota -= received;
2093 + *budget =- received;
2094 + if(rx_work_limit < 0)
2095 + goto not_done;
2096 +#endif
2097 +
2098 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2099 +
2100 + if(dmas & DMAS_h_m) {
2101 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2102 +#ifdef RC32434_PROC_DEBUG
2103 + lp->dma_halt_cnt++;
2104 +#endif
2105 + rd->devcs = 0;
2106 + skb = lp->rx_skb[lp->rx_next_done];
2107 + rd->ca = CPHYSADDR(skb->data);
2108 + rc32434_chain_rx(lp,rd);
2109 + }
2110 +
2111 +#ifdef CONFIG_IDT_USE_NAPI
2112 + netif_rx_complete(dev);
2113 +#endif
2114 + /* Enable D H E bit in Rx DMA */
2115 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2116 +#ifdef CONFIG_IDT_USE_NAPI
2117 + return 0;
2118 + not_done:
2119 + return 1;
2120 +#else
2121 + spin_unlock_irqrestore(&lp->lock, flags);
2122 + return;
2123 +#endif
2124 +
2125 +
2126 +}
2127 +
2128 +
2129 +
2130 +/* Ethernet Tx DMA interrupt */
2131 +static irqreturn_t
2132 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2133 +{
2134 + struct net_device *dev = (struct net_device *)dev_id;
2135 + struct rc32434_local *lp;
2136 + volatile u32 dmas,dmasm;
2137 + irqreturn_t retval;
2138 +
2139 + ASSERT(dev != NULL);
2140 +
2141 + lp = (struct rc32434_local *)dev->priv;
2142 +
2143 + spin_lock(&lp->lock);
2144 +
2145 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2146 +
2147 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2148 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2149 + /* Mask F E bit in Tx DMA */
2150 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2151 +
2152 + tasklet_hi_schedule(lp->tx_tasklet);
2153 +
2154 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2155 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2156 + lp->tx_chain_status = empty;
2157 + lp->tx_chain_head = lp->tx_chain_tail;
2158 + dev->trans_start = jiffies;
2159 + }
2160 +
2161 + if (dmas & DMAS_e_m)
2162 + ERR(": DMA error\n");
2163 +
2164 + retval = IRQ_HANDLED;
2165 + }
2166 + else
2167 + retval = IRQ_NONE;
2168 +
2169 + spin_unlock(&lp->lock);
2170 +
2171 + return retval;
2172 +}
2173 +
2174 +
2175 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2176 +{
2177 + struct net_device *dev = (struct net_device *)tx_data_dev;
2178 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2179 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2180 + u32 devcs;
2181 + unsigned long flags;
2182 + volatile u32 dmas;
2183 +
2184 + spin_lock_irqsave(&lp->lock, flags);
2185 +
2186 + /* process all desc that are done */
2187 + while(IS_DMA_FINISHED(td->control)) {
2188 + if(lp->tx_full == 1) {
2189 + netif_wake_queue(dev);
2190 + lp->tx_full = 0;
2191 + }
2192 +
2193 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2194 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2195 + lp->stats.tx_errors++;
2196 + lp->stats.tx_dropped++;
2197 +
2198 + /* should never happen */
2199 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2200 + }
2201 + else if (IS_TX_TOK(devcs)) {
2202 + lp->stats.tx_packets++;
2203 + }
2204 + else {
2205 + lp->stats.tx_errors++;
2206 + lp->stats.tx_dropped++;
2207 +
2208 + /* underflow */
2209 + if (IS_TX_UND_ERR(devcs))
2210 + lp->stats.tx_fifo_errors++;
2211 +
2212 + /* oversized frame */
2213 + if (IS_TX_OF_ERR(devcs))
2214 + lp->stats.tx_aborted_errors++;
2215 +
2216 + /* excessive deferrals */
2217 + if (IS_TX_ED_ERR(devcs))
2218 + lp->stats.tx_carrier_errors++;
2219 +
2220 + /* collisions: medium busy */
2221 + if (IS_TX_EC_ERR(devcs))
2222 + lp->stats.collisions++;
2223 +
2224 + /* late collision */
2225 + if (IS_TX_LC_ERR(devcs))
2226 + lp->stats.tx_window_errors++;
2227 +
2228 + }
2229 +
2230 + /* We must always free the original skb */
2231 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2232 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2233 + lp->tx_skb[lp->tx_next_done] = NULL;
2234 + }
2235 +
2236 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2237 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2238 + lp->td_ring[lp->tx_next_done].link = 0;
2239 + lp->td_ring[lp->tx_next_done].ca = 0;
2240 + lp->tx_count --;
2241 +
2242 + /* go on to next transmission */
2243 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2244 + td = &lp->td_ring[lp->tx_next_done];
2245 +
2246 + }
2247 +
2248 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2249 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2250 +
2251 + /* Enable F E bit in Tx DMA */
2252 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2253 + spin_unlock_irqrestore(&lp->lock, flags);
2254 +
2255 +}
2256 +
2257 +
2258 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2259 +{
2260 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2261 + return &lp->stats;
2262 +}
2263 +
2264 +
2265 +/*
2266 + * Set or clear the multicast filter for this adaptor.
2267 + */
2268 +static void rc32434_multicast_list(struct net_device *dev)
2269 +{
2270 + /* listen to broadcasts always and to treat */
2271 + /* IFF bits independantly */
2272 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2273 + unsigned long flags;
2274 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2275 +
2276 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2277 + recognise |= ETHARC_pro_m;
2278 +
2279 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2280 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2281 + else if (dev->mc_count > 0) {
2282 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2283 + recognise |= ETHARC_am_m; /* for the time being */
2284 + }
2285 +
2286 + spin_lock_irqsave(&lp->lock, flags);
2287 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2288 + spin_unlock_irqrestore(&lp->lock, flags);
2289 +}
2290 +
2291 +
2292 +static void rc32434_tx_timeout(struct net_device *dev)
2293 +{
2294 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2295 + unsigned long flags;
2296 +
2297 + spin_lock_irqsave(&lp->lock, flags);
2298 + rc32434_restart(dev);
2299 + spin_unlock_irqrestore(&lp->lock, flags);
2300 +
2301 +}
2302 +
2303 +
2304 +/*
2305 + * Initialize the RC32434 ethernet controller.
2306 + */
2307 +static int rc32434_init(struct net_device *dev)
2308 +{
2309 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2310 + int i, j;
2311 +
2312 + /* Disable DMA */
2313 + rc32434_abort_tx(dev);
2314 + rc32434_abort_rx(dev);
2315 +
2316 + /* reset ethernet logic */
2317 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2318 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2319 + dev->trans_start = jiffies;
2320 +
2321 + /* Enable Ethernet Interface */
2322 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2323 +
2324 +#ifndef CONFIG_IDT_USE_NAPI
2325 + tasklet_disable(lp->rx_tasklet);
2326 +#endif
2327 + tasklet_disable(lp->tx_tasklet);
2328 +
2329 + /* Initialize the transmit Descriptors */
2330 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2331 + lp->td_ring[i].control = DMAD_iof_m;
2332 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2333 + lp->td_ring[i].ca = 0;
2334 + lp->td_ring[i].link = 0;
2335 + if (lp->tx_skb[i] != NULL) {
2336 + dev_kfree_skb_any(lp->tx_skb[i]);
2337 + lp->tx_skb[i] = NULL;
2338 + }
2339 + }
2340 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2341 + lp-> tx_chain_status = empty;
2342 +
2343 + /*
2344 + * Initialize the receive descriptors so that they
2345 + * become a circular linked list, ie. let the last
2346 + * descriptor point to the first again.
2347 + */
2348 + for (i=0; i<RC32434_NUM_RDS; i++) {
2349 + struct sk_buff *skb = lp->rx_skb[i];
2350 +
2351 + if (lp->rx_skb[i] == NULL) {
2352 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2353 + if (skb == NULL) {
2354 + ERR("No memory in the system\n");
2355 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2356 + if (lp->rx_skb[j] != NULL)
2357 + dev_kfree_skb_any(lp->rx_skb[j]);
2358 +
2359 + return 1;
2360 + }
2361 + else {
2362 + skb->dev = dev;
2363 + skb_reserve(skb, 2);
2364 + lp->rx_skb[i] = skb;
2365 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2366 +
2367 + }
2368 + }
2369 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2370 + lp->rd_ring[i].devcs = 0;
2371 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2372 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2373 +
2374 + }
2375 + /* loop back */
2376 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2377 + lp->rx_next_done = 0;
2378 +
2379 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2380 + lp->rx_chain_head = 0;
2381 + lp->rx_chain_tail = 0;
2382 + lp->rx_chain_status = empty;
2383 +
2384 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2385 + /* Start Rx DMA */
2386 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2387 +
2388 + /* Enable F E bit in Tx DMA */
2389 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2390 + /* Enable D H E bit in Rx DMA */
2391 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2392 +
2393 + /* Accept only packets destined for this Ethernet device address */
2394 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2395 +
2396 + /* Set all Ether station address registers to their initial values */
2397 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2398 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2399 +
2400 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2401 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2402 +
2403 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2404 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2405 +
2406 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2407 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2408 +
2409 +
2410 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2411 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2412 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2413 +
2414 + /* Back to back inter-packet-gap */
2415 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2416 + /* Non - Back to back inter-packet-gap */
2417 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2418 +
2419 + /* Management Clock Prescaler Divisor */
2420 + /* Clock independent setting */
2421 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2422 + &lp->eth_regs->ethmcp);
2423 +
2424 + /* don't transmit until fifo contains 48b */
2425 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2426 +
2427 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2428 +
2429 +#ifndef CONFIG_IDT_USE_NAPI
2430 + tasklet_enable(lp->rx_tasklet);
2431 +#endif
2432 + tasklet_enable(lp->tx_tasklet);
2433 +
2434 + netif_start_queue(dev);
2435 +
2436 +
2437 + return 0;
2438 +
2439 +}
2440 +
2441 +
2442 +#ifndef MODULE
2443 +
2444 +static int __init rc32434_setup(char *options)
2445 +{
2446 + /* no options yet */
2447 + return 1;
2448 +}
2449 +
2450 +static int __init rc32434_setup_ethaddr0(char *options)
2451 +{
2452 + memcpy(mac0, options, 17);
2453 + mac0[17]= '\0';
2454 + return 1;
2455 +}
2456 +
2457 +__setup("rc32434eth=", rc32434_setup);
2458 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2459 +
2460 +
2461 +#endif /* MODULE */
2462 +
2463 +module_init(rc32434_init_module);
2464 +module_exit(rc32434_cleanup_module);
2465 +
2466 +
2467 +
2468 +
2469 +
2470 +
2471 +
2472 +
2473 +
2474 +
2475 +
2476 +
2477 +
2478 +
2479 diff -Nur linux-2.6.17/drivers/net/rc32434_eth.h linux-2.6.17-owrt/drivers/net/rc32434_eth.h
2480 --- linux-2.6.17/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2481 +++ linux-2.6.17-owrt/drivers/net/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
2482 @@ -0,0 +1,187 @@
2483 +/**************************************************************************
2484 + *
2485 + * BRIEF MODULE DESCRIPTION
2486 + * Definitions for IDT RC32434 on-chip ethernet controller.
2487 + *
2488 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2489 + *
2490 + * This program is free software; you can redistribute it and/or modify it
2491 + * under the terms of the GNU General Public License as published by the
2492 + * Free Software Foundation; either version 2 of the License, or (at your
2493 + * option) any later version.
2494 + *
2495 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2496 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2497 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2498 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2499 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2500 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2501 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2502 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2503 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2504 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2505 + *
2506 + * You should have received a copy of the GNU General Public License along
2507 + * with this program; if not, write to the Free Software Foundation, Inc.,
2508 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2509 + *
2510 + *
2511 + **************************************************************************
2512 + * May 2004 rkt, neb
2513 + *
2514 + * Initial Release
2515 + *
2516 + * Aug 2004
2517 + *
2518 + * Added NAPI
2519 + *
2520 + **************************************************************************
2521 + */
2522 +
2523 +
2524 +#include <asm/idt-boards/rc32434/rc32434.h>
2525 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2526 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2527 +
2528 +#define RC32434_DEBUG 2
2529 +//#define RC32434_PROC_DEBUG
2530 +#undef RC32434_DEBUG
2531 +
2532 +#ifdef RC32434_DEBUG
2533 +
2534 +/* use 0 for production, 1 for verification, >2 for debug */
2535 +static int rc32434_debug = RC32434_DEBUG;
2536 +#define ASSERT(expr) \
2537 + if(!(expr)) { \
2538 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2539 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2540 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2541 +#else
2542 +#define ASSERT(expr) do {} while (0)
2543 +#define DBG(lvl, format, arg...) do {} while (0)
2544 +#endif
2545 +
2546 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2547 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2548 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2549 +
2550 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2551 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2552 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2553 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2554 +
2555 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2556 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2557 +
2558 +/* the following must be powers of two */
2559 +#ifdef CONFIG_IDT_USE_NAPI
2560 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2561 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2562 +#else
2563 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2564 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2565 +#endif
2566 +
2567 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2568 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2569 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2570 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2571 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2572 +
2573 +#define RC32434_TX_TIMEOUT HZ * 100
2574 +
2575 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2576 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2577 +
2578 +enum status { filled, empty};
2579 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2580 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2581 +
2582 +
2583 +/* Information that need to be kept for each board. */
2584 +struct rc32434_local {
2585 + ETH_t eth_regs;
2586 + DMA_Chan_t rx_dma_regs;
2587 + DMA_Chan_t tx_dma_regs;
2588 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2589 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2590 +
2591 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2592 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2593 +
2594 +#ifndef CONFIG_IDT_USE_NAPI
2595 + struct tasklet_struct * rx_tasklet;
2596 +#endif
2597 + struct tasklet_struct * tx_tasklet;
2598 +
2599 + int rx_next_done;
2600 + int rx_chain_head;
2601 + int rx_chain_tail;
2602 + enum status rx_chain_status;
2603 +
2604 + int tx_next_done;
2605 + int tx_chain_head;
2606 + int tx_chain_tail;
2607 + enum status tx_chain_status;
2608 + int tx_count;
2609 + int tx_full;
2610 +
2611 + struct timer_list mii_phy_timer;
2612 + unsigned long duplex_mode;
2613 +
2614 + int rx_irq;
2615 + int tx_irq;
2616 + int ovr_irq;
2617 + int und_irq;
2618 +
2619 + struct net_device_stats stats;
2620 + spinlock_t lock;
2621 +
2622 + /* debug /proc entry */
2623 + struct proc_dir_entry *ps;
2624 + int dma_halt_cnt; int dma_run_cnt;
2625 +};
2626 +
2627 +extern unsigned int idt_cpu_freq;
2628 +
2629 +/* Index to functions, as function prototypes. */
2630 +static int rc32434_open(struct net_device *dev);
2631 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2632 +static void rc32434_mii_handler(unsigned long data);
2633 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2634 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2635 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2636 +#ifdef RC32434_REVISION
2637 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2638 +#endif
2639 +static int rc32434_close(struct net_device *dev);
2640 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2641 +static void rc32434_multicast_list(struct net_device *dev);
2642 +static int rc32434_init(struct net_device *dev);
2643 +static void rc32434_tx_timeout(struct net_device *dev);
2644 +
2645 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2646 +#ifdef CONFIG_IDT_USE_NAPI
2647 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2648 +#else
2649 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2650 +#endif
2651 +static void rc32434_cleanup_module(void);
2652 +static int rc32434_probe(int port_num);
2653 +int rc32434_init_module(void);
2654 +
2655 +
2656 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2657 +{
2658 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2659 + rc32434_writel(0x10, &ch->dmac);
2660 +
2661 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2662 + dev->trans_start = jiffies;
2663 +
2664 + rc32434_writel(0, &ch->dmas);
2665 + }
2666 +
2667 + rc32434_writel(0, &ch->dmadptr);
2668 + rc32434_writel(0, &ch->dmandptr);
2669 +}
2670 diff -Nur linux-2.6.17/include/asm-mips/bootinfo.h linux-2.6.17-owrt/include/asm-mips/bootinfo.h
2671 --- linux-2.6.17/include/asm-mips/bootinfo.h 2006-06-18 03:49:35.000000000 +0200
2672 +++ linux-2.6.17-owrt/include/asm-mips/bootinfo.h 2006-06-18 12:44:28.000000000 +0200
2673 @@ -218,6 +218,17 @@
2674 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2675 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2676
2677 +
2678 +/*
2679 + * Valid machtype for group ARUBA
2680 + */
2681 +#define MACH_GROUP_ARUBA 23
2682 +#define MACH_ARUBA_UNKNOWN 0
2683 +#define MACH_ARUBA_AP60 1
2684 +#define MACH_ARUBA_AP65 2
2685 +#define MACH_ARUBA_AP70 3
2686 +#define MACH_ARUBA_AP40 4
2687 +
2688 #define CL_SIZE COMMAND_LINE_SIZE
2689
2690 const char *get_system_type(void);
2691 diff -Nur linux-2.6.17/include/asm-mips/cpu.h linux-2.6.17-owrt/include/asm-mips/cpu.h
2692 --- linux-2.6.17/include/asm-mips/cpu.h 2006-06-18 03:49:35.000000000 +0200
2693 +++ linux-2.6.17-owrt/include/asm-mips/cpu.h 2006-06-18 12:45:56.000000000 +0200
2694 @@ -54,6 +54,9 @@
2695 #define PRID_IMP_R14000 0x0f00
2696 #define PRID_IMP_R8000 0x1000
2697 #define PRID_IMP_PR4450 0x1200
2698 +#define PRID_IMP_RC32334 0x1800
2699 +#define PRID_IMP_RC32355 0x1900
2700 +#define PRID_IMP_RC32365 0x1900
2701 #define PRID_IMP_R4600 0x2000
2702 #define PRID_IMP_R4700 0x2100
2703 #define PRID_IMP_TX39 0x2200
2704 @@ -200,7 +203,8 @@
2705 #define CPU_SB1A 62
2706 #define CPU_74K 63
2707 #define CPU_R14000 64
2708 -#define CPU_LAST 64
2709 +#define CPU_RC32300 65
2710 +#define CPU_LAST 65
2711
2712 /*
2713 * ISA Level encodings
2714 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2715 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2716 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-06-18 12:44:28.000000000 +0200
2717 @@ -0,0 +1,142 @@
2718 +/**************************************************************************
2719 + *
2720 + * BRIEF MODULE DESCRIPTION
2721 + * RC32300 helper routines
2722 + *
2723 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2724 + *
2725 + * This program is free software; you can redistribute it and/or modify it
2726 + * under the terms of the GNU General Public License as published by the
2727 + * Free Software Foundation; either version 2 of the License, or (at your
2728 + * option) any later version.
2729 + *
2730 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2731 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2732 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2733 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2734 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2735 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2736 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2737 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2738 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2739 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2740 + *
2741 + * You should have received a copy of the GNU General Public License along
2742 + * with this program; if not, write to the Free Software Foundation, Inc.,
2743 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2744 + *
2745 + *
2746 + **************************************************************************
2747 + * May 2004 P. Sadik.
2748 + *
2749 + * Initial Release
2750 + *
2751 + *
2752 + *
2753 + **************************************************************************
2754 + */
2755 +
2756 +#ifndef __IDT_RC32300_H__
2757 +#define __IDT_RC32300_H__
2758 +
2759 +#include <linux/delay.h>
2760 +#include <asm/io.h>
2761 +
2762 +
2763 +/* cpu pipeline flush */
2764 +static inline void rc32300_sync(void)
2765 +{
2766 + __asm__ volatile ("sync");
2767 +}
2768 +
2769 +static inline void rc32300_sync_udelay(int us)
2770 +{
2771 + __asm__ volatile ("sync");
2772 + udelay(us);
2773 +}
2774 +
2775 +static inline void rc32300_sync_delay(int ms)
2776 +{
2777 + __asm__ volatile ("sync");
2778 + mdelay(ms);
2779 +}
2780 +
2781 +/*
2782 + * Macros to access internal RC32300 registers. No byte
2783 + * swapping should be done when accessing the internal
2784 + * registers.
2785 + */
2786 +
2787 +static inline u8 rc32300_readb(unsigned long pa)
2788 +{
2789 + return *((volatile u8 *)KSEG1ADDR(pa));
2790 +}
2791 +static inline u16 rc32300_readw(unsigned long pa)
2792 +{
2793 + return *((volatile u16 *)KSEG1ADDR(pa));
2794 +}
2795 +static inline u32 rc32300_readl(unsigned long pa)
2796 +{
2797 + return *((volatile u32 *)KSEG1ADDR(pa));
2798 +}
2799 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2800 +{
2801 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2802 +}
2803 +static inline void rc32300_writew(u16 val, unsigned long pa)
2804 +{
2805 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2806 +}
2807 +static inline void rc32300_writel(u32 val, unsigned long pa)
2808 +{
2809 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2810 +}
2811 +
2812 +
2813 +#define local_readb __raw_readb
2814 +#define local_readw __raw_readw
2815 +#define local_readl __raw_readl
2816 +
2817 +#define local_writeb __raw_writeb
2818 +#define local_writew __raw_writew
2819 +#define local_writel __raw_writel
2820 +
2821 +
2822 +/*
2823 + * C access to CLZ and CLO instructions
2824 + * (count leading zeroes/ones).
2825 + */
2826 +static inline int rc32300_clz(unsigned long val)
2827 +{
2828 + int ret;
2829 + __asm__ volatile (
2830 + ".set\tnoreorder\n\t"
2831 + ".set\tnoat\n\t"
2832 + ".set\tmips32\n\t"
2833 + "clz\t%0,%1\n\t"
2834 + ".set\tmips0\n\t"
2835 + ".set\tat\n\t"
2836 + ".set\treorder"
2837 + : "=r" (ret)
2838 + : "r" (val));
2839 +
2840 + return ret;
2841 +}
2842 +static inline int rc32300_clo(unsigned long val)
2843 +{
2844 + int ret;
2845 + __asm__ volatile (
2846 + ".set\tnoreorder\n\t"
2847 + ".set\tnoat\n\t"
2848 + ".set\tmips32\n\t"
2849 + "clo\t%0,%1\n\t"
2850 + ".set\tmips0\n\t"
2851 + ".set\tat\n\t"
2852 + ".set\treorder"
2853 + : "=r" (ret)
2854 + : "r" (val));
2855 +
2856 + return ret;
2857 +}
2858 +
2859 +#endif // __IDT_RC32300_H__
2860 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2861 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2862 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-06-18 12:44:28.000000000 +0200
2863 @@ -0,0 +1,207 @@
2864 +/**************************************************************************
2865 + *
2866 + * BRIEF MODULE DESCRIPTION
2867 + * Definitions for IDT RC32334 CPU.
2868 + *
2869 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2870 + *
2871 + * This program is free software; you can redistribute it and/or modify it
2872 + * under the terms of the GNU General Public License as published by the
2873 + * Free Software Foundation; either version 2 of the License, or (at your
2874 + * option) any later version.
2875 + *
2876 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2877 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2878 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2879 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2880 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2881 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2882 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2883 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2884 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2885 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2886 + *
2887 + * You should have received a copy of the GNU General Public License along
2888 + * with this program; if not, write to the Free Software Foundation, Inc.,
2889 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2890 + *
2891 + *
2892 + **************************************************************************
2893 + * May 2004 P. Sadik.
2894 + *
2895 + * Initial Release
2896 + *
2897 + *
2898 + *
2899 + **************************************************************************
2900 + */
2901 +
2902 +
2903 +#ifndef __IDT_RC32334_H__
2904 +#define __IDT_RC32334_H__
2905 +
2906 +#include <linux/delay.h>
2907 +#include <asm/io.h>
2908 +
2909 +/* Base address of internal registers */
2910 +#define RC32334_REG_BASE 0x18000000
2911 +
2912 +/* CPU and IP Bus Control */
2913 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2914 +#define CPU_BTA 0xffffe204 // virtual!
2915 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2916 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2917 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2918 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2919 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2920 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2921 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2922 +
2923 +/* Memory Controller */
2924 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2925 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2926 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2927 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2928 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2929 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2930 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2931 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2932 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2933 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2934 +
2935 +/* PCI Controller */
2936 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2937 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2938 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2939 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2940 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2941 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2942 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2943 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2944 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2945 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2946 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2947 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2948 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2949 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2950 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2951 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2952 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2953 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2954 +
2955 +/* Timers */
2956 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2957 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2958 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2959 +#define TIMER_REG_OFFSET 0x10
2960 +
2961 +/* Programmable I/O */
2962 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2963 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2964 +
2965 +/*
2966 + * DMA
2967 + *
2968 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2969 + *
2970 + * DMA0: 18001400
2971 + * DMA1: 18001440
2972 + * DMA2: 18001900
2973 + * DMA3: 18001940
2974 + * NB: dma number must be immediate value or variable.
2975 + * It MUST NOT be a function since it would get called twice!
2976 + */
2977 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2978 +
2979 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2980 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2981 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2982 +
2983 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2984 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2985 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2986 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2987 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2988 +
2989 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2990 +
2991 +/* Expansion Interrupt Controller */
2992 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2993 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2994 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2995 +#define IC_GROUP_OFFSET 0x10
2996 +
2997 +#define NUM_INTR_GROUPS 15
2998 +/*
2999 + * The IRQ mapping is as follows:
3000 + *
3001 + * IRQ Mapped To
3002 + * --- -------------------
3003 + * 0 SW0 (IP0) SW0 intr
3004 + * 1 SW1 (IP1) SW1 intr
3005 + * 2 Int0 (IP2) board-specific
3006 + * 3 Int1 (IP3) board-specific
3007 + * 4 Int2 (IP4) board-specific
3008 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
3009 + * 6 Int4 (IP6) board-specific
3010 + * 7 Int5 (IP7) CP0 Timer
3011 + *
3012 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
3013 + * internally on the RC32334 is routed to the Expansion
3014 + * Interrupt Controller.
3015 + */
3016 +#define MIPS_CPU_TIMER_IRQ 7
3017 +
3018 +#define GROUP1_IRQ_BASE 8 // bus error
3019 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3020 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3021 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3022 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3023 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3024 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3025 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3026 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3027 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3028 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3029 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3030 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3031 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3032 +
3033 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3034 +
3035 +/* 16550 UARTs */
3036 +#ifdef __MIPSEB__
3037 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3038 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3039 +#else
3040 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3041 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3042 +#endif
3043 +
3044 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3045 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3046 +
3047 +#define IDT_CLOCK_MULT 2
3048 +
3049 +/* NVRAM */
3050 +#define NVRAM_BASE 0x12000000
3051 +#define NVRAM_ENVSIZE_OFF 4
3052 +#define NVRAM_ENVSTART_OFF 0x40
3053 +
3054 +/* LCD 4-digit display */
3055 +#define LCD_CLEAR 0x14000400
3056 +#define LCD_DIGIT0 0x1400000f
3057 +#define LCD_DIGIT1 0x14000008
3058 +#define LCD_DIGIT2 0x14000007
3059 +#define LCD_DIGIT3 0x14000003
3060 +
3061 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3062 +#define RC32334_SCC8530_IRQ 2
3063 +#define RC32334_PCI_INTA_IRQ 3
3064 +#define RC32334_PCI_INTB_IRQ 4
3065 +#define RC32334_PCI_INTC_IRQ 6
3066 +#define RC32334_PCI_INTD_IRQ 7
3067 +
3068 +#define RAM_SIZE (32*1024*1024)
3069 +
3070 +#endif // __IDT_RC32334_H__
3071 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3072 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3073 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-06-18 12:44:28.000000000 +0200
3074 @@ -0,0 +1,206 @@
3075 +/**************************************************************************
3076 + *
3077 + * BRIEF MODULE DESCRIPTION
3078 + * DMA controller defines on IDT RC32355
3079 + *
3080 + * Copyright 2004 IDT Inc.
3081 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3082 + *
3083 + *
3084 + * This program is free software; you can redistribute it and/or modify it
3085 + * under the terms of the GNU General Public License as published by the
3086 + * Free Software Foundation; either version 2 of the License, or (at your
3087 + * option) any later version.
3088 + *
3089 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3090 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3091 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3092 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3093 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3094 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3095 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3096 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3097 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3098 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3099 + *
3100 + * You should have received a copy of the GNU General Public License along
3101 + * with this program; if not, write to the Free Software Foundation, Inc.,
3102 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3103 + *
3104 + *
3105 + * May 2004 rkt
3106 + * Initial Release
3107 + *
3108 + **************************************************************************
3109 + */
3110 +
3111 +#ifndef BANYAN_DMA_H
3112 +#define BANYAN_DMA_H
3113 +#include <asm/idt-boards/rc32300/rc32300.h>
3114 +
3115 +/*
3116 + * An image of one RC32355 dma channel registers
3117 + */
3118 +typedef struct {
3119 + u32 dmac;
3120 + u32 dmas;
3121 + u32 dmasm;
3122 + u32 dmadptr;
3123 + u32 dmandptr;
3124 +} rc32355_dma_ch_t;
3125 +
3126 +/*
3127 + * An image of all RC32355 dma channel registers
3128 + */
3129 +typedef struct {
3130 + rc32355_dma_ch_t ch[16];
3131 +} rc32355_dma_regs_t;
3132 +
3133 +
3134 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3135 +
3136 +
3137 +/* DMAC register layout */
3138 +
3139 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3140 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3141 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3142 +
3143 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3144 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3145 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3146 +
3147 +/* DMAS and DMASM register layout */
3148 +
3149 +#define DMAS_F 0x01 /* Finished */
3150 +#define DMAS_D 0x02 /* Done */
3151 +#define DMAS_C 0x04 /* Chain */
3152 +#define DMAS_E 0x08 /* Error */
3153 +#define DMAS_H 0x10 /* Halt */
3154 +
3155 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3156 +#define DMA_HALT_TIMEOUT 500
3157 +
3158 +
3159 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3160 +{
3161 + int timeout=1;
3162 +
3163 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3164 + local_writel(0, &ch->dmac);
3165 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3166 + if (local_readl(&ch->dmas) & DMAS_H) {
3167 + local_writel(0, &ch->dmas);
3168 + break;
3169 + }
3170 + }
3171 + }
3172 +
3173 + return timeout ? 0 : 1;
3174 +}
3175 +
3176 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3177 +{
3178 + local_writel(0, &ch->dmandptr);
3179 + local_writel(dma_addr, &ch->dmadptr);
3180 +}
3181 +
3182 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3183 +{
3184 + local_writel(dma_addr, &ch->dmandptr);
3185 +}
3186 +
3187 +
3188 +/* The following can be used to describe DMA channels 0 to 15, and the */
3189 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3190 +
3191 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3192 +
3193 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3194 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3195 +
3196 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3197 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3198 +
3199 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3200 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3201 +
3202 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3203 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3204 +
3205 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3206 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3207 +#define DMA_DEV_ATMVCC(entry) 0
3208 +
3209 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3210 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3211 +
3212 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3213 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3214 +
3215 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3216 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3217 +
3218 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3219 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3220 +
3221 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3222 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3223 +
3224 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3225 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3226 +
3227 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3228 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3229 +
3230 +#define DMA_CHAN_USBIN 13 /* USB input */
3231 +#define DMA_DEV_USBIN 0 /* USB input */
3232 +
3233 +#define DMA_CHAN_USBOUT 14 /* USB output */
3234 +#define DMA_DEV_USBOUT 0 /* USB output */
3235 +
3236 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3237 +#define DMA_DEV_EXTERN 0 /* External DMA */
3238 +
3239 +/*
3240 + * An RC32355 dma descriptor in system memory
3241 + */
3242 +typedef struct {
3243 + u32 cmdstat; /* control and status */
3244 + u32 curr_addr; /* current address of data */
3245 + u32 devcs; /* peripheral-specific control and status */
3246 + u32 link; /* link to next descriptor */
3247 +} rc32355_dma_desc_t;
3248 +
3249 +/* Values for the descriptor cmdstat word */
3250 +
3251 +#define DMADESC_F 0x80000000u /* Finished bit */
3252 +#define DMADESC_D 0x40000000u /* Done bit */
3253 +#define DMADESC_T 0x20000000u /* Terminated bit */
3254 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3255 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3256 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3257 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3258 +
3259 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3260 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3261 +
3262 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3263 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3264 +
3265 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3266 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3267 +
3268 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3269 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3270 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3271 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3272 +
3273 +#define DMA_DEVCMD(devcmd) \
3274 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3275 +#define DMA_DS(ds) \
3276 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3277 +#define DMA_COUNT(count) \
3278 + ((count) & DMADESC_COUNT_MASK)
3279 +
3280 +#endif /* RC32355_DMA_H */
3281 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3282 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3283 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-06-18 12:44:28.000000000 +0200
3284 @@ -0,0 +1,442 @@
3285 +/**************************************************************************
3286 + *
3287 + * BRIEF MODULE DESCRIPTION
3288 + * Ethernet registers on IDT RC32355
3289 + *
3290 + * Copyright 2004 IDT Inc.
3291 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3292 + *
3293 + *
3294 + * This program is free software; you can redistribute it and/or modify it
3295 + * under the terms of the GNU General Public License as published by the
3296 + * Free Software Foundation; either version 2 of the License, or (at your
3297 + * option) any later version.
3298 + *
3299 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3300 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3301 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3302 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3303 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3304 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3305 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3306 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3307 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3308 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3309 + *
3310 + * You should have received a copy of the GNU General Public License along
3311 + * with this program; if not, write to the Free Software Foundation, Inc.,
3312 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3313 + *
3314 + *
3315 + * May 2004 rkt
3316 + * Initial Release
3317 + *
3318 + **************************************************************************
3319 + */
3320 +
3321 +
3322 +#ifndef RC32355_ETHER_H
3323 +#define RC32355_ETHER_H
3324 +
3325 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3326 +
3327 +/*
3328 + * A partial image of the RC32355 ethernet registers
3329 + */
3330 +typedef struct {
3331 + u32 ethintfc;
3332 + u32 ethfifott;
3333 + u32 etharc;
3334 + u32 ethhash0;
3335 + u32 ethhash1;
3336 + u32 ethfifost;
3337 + u32 ethfifos;
3338 + u32 ethodeops;
3339 + u32 ethis;
3340 + u32 ethos;
3341 + u32 ethmcp;
3342 + u32 _u1;
3343 + u32 ethid;
3344 + u32 _u2;
3345 + u32 _u3;
3346 + u32 _u4;
3347 + u32 ethod;
3348 + u32 _u5;
3349 + u32 _u6;
3350 + u32 _u7;
3351 + u32 ethodeop;
3352 + u32 _u8[43];
3353 + u32 ethsal0;
3354 + u32 ethsah0;
3355 + u32 ethsal1;
3356 + u32 ethsah1;
3357 + u32 ethsal2;
3358 + u32 ethsah2;
3359 + u32 ethsal3;
3360 + u32 ethsah3;
3361 + u32 ethrbc;
3362 + u32 ethrpc;
3363 + u32 ethrupc;
3364 + u32 ethrfc;
3365 + u32 ethtbc;
3366 + u32 ethgpf;
3367 + u32 _u9[50];
3368 + u32 ethmac1;
3369 + u32 ethmac2;
3370 + u32 ethipgt;
3371 + u32 ethipgr;
3372 + u32 ethclrt;
3373 + u32 ethmaxf;
3374 + u32 _u10;
3375 + u32 ethmtest;
3376 + u32 miimcfg;
3377 + u32 miimcmd;
3378 + u32 miimaddr;
3379 + u32 miimwtd;
3380 + u32 miimrdd;
3381 + u32 miimind;
3382 + u32 _u11;
3383 + u32 _u12;
3384 + u32 ethcfsa0;
3385 + u32 ethcfsa1;
3386 + u32 ethcfsa2;
3387 +} rc32355_eth_regs_t;
3388 +
3389 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3390 +
3391 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3392 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3393 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3394 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3395 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3396 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3397 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3398 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3399 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3400 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3401 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3402 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3403 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3404 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3405 +
3406 +/* for n in { 0, 1, 2, 3 } */
3407 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3408 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3409 +
3410 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3411 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3412 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3413 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3414 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3415 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3416 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3417 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3418 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3419 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3420 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3421 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3422 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3423 +
3424 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3425 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3426 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3427 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3428 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3429 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3430 +
3431 +/* for n in { 0, 1, 2 } */
3432 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3433 +
3434 +
3435 +/*
3436 + * Register Interpretations follow
3437 + */
3438 +
3439 +/******************************************************************************
3440 + * ETHINTFC register
3441 + *****************************************************************************/
3442 +
3443 +#define ETHERINTFC_EN (1<<0)
3444 +#define ETHERINTFC_ITS (1<<1)
3445 +#define ETHERINTFC_RES (1<<2)
3446 +#define ETHERINTFC_RIP (1<<2)
3447 +#define ETHERINTFC_JAM (1<<3)
3448 +
3449 +/******************************************************************************
3450 + * ETHFIFOTT register
3451 + *****************************************************************************/
3452 +
3453 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3454 +
3455 +/******************************************************************************
3456 + * ETHARC register
3457 + *****************************************************************************/
3458 +
3459 +#define ETHERARC_PRO (1<<0)
3460 +#define ETHERARC_AM (1<<1)
3461 +#define ETHERARC_AFM (1<<2)
3462 +#define ETHERARC_AB (1<<3)
3463 +
3464 +/******************************************************************************
3465 + * ETHHASH registers
3466 + *****************************************************************************/
3467 +
3468 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3469 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3470 +
3471 +/******************************************************************************
3472 + * ETHSA registers
3473 + *****************************************************************************/
3474 +
3475 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3476 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3477 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3478 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3479 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3480 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3481 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3482 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3483 +
3484 +/******************************************************************************
3485 + * ETHFIFOST register
3486 + *****************************************************************************/
3487 +
3488 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3489 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3490 +
3491 +/******************************************************************************
3492 + * ETHFIFOS register
3493 + *****************************************************************************/
3494 +
3495 +#define ETHERFIFOS_IR (1<<0)
3496 +#define ETHERFIFOS_OR (1<<1)
3497 +#define ETHERFIFOS_OVR (1<<2)
3498 +#define ETHERFIFOS_UND (1<<3)
3499 +
3500 +/******************************************************************************
3501 + * DATA registers
3502 + *****************************************************************************/
3503 +
3504 +#define ETHERID(v) (((v)&0xffff)<<0)
3505 +#define ETHEROD(v) (((v)&0xffff)<<0)
3506 +
3507 +/******************************************************************************
3508 + * ETHODEOPS register
3509 + *****************************************************************************/
3510 +
3511 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3512 +
3513 +/******************************************************************************
3514 + * ETHODEOP register
3515 + *****************************************************************************/
3516 +
3517 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3518 +
3519 +/******************************************************************************
3520 + * ETHIS register
3521 + *****************************************************************************/
3522 +
3523 +#define ETHERIS_EOP (1<<0)
3524 +#define ETHERIS_ROK (1<<2)
3525 +#define ETHERIS_FM (1<<3)
3526 +#define ETHERIS_MP (1<<4)
3527 +#define ETHERIS_BP (1<<5)
3528 +#define ETHERIS_VLT (1<<6)
3529 +#define ETHERIS_CF (1<<7)
3530 +#define ETHERIS_OVR (1<<8)
3531 +#define ETHERIS_CRC (1<<9)
3532 +#define ETHERIS_CV (1<<10)
3533 +#define ETHERIS_DB (1<<11)
3534 +#define ETHERIS_LE (1<<12)
3535 +#define ETHERIS_LOR (1<<13)
3536 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3537 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3538 +
3539 +/******************************************************************************
3540 + * ETHOS register
3541 + *****************************************************************************/
3542 +
3543 +#define ETHEROS_T (1<<0)
3544 +#define ETHEROS_TOK (1<<6)
3545 +#define ETHEROS_MP (1<<7)
3546 +#define ETHEROS_BP (1<<8)
3547 +#define ETHEROS_UND (1<<9)
3548 +#define ETHEROS_OF (1<<10)
3549 +#define ETHEROS_ED (1<<11)
3550 +#define ETHEROS_EC (1<<12)
3551 +#define ETHEROS_LC (1<<13)
3552 +#define ETHEROS_TD (1<<14)
3553 +#define ETHEROS_CRC (1<<15)
3554 +#define ETHEROS_LE (1<<16)
3555 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3556 +#define ETHEROS_PFD (1<<21)
3557 +
3558 +/******************************************************************************
3559 + * Statistics registers
3560 + *****************************************************************************/
3561 +
3562 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3563 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3564 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3565 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3566 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3567 +
3568 +/******************************************************************************
3569 + * ETHGPF register
3570 + *****************************************************************************/
3571 +
3572 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3573 +
3574 +/******************************************************************************
3575 + * MAC registers
3576 + *****************************************************************************/
3577 +//ETHMAC1
3578 +#define ETHERMAC1_RE (1<<0)
3579 +#define ETHERMAC1_PAF (1<<1)
3580 +#define ETHERMAC1_RFC (1<<2)
3581 +#define ETHERMAC1_TFC (1<<3)
3582 +#define ETHERMAC1_LB (1<<4)
3583 +#define ETHERMAC1_MR (1<<15)
3584 +
3585 +//ETHMAC2
3586 +#define ETHERMAC2_FD (1<<0)
3587 +#define ETHERMAC2_FLC (1<<1)
3588 +#define ETHERMAC2_HFE (1<<2)
3589 +#define ETHERMAC2_DC (1<<3)
3590 +#define ETHERMAC2_CEN (1<<4)
3591 +#define ETHERMAC2_PE (1<<5)
3592 +#define ETHERMAC2_VPE (1<<6)
3593 +#define ETHERMAC2_APE (1<<7)
3594 +#define ETHERMAC2_PPE (1<<8)
3595 +#define ETHERMAC2_LPE (1<<9)
3596 +#define ETHERMAC2_NB (1<<12)
3597 +#define ETHERMAC2_BP (1<<13)
3598 +#define ETHERMAC2_ED (1<<14)
3599 +
3600 +//ETHIPGT
3601 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3602 +
3603 +//ETHIPGR
3604 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3605 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3606 +
3607 +//ETHCLRT
3608 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3609 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3610 +
3611 +//ETHMAXF
3612 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3613 +
3614 +//ETHMTEST
3615 +#define ETHERMTEST_TB (1<<2)
3616 +
3617 +//ETHMCP
3618 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3619 +
3620 +//MIIMCFG
3621 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3622 +#define ETHERMIIMCFG_R (1<<15)
3623 +
3624 +//MIIMCMD
3625 +#define ETHERMIIMCMD_RD (1<<0)
3626 +#define ETHERMIIMCMD_SCN (1<<1)
3627 +
3628 +//MIIMADDR
3629 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3630 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3631 +
3632 +//MIIMWTD
3633 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3634 +
3635 +//MIIMRDD
3636 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3637 +
3638 +//MIIMIND
3639 +#define ETHERMIIMIND_BSY (1<<0)
3640 +#define ETHERMIIMIND_SCN (1<<1)
3641 +#define ETHERMIIMIND_NV (1<<2)
3642 +
3643 +//DMA DEVCS IN
3644 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3645 +#define ETHERDMA_IN_CES (1<<14)
3646 +#define ETHERDMA_IN_LOR (1<<13)
3647 +#define ETHERDMA_IN_LE (1<<12)
3648 +#define ETHERDMA_IN_DB (1<<11)
3649 +#define ETHERDMA_IN_CV (1<<10)
3650 +#define ETHERDMA_IN_CRC (1<<9)
3651 +#define ETHERDMA_IN_OVR (1<<8)
3652 +#define ETHERDMA_IN_CF (1<<7)
3653 +#define ETHERDMA_IN_VLT (1<<6)
3654 +#define ETHERDMA_IN_BP (1<<5)
3655 +#define ETHERDMA_IN_MP (1<<4)
3656 +#define ETHERDMA_IN_FM (1<<3)
3657 +#define ETHERDMA_IN_ROK (1<<2)
3658 +#define ETHERDMA_IN_LD (1<<1)
3659 +#define ETHERDMA_IN_FD (1<<0)
3660 +
3661 +//DMA DEVCS OUT
3662 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3663 +#define ETHERDMA_OUT_CNT 0x001e0000
3664 +#define ETHERDMA_OUT_SHFT 17
3665 +#define ETHERDMA_OUT_LE (1<<16)
3666 +
3667 +#define ETHERDMA_OUT_CRC (1<<15)
3668 +#define ETHERDMA_OUT_TD (1<<14)
3669 +#define ETHERDMA_OUT_LC (1<<13)
3670 +#define ETHERDMA_OUT_EC (1<<12)
3671 +#define ETHERDMA_OUT_ED (1<<11)
3672 +#define ETHERDMA_OUT_OF (1<<10)
3673 +#define ETHERDMA_OUT_UND (1<<9)
3674 +#define ETHERDMA_OUT_BP (1<<8)
3675 +#define ETHERDMA_OUT_MP (1<<7)
3676 +#define ETHERDMA_OUT_TOK (1<<6)
3677 +#define ETHERDMA_OUT_HEN (1<<5)
3678 +#define ETHERDMA_OUT_CEN (1<<4)
3679 +#define ETHERDMA_OUT_PEN (1<<3)
3680 +#define ETHERDMA_OUT_OEN (1<<2)
3681 +#define ETHERDMA_OUT_LD (1<<1)
3682 +#define ETHERDMA_OUT_FD (1<<0)
3683 +
3684 +#define RCV_ERRS \
3685 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3686 +#define TX_ERRS \
3687 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3688 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3689 +
3690 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3691 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3692 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3693 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3694 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3695 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3696 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3697 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3698 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3699 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3700 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3701 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3702 + Range */
3703 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3704 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3705 + received packet */
3706 +
3707 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3708 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3709 +
3710 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3711 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3712 + Underflow */
3713 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3714 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3715 + deferral */
3716 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3717 + collisions */
3718 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3719 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3720 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3721 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3722 +
3723 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3724 +
3725 +#endif /* RC32355_ETHER_H */
3726 +
3727 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3728 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3729 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-06-18 12:44:28.000000000 +0200
3730 @@ -0,0 +1,177 @@
3731 +/**************************************************************************
3732 + *
3733 + * BRIEF MODULE DESCRIPTION
3734 + * Definitions for IDT RC32355 CPU.
3735 + *
3736 + * Copyright 2004 IDT Inc.
3737 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3738 + *
3739 + *
3740 + * This program is free software; you can redistribute it and/or modify it
3741 + * under the terms of the GNU General Public License as published by the
3742 + * Free Software Foundation; either version 2 of the License, or (at your
3743 + * option) any later version.
3744 + *
3745 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3746 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3747 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3748 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3749 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3750 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3751 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3752 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3753 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3754 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3755 + *
3756 + * You should have received a copy of the GNU General Public License along
3757 + * with this program; if not, write to the Free Software Foundation, Inc.,
3758 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3759 + *
3760 + *
3761 + * May 2004 rkt
3762 + * Initial Release
3763 + *
3764 + **************************************************************************
3765 + */
3766 +
3767 +
3768 +#ifndef _RC32355_H_
3769 +#define _RC32355_H_
3770 +
3771 +#include <linux/delay.h>
3772 +#include <asm/io.h>
3773 +
3774 +/* Base address of internal registers */
3775 +#define RC32355_REG_BASE 0x18000000
3776 +
3777 +/* System ID Registers */
3778 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3779 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3780 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3781 +
3782 +/* Reset Controller */
3783 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3784 +
3785 +/* Device Controller */
3786 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3787 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3788 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3789 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3790 +#define DEV_REG_OFFSET 0x10
3791 +
3792 +/* SDRAM Controller */
3793 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3794 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3795 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3796 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3797 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3798 +
3799 +/* Bus Arbiter */
3800 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3801 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3802 +
3803 +/* Counters/Timers */
3804 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3805 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3806 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3807 +#define TIMER_REG_OFFSET 0x0C
3808 +
3809 +/* System Integrity */
3810 +
3811 +/* Interrupt Controller */
3812 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3813 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3814 +#define IC_GROUP_OFFSET 0x08
3815 +
3816 +#define NUM_INTR_GROUPS 5
3817 +/*
3818 + * The IRQ mapping is as follows:
3819 + *
3820 + * IRQ Mapped To
3821 + * --- -------------------
3822 + * 0 SW0 (IP0) SW0 intr
3823 + * 1 SW1 (IP1) SW1 intr
3824 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3825 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3826 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3827 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3828 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3829 + * 7 Int5 (IP7) CP0 Timer
3830 + *
3831 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3832 + * internally on the RC32355 is routed to the Expansion
3833 + * Interrupt Controller.
3834 + */
3835 +#define MIPS_CPU_TIMER_IRQ 7
3836 +
3837 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3838 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3839 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3840 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3841 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3842 +
3843 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3844 +
3845 +/* DMA - see rc32355_dma.h for full list of registers */
3846 +
3847 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3848 +#define DMA_CHAN_OFFSET 0x14
3849 +
3850 +/* GPIO Controller */
3851 +
3852 +/* TDM Bus */
3853 +
3854 +/* 16550 UARTs */
3855 +#ifdef __MIPSEB__
3856 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3857 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3858 +#else
3859 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3860 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3861 +#endif
3862 +
3863 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3864 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3865 +
3866 +/* ATM */
3867 +
3868 +/* Ethernet - see rc32355_eth.h for full list of registers */
3869 +
3870 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3871 +
3872 +
3873 +#define IDT_CLOCK_MULT 2
3874 +
3875 +/* Memory map of 79EB355 board */
3876 +
3877 +/* DRAM */
3878 +#define RAM_BASE 0x00000000
3879 +#define RAM_SIZE (32*1024*1024)
3880 +
3881 +/* SRAM (device 1) */
3882 +#define SRAM_BASE 0x02000000
3883 +#define SRAM_SIZE 0x00100000
3884 +
3885 +/* FLASH (device 2) */
3886 +#define FLASH_BASE 0x0C000000
3887 +#define FLASH_SIZE 0x00C00000
3888 +
3889 +/* ATM PHY (device 4) */
3890 +#define ATM_PHY_BASE 0x14000000
3891 +
3892 +/* TDM switch (device 3) */
3893 +#define TDM_BASE 0x1A000000
3894 +
3895 +/* LCD panel (device 3) */
3896 +#define LCD_BASE 0x1A002000
3897 +
3898 +/* RTC (DS1511W) (device 3) */
3899 +#define RTC_BASE 0x1A004000
3900 +
3901 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3902 +#define NVRAM_ADDR RTC_BASE + 0x10
3903 +#define NVRAM_DATA RTC_BASE + 0x13
3904 +#define NVRAM_ENVSIZE_OFF 4
3905 +#define NVRAM_ENVSTART_OFF 32
3906 +
3907 +#endif /* _RC32355_H_ */
3908 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3909 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3910 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-06-18 12:44:28.000000000 +0200
3911 @@ -0,0 +1,226 @@
3912 +/**************************************************************************
3913 + *
3914 + * BRIEF MODULE DESCRIPTION
3915 + * RC32365/336 DMA hardware abstraction.
3916 + *
3917 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3918 + *
3919 + * This program is free software; you can redistribute it and/or modify it
3920 + * under the terms of the GNU General Public License as published by the
3921 + * Free Software Foundation; either version 2 of the License, or (at your
3922 + * option) any later version.
3923 + *
3924 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3925 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3926 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3927 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3928 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3929 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3930 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3931 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3932 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3933 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3934 + *
3935 + * You should have received a copy of the GNU General Public License along
3936 + * with this program; if not, write to the Free Software Foundation, Inc.,
3937 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3938 + *
3939 + *
3940 + **************************************************************************
3941 + * May 2004 P. Sadik.
3942 + *
3943 + * Initial Release
3944 + *
3945 + *
3946 + *
3947 + **************************************************************************
3948 + */
3949 +
3950 +#ifndef __IDT_RC32365_DMA_H__
3951 +#define __IDT_RC32365_DMA_H__
3952 +
3953 +enum
3954 +{
3955 + DMA0_PhysicalAddress = 0x18038000,
3956 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3957 +
3958 + DMA0_VirtualAddress = 0xb8038000,
3959 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3960 +} ;
3961 +
3962 +/*
3963 + * DMA descriptor (in physical memory).
3964 + */
3965 +
3966 +typedef struct DMAD_s
3967 +{
3968 + u32 control ; // Control. use DMAD_*
3969 + u32 ca ; // Current Address.
3970 + u32 devcs ; // Device control and status.
3971 + u32 link ; // Next descriptor in chain.
3972 +} volatile *DMAD_t ;
3973 +
3974 +enum
3975 +{
3976 + DMAD_size = sizeof (struct DMAD_s),
3977 + DMAD_count_b = 0, // in DMAD_t -> control
3978 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3979 + DMAD_ds_b = 20, // in DMAD_t -> control
3980 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3981 + DMAD_ds_extToMem0_v = 0,
3982 + DMAD_ds_memToExt0_v = 1,
3983 + DMAD_ds_extToMem1_v = 0,
3984 + DMAD_ds_memToExt1_v = 1,
3985 + DMAD_ds_ethRcv0_v = 0,
3986 + DMAD_ds_ethXmt0_v = 0,
3987 + DMAD_ds_ethRcv1_v = 0,
3988 + DMAD_ds_ethXmt2_v = 0,
3989 + DMAD_ds_memToFifo_v = 0,
3990 + DMAD_ds_fifoToMem_v = 0,
3991 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3992 + DMAD_ds_pciToMem_v = 0,
3993 + DMAD_ds_memToPci_v = 0,
3994 + DMAD_ds_securityInput_v = 0,
3995 + DMAD_ds_securityOutput_v = 0,
3996 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3997 +
3998 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3999 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
4000 + DMAD_devcmd_byte_v = 0, //memory-to-memory
4001 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
4002 + DMAD_devcmd_word_v = 2, //memory-to-memory
4003 + DMAD_devcmd_2words_v = 3, //memory-to-memory
4004 + DMAD_devcmd_4words_v = 4, //memory-to-memory
4005 + DMAD_devcmd_6words_v = 5, //memory-to-memory
4006 + DMAD_devcmd_8words_v = 6, //memory-to-memory
4007 + DMAD_devcmd_16words_v = 7, //memory-to-memory
4008 + DMAD_cof_b = 25, // chain on finished
4009 + DMAD_cof_m = 0x02000000, //
4010 + DMAD_cod_b = 26, // chain on done
4011 + DMAD_cod_m = 0x04000000, //
4012 + DMAD_iof_b = 27, // interrupt on finished
4013 + DMAD_iof_m = 0x08000000, //
4014 + DMAD_iod_b = 28, // interrupt on done
4015 + DMAD_iod_m = 0x10000000, //
4016 + DMAD_t_b = 29, // terminated
4017 + DMAD_t_m = 0x20000000, //
4018 + DMAD_d_b = 30, // done
4019 + DMAD_d_m = 0x40000000, //
4020 + DMAD_f_b = 31, // finished
4021 + DMAD_f_m = 0x80000000, //
4022 +} ;
4023 +
4024 +/*
4025 + * DMA register (within Internal Register Map).
4026 + */
4027 +
4028 +struct DMA_Chan_s
4029 +{
4030 + u32 dmac ; // Control.
4031 + u32 dmas ; // Status.
4032 + u32 dmasm ; // Mask.
4033 + u32 dmadptr ; // Descriptor pointer.
4034 + u32 dmandptr ; // Next descriptor pointer.
4035 +};
4036 +
4037 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4038 +
4039 +//DMA_Channels use DMACH_count instead
4040 +
4041 +enum
4042 +{
4043 + DMAC_run_b = 0, //
4044 + DMAC_run_m = 0x00000001, //
4045 + DMAC_dm_b = 1, // done mask
4046 + DMAC_dm_m = 0x00000002, //
4047 + DMAC_mode_b = 2, //
4048 + DMAC_mode_m = 0x0000000c, //
4049 + DMAC_mode_auto_v = 0,
4050 + DMAC_mode_burst_v = 1,
4051 + DMAC_mode_transfer_v = 2, //usually used
4052 + DMAC_mode_reserved_v = 3,
4053 + DMAC_a_b = 4, //
4054 + DMAC_a_m = 0x00000010, //
4055 +
4056 + DMAS_f_b = 0, // finished (sticky)
4057 + DMAS_f_m = 0x00000001, //
4058 + DMAS_d_b = 1, // done (sticky)
4059 + DMAS_d_m = 0x00000002, //
4060 + DMAS_c_b = 2, // chain (sticky)
4061 + DMAS_c_m = 0x00000004, //
4062 + DMAS_e_b = 3, // error (sticky)
4063 + DMAS_e_m = 0x00000008, //
4064 + DMAS_h_b = 4, // halt (sticky)
4065 + DMAS_h_m = 0x00000010, //
4066 +
4067 + DMASM_f_b = 0, // finished (1=mask)
4068 + DMASM_f_m = 0x00000001, //
4069 + DMASM_d_b = 1, // done (1=mask)
4070 + DMASM_d_m = 0x00000002, //
4071 + DMASM_c_b = 2, // chain (1=mask)
4072 + DMASM_c_m = 0x00000004, //
4073 + DMASM_e_b = 3, // error (1=mask)
4074 + DMASM_e_m = 0x00000008, //
4075 + DMASM_h_b = 4, // halt (1=mask)
4076 + DMASM_h_m = 0x00000010, //
4077 +} ;
4078 +
4079 +/*
4080 + * DMA channel definitions
4081 + */
4082 +
4083 +enum
4084 +{
4085 + DMACH_ethRcv0 = 0,
4086 + DMACH_ethXmt0 = 1,
4087 + DMACH_ethRcv1 = 2,
4088 + DMACH_ethXmt2 = 3,
4089 + DMACH_pciToMem = 4,
4090 + DMACH_memToPci = 5,
4091 + DMACH_securityInput = 6,
4092 + DMACH_securityOutput = 7,
4093 + DMACH_rng = 8,
4094 +
4095 + DMACH_count //must be last
4096 +};
4097 +
4098 +
4099 +typedef struct DMAC_s
4100 +{
4101 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4102 +} volatile *DMA_t ;
4103 +
4104 +
4105 +/*
4106 + * External DMA parameters
4107 +*/
4108 +
4109 +enum
4110 +{
4111 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4112 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4113 + DMADEVCMD_ts_byte_v = 0,
4114 + DMADEVCMD_ts_halfword_v = 1,
4115 + DMADEVCMD_ts_word_v = 2,
4116 + DMADEVCMD_ts_2word_v = 3,
4117 + DMADEVCMD_ts_4word_v = 4,
4118 + DMADEVCMD_ts_6word_v = 5,
4119 + DMADEVCMD_ts_8word_v = 6,
4120 + DMADEVCMD_ts_16word_v = 7
4121 +};
4122 +
4123 +
4124 +#if 1 // aws - Compatibility.
4125 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4126 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4127 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4128 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4129 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4130 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4131 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4132 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4133 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4134 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4135 +#endif // aws - Compatibility.
4136 +
4137 +#endif // __IDT_RC32365_DMA_H__
4138 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4139 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4140 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-06-18 12:44:28.000000000 +0200
4141 @@ -0,0 +1,86 @@
4142 +/**************************************************************************
4143 + *
4144 + * BRIEF MODULE DESCRIPTION
4145 + * RC32365/336 DMA interface routines.
4146 + *
4147 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4148 + *
4149 + * This program is free software; you can redistribute it and/or modify it
4150 + * under the terms of the GNU General Public License as published by the
4151 + * Free Software Foundation; either version 2 of the License, or (at your
4152 + * option) any later version.
4153 + *
4154 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4155 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4156 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4157 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4158 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4159 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4160 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4161 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4162 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4163 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4164 + *
4165 + * You should have received a copy of the GNU General Public License along
4166 + * with this program; if not, write to the Free Software Foundation, Inc.,
4167 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4168 + *
4169 + *
4170 + **************************************************************************
4171 + * May 2004 P. Sadik.
4172 + *
4173 + * Initial Release
4174 + *
4175 + *
4176 + *
4177 + **************************************************************************
4178 + */
4179 +
4180 +#ifndef __IDT_RC32365_DMA_V_H__
4181 +#define __IDT_RC32365_DMA_V_H__
4182 +
4183 +
4184 +#include <asm/idt-boards/rc32300/rc32300.h>
4185 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4186 +#include <asm/idt-boards/rc32300/rc32365.h>
4187 +
4188 +#define DMA_CHAN_OFFSET 0x14
4189 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4190 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4191 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4192 +
4193 +#define DMA_COUNT(count) \
4194 + ((count) & DMAD_count_m)
4195 +
4196 +#define DMA_HALT_TIMEOUT 500
4197 +
4198 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4199 +{
4200 + int timeout=1;
4201 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4202 + local_writel(0, &ch->dmac);
4203 +
4204 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4205 + if (local_readl(&ch->dmas) & DMAS_h_m) {
4206 + local_writel(0, &ch->dmas);
4207 + break;
4208 + }
4209 + }
4210 +
4211 + }
4212 +
4213 + return timeout ? 0 : 1;
4214 +}
4215 +
4216 +
4217 +static inline void rc32365_start_dma(DMA_Chan_t ch, u32 dma_addr)
4218 +{
4219 + local_writel(0, &ch->dmandptr);
4220 + local_writel(dma_addr, &ch->dmadptr);
4221 +}
4222 +
4223 +static inline void rc32365_chain_dma(DMA_Chan_t ch, u32 dma_addr)
4224 +{
4225 + local_writel(dma_addr, &ch->dmandptr);
4226 +}
4227 +#endif //__IDT_RC32365_DMA_V_H__
4228 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h
4229 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 1970-01-01 01:00:00.000000000 +0100
4230 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth.h 2006-06-18 12:44:28.000000000 +0200
4231 @@ -0,0 +1,344 @@
4232 +/**************************************************************************
4233 + *
4234 + * BRIEF MODULE DESCRIPTION
4235 + * RC32365/336 Ethernet hardware abstraction.
4236 + *
4237 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4238 + *
4239 + * This program is free software; you can redistribute it and/or modify it
4240 + * under the terms of the GNU General Public License as published by the
4241 + * Free Software Foundation; either version 2 of the License, or (at your
4242 + * option) any later version.
4243 + *
4244 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4245 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4246 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4247 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4248 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4249 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4250 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4251 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4252 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4253 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4254 + *
4255 + * You should have received a copy of the GNU General Public License along
4256 + * with this program; if not, write to the Free Software Foundation, Inc.,
4257 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4258 + *
4259 + *
4260 + **************************************************************************
4261 + * May 2004 P. Sadik.
4262 + *
4263 + * Initial Release
4264 + *
4265 + *
4266 + *
4267 + **************************************************************************
4268 + */
4269 +
4270 +#ifndef __IDT_RC32365_ETH_H__
4271 +#define __IDT_RC32365_ETH_H__
4272 +
4273 +enum
4274 +{
4275 + ETH0_PhysicalAddress = 0x18058000,
4276 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
4277 + ETH0_VirtualAddress = 0xb8058000,
4278 +
4279 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
4280 +
4281 + ETH1_PhysicalAddress = 0x18060000,
4282 + ETH1_VirtualAddress = 0xb8060000, // Default
4283 +} ;
4284 +
4285 +typedef struct
4286 +{
4287 + u32 ethintfc ;
4288 + u32 ethfifott ;
4289 + u32 etharc ;
4290 + u32 ethhash0 ;
4291 + u32 ethhash1 ;
4292 + u32 ethu0 [4] ; // Reserved.
4293 + u32 ethpfs ;
4294 + u32 ethmcp ;
4295 + u32 eth_u1 [10] ; // Reserved.
4296 + u32 ethspare ;
4297 + u32 eth_u2 [42] ; // Reserved.
4298 + u32 ethsal0 ;
4299 + u32 ethsah0 ;
4300 + u32 ethsal1 ;
4301 + u32 ethsah1 ;
4302 + u32 ethsal2 ;
4303 + u32 ethsah2 ;
4304 + u32 ethsal3 ;
4305 + u32 ethsah3 ;
4306 + u32 ethrbc ;
4307 + u32 ethrpc ;
4308 + u32 ethrupc ;
4309 + u32 ethrfc ;
4310 + u32 ethtbc ;
4311 + u32 ethgpf ;
4312 + u32 eth_u9 [50] ; // Reserved.
4313 + u32 ethmac1 ;
4314 + u32 ethmac2 ;
4315 + u32 ethipgt ;
4316 + u32 ethipgr ;
4317 + u32 ethclrt ;
4318 + u32 ethmaxf ;
4319 + u32 eth_u10 ; // Reserved.
4320 + u32 ethmtest ;
4321 + u32 miimcfg ;
4322 + u32 miimcmd ;
4323 + u32 miimaddr ;
4324 + u32 miimwtd ;
4325 + u32 miimrdd ;
4326 + u32 miimind ;
4327 + u32 eth_u11 ; // Reserved.
4328 + u32 eth_u12 ; // Reserved.
4329 + u32 ethcfsa0 ;
4330 + u32 ethcfsa1 ;
4331 + u32 ethcfsa2 ;
4332 +} volatile *ETH_t;
4333 +
4334 +enum
4335 +{
4336 + ETHINTFC_en_b = 0,
4337 + ETHINTFC_en_m = 0x00000001,
4338 + ETHINTFC_its_b = 1,
4339 + ETHINTFC_its_m = 0x00000002,
4340 + ETHINTFC_rip_b = 2,
4341 + ETHINTFC_rip_m = 0x00000004,
4342 + ETHINTFC_jam_b = 3,
4343 + ETHINTFC_jam_m = 0x00000008,
4344 + ETHINTFC_ovr_b = 4,
4345 + ETHINTFC_ovr_m = 0x00000010,
4346 + ETHINTFC_und_b = 5,
4347 + ETHINTFC_und_m = 0x00000020,
4348 +
4349 + ETHFIFOTT_tth_b = 0,
4350 + ETHFIFOTT_tth_m = 0x0000007f,
4351 +
4352 + ETHARC_pro_b = 0,
4353 + ETHARC_pro_m = 0x00000001,
4354 + ETHARC_am_b = 1,
4355 + ETHARC_am_m = 0x00000002,
4356 + ETHARC_afm_b = 2,
4357 + ETHARC_afm_m = 0x00000004,
4358 + ETHARC_ab_b = 3,
4359 + ETHARC_ab_m = 0x00000008,
4360 +
4361 + ETHSAL_byte5_b = 0,
4362 + ETHSAL_byte5_m = 0x000000ff,
4363 + ETHSAL_byte4_b = 8,
4364 + ETHSAL_byte4_m = 0x0000ff00,
4365 + ETHSAL_byte3_b = 16,
4366 + ETHSAL_byte3_m = 0x00ff0000,
4367 + ETHSAL_byte2_b = 24,
4368 + ETHSAL_byte2_m = 0xff000000,
4369 +
4370 + ETHSAH_byte1_b = 0,
4371 + ETHSAH_byte1_m = 0x000000ff,
4372 + ETHSAH_byte0_b = 8,
4373 + ETHSAH_byte0_m = 0x0000ff00,
4374 +
4375 + ETHGPF_ptv_b = 0,
4376 + ETHGPF_ptv_m = 0x0000ffff,
4377 +
4378 + ETHPFS_pfd_b = 0,
4379 + ETHPFS_pfd_m = 0x00000001,
4380 +
4381 + ETHCFSA0_cfsa4_b = 0,
4382 + ETHCFSA0_cfsa4_m = 0x000000ff,
4383 + ETHCFSA0_cfsa5_b = 8,
4384 + ETHCFSA0_cfsa5_m = 0x0000ff00,
4385 +
4386 + ETHCFSA1_cfsa2_b = 0,
4387 + ETHCFSA1_cfsa2_m = 0x000000ff,
4388 + ETHCFSA1_cfsa3_b = 8,
4389 + ETHCFSA1_cfsa3_m = 0x0000ff00,
4390 +
4391 + ETHCFSA2_cfsa0_b = 0,
4392 + ETHCFSA2_cfsa0_m = 0x000000ff,
4393 + ETHCFSA2_cfsa1_b = 8,
4394 + ETHCFSA2_cfsa1_m = 0x0000ff00,
4395 +
4396 + ETHMAC1_re_b = 0,
4397 + ETHMAC1_re_m = 0x00000001,
4398 + ETHMAC1_paf_b = 1,
4399 + ETHMAC1_paf_m = 0x00000002,
4400 + ETHMAC1_rfc_b = 2,
4401 + ETHMAC1_rfc_m = 0x00000004,
4402 + ETHMAC1_tfc_b = 3,
4403 + ETHMAC1_tfc_m = 0x00000008,
4404 + ETHMAC1_lb_b = 4,
4405 + ETHMAC1_lb_m = 0x00000010,
4406 + ETHMAC1_mr_b = 31,
4407 + ETHMAC1_mr_m = 0x80000000,
4408 +
4409 + ETHMAC2_fd_b = 0,
4410 + ETHMAC2_fd_m = 0x00000001,
4411 + ETHMAC2_flc_b = 1,
4412 + ETHMAC2_flc_m = 0x00000002,
4413 + ETHMAC2_hfe_b = 2,
4414 + ETHMAC2_hfe_m = 0x00000004,
4415 + ETHMAC2_dc_b = 3,
4416 + ETHMAC2_dc_m = 0x00000008,
4417 + ETHMAC2_cen_b = 4,
4418 + ETHMAC2_cen_m = 0x00000010,
4419 + ETHMAC2_pe_b = 5,
4420 + ETHMAC2_pe_m = 0x00000020,
4421 + ETHMAC2_vpe_b = 6,
4422 + ETHMAC2_vpe_m = 0x00000040,
4423 + ETHMAC2_ape_b = 7,
4424 + ETHMAC2_ape_m = 0x00000080,
4425 + ETHMAC2_ppe_b = 8,
4426 + ETHMAC2_ppe_m = 0x00000100,
4427 + ETHMAC2_lpe_b = 9,
4428 + ETHMAC2_lpe_m = 0x00000200,
4429 + ETHMAC2_nb_b = 12,
4430 + ETHMAC2_nb_m = 0x00001000,
4431 + ETHMAC2_bp_b = 13,
4432 + ETHMAC2_bp_m = 0x00002000,
4433 + ETHMAC2_ed_b = 14,
4434 + ETHMAC2_ed_m = 0x00004000,
4435 +
4436 + ETHIPGT_ipgt_b = 0,
4437 + ETHIPGT_ipgt_m = 0x0000007f,
4438 +
4439 + ETHIPGR_ipgr2_b = 0,
4440 + ETHIPGR_ipgr2_m = 0x0000007f,
4441 + ETHIPGR_ipgr1_b = 8,
4442 + ETHIPGR_ipgr1_m = 0x00007f00,
4443 +
4444 + ETHCLRT_maxret_b = 0,
4445 + ETHCLRT_maxret_m = 0x0000000f,
4446 + ETHCLRT_colwin_b = 8,
4447 + ETHCLRT_colwin_m = 0x00003f00,
4448 +
4449 + ETHMAXF_maxf_b = 0,
4450 + ETHMAXF_maxf_m = 0x0000ffff,
4451 +
4452 + ETHMTEST_tb_b = 2,
4453 + ETHMTEST_tb_m = 0x00000004,
4454 +
4455 + ETHMCP_div_b = 0,
4456 + ETHMCP_div_m = 0x000000ff,
4457 +
4458 + MIIMCFG_rsv_b = 0,
4459 + MIIMCFG_rsv_m = 0x0000000c,
4460 +
4461 + MIIMCMD_rd_b = 0,
4462 + MIIMCMD_rd_m = 0x00000001,
4463 + MIIMCMD_scn_b = 1,
4464 + MIIMCMD_scn_m = 0x00000002,
4465 +
4466 + MIIMADDR_regaddr_b = 0,
4467 + MIIMADDR_regaddr_m = 0x0000001f,
4468 + MIIMADDR_phyaddr_b = 8,
4469 + MIIMADDR_phyaddr_m = 0x00001f00,
4470 +
4471 + MIIMWTD_wdata_b = 0,
4472 + MIIMWTD_wdata_m = 0x0000ffff,
4473 +
4474 + MIIMRDD_rdata_b = 0,
4475 + MIIMRDD_rdata_m = 0x0000ffff,
4476 +
4477 + MIIMIND_bsy_b = 0,
4478 + MIIMIND_bsy_m = 0x00000001,
4479 + MIIMIND_scn_b = 1,
4480 + MIIMIND_scn_m = 0x00000002,
4481 + MIIMIND_nv_b = 2,
4482 + MIIMIND_nv_m = 0x00000004,
4483 +
4484 +} ;
4485 +
4486 +/*
4487 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
4488 + */
4489 +enum
4490 +{
4491 + ETHRX_fd_b = 0,
4492 + ETHRX_fd_m = 0x00000001,
4493 + ETHRX_ld_b = 1,
4494 + ETHRX_ld_m = 0x00000002,
4495 + ETHRX_rok_b = 2,
4496 + ETHRX_rok_m = 0x00000004,
4497 + ETHRX_fm_b = 3,
4498 + ETHRX_fm_m = 0x00000008,
4499 + ETHRX_mp_b = 4,
4500 + ETHRX_mp_m = 0x00000010,
4501 + ETHRX_bp_b = 5,
4502 + ETHRX_bp_m = 0x00000020,
4503 + ETHRX_vlt_b = 6,
4504 + ETHRX_vlt_m = 0x00000040,
4505 + ETHRX_cf_b = 7,
4506 + ETHRX_cf_m = 0x00000080,
4507 + ETHRX_ovr_b = 8,
4508 + ETHRX_ovr_m = 0x00000100,
4509 + ETHRX_crc_b = 9,
4510 + ETHRX_crc_m = 0x00000200,
4511 + ETHRX_cv_b = 10,
4512 + ETHRX_cv_m = 0x00000400,
4513 + ETHRX_db_b = 11,
4514 + ETHRX_db_m = 0x00000800,
4515 + ETHRX_le_b = 12,
4516 + ETHRX_le_m = 0x00001000,
4517 + ETHRX_lor_b = 13,
4518 + ETHRX_lor_m = 0x00002000,
4519 + ETHRX_ces_b = 14,
4520 + ETHRX_ces_m = 0x00004000,
4521 + ETHRX_length_b = 16,
4522 + ETHRX_length_m = 0xffff0000,
4523 +
4524 + ETHTX_fd_b = 0,
4525 + ETHTX_fd_m = 0x00000001,
4526 + ETHTX_ld_b = 1,
4527 + ETHTX_ld_m = 0x00000002,
4528 + ETHTX_oen_b = 2,
4529 + ETHTX_oen_m = 0x00000004,
4530 + ETHTX_pen_b = 3,
4531 + ETHTX_pen_m = 0x00000008,
4532 + ETHTX_cen_b = 4,
4533 + ETHTX_cen_m = 0x00000010,
4534 + ETHTX_hen_b = 5,
4535 + ETHTX_hen_m = 0x00000020,
4536 + ETHTX_tok_b = 6,
4537 + ETHTX_tok_m = 0x00000040,
4538 + ETHTX_mp_b = 7,
4539 + ETHTX_mp_m = 0x00000080,
4540 + ETHTX_bp_b = 8,
4541 + ETHTX_bp_m = 0x00000100,
4542 + ETHTX_und_b = 9,
4543 + ETHTX_und_m = 0x00000200,
4544 + ETHTX_of_b = 10,
4545 + ETHTX_of_m = 0x00000400,
4546 + ETHTX_ed_b = 11,
4547 + ETHTX_ed_m = 0x00000800,
4548 + ETHTX_ec_b = 12,
4549 + ETHTX_ec_m = 0x00001000,
4550 + ETHTX_lc_b = 13,
4551 + ETHTX_lc_m = 0x00002000,
4552 + ETHTX_td_b = 14,
4553 + ETHTX_td_m = 0x00004000,
4554 + ETHTX_crc_b = 15,
4555 + ETHTX_crc_m = 0x00008000,
4556 + ETHTX_le_b = 16,
4557 + ETHTX_le_m = 0x00010000,
4558 + ETHTX_cc_b = 17,
4559 + ETHTX_cc_m = 0x001E0000,
4560 +} ;
4561 +
4562 +enum
4563 +{
4564 + ETH0_IPABMC_PhysicalAddress = 0x18040010,
4565 + ETH0_IPABMC_VirtualAddress = 0xb8040000,
4566 + ETH1_IPABMC_PhysicalAddress = 0x18040018,
4567 + ETH1_IPABMC_VirtualAddress = 0xb8040018,
4568 +} ;
4569 +
4570 +typedef struct
4571 +{
4572 + u32 ipabmcrx ;
4573 + u32 ipabmctx ;
4574 +}volatile *IPABM_ETH_t;
4575 +#endif //__IDT_RC32365_ETH_H__
4576 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h
4577 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 1970-01-01 01:00:00.000000000 +0100
4578 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_eth_v.h 2006-06-18 12:44:28.000000000 +0200
4579 @@ -0,0 +1,72 @@
4580 +/**************************************************************************
4581 + *
4582 + * BRIEF MODULE DESCRIPTION
4583 + * RC32365/336 Ethernet status checking.
4584 + *
4585 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4586 + *
4587 + * This program is free software; you can redistribute it and/or modify it
4588 + * under the terms of the GNU General Public License as published by the
4589 + * Free Software Foundation; either version 2 of the License, or (at your
4590 + * option) any later version.
4591 + *
4592 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4593 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4594 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4595 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4596 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4597 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4598 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4599 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4600 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4601 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4602 + *
4603 + * You should have received a copy of the GNU General Public License along
4604 + * with this program; if not, write to the Free Software Foundation, Inc.,
4605 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4606 + *
4607 + *
4608 + **************************************************************************
4609 + * May 2004 P. Sadik.
4610 + *
4611 + * Initial Release
4612 + *
4613 + *
4614 + *
4615 + **************************************************************************
4616 + */
4617 +
4618 +#ifndef __IDT_RC32365_ETH_V_H__
4619 +#define __IDT_RC32365_ETH_V_H__
4620 +#include <asm/idt-boards/rc32300/rc32365_eth.h>
4621 +
4622 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
4623 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
4624 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
4625 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
4626 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
4627 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
4628 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
4629 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
4630 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
4631 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
4632 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
4633 +
4634 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
4635 +
4636 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
4637 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
4638 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
4639 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
4640 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
4641 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
4642 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
4643 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
4644 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
4645 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
4646 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
4647 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
4648 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
4649 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
4650 +
4651 +#endif //__IDT_RC32365_ETH_V_H__
4652 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h
4653 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 1970-01-01 01:00:00.000000000 +0100
4654 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio.h 2006-06-18 12:44:28.000000000 +0200
4655 @@ -0,0 +1,181 @@
4656 +/**************************************************************************
4657 + *
4658 + * BRIEF MODULE DESCRIPTION
4659 + * RC32365/336 GPIO hardware abstraction.
4660 + *
4661 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4662 + *
4663 + * This program is free software; you can redistribute it and/or modify it
4664 + * under the terms of the GNU General Public License as published by the
4665 + * Free Software Foundation; either version 2 of the License, or (at your
4666 + * option) any later version.
4667 + *
4668 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4669 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4670 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4671 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4672 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4673 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4674 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4675 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4676 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4677 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4678 + *
4679 + * You should have received a copy of the GNU General Public License along
4680 + * with this program; if not, write to the Free Software Foundation, Inc.,
4681 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4682 + *
4683 + *
4684 + **************************************************************************
4685 + * May 2004 P. Sadik.
4686 + *
4687 + * Initial Release
4688 + *
4689 + *
4690 + *
4691 + **************************************************************************
4692 + */
4693 +
4694 +#ifndef __IDT_RC32365_GPIO_H__
4695 +#define __IDT_RC32365_GPIO_H__
4696 +
4697 +enum
4698 +{
4699 + GPIO0_PhysicalAddress = 0x18048000,
4700 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
4701 +
4702 + GPIO0_VirtualAddress = 0xb8048000,
4703 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
4704 +} ;
4705 +
4706 +typedef struct
4707 +{
4708 + u32 gpiofunc; /* GPIO Function Register
4709 + * gpiofunc[x]==0 bit = gpio
4710 + * func[x]==1 bit = altfunc
4711 + */
4712 + u32 gpiocfg; /* GPIO Configuration Register
4713 + * gpiocfg[x]==0 bit = input
4714 + * gpiocfg[x]==1 bit = output
4715 + */
4716 + u32 gpiod; /* GPIO Data Register
4717 + * gpiod[x] read/write gpio pinX status
4718 + */
4719 + u32 gpioilevel; /* GPIO Interrupt Status Register
4720 + * interrupt level (see gpioistat)
4721 + */
4722 + u32 gpioistat; /* Gpio Interrupt Status Register
4723 + * istat[x] = (gpiod[x] == level[x])
4724 + * cleared in ISR (STICKY bits)
4725 + */
4726 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
4727 +} volatile * GPIO_t ;
4728 +
4729 +typedef enum
4730 +{
4731 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
4732 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
4733 + GPIO_input_v = 0, // gpiocfg use pin as input.
4734 + GPIO_output_v = 1, // gpiocfg use pin as output.
4735 + GPIO_pin0_b = 0,
4736 + GPIO_pin0_m = 0x00000001,
4737 + GPIO_pin1_b = 1,
4738 + GPIO_pin1_m = 0x00000002,
4739 + GPIO_pin2_b = 2,
4740 + GPIO_pin2_m = 0x00000004,
4741 + GPIO_pin3_b = 3,
4742 + GPIO_pin3_m = 0x00000008,
4743 + GPIO_pin4_b = 4,
4744 + GPIO_pin4_m = 0x00000010,
4745 + GPIO_pin5_b = 5,
4746 + GPIO_pin5_m = 0x00000020,
4747 + GPIO_pin6_b = 6,
4748 + GPIO_pin6_m = 0x00000040,
4749 + GPIO_pin7_b = 7,
4750 + GPIO_pin7_m = 0x00000080,
4751 + GPIO_pin8_b = 8,
4752 + GPIO_pin8_m = 0x00000100,
4753 + GPIO_pin9_b = 9,
4754 + GPIO_pin9_m = 0x00000200,
4755 + GPIO_pin10_b = 10,
4756 + GPIO_pin10_m = 0x00000400,
4757 + GPIO_pin11_b = 11,
4758 + GPIO_pin11_m = 0x00000800,
4759 + GPIO_pin12_b = 12,
4760 + GPIO_pin12_m = 0x00001000,
4761 + GPIO_pin13_b = 13,
4762 + GPIO_pin13_m = 0x00002000,
4763 + GPIO_pin14_b = 14,
4764 + GPIO_pin14_m = 0x00004000,
4765 + GPIO_pin15_b = 15,
4766 + GPIO_pin15_m = 0x00008000,
4767 +
4768 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
4769 +
4770 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
4771 + GPIO_u0sout_m = GPIO_pin0_m,
4772 + GPIO_u0sout_cfg_v = GPIO_output_v,
4773 +
4774 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
4775 + GPIO_u0sinp_m = GPIO_pin1_m,
4776 + GPIO_u0sinp_cfg_v = GPIO_input_v,
4777 +
4778 + GPIO_maddr22_b = GPIO_pin2_b, // M&P bus bit 22.
4779 + GPIO_maddr22_m = GPIO_pin2_m,
4780 + GPIO_maddr22_cfg_v = GPIO_output_v,
4781 +
4782 + GPIO_maddr23_b = GPIO_pin3_b, // M&P bus bit 23.
4783 + GPIO_maddr23_m = GPIO_pin3_m,
4784 + GPIO_maddr23_cfg_v = GPIO_output_v,
4785 +
4786 + GPIO_maddr24_b = GPIO_pin4_b, // M&P bus bit 24.
4787 + GPIO_maddr24_m = GPIO_pin4_m,
4788 + GPIO_maddr24_cfg_v = GPIO_output_v,
4789 +
4790 + GPIO_maddr25_b = GPIO_pin5_b, // M&P bus bit 25.
4791 + GPIO_maddr25_m = GPIO_pin5_m,
4792 + GPIO_maddr25_cfg_v = GPIO_output_v,
4793 +
4794 + GPIO_rngclk_b = GPIO_pin6_b, // reserved.
4795 + GPIO_rngclk_m = GPIO_pin6_m,
4796 + GPIO_rngclk_cfg_v = GPIO_input_v,
4797 +
4798 + GPIO_sdckenp_b = GPIO_pin7_b, // reserved.
4799 + GPIO_sdckenp_m = GPIO_pin7_m,
4800 + GPIO_sdckenp_cfg_v = GPIO_output_v,
4801 +
4802 + GPIO_cen1_b = GPIO_pin8_b, // reserved.
4803 + GPIO_cen1_m = GPIO_pin8_m,
4804 + GPIO_cen1_cfg_v = GPIO_output_v,
4805 +
4806 + GPIO_cen2_b = GPIO_pin9_b, // reserved.
4807 + GPIO_cen2_m = GPIO_pin9_m,
4808 + GPIO_cen2_cfg_v = GPIO_output_v,
4809 +
4810 + GPIO_regn_b = GPIO_pin10_b, // reserved.
4811 + GPIO_regn_m = GPIO_pin10_m,
4812 + GPIO_regn_cfg_v = GPIO_output_v,
4813 +
4814 + GPIO_iordn_b = GPIO_pin11_b, // reserved.
4815 + GPIO_iordn_m = GPIO_pin11_m,
4816 + GPIO_iordn_cfg_v = GPIO_output_v,
4817 +
4818 + GPIO_iowrn_b = GPIO_pin12_b, // reserved.
4819 + GPIO_iowrn_m = GPIO_pin12_m,
4820 + GPIO_iowrn_cfg_v = GPIO_output_v,
4821 +
4822 + GPIO_pcireqn2_b = GPIO_pin13_b, // PCI messaging int.
4823 + GPIO_pcireqn2_m = GPIO_pin13_m,
4824 + GPIO_pcireqn2_cfg_v = GPIO_input_v,
4825 +
4826 + GPIO_pcigntn2_b = GPIO_pin14_b, // PCI messaging int.
4827 + GPIO_pcigntn2_m = GPIO_pin14_m,
4828 + GPIO_pcigntn2_cfg_v = GPIO_output_v,
4829 +
4830 + GPIO_pcimuintn_b = GPIO_pin15_b, // PCI messaging int.
4831 + GPIO_pcimuintn_m = GPIO_pin15_m,
4832 + GPIO_pcimuintn_cfg_v= GPIO_output_v,
4833 +
4834 +} GPIO_DEFS_t;
4835 +
4836 +#endif //__IDT_RC32365_GPIO_H__
4837 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h
4838 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 1970-01-01 01:00:00.000000000 +0100
4839 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_gpio_v.h 2006-06-18 12:44:28.000000000 +0200
4840 @@ -0,0 +1,91 @@
4841 +/**************************************************************************
4842 + *
4843 + * BRIEF MODULE DESCRIPTION
4844 + * Routines to set/clear/toggle GPIO on RC32365
4845 + *
4846 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4847 + *
4848 + * This program is free software; you can redistribute it and/or modify it
4849 + * under the terms of the GNU General Public License as published by the
4850 + * Free Software Foundation; either version 2 of the License, or (at your
4851 + * option) any later version.
4852 + *
4853 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4854 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4855 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4856 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4857 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4858 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4859 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4860 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4861 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4862 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4863 + *
4864 + * You should have received a copy of the GNU General Public License along
4865 + * with this program; if not, write to the Free Software Foundation, Inc.,
4866 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4867 + *
4868 + *
4869 + **************************************************************************
4870 + * May 2004 P. Sadik.
4871 + *
4872 + * Initial Release
4873 + *
4874 + *
4875 + *
4876 + **************************************************************************
4877 + */
4878 +#ifndef __IDT_RC32365_GPIO_V_H__
4879 +#define __IDT_RC32365_GPIO_V_H__
4880 +
4881 +
4882 +#ifdef _LANGUAGE_ASSEMBLY
4883 +#define SET_GPIO(pin) \
4884 + lui t5,0xb804 ; \
4885 + ori t5,t5,0x8000 ; \
4886 + lw t4,8(t5) ; \
4887 + ori t4,t4,pin ; \
4888 + sw t4,8(t5) ;
4889 +
4890 +#define CLEAR_GPIO(pin) \
4891 + lui t5,0xb804 ; \
4892 + ori t5,t5,0x8000 ; \
4893 + lw t4,8(t5) ; \
4894 + lui t6,0xFFFF; \
4895 + ori t6,t6,0xFFFF; \
4896 + xori t6,t6,pin ; \
4897 + and t4,t6 ; \
4898 + sw t4,8(t5) ;
4899 +
4900 +#define TOGGLE_GPIO(pin) \
4901 + lui t5,0xb804 ; \
4902 + ori t5,t5,0x8000 ; \
4903 + lw t4,8(t5) ; \
4904 + xori t4,t4,pin ; \
4905 + sw t4,8(t5) ;
4906 +
4907 +#else // !_LANGUAGE_ASSEMBLY
4908 +#include <asm/rc32300/types.h>
4909 +#include <asm/rc32300/rc32365_gpio.h>
4910 +#include <asm/rc32300/rc32365.h>
4911 +
4912 +static inline void set_gpio(unsigned long pin)
4913 +{
4914 + idt_gpio->gpiod |= pin;
4915 +}
4916 +
4917 +static inline void clear_gpio(unsigned long pin)
4918 +{
4919 + idt_gpio->gpiod &= ~pin;
4920 +}
4921 +static inline void toggle_gpio(unsigned long pin)
4922 +{
4923 + idt_gpio->gpiod ^= pin;
4924 +}
4925 +#define SET_GPIO(pin) set_gpio(pin)
4926 +#define CLEAR_GPIO(pin) clear_gpio(pin)
4927 +#define TOGGLE_GPIO(pin) toggle_gpio(pin)
4928 +#endif // _LANGUAGE_ASSEMBLY
4929 +
4930 +#endif //__IDT_RC32365_GPIO_V_H__
4931 +
4932 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h
4933 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365.h 1970-01-01 01:00:00.000000000 +0100
4934 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365.h 2006-06-18 12:44:28.000000000 +0200
4935 @@ -0,0 +1,160 @@
4936 +/**************************************************************************
4937 + *
4938 + * BRIEF MODULE DESCRIPTION
4939 + * Definitions for IDT RC32365 CPU.
4940 + *
4941 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4942 + *
4943 + * This program is free software; you can redistribute it and/or modify it
4944 + * under the terms of the GNU General Public License as published by the
4945 + * Free Software Foundation; either version 2 of the License, or (at your
4946 + * option) any later version.
4947 + *
4948 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4949 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4950 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4951 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4952 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4953 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4954 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4955 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4956 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4957 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4958 + *
4959 + * You should have received a copy of the GNU General Public License along
4960 + * with this program; if not, write to the Free Software Foundation, Inc.,
4961 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4962 + *
4963 + *
4964 + **************************************************************************
4965 + * May 2004 P. Sadik.
4966 + *
4967 + * Initial Release
4968 + *
4969 + *
4970 + *
4971 + **************************************************************************
4972 + */
4973 +
4974 +#ifndef __IDT_RC32365_H__
4975 +#define __IDT_RC32365_H__
4976 +
4977 +extern unsigned int cedar_za;
4978 +
4979 +/* Base address of internal registers */
4980 +#define RC32365_REG_BASE 0x18000000
4981 +
4982 +/* System ID Registers */
4983 +#define CPU_SYSID (RC32365_REG_BASE + 0x00018)
4984 +#define CPU_DEVTYPE (RC32365_REG_BASE + 0x0001c)
4985 +
4986 +/* Reset Controller */
4987 +#define RESET_CNTL (RC32365_REG_BASE + 0x08000)
4988 +#define BOOT_VECTOR (RC32365_REG_BASE + 0x08004)
4989 +
4990 +/* Device Controller */
4991 +#define DEV0_BASE (RC32365_REG_BASE + 0x10000)
4992 +#define DEV0_MASK (RC32365_REG_BASE + 0x10004)
4993 +#define DEV0_CNTL (RC32365_REG_BASE + 0x10008)
4994 +#define DEV0_TIMING (RC32365_REG_BASE + 0x1000c)
4995 +#define DEV_REG_OFFSET 0x10
4996 +
4997 +/* SDRAM Controller */
4998 +#define SDRAM0_BASE (RC32365_REG_BASE + 0x18000)
4999 +#define SDRAM0_MASK (RC32365_REG_BASE + 0x18004)
5000 +#define SDRAM1_BASE (RC32365_REG_BASE + 0x18008)
5001 +#define SDRAM1_MASK (RC32365_REG_BASE + 0x1800c)
5002 +#define SDRAM_CNTL (RC32365_REG_BASE + 0x18010)
5003 +
5004 +/* Counters/Timers */
5005 +#define TIMER0_COUNT (RC32365_REG_BASE + 0x20000)
5006 +#define TIMER0_COMPARE (RC32365_REG_BASE + 0x20004)
5007 +#define TIMER0_CNTL (RC32365_REG_BASE + 0x20008)
5008 +#define TIMER0_SELECT (RC32365_REG_BASE + 0x2000c)
5009 +#define TIMER_REG_OFFSET 0x10
5010 +
5011 +/* System Integrity */
5012 +
5013 +/* Interrupt Controller */
5014 +#define IC_GROUP0_PEND (RC32365_REG_BASE + 0x30000)
5015 +#define IC_GROUP0_TEST (RC32365_REG_BASE + 0x30004)
5016 +#define IC_GROUP0_MASK (RC32365_REG_BASE + 0x30008)
5017 +#define IC_GROUP_OFFSET 0x0c
5018 +
5019 +#define NUM_INTR_GROUPS 5
5020 +/*
5021 + * The IRQ mapping is as follows:
5022 + *
5023 + * IRQ Mapped To
5024 + * --- -------------------
5025 + * 0 SW0 (IP0) SW0 intr
5026 + * 1 SW1 (IP1) SW1 intr
5027 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
5028 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
5029 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
5030 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
5031 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
5032 + * 7 Int5 (IP7) CP0 Timer
5033 + *
5034 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
5035 + * internally on the RC32365 is routed to the Expansion
5036 + * Interrupt Controller.
5037 + */
5038 +#define MIPS_CPU_TIMER_IRQ 7
5039 +
5040 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
5041 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
5042 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // RNG, SEC
5043 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // Eth, PCI, UARTs
5044 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
5045 +
5046 +#define RC32365_NR_IRQS (GROUP4_IRQ_BASE + 32)
5047 +
5048 +/* DMA - see rc32365_dma.h for full list of registers */
5049 +
5050 +#define RC32365_DMA_BASE (RC32365_REG_BASE + 0x38000)
5051 +#define DMA_CHAN_OFFSET 0x14
5052 +
5053 +/* GPIO Controller */
5054 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
5055 +
5056 +/* 16550 UARTs */
5057 +#ifdef __MIPSEB__
5058 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50003)
5059 +#else
5060 +#define RC32300_UART0_BASE (RC32365_REG_BASE + 0x50000)
5061 +#endif
5062 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 0)
5063 +
5064 +/* Ethernet - see rc32365_eth.h for full list of registers */
5065 +
5066 +#define RC32365_ETH_BASE (RC32365_REG_BASE + 0x58000)
5067 +
5068 +#define IDT_CLOCK_MULT 2
5069 +
5070 +/* FLASH (device 1) */
5071 +#define FLASH_BASE 0x08000000
5072 +#define FLASH_SIZE 0x00800000
5073 +
5074 +/* LCD 4-digit display (device 2) */
5075 +#define LCD_DIGIT0 0x0C000003
5076 +#define LCD_DIGIT1 0x0C000002
5077 +#define LCD_DIGIT2 0x0C000001
5078 +#define LCD_DIGIT3 0x0C000000
5079 +
5080 +/* RTC (DS1553) (device 2) */
5081 +#define RTC_BASE 0x0c800000
5082 +/* NVRAM */
5083 +#define NVRAM_BASE RTC_BASE
5084 +#define NVRAM_ENVSIZE_OFF 4
5085 +#define NVRAM_ENVSTART_OFF 32
5086 +
5087 +/* Interrupts routed on 79EB365 board */
5088 +#define RC32365_PCI_INTA_IRQ (GROUP4_IRQ_BASE + 8)
5089 +#define RC32365_PCI_INTB_IRQ (GROUP4_IRQ_BASE + 9)
5090 +#define RC32365_PCI_INTC_IRQ (GROUP4_IRQ_BASE + 10)
5091 +#define RC32365_PCI_INTD_IRQ (GROUP4_IRQ_BASE + 11)
5092 +
5093 +#define RAM_SIZE (32 * 1024 * 1024)
5094 +
5095 +#endif //__IDT_RC32365_H__
5096 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h
5097 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 1970-01-01 01:00:00.000000000 +0100
5098 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci.h 2006-06-18 12:44:28.000000000 +0200
5099 @@ -0,0 +1,515 @@
5100 +/**************************************************************************
5101 + *
5102 + * BRIEF MODULE DESCRIPTION
5103 + * Datatype declaration for IDT 79EB365/336 PCI
5104 + *
5105 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5106 + *
5107 + * This program is free software; you can redistribute it and/or modify it
5108 + * under the terms of the GNU General Public License as published by the
5109 + * Free Software Foundation; either version 2 of the License, or (at your
5110 + * option) any later version.
5111 + *
5112 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5113 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5114 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5115 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5116 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5117 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5118 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5119 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5120 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5121 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5122 + *
5123 + * You should have received a copy of the GNU General Public License along
5124 + * with this program; if not, write to the Free Software Foundation, Inc.,
5125 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5126 + *
5127 + *
5128 + **************************************************************************
5129 + * May 2004 P. Sadik.
5130 + *
5131 + * Initial Release
5132 + *
5133 + *
5134 + *
5135 + **************************************************************************
5136 + */
5137 +
5138 +#ifndef __IDT_RC32365_PCI_H__
5139 +#define __IDT_RC32365_PCI_H__
5140 +
5141 +enum
5142 +{
5143 + PCI0_PhysicalAddress = 0x18068000,
5144 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
5145 +
5146 + PCI0_VirtualAddress = 0xb8068000,
5147 + PCI_VirtualAddress = PCI0_VirtualAddress,
5148 +} ;
5149 +
5150 +enum
5151 +{
5152 + PCI_LbaCount = 4, // Local base addresses.
5153 +} ;
5154 +
5155 +typedef struct
5156 +{
5157 + u32 a ; // Address.
5158 + u32 c ; // Control.
5159 + u32 m ; // mapping.
5160 +} PCI_Map_s ;
5161 +
5162 +typedef struct
5163 +{
5164 + u32 pcic ;
5165 + u32 pcis ;
5166 + u32 pcism ;
5167 + u32 pcicfga ;
5168 + u32 pcicfgd ;
5169 + PCI_Map_s pcilba [PCI_LbaCount] ;
5170 + u32 pcidac ;
5171 + u32 pcidas ;
5172 + u32 pcidasm ;
5173 + u32 pcidad ;
5174 + u32 pcidma8c ;
5175 + u32 pcidma9c ;
5176 + u32 pcitc ;
5177 +} volatile *PCI_t ;
5178 +
5179 +// PCI messaging unit.
5180 +enum
5181 +{
5182 + PCIM_Count = 2,
5183 +} ;
5184 +typedef struct
5185 +{
5186 + u32 pciim [PCIM_Count] ;
5187 + u32 pciom [PCIM_Count] ;
5188 + u32 pciid ;
5189 + u32 pciiic ;
5190 + u32 pciiim ;
5191 + u32 pciiod ;
5192 + u32 pciioic ;
5193 + u32 pciioim ;
5194 +} volatile *PCIM_t ;
5195 +
5196 +/*******************************************************************************
5197 + *
5198 + * PCI Control Register
5199 + *
5200 + ******************************************************************************/
5201 +enum
5202 +{
5203 + PCIC_en_b = 0,
5204 + PCIC_en_m = 0x00000001,
5205 + PCIC_tnr_b = 1,
5206 + PCIC_tnr_m = 0x00000002,
5207 + PCIC_sce_b = 2,
5208 + PCIC_sce_m = 0x00000004,
5209 + PCIC_ien_b = 3,
5210 + PCIC_ien_m = 0x00000008,
5211 + PCIC_aaa_b = 4,
5212 + PCIC_aaa_m = 0x00000010,
5213 + PCIC_eap_b = 5,
5214 + PCIC_eap_m = 0x00000020,
5215 + PCIC_pcim_b = 6,
5216 + PCIC_pcim_m = 0x000001c0,
5217 + PCIC_pcim_disabled_v = 0,
5218 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
5219 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
5220 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
5221 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
5222 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
5223 + PCIC_pcim_reserved6_v = 6,
5224 + PCIC_pcim_reserved7_v = 7,
5225 + PCIC_igm_b = 9,
5226 + PCIC_igm_m = 0x00000200,
5227 +} ;
5228 +
5229 +/*******************************************************************************
5230 + *
5231 + * PCI Status Register
5232 + *
5233 + ******************************************************************************/
5234 +enum {
5235 + PCIS_eed_b = 0,
5236 + PCIS_eed_m = 0x00000001,
5237 + PCIS_wr_b = 1,
5238 + PCIS_wr_m = 0x00000002,
5239 + PCIS_nmi_b = 2,
5240 + PCIS_nmi_m = 0x00000004,
5241 + PCIS_ii_b = 3,
5242 + PCIS_ii_m = 0x00000008,
5243 + PCIS_cwe_b = 4,
5244 + PCIS_cwe_m = 0x00000010,
5245 + PCIS_cre_b = 5,
5246 + PCIS_cre_m = 0x00000020,
5247 + PCIS_mdpe_b = 6,
5248 + PCIS_mdpe_m = 0x00000040,
5249 + PCIS_sta_b = 7,
5250 + PCIS_sta_m = 0x00000080,
5251 + PCIS_rta_b = 8,
5252 + PCIS_rta_m = 0x00000100,
5253 + PCIS_rma_b = 9,
5254 + PCIS_rma_m = 0x00000200,
5255 + PCIS_sse_b = 10,
5256 + PCIS_sse_m = 0x00000400,
5257 + PCIS_ose_b = 11,
5258 + PCIS_ose_m = 0x00000800,
5259 + PCIS_pe_b = 12,
5260 + PCIS_pe_m = 0x00001000,
5261 + PCIS_tae_b = 13,
5262 + PCIS_tae_m = 0x00002000,
5263 + PCIS_rle_b = 14,
5264 + PCIS_rle_m = 0x00004000,
5265 + PCIS_bme_b = 15,
5266 + PCIS_bme_m = 0x00008000,
5267 + PCIS_prd_b = 16,
5268 + PCIS_prd_m = 0x00010000,
5269 + PCIS_rip_b = 17,
5270 + PCIS_rip_m = 0x00020000,
5271 +} ;
5272 +
5273 +/*******************************************************************************
5274 + *
5275 + * PCI Status Mask Register
5276 + *
5277 + ******************************************************************************/
5278 +enum {
5279 + PCISM_eed_b = 0,
5280 + PCISM_eed_m = 0x00000001,
5281 + PCISM_wr_b = 1,
5282 + PCISM_wr_m = 0x00000002,
5283 + PCISM_nmi_b = 2,
5284 + PCISM_nmi_m = 0x00000004,
5285 + PCISM_ii_b = 3,
5286 + PCISM_ii_m = 0x00000008,
5287 + PCISM_cwe_b = 4,
5288 + PCISM_cwe_m = 0x00000010,
5289 + PCISM_cre_b = 5,
5290 + PCISM_cre_m = 0x00000020,
5291 + PCISM_mdpe_b = 6,
5292 + PCISM_mdpe_m = 0x00000040,
5293 + PCISM_sta_b = 7,
5294 + PCISM_sta_m = 0x00000080,
5295 + PCISM_rta_b = 8,
5296 + PCISM_rta_m = 0x00000100,
5297 + PCISM_rma_b = 9,
5298 + PCISM_rma_m = 0x00000200,
5299 + PCISM_sse_b = 10,
5300 + PCISM_sse_m = 0x00000400,
5301 + PCISM_ose_b = 11,
5302 + PCISM_ose_m = 0x00000800,
5303 + PCISM_pe_b = 12,
5304 + PCISM_pe_m = 0x00001000,
5305 + PCISM_tae_b = 13,
5306 + PCISM_tae_m = 0x00002000,
5307 + PCISM_rle_b = 14,
5308 + PCISM_rle_m = 0x00004000,
5309 + PCISM_bme_b = 15,
5310 + PCISM_bme_m = 0x00008000,
5311 + PCISM_prd_b = 16,
5312 + PCISM_prd_m = 0x00010000,
5313 + PCISM_rip_b = 17,
5314 + PCISM_rip_m = 0x00020000,
5315 +} ;
5316 +
5317 +/*******************************************************************************
5318 + *
5319 + * PCI Configuration Address Register
5320 + *
5321 + ******************************************************************************/
5322 +enum {
5323 + PCICFGA_reg_b = 2,
5324 + PCICFGA_reg_m = 0x000000fc,
5325 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
5326 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
5327 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
5328 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
5329 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
5330 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
5331 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
5332 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
5333 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
5334 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
5335 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
5336 + PCICFGA_reg_pba0m_v = 0x48>>2,
5337 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
5338 + PCICFGA_reg_pba1m_v = 0x50>>2,
5339 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
5340 + PCICFGA_reg_pba2m_v = 0x58>>2,
5341 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
5342 + PCICFGA_reg_pba3m_v = 0x60>>2,
5343 + PCICFGA_reg_pmgt_v = 0x64>>2,
5344 + PCICFGA_func_b = 8,
5345 + PCICFGA_func_m = 0x00000700,
5346 + PCICFGA_dev_b = 11,
5347 + PCICFGA_dev_m = 0x0000f800,
5348 + PCICFGA_dev_internal_v = 0,
5349 + PCICFGA_bus_b = 16,
5350 + PCICFGA_bus_m = 0x00ff0000,
5351 + PCICFGA_bus_type0_v = 0, //local bus
5352 + PCICFGA_en_b = 31, // read only
5353 + PCICFGA_en_m = 0x80000000,
5354 +} ;
5355 +
5356 +enum {
5357 + PCFGID_vendor_b = 0,
5358 + PCFGID_vendor_m = 0x0000ffff,
5359 + PCFGID_vendor_IDT_v = 0x111d,
5360 + PCFGID_device_b = 16,
5361 + PCFGID_device_m = 0xffff0000,
5362 + PCFGID_device_Acaciade_v = 0x0207,
5363 +
5364 + PCFG04_command_ioena_b = 1,
5365 + PCFG04_command_ioena_m = 0x00000001,
5366 + PCFG04_command_memena_b = 2,
5367 + PCFG04_command_memena_m = 0x00000002,
5368 + PCFG04_command_bmena_b = 3,
5369 + PCFG04_command_bmena_m = 0x00000004,
5370 + PCFG04_command_mwinv_b = 5,
5371 + PCFG04_command_mwinv_m = 0x00000010,
5372 + PCFG04_command_parena_b = 7,
5373 + PCFG04_command_parena_m = 0x00000040,
5374 + PCFG04_command_serrena_b = 9,
5375 + PCFG04_command_serrena_m = 0x00000100,
5376 + PCFG04_command_fastbbena_b = 10,
5377 + PCFG04_command_fastbbena_m = 0x00000200,
5378 + PCFG04_status_b = 16,
5379 + PCFG04_status_m = 0xffff0000,
5380 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
5381 + PCFG04_status_66MHz_m = 0x00200000,
5382 + PCFG04_status_fbb_b = 23,
5383 + PCFG04_status_fbb_m = 0x00800000,
5384 + PCFG04_status_mdpe_b = 24,
5385 + PCFG04_status_mdpe_m = 0x01000000,
5386 + PCFG04_status_dst_b = 25,
5387 + PCFG04_status_dst_m = 0x06000000,
5388 + PCFG04_status_sta_b = 27,
5389 + PCFG04_status_sta_m = 0x08000000,
5390 + PCFG04_status_rta_b = 28,
5391 + PCFG04_status_rta_m = 0x10000000,
5392 + PCFG04_status_rma_b = 29,
5393 + PCFG04_status_rma_m = 0x20000000,
5394 + PCFG04_status_sse_b = 30,
5395 + PCFG04_status_sse_m = 0x40000000,
5396 + PCFG04_status_pe_b = 31,
5397 + PCFG04_status_pe_m = 0x40000000,
5398 +
5399 + PCFG08_revId_b = 0,
5400 + PCFG08_revId_m = 0x000000ff,
5401 + PCFG08_classCode_b = 0,
5402 + PCFG08_classCode_m = 0xffffff00,
5403 + PCFG08_classCode_bridge_v = 06,
5404 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
5405 + PCFG0C_cacheline_b = 0,
5406 + PCFG0C_cacheline_m = 0x000000ff,
5407 + PCFG0C_masterLatency_b = 8,
5408 + PCFG0C_masterLatency_m = 0x0000ff00,
5409 + PCFG0C_headerType_b = 16,
5410 + PCFG0C_headerType_m = 0x00ff0000,
5411 + PCFG0C_bist_b = 24,
5412 + PCFG0C_bist_m = 0xff000000,
5413 +
5414 + PCIPBA_msi_b = 0,
5415 + PCIPBA_msi_m = 0x00000001,
5416 + PCIPBA_p_b = 3,
5417 + PCIPBA_p_m = 0x00000004,
5418 + PCIPBA_baddr_b = 8,
5419 + PCIPBA_baddr_m = 0xffffff00,
5420 +
5421 + PCFGSS_vendorId_b = 0,
5422 + PCFGSS_vendorId_m = 0x0000ffff,
5423 + PCFGSS_id_b = 16,
5424 + PCFGSS_id_m = 0xffff0000,
5425 +
5426 + PCFG3C_interruptLine_b = 0,
5427 + PCFG3C_interruptLine_m = 0x000000ff,
5428 + PCFG3C_interruptPin_b = 8,
5429 + PCFG3C_interruptPin_m = 0x0000ff00,
5430 + PCFG3C_minGrant_b = 16,
5431 + PCFG3C_minGrant_m = 0x00ff0000,
5432 + PCFG3C_maxLat_b = 24,
5433 + PCFG3C_maxLat_m = 0xff000000,
5434 +
5435 + PCIPBAC_msi_b = 0,
5436 + PCIPBAC_msi_m = 0x00000001,
5437 + PCIPBAC_p_b = 1,
5438 + PCIPBAC_p_m = 0x00000002,
5439 + PCIPBAC_size_b = 2,
5440 + PCIPBAC_size_m = 0x0000007c,
5441 + PCIPBAC_sb_b = 7,
5442 + PCIPBAC_sb_m = 0x00000080,
5443 + PCIPBAC_pp_b = 8,
5444 + PCIPBAC_pp_m = 0x00000100,
5445 + PCIPBAC_mr_b = 9,
5446 + PCIPBAC_mr_m = 0x00000600,
5447 + PCIPBAC_mr_read_v =0, //no prefetching
5448 + PCIPBAC_mr_readLine_v =1,
5449 + PCIPBAC_mr_readMult_v =2,
5450 + PCIPBAC_mrl_b = 11,
5451 + PCIPBAC_mrl_m = 0x00000800,
5452 + PCIPBAC_mrm_b = 12,
5453 + PCIPBAC_mrm_m = 0x00001000,
5454 + PCIPBAC_trp_b = 13,
5455 + PCIPBAC_trp_m = 0x00002000,
5456 +
5457 + PCFG40_trdyTimeout_b = 0,
5458 + PCFG40_trdyTimeout_m = 0x000000ff,
5459 + PCFG40_retryLim_b = 8,
5460 + PCFG40_retryLim_m = 0x0000ff00,
5461 +};
5462 +
5463 +/*******************************************************************************
5464 + *
5465 + * PCI Local Base Address [0|1|2|3] Register
5466 + *
5467 + ******************************************************************************/
5468 +enum {
5469 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
5470 + PCILBA_baddr_m = 0xffffff00,
5471 +} ;
5472 +/*******************************************************************************
5473 + *
5474 + * PCI Local Base Address Control Register
5475 + *
5476 + ******************************************************************************/
5477 +enum {
5478 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
5479 + PCILBAC_msi_m = 0x00000001,
5480 + PCILBAC_msi_mem_v = 0,
5481 + PCILBAC_msi_io_v = 1,
5482 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
5483 + PCILBAC_size_m = 0x0000007c,
5484 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
5485 + PCILBAC_sb_m = 0x00000080,
5486 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
5487 + PCILBAC_rt_m = 0x00000100,
5488 + PCILBAC_rt_noprefetch_v = 0, // mem read
5489 + PCILBAC_rt_prefetch_v = 1, // mem readline
5490 +} ;
5491 +
5492 +/*******************************************************************************
5493 + *
5494 + * PCI Local Base Address [0|1|2|3] Mapping Register
5495 + *
5496 + ******************************************************************************/
5497 +enum {
5498 + PCILBAM_maddr_b = 8,
5499 + PCILBAM_maddr_m = 0xffffff00,
5500 +} ;
5501 +
5502 +/*******************************************************************************
5503 + *
5504 + * PCI Decoupled Access Control Register
5505 + *
5506 + ******************************************************************************/
5507 +enum {
5508 + PCIDAC_den_b = 0,
5509 + PCIDAC_den_m = 0x00000001,
5510 +} ;
5511 +
5512 +/*******************************************************************************
5513 + *
5514 + * PCI Decoupled Access Status Register
5515 + *
5516 + ******************************************************************************/
5517 +enum {
5518 + PCIDAS_d_b = 0,
5519 + PCIDAS_d_m = 0x00000001,
5520 + PCIDAS_b_b = 1,
5521 + PCIDAS_b_m = 0x00000002,
5522 + PCIDAS_e_b = 2,
5523 + PCIDAS_e_m = 0x00000004,
5524 + PCIDAS_ofe_b = 3,
5525 + PCIDAS_ofe_m = 0x00000008,
5526 + PCIDAS_off_b = 4,
5527 + PCIDAS_off_m = 0x00000010,
5528 + PCIDAS_ife_b = 5,
5529 + PCIDAS_ife_m = 0x00000020,
5530 + PCIDAS_iff_b = 6,
5531 + PCIDAS_iff_m = 0x00000040,
5532 +} ;
5533 +
5534 +/*******************************************************************************
5535 + *
5536 + * PCI DMA Channel 8 Configuration Register
5537 + *
5538 + ******************************************************************************/
5539 +enum
5540 +{
5541 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
5542 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
5543 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
5544 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
5545 +} ;
5546 +
5547 +/*******************************************************************************
5548 + *
5549 + * PCI DMA Channel 9 Configuration Register
5550 + *
5551 + ******************************************************************************/
5552 +enum
5553 +{
5554 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
5555 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
5556 +} ;
5557 +
5558 +/*******************************************************************************
5559 + *
5560 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
5561 + *
5562 + ******************************************************************************/
5563 +enum {
5564 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
5565 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
5566 + // These are for reads (DMA channel 8)
5567 + PCIDMAD_devcmd_mr_v = 0, //memory read
5568 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
5569 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
5570 + PCIDMAD_devcmd_ior_v = 3, //I/O read
5571 + // These are for writes (DMA channel 9)
5572 + PCIDMAD_devcmd_mw_v = 0, //memory write
5573 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
5574 + PCIDMAD_devcmd_iow_v = 3, //I/O write
5575 +
5576 + // Swap byte field applies to both DMA channel 8 and 9
5577 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
5578 + PCIDMAD_sb_m = 0x01000000, // swap byte field
5579 +} ;
5580 +
5581 +
5582 +/*******************************************************************************
5583 + *
5584 + * PCI Target Control Register
5585 + *
5586 + ******************************************************************************/
5587 +enum
5588 +{
5589 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
5590 + PCITC_rtimer_m = 0x000000ff,
5591 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
5592 + PCITC_dtimer_m = 0x0000ff00,
5593 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
5594 + PCITC_rdr_m = 0x00040000,
5595 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
5596 + PCITC_ddt_m = 0x00080000,
5597 +} ;
5598 +/*******************************************************************************
5599 + *
5600 + * PCI messaging unit [applies to both inbound and outbound registers ]
5601 + *
5602 + ******************************************************************************/
5603 +enum
5604 +{
5605 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5606 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
5607 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5608 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
5609 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
5610 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
5611 +};
5612 +
5613 +
5614 +#endif // __IDT_RC32365_PCI_H__
5615 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h
5616 --- linux-2.6.17/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 1970-01-01 01:00:00.000000000 +0100
5617 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32300/rc32365_pci_v.h 2006-06-18 12:44:28.000000000 +0200
5618 @@ -0,0 +1,217 @@
5619 +/**************************************************************************
5620 + *
5621 + * BRIEF MODULE DESCRIPTION
5622 + * PCI header values for IDT 79EB365/336
5623 + *
5624 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5625 + *
5626 + * This program is free software; you can redistribute it and/or modify it
5627 + * under the terms of the GNU General Public License as published by the
5628 + * Free Software Foundation; either version 2 of the License, or (at your
5629 + * option) any later version.
5630 + *
5631 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5632 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5633 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5634 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5635 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5636 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5637 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5638 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5639 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5640 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5641 + *
5642 + * You should have received a copy of the GNU General Public License along
5643 + * with this program; if not, write to the Free Software Foundation, Inc.,
5644 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5645 + *
5646 + *
5647 + **************************************************************************
5648 + * May 2004 P. Sadik.
5649 + *
5650 + * Initial Release
5651 + *
5652 + *
5653 + *
5654 + **************************************************************************
5655 + */
5656 +
5657 +#ifndef __IDT_RC32365_PCI_V_H__
5658 +#define __IDT_RC32365_PCI_V_H__
5659 +
5660 +
5661 +#define PCI_MSG_VirtualAddress 0xB806C010
5662 +#define rc32365_pci ((volatile PCI_t) PCI0_VirtualAddress)
5663 +#define rc32365_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
5664 +
5665 +#define PCIM_SHFT 0x6
5666 +#define PCIM_BIT_LEN 0x7
5667 +#define PCIM_H_EA 0x3
5668 +#define PCIM_H_IA_FIX 0x4
5669 +#define PCIM_H_IA_RR 0x5
5670 +
5671 +#define PCI_ADDR_START 0x50000000
5672 +
5673 +#define CPUTOPCI_MEM_WIN 0x02000000
5674 +#define CPUTOPCI_IO_WIN 0x00100000
5675 +#define PCILBA_SIZE_SHFT 2
5676 +#define PCILBA_SIZE_MASK 0x1F
5677 +#define SIZE_256MB 0x1C
5678 +#define SIZE_128MB 0x1B
5679 +#define SIZE_64MB 0x1A
5680 +#define SIZE_32MB 0x19
5681 +#define SIZE_16MB 0x18
5682 +#define SIZE_4MB 0x16
5683 +#define SIZE_2MB 0x15
5684 +#define SIZE_1MB 0x14
5685 +#define CEDAR_CONFIG0_ADDR 0x80000000
5686 +#define CEDAR_CONFIG1_ADDR 0x80000004
5687 +#define CEDAR_CONFIG2_ADDR 0x80000008
5688 +#define CEDAR_CONFIG3_ADDR 0x8000000C
5689 +#define CEDAR_CONFIG4_ADDR 0x80000010
5690 +#define CEDAR_CONFIG5_ADDR 0x80000014
5691 +#define CEDAR_CONFIG6_ADDR 0x80000018
5692 +#define CEDAR_CONFIG7_ADDR 0x8000001C
5693 +#define CEDAR_CONFIG8_ADDR 0x80000020
5694 +#define CEDAR_CONFIG9_ADDR 0x80000024
5695 +#define CEDAR_CONFIG10_ADDR 0x80000028
5696 +#define CEDAR_CONFIG11_ADDR 0x8000002C
5697 +#define CEDAR_CONFIG12_ADDR 0x80000030
5698 +#define CEDAR_CONFIG13_ADDR 0x80000034
5699 +#define CEDAR_CONFIG14_ADDR 0x80000038
5700 +#define CEDAR_CONFIG15_ADDR 0x8000003C
5701 +#define CEDAR_CONFIG16_ADDR 0x80000040
5702 +#define CEDAR_CONFIG17_ADDR 0x80000044
5703 +#define CEDAR_CONFIG18_ADDR 0x80000048
5704 +#define CEDAR_CONFIG19_ADDR 0x8000004C
5705 +#define CEDAR_CONFIG20_ADDR 0x80000050
5706 +#define CEDAR_CONFIG21_ADDR 0x80000054
5707 +#define CEDAR_CONFIG22_ADDR 0x80000058
5708 +#define CEDAR_CONFIG23_ADDR 0x8000005C
5709 +#define CEDAR_CONFIG24_ADDR 0x80000060
5710 +#define CEDAR_CONFIG25_ADDR 0x80000064
5711 +#define CEDAR_CMD (PCFG04_command_ioena_m | \
5712 + PCFG04_command_memena_m | \
5713 + PCFG04_command_bmena_m | \
5714 + PCFG04_command_mwinv_m | \
5715 + PCFG04_command_parena_m | \
5716 + PCFG04_command_serrena_m )
5717 +
5718 +#define CEDAR_STAT (PCFG04_status_mdpe_m | \
5719 + PCFG04_status_sta_m | \
5720 + PCFG04_status_rta_m | \
5721 + PCFG04_status_rma_m | \
5722 + PCFG04_status_sse_m | \
5723 + PCFG04_status_pe_m)
5724 +
5725 +#define CEDAR_CNFG1 ((CEDAR_STAT << 16) | \
5726 + CEDAR_CMD)
5727 +
5728 +#define CEDAR_REVID 0
5729 +#define CEDAR_CLASS_CODE 0
5730 +#define CEDAR_CNFG2 ((CEDAR_CLASS_CODE << 8) | \
5731 + CEDAR_REVID)
5732 +
5733 +#define CEDAR_CACHE_LINE_SIZE 4
5734 +#define CEDAR_MASTER_LAT 0x3c
5735 +#define CEDAR_HEADER_TYPE 0
5736 +#define CEDAR_BIST 0
5737 +
5738 +#define CEDAR_CNFG3 ((CEDAR_BIST << 24) | \
5739 + (CEDAR_HEADER_TYPE << 16) | \
5740 + (CEDAR_MASTER_LAT << 8) | \
5741 + CEDAR_CACHE_LINE_SIZE)
5742 +
5743 +#define CEDAR_BAR0 0x00000008 /* 128 MB Memory */
5744 +#define CEDAR_BAR1 0x18800001 /* 1 MB IO */
5745 +#define CEDAR_BAR2 0x18000001 /* 2 MB IO window for Cedar
5746 + internal Registers */
5747 +#define CEDAR_BAR3 0x48000008 /* Spare 128 MB Memory */
5748 +
5749 +#define CEDAR_CNFG4 CEDAR_BAR0
5750 +#define CEDAR_CNFG5 CEDAR_BAR1
5751 +#define CEDAR_CNFG6 CEDAR_BAR2
5752 +#define CEDAR_CNFG7 CEDAR_BAR3
5753 +
5754 +#define CEDAR_SUBSYS_VENDOR_ID 0
5755 +#define CEDAR_SUBSYSTEM_ID 0
5756 +#define CEDAR_CNFG8 0
5757 +#define CEDAR_CNFG9 0
5758 +#define CEDAR_CNFG10 0
5759 +#define CEDAR_CNFG11 ((CEDAR_SUBSYS_VENDOR_ID << 16) | \
5760 + CEDAR_SUBSYSTEM_ID)
5761 +#define CEDAR_INT_LINE 1
5762 +#define CEDAR_INT_PIN 1
5763 +#define CEDAR_MIN_GNT 8
5764 +#define CEDAR_MAX_LAT 0x38
5765 +#define CEDAR_CNFG12 0
5766 +#define CEDAR_CNFG13 0
5767 +#define CEDAR_CNFG14 0
5768 +#define CEDAR_CNFG15 ((CEDAR_MAX_LAT << 24) | \
5769 + (CEDAR_MIN_GNT << 16) | \
5770 + (CEDAR_INT_PIN << 8) | \
5771 + CEDAR_INT_LINE)
5772 +#define CEDAR_RETRY_LIMIT 0x80
5773 +#define CEDAR_TRDY_LIMIT 0x80
5774 +#define CEDAR_CNFG16 ((CEDAR_RETRY_LIMIT << 8) | \
5775 + CEDAR_TRDY_LIMIT)
5776 +#define PCI_PBAxC_R 0x0
5777 +#define PCI_PBAxC_RL 0x1
5778 +#define PCI_PBAxC_RM 0x2
5779 +#define SIZE_SHFT 2
5780 +#ifdef __MIPSEB__
5781 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5782 + PCIPBAC_pp_m | \
5783 + PCIPBAC_sb_m | \
5784 + (SIZE_128MB << SIZE_SHFT) | \
5785 + PCIPBAC_p_m)
5786 +#else
5787 +
5788 +#define CEDAR_PBA0C (((1 & 0x3) << PCIPBAC_mr_b) | \
5789 + PCIPBAC_pp_m | \
5790 + (SIZE_128MB << SIZE_SHFT) | \
5791 + PCIPBAC_p_m)
5792 +#endif
5793 +#define CEDAR_CNFG17 CEDAR_PBA0C
5794 +#define CEDAR_PBA0M 0x0
5795 +#define CEDAR_CNFG18 CEDAR_PBA0M
5796 +
5797 +#ifdef __MIPSEB__
5798 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5799 + PCIPBAC_sb_m | \
5800 + PCIPBAC_msi_m)
5801 +#else
5802 +#define CEDAR_PBA1C ((SIZE_1MB << SIZE_SHFT) | \
5803 + PCIPBAC_msi_m)
5804 +#endif
5805 +#define CEDAR_CNFG19 CEDAR_PBA1C
5806 +#define CEDAR_PBA1M 0x0
5807 +#define CEDAR_CNFG20 CEDAR_PBA1M
5808 +
5809 +#ifdef __MIPSEB__
5810 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5811 + PCIPBAC_sb_m | \
5812 + PCIPBAC_msi_m)
5813 +#else
5814 +#define CEDAR_PBA2C ((SIZE_2MB << SIZE_SHFT) | \
5815 + PCIPBAC_msi_m)
5816 +#endif
5817 +
5818 +#define CEDAR_CNFG21 CEDAR_PBA2C
5819 +#define CEDAR_PBA2M 0x18000000
5820 +#define CEDAR_CNFG22 CEDAR_PBA2M
5821 +
5822 +#ifdef __MIPSEB__
5823 +#define CEDAR_PBA3C PCIPBAC_sb_m
5824 +#else
5825 +#define CEDAR_PBA3C 0
5826 +#endif
5827 +
5828 +#define CEDAR_CNFG23 CEDAR_PBA3C
5829 +#define CEDAR_PBA3M 0
5830 +#define CEDAR_CNFG24 CEDAR_PBA3M
5831 +
5832 +#define PCITC_DTIMER_VAL 8
5833 +#define PCITC_RTIMER_VAL 0x10
5834 +
5835 +#endif //__IDT_RC32365_PCI_V_H__
5836 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h
5837 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 1970-01-01 01:00:00.000000000 +0100
5838 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma.h 2006-06-18 12:44:28.000000000 +0200
5839 @@ -0,0 +1,205 @@
5840 +/**************************************************************************
5841 + *
5842 + * BRIEF MODULE DESCRIPTION
5843 + * DMA register definition
5844 + *
5845 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
5846 + *
5847 + * This program is free software; you can redistribute it and/or modify it
5848 + * under the terms of the GNU General Public License as published by the
5849 + * Free Software Foundation; either version 2 of the License, or (at your
5850 + * option) any later version.
5851 + *
5852 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
5853 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
5854 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
5855 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
5856 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5857 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
5858 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5859 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
5860 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5861 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5862 + *
5863 + * You should have received a copy of the GNU General Public License along
5864 + * with this program; if not, write to the Free Software Foundation, Inc.,
5865 + * 675 Mass Ave, Cambridge, MA 02139, USA.
5866 + *
5867 + *
5868 + **************************************************************************
5869 + * May 2004 rkt, neb
5870 + *
5871 + * Initial Release
5872 + *
5873 + *
5874 + *
5875 + **************************************************************************
5876 + */
5877 +
5878 +#ifndef __IDT_DMA_H__
5879 +#define __IDT_DMA_H__
5880 +
5881 +enum
5882 +{
5883 + DMA0_PhysicalAddress = 0x18040000,
5884 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
5885 +
5886 + DMA0_VirtualAddress = 0xb8040000,
5887 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
5888 +} ;
5889 +
5890 +/*
5891 + * DMA descriptor (in physical memory).
5892 + */
5893 +
5894 +typedef struct DMAD_s
5895 +{
5896 + u32 control ; // Control. use DMAD_*
5897 + u32 ca ; // Current Address.
5898 + u32 devcs ; // Device control and status.
5899 + u32 link ; // Next descriptor in chain.
5900 +} volatile *DMAD_t ;
5901 +
5902 +enum
5903 +{
5904 + DMAD_size = sizeof (struct DMAD_s),
5905 + DMAD_count_b = 0, // in DMAD_t -> control
5906 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
5907 + DMAD_ds_b = 20, // in DMAD_t -> control
5908 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
5909 + DMAD_ds_ethRcv0_v = 0,
5910 + DMAD_ds_ethXmt0_v = 0,
5911 + DMAD_ds_memToFifo_v = 0,
5912 + DMAD_ds_fifoToMem_v = 0,
5913 + DMAD_ds_pciToMem_v = 0,
5914 + DMAD_ds_memToPci_v = 0,
5915 +
5916 + DMAD_devcmd_b = 22, // in DMAD_t -> control
5917 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
5918 + DMAD_devcmd_byte_v = 0, //memory-to-memory
5919 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
5920 + DMAD_devcmd_word_v = 2, //memory-to-memory
5921 + DMAD_devcmd_2words_v = 3, //memory-to-memory
5922 + DMAD_devcmd_4words_v = 4, //memory-to-memory
5923 + DMAD_devcmd_6words_v = 5, //memory-to-memory
5924 + DMAD_devcmd_8words_v = 6, //memory-to-memory
5925 + DMAD_devcmd_16words_v = 7, //memory-to-memory
5926 + DMAD_cof_b = 25, // chain on finished
5927 + DMAD_cof_m = 0x02000000, //
5928 + DMAD_cod_b = 26, // chain on done
5929 + DMAD_cod_m = 0x04000000, //
5930 + DMAD_iof_b = 27, // interrupt on finished
5931 + DMAD_iof_m = 0x08000000, //
5932 + DMAD_iod_b = 28, // interrupt on done
5933 + DMAD_iod_m = 0x10000000, //
5934 + DMAD_t_b = 29, // terminated
5935 + DMAD_t_m = 0x20000000, //
5936 + DMAD_d_b = 30, // done
5937 + DMAD_d_m = 0x40000000, //
5938 + DMAD_f_b = 31, // finished
5939 + DMAD_f_m = 0x80000000, //
5940 +} ;
5941 +
5942 +/*
5943 + * DMA register (within Internal Register Map).
5944 + */
5945 +
5946 +struct DMA_Chan_s
5947 +{
5948 + u32 dmac ; // Control.
5949 + u32 dmas ; // Status.
5950 + u32 dmasm ; // Mask.
5951 + u32 dmadptr ; // Descriptor pointer.
5952 + u32 dmandptr ; // Next descriptor pointer.
5953 +};
5954 +
5955 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
5956 +
5957 +//DMA_Channels use DMACH_count instead
5958 +
5959 +enum
5960 +{
5961 + DMAC_run_b = 0, //
5962 + DMAC_run_m = 0x00000001, //
5963 + DMAC_dm_b = 1, // done mask
5964 + DMAC_dm_m = 0x00000002, //
5965 + DMAC_mode_b = 2, //
5966 + DMAC_mode_m = 0x0000000c, //
5967 + DMAC_mode_auto_v = 0,
5968 + DMAC_mode_burst_v = 1,
5969 + DMAC_mode_transfer_v = 2, //usually used
5970 + DMAC_mode_reserved_v = 3,
5971 + DMAC_a_b = 4, //
5972 + DMAC_a_m = 0x00000010, //
5973 +
5974 + DMAS_f_b = 0, // finished (sticky)
5975 + DMAS_f_m = 0x00000001, //
5976 + DMAS_d_b = 1, // done (sticky)
5977 + DMAS_d_m = 0x00000002, //
5978 + DMAS_c_b = 2, // chain (sticky)
5979 + DMAS_c_m = 0x00000004, //
5980 + DMAS_e_b = 3, // error (sticky)
5981 + DMAS_e_m = 0x00000008, //
5982 + DMAS_h_b = 4, // halt (sticky)
5983 + DMAS_h_m = 0x00000010, //
5984 +
5985 + DMASM_f_b = 0, // finished (1=mask)
5986 + DMASM_f_m = 0x00000001, //
5987 + DMASM_d_b = 1, // done (1=mask)
5988 + DMASM_d_m = 0x00000002, //
5989 + DMASM_c_b = 2, // chain (1=mask)
5990 + DMASM_c_m = 0x00000004, //
5991 + DMASM_e_b = 3, // error (1=mask)
5992 + DMASM_e_m = 0x00000008, //
5993 + DMASM_h_b = 4, // halt (1=mask)
5994 + DMASM_h_m = 0x00000010, //
5995 +} ;
5996 +
5997 +/*
5998 + * DMA channel definitions
5999 + */
6000 +
6001 +enum
6002 +{
6003 + DMACH_ethRcv0 = 0,
6004 + DMACH_ethXmt0 = 1,
6005 + DMACH_memToFifo = 2,
6006 + DMACH_fifoToMem = 3,
6007 + DMACH_pciToMem = 4,
6008 + DMACH_memToPci = 5,
6009 +
6010 + DMACH_count //must be last
6011 +};
6012 +
6013 +
6014 +typedef struct DMAC_s
6015 +{
6016 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
6017 +} volatile *DMA_t ;
6018 +
6019 +
6020 +/*
6021 + * External DMA parameters
6022 +*/
6023 +
6024 +enum
6025 +{
6026 + DMADEVCMD_ts_b = 0, // ts field in devcmd
6027 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
6028 + DMADEVCMD_ts_byte_v = 0,
6029 + DMADEVCMD_ts_halfword_v = 1,
6030 + DMADEVCMD_ts_word_v = 2,
6031 + DMADEVCMD_ts_2word_v = 3,
6032 + DMADEVCMD_ts_4word_v = 4,
6033 + DMADEVCMD_ts_6word_v = 5,
6034 + DMADEVCMD_ts_8word_v = 6,
6035 + DMADEVCMD_ts_16word_v = 7
6036 +};
6037 +
6038 +
6039 +#endif // __IDT_DMA_H__
6040 +
6041 +
6042 +
6043 +
6044 +
6045 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h
6046 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 1970-01-01 01:00:00.000000000 +0100
6047 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_dma_v.h 2006-06-18 12:44:28.000000000 +0200
6048 @@ -0,0 +1,89 @@
6049 +/**************************************************************************
6050 + *
6051 + * BRIEF MODULE DESCRIPTION
6052 + * Definitions for DMA controller.
6053 + *
6054 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6055 + *
6056 + * This program is free software; you can redistribute it and/or modify it
6057 + * under the terms of the GNU General Public License as published by the
6058 + * Free Software Foundation; either version 2 of the License, or (at your
6059 + * option) any later version.
6060 + *
6061 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6062 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6063 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6064 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6065 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6066 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6067 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6068 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6069 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6070 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6071 + *
6072 + * You should have received a copy of the GNU General Public License along
6073 + * with this program; if not, write to the Free Software Foundation, Inc.,
6074 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6075 + *
6076 + *
6077 + **************************************************************************
6078 + * May 2004 rkt, neb.
6079 + *
6080 + * Initial Release
6081 + *
6082 + *
6083 + *
6084 + **************************************************************************
6085 + */
6086 +
6087 +#ifndef __IDT_DMA_V_H__
6088 +#define __IDT_DMA_V_H__
6089 +
6090 +#include <asm/idt-boards/rc32434/rc32434_dma.h>
6091 +#include <asm/idt-boards/rc32434/rc32434.h>
6092 +
6093 +#define DMA_CHAN_OFFSET 0x14
6094 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
6095 +#define DMA_COUNT(count) \
6096 + ((count) & DMAD_count_m)
6097 +
6098 +#define DMA_HALT_TIMEOUT 500
6099 +
6100 +
6101 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
6102 +{
6103 + int timeout=1;
6104 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
6105 + rc32434_writel(0, &ch->dmac);
6106 +
6107 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
6108 + if (rc32434_readl(&ch->dmas) & DMAS_h_m) {
6109 + rc32434_writel(0, &ch->dmas);
6110 + break;
6111 + }
6112 + }
6113 +
6114 + }
6115 +
6116 + return timeout ? 0 : 1;
6117 +}
6118 +
6119 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
6120 +{
6121 + rc32434_writel(0, &ch->dmandptr);
6122 + rc32434_writel(dma_addr, &ch->dmadptr);
6123 +}
6124 +
6125 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
6126 +{
6127 + rc32434_writel(dma_addr, &ch->dmandptr);
6128 +}
6129 +
6130 +#endif // __IDT_DMA_V_H__
6131 +
6132 +
6133 +
6134 +
6135 +
6136 +
6137 +
6138 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h
6139 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
6140 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth.h 2006-06-18 12:44:28.000000000 +0200
6141 @@ -0,0 +1,333 @@
6142 +/**************************************************************************
6143 + *
6144 + * BRIEF MODULE DESCRIPTION
6145 + * Ethernet register definition
6146 + *
6147 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6148 + *
6149 + * This program is free software; you can redistribute it and/or modify it
6150 + * under the terms of the GNU General Public License as published by the
6151 + * Free Software Foundation; either version 2 of the License, or (at your
6152 + * option) any later version.
6153 + *
6154 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6155 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6156 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6157 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6158 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6159 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6160 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6161 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6162 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6163 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6164 + *
6165 + * You should have received a copy of the GNU General Public License along
6166 + * with this program; if not, write to the Free Software Foundation, Inc.,
6167 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6168 + *
6169 + *
6170 + **************************************************************************
6171 + * May 2004 rkt, neb.
6172 + *
6173 + * Initial Release
6174 + *
6175 + *
6176 + *
6177 + **************************************************************************
6178 + */
6179 +
6180 +#ifndef __IDT_ETH_H__
6181 +#define __IDT_ETH_H__
6182 +
6183 +
6184 +enum
6185 +{
6186 + ETH0_PhysicalAddress = 0x18060000,
6187 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
6188 +
6189 + ETH0_VirtualAddress = 0xb8060000,
6190 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
6191 +} ;
6192 +
6193 +typedef struct
6194 +{
6195 + u32 ethintfc ;
6196 + u32 ethfifott ;
6197 + u32 etharc ;
6198 + u32 ethhash0 ;
6199 + u32 ethhash1 ;
6200 + u32 ethu0 [4] ; // Reserved.
6201 + u32 ethpfs ;
6202 + u32 ethmcp ;
6203 + u32 eth_u1 [10] ; // Reserved.
6204 + u32 ethspare ;
6205 + u32 eth_u2 [42] ; // Reserved.
6206 + u32 ethsal0 ;
6207 + u32 ethsah0 ;
6208 + u32 ethsal1 ;
6209 + u32 ethsah1 ;
6210 + u32 ethsal2 ;
6211 + u32 ethsah2 ;
6212 + u32 ethsal3 ;
6213 + u32 ethsah3 ;
6214 + u32 ethrbc ;
6215 + u32 ethrpc ;
6216 + u32 ethrupc ;
6217 + u32 ethrfc ;
6218 + u32 ethtbc ;
6219 + u32 ethgpf ;
6220 + u32 eth_u9 [50] ; // Reserved.
6221 + u32 ethmac1 ;
6222 + u32 ethmac2 ;
6223 + u32 ethipgt ;
6224 + u32 ethipgr ;
6225 + u32 ethclrt ;
6226 + u32 ethmaxf ;
6227 + u32 eth_u10 ; // Reserved.
6228 + u32 ethmtest ;
6229 + u32 miimcfg ;
6230 + u32 miimcmd ;
6231 + u32 miimaddr ;
6232 + u32 miimwtd ;
6233 + u32 miimrdd ;
6234 + u32 miimind ;
6235 + u32 eth_u11 ; // Reserved.
6236 + u32 eth_u12 ; // Reserved.
6237 + u32 ethcfsa0 ;
6238 + u32 ethcfsa1 ;
6239 + u32 ethcfsa2 ;
6240 +} volatile *ETH_t;
6241 +
6242 +enum
6243 +{
6244 + ETHINTFC_en_b = 0,
6245 + ETHINTFC_en_m = 0x00000001,
6246 + ETHINTFC_its_b = 1,
6247 + ETHINTFC_its_m = 0x00000002,
6248 + ETHINTFC_rip_b = 2,
6249 + ETHINTFC_rip_m = 0x00000004,
6250 + ETHINTFC_jam_b = 3,
6251 + ETHINTFC_jam_m = 0x00000008,
6252 + ETHINTFC_ovr_b = 4,
6253 + ETHINTFC_ovr_m = 0x00000010,
6254 + ETHINTFC_und_b = 5,
6255 + ETHINTFC_und_m = 0x00000020,
6256 +
6257 + ETHFIFOTT_tth_b = 0,
6258 + ETHFIFOTT_tth_m = 0x0000007f,
6259 +
6260 + ETHARC_pro_b = 0,
6261 + ETHARC_pro_m = 0x00000001,
6262 + ETHARC_am_b = 1,
6263 + ETHARC_am_m = 0x00000002,
6264 + ETHARC_afm_b = 2,
6265 + ETHARC_afm_m = 0x00000004,
6266 + ETHARC_ab_b = 3,
6267 + ETHARC_ab_m = 0x00000008,
6268 +
6269 + ETHSAL_byte5_b = 0,
6270 + ETHSAL_byte5_m = 0x000000ff,
6271 + ETHSAL_byte4_b = 8,
6272 + ETHSAL_byte4_m = 0x0000ff00,
6273 + ETHSAL_byte3_b = 16,
6274 + ETHSAL_byte3_m = 0x00ff0000,
6275 + ETHSAL_byte2_b = 24,
6276 + ETHSAL_byte2_m = 0xff000000,
6277 +
6278 + ETHSAH_byte1_b = 0,
6279 + ETHSAH_byte1_m = 0x000000ff,
6280 + ETHSAH_byte0_b = 8,
6281 + ETHSAH_byte0_m = 0x0000ff00,
6282 +
6283 + ETHGPF_ptv_b = 0,
6284 + ETHGPF_ptv_m = 0x0000ffff,
6285 +
6286 + ETHPFS_pfd_b = 0,
6287 + ETHPFS_pfd_m = 0x00000001,
6288 +
6289 + ETHCFSA0_cfsa4_b = 0,
6290 + ETHCFSA0_cfsa4_m = 0x000000ff,
6291 + ETHCFSA0_cfsa5_b = 8,
6292 + ETHCFSA0_cfsa5_m = 0x0000ff00,
6293 +
6294 + ETHCFSA1_cfsa2_b = 0,
6295 + ETHCFSA1_cfsa2_m = 0x000000ff,
6296 + ETHCFSA1_cfsa3_b = 8,
6297 + ETHCFSA1_cfsa3_m = 0x0000ff00,
6298 +
6299 + ETHCFSA2_cfsa0_b = 0,
6300 + ETHCFSA2_cfsa0_m = 0x000000ff,
6301 + ETHCFSA2_cfsa1_b = 8,
6302 + ETHCFSA2_cfsa1_m = 0x0000ff00,
6303 +
6304 + ETHMAC1_re_b = 0,
6305 + ETHMAC1_re_m = 0x00000001,
6306 + ETHMAC1_paf_b = 1,
6307 + ETHMAC1_paf_m = 0x00000002,
6308 + ETHMAC1_rfc_b = 2,
6309 + ETHMAC1_rfc_m = 0x00000004,
6310 + ETHMAC1_tfc_b = 3,
6311 + ETHMAC1_tfc_m = 0x00000008,
6312 + ETHMAC1_lb_b = 4,
6313 + ETHMAC1_lb_m = 0x00000010,
6314 + ETHMAC1_mr_b = 31,
6315 + ETHMAC1_mr_m = 0x80000000,
6316 +
6317 + ETHMAC2_fd_b = 0,
6318 + ETHMAC2_fd_m = 0x00000001,
6319 + ETHMAC2_flc_b = 1,
6320 + ETHMAC2_flc_m = 0x00000002,
6321 + ETHMAC2_hfe_b = 2,
6322 + ETHMAC2_hfe_m = 0x00000004,
6323 + ETHMAC2_dc_b = 3,
6324 + ETHMAC2_dc_m = 0x00000008,
6325 + ETHMAC2_cen_b = 4,
6326 + ETHMAC2_cen_m = 0x00000010,
6327 + ETHMAC2_pe_b = 5,
6328 + ETHMAC2_pe_m = 0x00000020,
6329 + ETHMAC2_vpe_b = 6,
6330 + ETHMAC2_vpe_m = 0x00000040,
6331 + ETHMAC2_ape_b = 7,
6332 + ETHMAC2_ape_m = 0x00000080,
6333 + ETHMAC2_ppe_b = 8,
6334 + ETHMAC2_ppe_m = 0x00000100,
6335 + ETHMAC2_lpe_b = 9,
6336 + ETHMAC2_lpe_m = 0x00000200,
6337 + ETHMAC2_nb_b = 12,
6338 + ETHMAC2_nb_m = 0x00001000,
6339 + ETHMAC2_bp_b = 13,
6340 + ETHMAC2_bp_m = 0x00002000,
6341 + ETHMAC2_ed_b = 14,
6342 + ETHMAC2_ed_m = 0x00004000,
6343 +
6344 + ETHIPGT_ipgt_b = 0,
6345 + ETHIPGT_ipgt_m = 0x0000007f,
6346 +
6347 + ETHIPGR_ipgr2_b = 0,
6348 + ETHIPGR_ipgr2_m = 0x0000007f,
6349 + ETHIPGR_ipgr1_b = 8,
6350 + ETHIPGR_ipgr1_m = 0x00007f00,
6351 +
6352 + ETHCLRT_maxret_b = 0,
6353 + ETHCLRT_maxret_m = 0x0000000f,
6354 + ETHCLRT_colwin_b = 8,
6355 + ETHCLRT_colwin_m = 0x00003f00,
6356 +
6357 + ETHMAXF_maxf_b = 0,
6358 + ETHMAXF_maxf_m = 0x0000ffff,
6359 +
6360 + ETHMTEST_tb_b = 2,
6361 + ETHMTEST_tb_m = 0x00000004,
6362 +
6363 + ETHMCP_div_b = 0,
6364 + ETHMCP_div_m = 0x000000ff,
6365 +
6366 + MIIMCFG_rsv_b = 0,
6367 + MIIMCFG_rsv_m = 0x0000000c,
6368 +
6369 + MIIMCMD_rd_b = 0,
6370 + MIIMCMD_rd_m = 0x00000001,
6371 + MIIMCMD_scn_b = 1,
6372 + MIIMCMD_scn_m = 0x00000002,
6373 +
6374 + MIIMADDR_regaddr_b = 0,
6375 + MIIMADDR_regaddr_m = 0x0000001f,
6376 + MIIMADDR_phyaddr_b = 8,
6377 + MIIMADDR_phyaddr_m = 0x00001f00,
6378 +
6379 + MIIMWTD_wdata_b = 0,
6380 + MIIMWTD_wdata_m = 0x0000ffff,
6381 +
6382 + MIIMRDD_rdata_b = 0,
6383 + MIIMRDD_rdata_m = 0x0000ffff,
6384 +
6385 + MIIMIND_bsy_b = 0,
6386 + MIIMIND_bsy_m = 0x00000001,
6387 + MIIMIND_scn_b = 1,
6388 + MIIMIND_scn_m = 0x00000002,
6389 + MIIMIND_nv_b = 2,
6390 + MIIMIND_nv_m = 0x00000004,
6391 +
6392 +} ;
6393 +
6394 +/*
6395 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
6396 + */
6397 +enum
6398 +{
6399 + ETHRX_fd_b = 0,
6400 + ETHRX_fd_m = 0x00000001,
6401 + ETHRX_ld_b = 1,
6402 + ETHRX_ld_m = 0x00000002,
6403 + ETHRX_rok_b = 2,
6404 + ETHRX_rok_m = 0x00000004,
6405 + ETHRX_fm_b = 3,
6406 + ETHRX_fm_m = 0x00000008,
6407 + ETHRX_mp_b = 4,
6408 + ETHRX_mp_m = 0x00000010,
6409 + ETHRX_bp_b = 5,
6410 + ETHRX_bp_m = 0x00000020,
6411 + ETHRX_vlt_b = 6,
6412 + ETHRX_vlt_m = 0x00000040,
6413 + ETHRX_cf_b = 7,
6414 + ETHRX_cf_m = 0x00000080,
6415 + ETHRX_ovr_b = 8,
6416 + ETHRX_ovr_m = 0x00000100,
6417 + ETHRX_crc_b = 9,
6418 + ETHRX_crc_m = 0x00000200,
6419 + ETHRX_cv_b = 10,
6420 + ETHRX_cv_m = 0x00000400,
6421 + ETHRX_db_b = 11,
6422 + ETHRX_db_m = 0x00000800,
6423 + ETHRX_le_b = 12,
6424 + ETHRX_le_m = 0x00001000,
6425 + ETHRX_lor_b = 13,
6426 + ETHRX_lor_m = 0x00002000,
6427 + ETHRX_ces_b = 14,
6428 + ETHRX_ces_m = 0x00004000,
6429 + ETHRX_length_b = 16,
6430 + ETHRX_length_m = 0xffff0000,
6431 +
6432 + ETHTX_fd_b = 0,
6433 + ETHTX_fd_m = 0x00000001,
6434 + ETHTX_ld_b = 1,
6435 + ETHTX_ld_m = 0x00000002,
6436 + ETHTX_oen_b = 2,
6437 + ETHTX_oen_m = 0x00000004,
6438 + ETHTX_pen_b = 3,
6439 + ETHTX_pen_m = 0x00000008,
6440 + ETHTX_cen_b = 4,
6441 + ETHTX_cen_m = 0x00000010,
6442 + ETHTX_hen_b = 5,
6443 + ETHTX_hen_m = 0x00000020,
6444 + ETHTX_tok_b = 6,
6445 + ETHTX_tok_m = 0x00000040,
6446 + ETHTX_mp_b = 7,
6447 + ETHTX_mp_m = 0x00000080,
6448 + ETHTX_bp_b = 8,
6449 + ETHTX_bp_m = 0x00000100,
6450 + ETHTX_und_b = 9,
6451 + ETHTX_und_m = 0x00000200,
6452 + ETHTX_of_b = 10,
6453 + ETHTX_of_m = 0x00000400,
6454 + ETHTX_ed_b = 11,
6455 + ETHTX_ed_m = 0x00000800,
6456 + ETHTX_ec_b = 12,
6457 + ETHTX_ec_m = 0x00001000,
6458 + ETHTX_lc_b = 13,
6459 + ETHTX_lc_m = 0x00002000,
6460 + ETHTX_td_b = 14,
6461 + ETHTX_td_m = 0x00004000,
6462 + ETHTX_crc_b = 15,
6463 + ETHTX_crc_m = 0x00008000,
6464 + ETHTX_le_b = 16,
6465 + ETHTX_le_m = 0x00010000,
6466 + ETHTX_cc_b = 17,
6467 + ETHTX_cc_m = 0x001E0000,
6468 +} ;
6469 +
6470 +#endif // __IDT_ETH_H__
6471 +
6472 +
6473 +
6474 +
6475 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h
6476 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 1970-01-01 01:00:00.000000000 +0100
6477 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_eth_v.h 2006-06-18 12:44:28.000000000 +0200
6478 @@ -0,0 +1,77 @@
6479 +/**************************************************************************
6480 + *
6481 + * BRIEF MODULE DESCRIPTION
6482 + * Ethernet register definition
6483 + *
6484 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6485 + *
6486 + * This program is free software; you can redistribute it and/or modify it
6487 + * under the terms of the GNU General Public License as published by the
6488 + * Free Software Foundation; either version 2 of the License, or (at your
6489 + * option) any later version.
6490 + *
6491 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6492 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6493 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6494 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6495 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6496 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6497 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6498 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6499 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6500 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6501 + *
6502 + * You should have received a copy of the GNU General Public License along
6503 + * with this program; if not, write to the Free Software Foundation, Inc.,
6504 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6505 + *
6506 + *
6507 + **************************************************************************
6508 + * May 2004 rkt, neb.
6509 + *
6510 + * Initial Release
6511 + *
6512 + *
6513 + *
6514 + **************************************************************************
6515 + */
6516 +
6517 +#ifndef __IDT_ETH_V_H__
6518 +#define __IDT_ETH_V_H__
6519 +
6520 +#include <asm/idt-boards/rc32434/rc32434_eth.h>
6521 +
6522 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
6523 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
6524 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
6525 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
6526 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
6527 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
6528 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
6529 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
6530 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
6531 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
6532 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
6533 +
6534 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
6535 +
6536 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
6537 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
6538 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
6539 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
6540 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
6541 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
6542 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
6543 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
6544 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
6545 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
6546 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
6547 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
6548 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
6549 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
6550 +#endif // __IDT_ETH_V_H__
6551 +
6552 +
6553 +
6554 +
6555 +
6556 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h
6557 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 1970-01-01 01:00:00.000000000 +0100
6558 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_gpio.h 2006-06-18 12:44:28.000000000 +0200
6559 @@ -0,0 +1,167 @@
6560 +/**************************************************************************
6561 + *
6562 + * BRIEF MODULE DESCRIPTION
6563 + * GPIO register definition
6564 + *
6565 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6566 + *
6567 + * This program is free software; you can redistribute it and/or modify it
6568 + * under the terms of the GNU General Public License as published by the
6569 + * Free Software Foundation; either version 2 of the License, or (at your
6570 + * option) any later version.
6571 + *
6572 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6573 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6574 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6575 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6576 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6577 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6578 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6579 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6580 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6581 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6582 + *
6583 + * You should have received a copy of the GNU General Public License along
6584 + * with this program; if not, write to the Free Software Foundation, Inc.,
6585 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6586 + *
6587 + *
6588 + **************************************************************************
6589 + * May 2004 rkt, neb.
6590 + *
6591 + * Initial Release
6592 + *
6593 + *
6594 + *
6595 + **************************************************************************
6596 + */
6597 +
6598 +#ifndef __IDT_GPIO_H__
6599 +#define __IDT_GPIO_H__
6600 +
6601 +enum
6602 +{
6603 + GPIO0_PhysicalAddress = 0x18050000,
6604 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
6605 +
6606 + GPIO0_VirtualAddress = 0xb8050000,
6607 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
6608 +} ;
6609 +
6610 +typedef struct
6611 +{
6612 + u32 gpiofunc; /* GPIO Function Register
6613 + * gpiofunc[x]==0 bit = gpio
6614 + * func[x]==1 bit = altfunc
6615 + */
6616 + u32 gpiocfg; /* GPIO Configuration Register
6617 + * gpiocfg[x]==0 bit = input
6618 + * gpiocfg[x]==1 bit = output
6619 + */
6620 + u32 gpiod; /* GPIO Data Register
6621 + * gpiod[x] read/write gpio pinX status
6622 + */
6623 + u32 gpioilevel; /* GPIO Interrupt Status Register
6624 + * interrupt level (see gpioistat)
6625 + */
6626 + u32 gpioistat; /* Gpio Interrupt Status Register
6627 + * istat[x] = (gpiod[x] == level[x])
6628 + * cleared in ISR (STICKY bits)
6629 + */
6630 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
6631 +} volatile * GPIO_t ;
6632 +
6633 +typedef enum
6634 +{
6635 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
6636 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
6637 + GPIO_input_v = 0, // gpiocfg use pin as input.
6638 + GPIO_output_v = 1, // gpiocfg use pin as output.
6639 + GPIO_pin0_b = 0,
6640 + GPIO_pin0_m = 0x00000001,
6641 + GPIO_pin1_b = 1,
6642 + GPIO_pin1_m = 0x00000002,
6643 + GPIO_pin2_b = 2,
6644 + GPIO_pin2_m = 0x00000004,
6645 + GPIO_pin3_b = 3,
6646 + GPIO_pin3_m = 0x00000008,
6647 + GPIO_pin4_b = 4,
6648 + GPIO_pin4_m = 0x00000010,
6649 + GPIO_pin5_b = 5,
6650 + GPIO_pin5_m = 0x00000020,
6651 + GPIO_pin6_b = 6,
6652 + GPIO_pin6_m = 0x00000040,
6653 + GPIO_pin7_b = 7,
6654 + GPIO_pin7_m = 0x00000080,
6655 + GPIO_pin8_b = 8,
6656 + GPIO_pin8_m = 0x00000100,
6657 + GPIO_pin9_b = 9,
6658 + GPIO_pin9_m = 0x00000200,
6659 + GPIO_pin10_b = 10,
6660 + GPIO_pin10_m = 0x00000400,
6661 + GPIO_pin11_b = 11,
6662 + GPIO_pin11_m = 0x00000800,
6663 + GPIO_pin12_b = 12,
6664 + GPIO_pin12_m = 0x00001000,
6665 + GPIO_pin13_b = 13,
6666 + GPIO_pin13_m = 0x00002000,
6667 +
6668 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
6669 +
6670 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
6671 + GPIO_u0sout_m = GPIO_pin0_m,
6672 + GPIO_u0sout_cfg_v = GPIO_output_v,
6673 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
6674 + GPIO_u0sinp_m = GPIO_pin1_m,
6675 + GPIO_u0sinp_cfg_v = GPIO_input_v,
6676 + GPIO_u0rtsn_b = GPIO_pin2_b, // UART 0 req. to send.
6677 + GPIO_u0rtsn_m = GPIO_pin2_m,
6678 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
6679 + GPIO_u0ctsn_b = GPIO_pin3_b, // UART 0 clear to send.
6680 + GPIO_u0ctsn_m = GPIO_pin3_m,
6681 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
6682 +
6683 + GPIO_maddr22_b = GPIO_pin4_b, // M&P bus bit 22.
6684 + GPIO_maddr22_m = GPIO_pin4_m,
6685 + GPIO_maddr22_cfg_v = GPIO_output_v,
6686 +
6687 + GPIO_maddr23_b = GPIO_pin5_b, // M&P bus bit 23.
6688 + GPIO_maddr23_m = GPIO_pin5_m,
6689 + GPIO_maddr23_cfg_v = GPIO_output_v,
6690 +
6691 + GPIO_maddr24_b = GPIO_pin6_b, // M&P bus bit 24.
6692 + GPIO_maddr24_m = GPIO_pin6_m,
6693 + GPIO_maddr24_cfg_v = GPIO_output_v,
6694 +
6695 + GPIO_maddr25_b = GPIO_pin7_b, // M&P bus bit 25.
6696 + GPIO_maddr25_m = GPIO_pin7_m,
6697 + GPIO_maddr25_cfg_v = GPIO_output_v,
6698 +
6699 + GPIO_cpudmadebug_b = GPIO_pin8_b, // CPU or DMA debug pin
6700 + GPIO_cpudmadebug_m = GPIO_pin8_m,
6701 + GPIO_cpudmadebug_cfg_v = GPIO_output_v,
6702 +
6703 + GPIO_pcireq4_b = GPIO_pin9_b, // PCI Request 4
6704 + GPIO_pcireq4_m = GPIO_pin9_m,
6705 + GPIO_pcireq4_cfg_v = GPIO_input_v,
6706 +
6707 + GPIO_pcigrant4_b = GPIO_pin10_b, // PCI Grant 4
6708 + GPIO_pcigrant4_m = GPIO_pin10_m,
6709 + GPIO_pcigrant4_cfg_v = GPIO_output_v,
6710 +
6711 + GPIO_pcireq5_b = GPIO_pin11_b, // PCI Request 5
6712 + GPIO_pcireq5_m = GPIO_pin11_m,
6713 + GPIO_pcireq5_cfg_v = GPIO_input_v,
6714 +
6715 + GPIO_pcigrant5_b = GPIO_pin12_b, // PCI Grant 5
6716 + GPIO_pcigrant5_m = GPIO_pin12_m,
6717 + GPIO_pcigrant5_cfg_v = GPIO_output_v,
6718 +
6719 + GPIO_pcimuintn_b = GPIO_pin13_b, // PCI messaging int.
6720 + GPIO_pcimuintn_m = GPIO_pin13_m,
6721 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
6722 +
6723 +} GPIO_DEFS_t;
6724 +
6725 +#endif // __IDT_GPIO_H__
6726 +
6727 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h
6728 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434.h 1970-01-01 01:00:00.000000000 +0100
6729 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434.h 2006-06-18 12:44:28.000000000 +0200
6730 @@ -0,0 +1,199 @@
6731 + /**************************************************************************
6732 + *
6733 + * BRIEF MODULE DESCRIPTION
6734 + * Definitions for IDT RC32434 CPU
6735 + *
6736 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6737 + *
6738 + * This program is free software; you can redistribute it and/or modify it
6739 + * under the terms of the GNU General Public License as published by the
6740 + * Free Software Foundation; either version 2 of the License, or (at your
6741 + * option) any later version.
6742 + *
6743 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6744 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6745 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6746 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6747 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6748 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6749 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6750 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6751 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6752 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6753 + *
6754 + * You should have received a copy of the GNU General Public License along
6755 + * with this program; if not, write to the Free Software Foundation, Inc.,
6756 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6757 + *
6758 + *
6759 + **************************************************************************
6760 + * May 2004 rkt, neb.
6761 + *
6762 + * Initial Release
6763 + *
6764 + *
6765 + *
6766 + **************************************************************************
6767 + */
6768 +
6769 +#ifndef _RC32434_H_
6770 +#define _RC32434_H_
6771 +
6772 +#include <linux/config.h>
6773 +#include <linux/delay.h>
6774 +#include <asm/io.h>
6775 +#include <asm/idt-boards/rc32434/rc32434_timer.h>
6776 +
6777 +#define RC32434_REG_BASE 0x18000000
6778 +
6779 +
6780 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
6781 +#define idt_timer ((volatile TIM_t) TIM0_VirtualAddress)
6782 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
6783 +
6784 +#define IDT_CLOCK_MULT 2
6785 +#define MIPS_CPU_TIMER_IRQ 7
6786 +/* Interrupt Controller */
6787 +#define IC_GROUP0_PEND (RC32434_REG_BASE + 0x38000)
6788 +#define IC_GROUP0_MASK (RC32434_REG_BASE + 0x38008)
6789 +#define IC_GROUP_OFFSET 0x0C
6790 +#define RTC_BASE 0xBA001FF0
6791 +
6792 +#define NUM_INTR_GROUPS 5
6793 +/* 16550 UARTs */
6794 +
6795 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
6796 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
6797 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
6798 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
6799 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
6800 +
6801 +#ifdef __MIPSEB__
6802 +
6803 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
6804 +#define EB434_UART1_BASE (0x19800003)
6805 +
6806 +#else
6807 +
6808 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
6809 +#define EB434_UART1_BASE (0x19800000)
6810 +
6811 +#endif
6812 +
6813 +#define RC32434_UART0_IRQ GROUP3_IRQ_BASE + 0
6814 +#define EB434_UART1_IRQ GROUP4_IRQ_BASE + 11
6815 +
6816 +#define RC32434_NR_IRQS (GROUP4_IRQ_BASE + 32)
6817 +
6818 +/* cpu pipeline flush */
6819 +static inline void rc32434_sync(void)
6820 +{
6821 + __asm__ volatile ("sync");
6822 +}
6823 +
6824 +static inline void rc32434_sync_udelay(int us)
6825 +{
6826 + __asm__ volatile ("sync");
6827 + udelay(us);
6828 +}
6829 +
6830 +static inline void rc32434_sync_delay(int ms)
6831 +{
6832 + __asm__ volatile ("sync");
6833 + mdelay(ms);
6834 +}
6835 +
6836 +
6837 +
6838 +/*
6839 + * Macros to access internal RC32434 registers. No byte
6840 + * swapping should be done when accessing the internal
6841 + * registers.
6842 + */
6843 +
6844 +#define rc32434_readb __raw_readb
6845 +#define rc32434_readw __raw_readw
6846 +#define rc32434_readl __raw_readl
6847 +
6848 +#define rc32434_writeb __raw_writeb
6849 +#define rc32434_writew __raw_writew
6850 +#define rc32434_writel __raw_writel
6851 +
6852 +#if 0
6853 +static inline u8 rc32434_readb(unsigned long pa)
6854 +{
6855 + return *((volatile u8 *)KSEG1ADDR(pa));
6856 +}
6857 +static inline u16 rc32434_readw(unsigned long pa)
6858 +{
6859 + return *((volatile u16 *)KSEG1ADDR(pa));
6860 +}
6861 +static inline u32 rc32434_readl(unsigned long pa)
6862 +{
6863 + return *((volatile u32 *)KSEG1ADDR(pa));
6864 +}
6865 +static inline void rc32434_writeb(u8 val, unsigned long pa)
6866 +{
6867 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
6868 +}
6869 +static inline void rc32434_writew(u16 val, unsigned long pa)
6870 +{
6871 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
6872 +}
6873 +static inline void rc32434_writel(u32 val, unsigned long pa)
6874 +{
6875 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
6876 +}
6877 +
6878 +#endif
6879 +
6880 +
6881 +/*
6882 + * C access to CLZ and CLO instructions
6883 + * (count leading zeroes/ones).
6884 + */
6885 +static inline int rc32434_clz(unsigned long val)
6886 +{
6887 + int ret;
6888 + __asm__ volatile (
6889 + ".set\tnoreorder\n\t"
6890 + ".set\tnoat\n\t"
6891 + ".set\tmips32\n\t"
6892 + "clz\t%0,%1\n\t"
6893 + ".set\tmips0\n\t"
6894 + ".set\tat\n\t"
6895 + ".set\treorder"
6896 + : "=r" (ret)
6897 + : "r" (val));
6898 +
6899 + return ret;
6900 +}
6901 +static inline int rc32434_clo(unsigned long val)
6902 +{
6903 + int ret;
6904 + __asm__ volatile (
6905 + ".set\tnoreorder\n\t"
6906 + ".set\tnoat\n\t"
6907 + ".set\tmips32\n\t"
6908 + "clo\t%0,%1\n\t"
6909 + ".set\tmips0\n\t"
6910 + ".set\tat\n\t"
6911 + ".set\treorder"
6912 + : "=r" (ret)
6913 + : "r" (val));
6914 +
6915 + return ret;
6916 +}
6917 +#endif /* _RC32434_H_ */
6918 +
6919 +
6920 +
6921 +
6922 +
6923 +
6924 +
6925 +
6926 +
6927 +
6928 +
6929 +
6930 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h
6931 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 1970-01-01 01:00:00.000000000 +0100
6932 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_integ.h 2006-06-18 12:44:28.000000000 +0200
6933 @@ -0,0 +1,90 @@
6934 +/**************************************************************************
6935 + *
6936 + * BRIEF MODULE DESCRIPTION
6937 + * System Integrity register definition
6938 + *
6939 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
6940 + *
6941 + * This program is free software; you can redistribute it and/or modify it
6942 + * under the terms of the GNU General Public License as published by the
6943 + * Free Software Foundation; either version 2 of the License, or (at your
6944 + * option) any later version.
6945 + *
6946 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
6947 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
6948 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
6949 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
6950 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
6951 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
6952 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
6953 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
6954 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
6955 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
6956 + *
6957 + * You should have received a copy of the GNU General Public License along
6958 + * with this program; if not, write to the Free Software Foundation, Inc.,
6959 + * 675 Mass Ave, Cambridge, MA 02139, USA.
6960 + *
6961 + *
6962 + **************************************************************************
6963 + * May 2004 rkt, neb
6964 + *
6965 + * Initial Release
6966 + *
6967 + *
6968 + *
6969 + **************************************************************************
6970 + */
6971 +
6972 +#ifndef __IDT_INTEG_H__
6973 +#define __IDT_INTEG_H__
6974 +
6975 +enum
6976 +{
6977 + INTEG0_PhysicalAddress = 0x18030000,
6978 + INTEG_PhysicalAddress = INTEG0_PhysicalAddress, // Default
6979 +
6980 + INTEG0_VirtualAddress = 0xB8030000,
6981 + INTEG_VirtualAddress = INTEG0_VirtualAddress, // Default
6982 +} ;
6983 +
6984 +// if you are looking for CEA, try rst.h
6985 +typedef struct
6986 +{
6987 + u32 filler [0xc] ; // 0x30 bytes unused.
6988 + u32 errcs ; // sticky use ERRCS_
6989 + u32 wtcount ; // Watchdog timer count reg.
6990 + u32 wtcompare ; // Watchdog timer timeout value.
6991 + u32 wtc ; // Watchdog timer control. use WTC_
6992 +} volatile *INTEG_t ;
6993 +
6994 +enum
6995 +{
6996 + ERRCS_wto_b = 0, // In INTEG_t -> errcs
6997 + ERRCS_wto_m = 0x00000001,
6998 + ERRCS_wne_b = 1, // In INTEG_t -> errcs
6999 + ERRCS_wne_m = 0x00000002,
7000 + ERRCS_ucw_b = 2, // In INTEG_t -> errcs
7001 + ERRCS_ucw_m = 0x00000004,
7002 + ERRCS_ucr_b = 3, // In INTEG_t -> errcs
7003 + ERRCS_ucr_m = 0x00000008,
7004 + ERRCS_upw_b = 4, // In INTEG_t -> errcs
7005 + ERRCS_upw_m = 0x00000010,
7006 + ERRCS_upr_b = 5, // In INTEG_t -> errcs
7007 + ERRCS_upr_m = 0x00000020,
7008 + ERRCS_udw_b = 6, // In INTEG_t -> errcs
7009 + ERRCS_udw_m = 0x00000040,
7010 + ERRCS_udr_b = 7, // In INTEG_t -> errcs
7011 + ERRCS_udr_m = 0x00000080,
7012 + ERRCS_sae_b = 8, // In INTEG_t -> errcs
7013 + ERRCS_sae_m = 0x00000100,
7014 + ERRCS_wre_b = 9, // In INTEG_t -> errcs
7015 + ERRCS_wre_m = 0x00000200,
7016 +
7017 + WTC_en_b = 0, // In INTEG_t -> wtc
7018 + WTC_en_m = 0x00000001,
7019 + WTC_to_b = 1, // In INTEG_t -> wtc
7020 + WTC_to_m = 0x00000002,
7021 +} ;
7022 +
7023 +#endif // __IDT_INTEG_H__
7024 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h
7025 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_int.h 1970-01-01 01:00:00.000000000 +0100
7026 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_int.h 2006-06-18 12:44:28.000000000 +0200
7027 @@ -0,0 +1,174 @@
7028 +/**************************************************************************
7029 + *
7030 + * BRIEF MODULE DESCRIPTION
7031 + * Interrupt Controller register definition.
7032 + *
7033 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7034 + *
7035 + * This program is free software; you can redistribute it and/or modify it
7036 + * under the terms of the GNU General Public License as published by the
7037 + * Free Software Foundation; either version 2 of the License, or (at your
7038 + * option) any later version.
7039 + *
7040 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7041 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7042 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7043 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7044 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7045 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7046 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7047 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7048 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7049 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7050 + *
7051 + * You should have received a copy of the GNU General Public License along
7052 + * with this program; if not, write to the Free Software Foundation, Inc.,
7053 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7054 + *
7055 + *
7056 + **************************************************************************
7057 + * May 2004 rkt, neb.
7058 + *
7059 + * Initial Release
7060 + *
7061 + *
7062 + *
7063 + **************************************************************************
7064 + */
7065 +
7066 +#ifndef __IDT_INT_H__
7067 +#define __IDT_INT_H__
7068 +
7069 +enum
7070 +{
7071 + INT0_PhysicalAddress = 0x18038000,
7072 + INT_PhysicalAddress = INT0_PhysicalAddress, // Default
7073 +
7074 + INT0_VirtualAddress = 0xB8038000,
7075 + INT_VirtualAddress = INT0_VirtualAddress, // Default
7076 +} ;
7077 +
7078 +struct INT_s
7079 +{
7080 + u32 ipend ; //Pending interrupts. use INT?_
7081 + u32 itest ; //Test bits. use INT?_
7082 + u32 imask ; //Interrupt disabled when set. use INT?_
7083 +} ;
7084 +
7085 +enum
7086 +{
7087 + IPEND2 = 0, // HW 2 interrupt to core. use INT2_
7088 + IPEND3 = 1, // HW 3 interrupt to core. use INT3_
7089 + IPEND4 = 2, // HW 4 interrupt to core. use INT4_
7090 + IPEND5 = 3, // HW 5 interrupt to core. use INT5_
7091 + IPEND6 = 4, // HW 6 interrupt to core. use INT6_
7092 +
7093 + IPEND_count, // must be last (used in loops)
7094 + IPEND_min = IPEND2 // min IPEND (used in loops)
7095 +};
7096 +
7097 +typedef struct INTC_s
7098 +{
7099 + struct INT_s i [IPEND_count] ;// use i[IPEND?] = INT?_
7100 + u32 nmips ; // use NMIPS_
7101 +} volatile *INT_t ;
7102 +
7103 +enum
7104 +{
7105 + INT2_timer0_b = 0,
7106 + INT2_timer0_m = 0x00000001,
7107 + INT2_timer1_b = 1,
7108 + INT2_timer1_m = 0x00000002,
7109 + INT2_timer2_b = 2,
7110 + INT2_timer2_m = 0x00000004,
7111 + INT2_refresh_b = 3,
7112 + INT2_refresh_m = 0x00000008,
7113 + INT2_watchdogTimeout_b = 4,
7114 + INT2_watchdogTimeout_m = 0x00000010,
7115 + INT2_undecodedCpuWrite_b = 5,
7116 + INT2_undecodedCpuWrite_m = 0x00000020,
7117 + INT2_undecodedCpuRead_b = 6,
7118 + INT2_undecodedCpuRead_m = 0x00000040,
7119 + INT2_undecodedPciWrite_b = 7,
7120 + INT2_undecodedPciWrite_m = 0x00000080,
7121 + INT2_undecodedPciRead_b = 8,
7122 + INT2_undecodedPciRead_m = 0x00000100,
7123 + INT2_undecodedDmaWrite_b = 9,
7124 + INT2_undecodedDmaWrite_m = 0x00000200,
7125 + INT2_undecodedDmaRead_b = 10,
7126 + INT2_undecodedDmaRead_m = 0x00000400,
7127 + INT2_ipBusSlaveAckError_b = 11,
7128 + INT2_ipBusSlaveAckError_m = 0x00000800,
7129 +
7130 + INT3_dmaChannel0_b = 0,
7131 + INT3_dmaChannel0_m = 0x00000001,
7132 + INT3_dmaChannel1_b = 1,
7133 + INT3_dmaChannel1_m = 0x00000002,
7134 + INT3_dmaChannel2_b = 2,
7135 + INT3_dmaChannel2_m = 0x00000004,
7136 + INT3_dmaChannel3_b = 3,
7137 + INT3_dmaChannel3_m = 0x00000008,
7138 + INT3_dmaChannel4_b = 4,
7139 + INT3_dmaChannel4_m = 0x00000010,
7140 + INT3_dmaChannel5_b = 5,
7141 + INT3_dmaChannel5_m = 0x00000020,
7142 +
7143 + INT5_uartGeneral0_b = 0,
7144 + INT5_uartGeneral0_m = 0x00000001,
7145 + INT5_uartTxrdy0_b = 1,
7146 + INT5_uartTxrdy0_m = 0x00000002,
7147 + INT5_uartRxrdy0_b = 2,
7148 + INT5_uartRxrdy0_m = 0x00000004,
7149 + INT5_pci_b = 3,
7150 + INT5_pci_m = 0x00000008,
7151 + INT5_pciDecoupled_b = 4,
7152 + INT5_pciDecoupled_m = 0x00000010,
7153 + INT5_spi_b = 5,
7154 + INT5_spi_m = 0x00000020,
7155 + INT5_deviceDecoupled_b = 6,
7156 + INT5_deviceDecoupled_m = 0x00000040,
7157 + INT5_eth0Ovr_b = 9,
7158 + INT5_eth0Ovr_m = 0x00000200,
7159 + INT5_eth0Und_b = 10,
7160 + INT5_eth0Und_m = 0x00000400,
7161 + INT5_eth0Pfd_b = 11,
7162 + INT5_eth0Pfd_m = 0x00000800,
7163 + INT5_nvram_b = 12,
7164 + INT5_nvram_m = 0x00001000,
7165 +
7166 + INT6_gpio0_b = 0,
7167 + INT6_gpio0_m = 0x00000001,
7168 + INT6_gpio1_b = 1,
7169 + INT6_gpio1_m = 0x00000002,
7170 + INT6_gpio2_b = 2,
7171 + INT6_gpio2_m = 0x00000004,
7172 + INT6_gpio3_b = 3,
7173 + INT6_gpio3_m = 0x00000008,
7174 + INT6_gpio4_b = 4,
7175 + INT6_gpio4_m = 0x00000010,
7176 + INT6_gpio5_b = 5,
7177 + INT6_gpio5_m = 0x00000020,
7178 + INT6_gpio6_b = 6,
7179 + INT6_gpio6_m = 0x00000040,
7180 + INT6_gpio7_b = 7,
7181 + INT6_gpio7_m = 0x00000080,
7182 + INT6_gpio8_b = 8,
7183 + INT6_gpio8_m = 0x00000100,
7184 + INT6_gpio9_b = 9,
7185 + INT6_gpio9_m = 0x00000200,
7186 + INT6_gpio10_b = 10,
7187 + INT6_gpio10_m = 0x00000400,
7188 + INT6_gpio11_b = 11,
7189 + INT6_gpio11_m = 0x00000800,
7190 + INT6_gpio12_b = 12,
7191 + INT6_gpio12_m = 0x00001000,
7192 + INT6_gpio13_b = 13,
7193 + INT6_gpio13_m = 0x00002000,
7194 +
7195 + NMIPS_gpio_b = 0,
7196 + NMIPS_gpio_m = 0x00000001,
7197 +} ;
7198 +
7199 +#endif // __IDT_INT_H__
7200 +
7201 +
7202 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h
7203 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 1970-01-01 01:00:00.000000000 +0100
7204 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_iparb.h 2006-06-18 12:44:28.000000000 +0200
7205 @@ -0,0 +1,111 @@
7206 +/**************************************************************************
7207 + *
7208 + * BRIEF MODULE DESCRIPTION
7209 + * IP Arbiter register definitions
7210 + *
7211 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7212 + *
7213 + * This program is free software; you can redistribute it and/or modify it
7214 + * under the terms of the GNU General Public License as published by the
7215 + * Free Software Foundation; either version 2 of the License, or (at your
7216 + * option) any later version.
7217 + *
7218 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7219 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7220 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7221 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7222 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7223 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7224 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7225 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7226 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7227 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7228 + *
7229 + * You should have received a copy of the GNU General Public License along
7230 + * with this program; if not, write to the Free Software Foundation, Inc.,
7231 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7232 + *
7233 + *
7234 + **************************************************************************
7235 + * May 2004 rkt,neb
7236 + *
7237 + * Initial Release
7238 + *
7239 + *
7240 + *
7241 + **************************************************************************
7242 + */
7243 +
7244 +#ifndef __IDT_IPARB_H__
7245 +#define __IDT_IPARB_H__
7246 +
7247 +enum
7248 +{
7249 + IPARB0_PhysicalAddress = 0x18048000,
7250 + IPARB_PhysicalAddress = IPARB0_PhysicalAddress, // Default
7251 +
7252 + IPARB0_VirtualAddress = 0xB8048000,
7253 + IPARB_VirtualAddress = IPARB0_VirtualAddress, // Default
7254 +} ;
7255 +
7256 +enum
7257 +{
7258 + IPABMXC_ethernet0Receive = 0,
7259 + IPABMXC_ethernet0Transmit = 1,
7260 + IPABMXC_memoryToHoldFifo = 2,
7261 + IPABMXC_holdFifoToMemory = 3,
7262 + IPABMXC_pciToMemory = 4,
7263 + IPABMXC_memoryToPci = 5,
7264 + IPABMXC_pciTarget = 6,
7265 + IPABMXC_pciTargetStart = 7,
7266 + IPABMXC_cpuToIpBus = 8,
7267 +
7268 + IPABMXC_Count, // Must be last in list !
7269 + IPABMXC_Min = IPABMXC_ethernet0Receive,
7270 +
7271 + IPAPXC_PriorityCount = 4, // 3-highest, 0-lowest.
7272 +} ;
7273 +
7274 +typedef struct
7275 +{
7276 + u32 ipapc [IPAPXC_PriorityCount] ; // ipapc[IPAPXC_] = IPAPC_
7277 + u32 ipabmc [IPABMXC_Count] ; // ipabmc[IPABMXC_] = IPABMC_
7278 + u32 ipac ; // use IPAC_
7279 + u32 ipaitcc; // use IPAITCC_
7280 + u32 ipaspare ;
7281 +} volatile * IPARB_t ;
7282 +
7283 +enum
7284 +{
7285 + IPAC_dp_b = 0,
7286 + IPAC_dp_m = 0x00000001,
7287 + IPAC_dep_b = 1,
7288 + IPAC_dep_m = 0x00000002,
7289 + IPAC_drm_b = 2,
7290 + IPAC_drm_m = 0x00000004,
7291 + IPAC_dwm_b = 3,
7292 + IPAC_dwm_m = 0x00000008,
7293 + IPAC_msk_b = 4,
7294 + IPAC_msk_m = 0x00000010,
7295 +
7296 + IPAPC_ptc_b = 0,
7297 + IPAPC_ptc_m = 0x00003fff,
7298 + IPAPC_mf_b = 14,
7299 + IPAPC_mf_m = 0x00004000,
7300 + IPAPC_cptc_b = 16,
7301 + IPAPC_cptc_m = 0x3fff0000,
7302 +
7303 + IPAITCC_itcc = 0,
7304 + IPAITCC_itcc, = 0x000001ff,
7305 +
7306 + IPABMC_mtc_b = 0,
7307 + IPABMC_mtc_m = 0x00000fff,
7308 + IPABMC_p_b = 12,
7309 + IPABMC_p_m = 0x00003000,
7310 + IPABMC_msk_b = 14,
7311 + IPABMC_msk_m = 0x00004000,
7312 + IPABMC_cmtc_b = 16,
7313 + IPABMC_cmtc_m = 0x0fff0000,
7314 +};
7315 +
7316 +#endif // __IDT_IPARB_H__
7317 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h
7318 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 1970-01-01 01:00:00.000000000 +0100
7319 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_pci.h 2006-06-18 12:44:28.000000000 +0200
7320 @@ -0,0 +1,695 @@
7321 +/**************************************************************************
7322 + *
7323 + * BRIEF MODULE DESCRIPTION
7324 + * PCI register definitio
7325 + *
7326 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
7327 + *
7328 + * This program is free software; you can redistribute it and/or modify it
7329 + * under the terms of the GNU General Public License as published by the
7330 + * Free Software Foundation; either version 2 of the License, or (at your
7331 + * option) any later version.
7332 + *
7333 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
7334 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
7335 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
7336 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
7337 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
7338 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
7339 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
7340 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
7341 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
7342 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
7343 + *
7344 + * You should have received a copy of the GNU General Public License along
7345 + * with this program; if not, write to the Free Software Foundation, Inc.,
7346 + * 675 Mass Ave, Cambridge, MA 02139, USA.
7347 + *
7348 + *
7349 + **************************************************************************
7350 + * May 2004 rkt, neb.
7351 + *
7352 + * Initial Release
7353 + *
7354 + *
7355 + *
7356 + **************************************************************************
7357 + */
7358 +
7359 +#ifndef __IDT_PCI_H__
7360 +#define __IDT_PCI_H__
7361 +
7362 +enum
7363 +{
7364 + PCI0_PhysicalAddress = 0x18080000,
7365 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
7366 +
7367 + PCI0_VirtualAddress = 0xB8080000,
7368 + PCI_VirtualAddress = PCI0_VirtualAddress,
7369 +} ;
7370 +
7371 +enum
7372 +{
7373 + PCI_LbaCount = 4, // Local base addresses.
7374 +} ;
7375 +
7376 +typedef struct
7377 +{
7378 + u32 a ; // Address.
7379 + u32 c ; // Control.
7380 + u32 m ; // mapping.
7381 +} PCI_Map_s ;
7382 +
7383 +typedef struct
7384 +{
7385 + u32 pcic ;
7386 + u32 pcis ;
7387 + u32 pcism ;
7388 + u32 pcicfga ;
7389 + u32 pcicfgd ;
7390 + PCI_Map_s pcilba [PCI_LbaCount] ;
7391 + u32 pcidac ;
7392 + u32 pcidas ;
7393 + u32 pcidasm ;
7394 + u32 pcidad ;
7395 + u32 pcidma8c ;
7396 + u32 pcidma9c ;
7397 + u32 pcitc ;
7398 +} volatile *PCI_t ;
7399 +
7400 +// PCI messaging unit.
7401 +enum
7402 +{
7403 + PCIM_Count = 2,
7404 +} ;
7405 +typedef struct
7406 +{
7407 + u32 pciim [PCIM_Count] ;
7408 + u32 pciom [PCIM_Count] ;
7409 + u32 pciid ;
7410 + u32 pciiic ;
7411 + u32 pciiim ;
7412 + u32 pciiod ;
7413 + u32 pciioic ;
7414 + u32 pciioim ;
7415 +} volatile *PCIM_t ;
7416 +
7417 +/*******************************************************************************
7418 + *
7419 + * PCI Control Register
7420 + *
7421 + ******************************************************************************/
7422 +enum
7423 +{
7424 + PCIC_en_b = 0,
7425 + PCIC_en_m = 0x00000001,
7426 + PCIC_tnr_b = 1,
7427 + PCIC_tnr_m = 0x00000002,
7428 + PCIC_sce_b = 2,
7429 + PCIC_sce_m = 0x00000004,
7430 + PCIC_ien_b = 3,
7431 + PCIC_ien_m = 0x00000008,
7432 + PCIC_aaa_b = 4,
7433 + PCIC_aaa_m = 0x00000010,
7434 + PCIC_eap_b = 5,
7435 + PCIC_eap_m = 0x00000020,
7436 + PCIC_pcim_b = 6,
7437 + PCIC_pcim_m = 0x000001c0,
7438 + PCIC_pcim_disabled_v = 0,
7439 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
7440 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
7441 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
7442 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
7443 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
7444 + PCIC_pcim_reserved6_v = 6,
7445 + PCIC_pcim_reserved7_v = 7,
7446 + PCIC_igm_b = 9,
7447 + PCIC_igm_m = 0x00000200,
7448 +} ;
7449 +
7450 +/*******************************************************************************
7451 + *
7452 + * PCI Status Register
7453 + *
7454 + ******************************************************************************/
7455 +enum {
7456 + PCIS_eed_b = 0,
7457 + PCIS_eed_m = 0x00000001,
7458 + PCIS_wr_b = 1,
7459 + PCIS_wr_m = 0x00000002,
7460 + PCIS_nmi_b = 2,
7461 + PCIS_nmi_m = 0x00000004,
7462 + PCIS_ii_b = 3,
7463 + PCIS_ii_m = 0x00000008,
7464 + PCIS_cwe_b = 4,
7465 + PCIS_cwe_m = 0x00000010,
7466 + PCIS_cre_b = 5,
7467 + PCIS_cre_m = 0x00000020,
7468 + PCIS_mdpe_b = 6,
7469 + PCIS_mdpe_m = 0x00000040,
7470 + PCIS_sta_b = 7,
7471 + PCIS_sta_m = 0x00000080,
7472 + PCIS_rta_b = 8,
7473 + PCIS_rta_m = 0x00000100,
7474 + PCIS_rma_b = 9,
7475 + PCIS_rma_m = 0x00000200,
7476 + PCIS_sse_b = 10,
7477 + PCIS_sse_m = 0x00000400,
7478 + PCIS_ose_b = 11,
7479 + PCIS_ose_m = 0x00000800,
7480 + PCIS_pe_b = 12,
7481 + PCIS_pe_m = 0x00001000,
7482 + PCIS_tae_b = 13,
7483 + PCIS_tae_m = 0x00002000,
7484 + PCIS_rle_b = 14,
7485 + PCIS_rle_m = 0x00004000,
7486 + PCIS_bme_b = 15,
7487 + PCIS_bme_m = 0x00008000,
7488 + PCIS_prd_b = 16,
7489 + PCIS_prd_m = 0x00010000,
7490 + PCIS_rip_b = 17,
7491 + PCIS_rip_m = 0x00020000,
7492 +} ;
7493 +
7494 +/*******************************************************************************
7495 + *
7496 + * PCI Status Mask Register
7497 + *
7498 + ******************************************************************************/
7499 +enum {
7500 + PCISM_eed_b = 0,
7501 + PCISM_eed_m = 0x00000001,
7502 + PCISM_wr_b = 1,
7503 + PCISM_wr_m = 0x00000002,
7504 + PCISM_nmi_b = 2,
7505 + PCISM_nmi_m = 0x00000004,
7506 + PCISM_ii_b = 3,
7507 + PCISM_ii_m = 0x00000008,
7508 + PCISM_cwe_b = 4,
7509 + PCISM_cwe_m = 0x00000010,
7510 + PCISM_cre_b = 5,
7511 + PCISM_cre_m = 0x00000020,
7512 + PCISM_mdpe_b = 6,
7513 + PCISM_mdpe_m = 0x00000040,
7514 + PCISM_sta_b = 7,
7515 + PCISM_sta_m = 0x00000080,
7516 + PCISM_rta_b = 8,
7517 + PCISM_rta_m = 0x00000100,
7518 + PCISM_rma_b = 9,
7519 + PCISM_rma_m = 0x00000200,
7520 + PCISM_sse_b = 10,
7521 + PCISM_sse_m = 0x00000400,
7522 + PCISM_ose_b = 11,
7523 + PCISM_ose_m = 0x00000800,
7524 + PCISM_pe_b = 12,
7525 + PCISM_pe_m = 0x00001000,
7526 + PCISM_tae_b = 13,
7527 + PCISM_tae_m = 0x00002000,
7528 + PCISM_rle_b = 14,
7529 + PCISM_rle_m = 0x00004000,
7530 + PCISM_bme_b = 15,
7531 + PCISM_bme_m = 0x00008000,
7532 + PCISM_prd_b = 16,
7533 + PCISM_prd_m = 0x00010000,
7534 + PCISM_rip_b = 17,
7535 + PCISM_rip_m = 0x00020000,
7536 +} ;
7537 +
7538 +/*******************************************************************************
7539 + *
7540 + * PCI Configuration Address Register
7541 + *
7542 + ******************************************************************************/
7543 +enum {
7544 + PCICFGA_reg_b = 2,
7545 + PCICFGA_reg_m = 0x000000fc,
7546 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
7547 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
7548 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
7549 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
7550 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
7551 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
7552 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
7553 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
7554 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
7555 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
7556 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
7557 + PCICFGA_reg_pba0m_v = 0x48>>2,
7558 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
7559 + PCICFGA_reg_pba1m_v = 0x50>>2,
7560 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
7561 + PCICFGA_reg_pba2m_v = 0x58>>2,
7562 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
7563 + PCICFGA_reg_pba3m_v = 0x60>>2,
7564 + PCICFGA_reg_pmgt_v = 0x64>>2,
7565 + PCICFGA_func_b = 8,
7566 + PCICFGA_func_m = 0x00000700,
7567 + PCICFGA_dev_b = 11,
7568 + PCICFGA_dev_m = 0x0000f800,
7569 + PCICFGA_dev_internal_v = 0,
7570 + PCICFGA_bus_b = 16,
7571 + PCICFGA_bus_m = 0x00ff0000,
7572 + PCICFGA_bus_type0_v = 0, //local bus
7573 + PCICFGA_en_b = 31, // read only
7574 + PCICFGA_en_m = 0x80000000,
7575 +} ;
7576 +
7577 +enum {
7578 + PCFGID_vendor_b = 0,
7579 + PCFGID_vendor_m = 0x0000ffff,
7580 + PCFGID_vendor_IDT_v = 0x111d,
7581 + PCFGID_device_b = 16,
7582 + PCFGID_device_m = 0xffff0000,
7583 + PCFGID_device_Korinade_v = 0x0214,
7584 +
7585 + PCFG04_command_ioena_b = 1,
7586 + PCFG04_command_ioena_m = 0x00000001,
7587 + PCFG04_command_memena_b = 2,
7588 + PCFG04_command_memena_m = 0x00000002,
7589 + PCFG04_command_bmena_b = 3,
7590 + PCFG04_command_bmena_m = 0x00000004,
7591 + PCFG04_command_mwinv_b = 5,
7592 + PCFG04_command_mwinv_m = 0x00000010,
7593 + PCFG04_command_parena_b = 7,
7594 + PCFG04_command_parena_m = 0x00000040,
7595 + PCFG04_command_serrena_b = 9,
7596 + PCFG04_command_serrena_m = 0x00000100,
7597 + PCFG04_command_fastbbena_b = 10,
7598 + PCFG04_command_fastbbena_m = 0x00000200,
7599 + PCFG04_status_b = 16,
7600 + PCFG04_status_m = 0xffff0000,
7601 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
7602 + PCFG04_status_66MHz_m = 0x00200000,
7603 + PCFG04_status_fbb_b = 23,
7604 + PCFG04_status_fbb_m = 0x00800000,
7605 + PCFG04_status_mdpe_b = 24,
7606 + PCFG04_status_mdpe_m = 0x01000000,
7607 + PCFG04_status_dst_b = 25,
7608 + PCFG04_status_dst_m = 0x06000000,
7609 + PCFG04_status_sta_b = 27,
7610 + PCFG04_status_sta_m = 0x08000000,
7611 + PCFG04_status_rta_b = 28,
7612 + PCFG04_status_rta_m = 0x10000000,
7613 + PCFG04_status_rma_b = 29,
7614 + PCFG04_status_rma_m = 0x20000000,
7615 + PCFG04_status_sse_b = 30,
7616 + PCFG04_status_sse_m = 0x40000000,
7617 + PCFG04_status_pe_b = 31,
7618 + PCFG04_status_pe_m = 0x40000000,
7619 +
7620 + PCFG08_revId_b = 0,
7621 + PCFG08_revId_m = 0x000000ff,
7622 + PCFG08_classCode_b = 0,
7623 + PCFG08_classCode_m = 0xffffff00,
7624 + PCFG08_classCode_bridge_v = 06,
7625 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
7626 + PCFG0C_cacheline_b = 0,
7627 + PCFG0C_cacheline_m = 0x000000ff,
7628 + PCFG0C_masterLatency_b = 8,
7629 + PCFG0C_masterLatency_m = 0x0000ff00,
7630 + PCFG0C_headerType_b = 16,
7631 + PCFG0C_headerType_m = 0x00ff0000,
7632 + PCFG0C_bist_b = 24,
7633 + PCFG0C_bist_m = 0xff000000,
7634 +
7635 + PCIPBA_msi_b = 0,
7636 + PCIPBA_msi_m = 0x00000001,
7637 + PCIPBA_p_b = 3,
7638 + PCIPBA_p_m = 0x00000004,
7639 + PCIPBA_baddr_b = 8,
7640 + PCIPBA_baddr_m = 0xffffff00,
7641 +
7642 + PCFGSS_vendorId_b = 0,
7643 + PCFGSS_vendorId_m = 0x0000ffff,
7644 + PCFGSS_id_b = 16,
7645 + PCFGSS_id_m = 0xffff0000,
7646 +
7647 + PCFG3C_interruptLine_b = 0,
7648 + PCFG3C_interruptLine_m = 0x000000ff,
7649 + PCFG3C_interruptPin_b = 8,
7650 + PCFG3C_interruptPin_m = 0x0000ff00,
7651 + PCFG3C_minGrant_b = 16,
7652 + PCFG3C_minGrant_m = 0x00ff0000,
7653 + PCFG3C_maxLat_b = 24,
7654 + PCFG3C_maxLat_m = 0xff000000,
7655 +
7656 + PCIPBAC_msi_b = 0,
7657 + PCIPBAC_msi_m = 0x00000001,
7658 + PCIPBAC_p_b = 1,
7659 + PCIPBAC_p_m = 0x00000002,
7660 + PCIPBAC_size_b = 2,
7661 + PCIPBAC_size_m = 0x0000007c,
7662 + PCIPBAC_sb_b = 7,
7663 + PCIPBAC_sb_m = 0x00000080,
7664 + PCIPBAC_pp_b = 8,
7665 + PCIPBAC_pp_m = 0x00000100,
7666 + PCIPBAC_mr_b = 9,
7667 + PCIPBAC_mr_m = 0x00000600,
7668 + PCIPBAC_mr_read_v =0, //no prefetching
7669 + PCIPBAC_mr_readLine_v =1,
7670 + PCIPBAC_mr_readMult_v =2,
7671 + PCIPBAC_mrl_b = 11,
7672 + PCIPBAC_mrl_m = 0x00000800,
7673 + PCIPBAC_mrm_b = 12,
7674 + PCIPBAC_mrm_m = 0x00001000,
7675 + PCIPBAC_trp_b = 13,
7676 + PCIPBAC_trp_m = 0x00002000,
7677 +
7678 + PCFG40_trdyTimeout_b = 0,
7679 + PCFG40_trdyTimeout_m = 0x000000ff,
7680 + PCFG40_retryLim_b = 8,
7681 + PCFG40_retryLim_m = 0x0000ff00,
7682 +};
7683 +
7684 +/*******************************************************************************
7685 + *
7686 + * PCI Local Base Address [0|1|2|3] Register
7687 + *
7688 + ******************************************************************************/
7689 +enum {
7690 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
7691 + PCILBA_baddr_m = 0xffffff00,
7692 +} ;
7693 +/*******************************************************************************
7694 + *
7695 + * PCI Local Base Address Control Register
7696 + *
7697 + ******************************************************************************/
7698 +enum {
7699 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
7700 + PCILBAC_msi_m = 0x00000001,
7701 + PCILBAC_msi_mem_v = 0,
7702 + PCILBAC_msi_io_v = 1,
7703 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
7704 + PCILBAC_size_m = 0x0000007c,
7705 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
7706 + PCILBAC_sb_m = 0x00000080,
7707 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
7708 + PCILBAC_rt_m = 0x00000100,
7709 + PCILBAC_rt_noprefetch_v = 0, // mem read
7710 + PCILBAC_rt_prefetch_v = 1, // mem readline
7711 +} ;
7712 +
7713 +/*******************************************************************************
7714 + *
7715 + * PCI Local Base Address [0|1|2|3] Mapping Register
7716 + *
7717 + ******************************************************************************/
7718 +enum {
7719 + PCILBAM_maddr_b = 8,
7720 + PCILBAM_maddr_m = 0xffffff00,
7721 +} ;
7722 +
7723 +/*******************************************************************************
7724 + *
7725 + * PCI Decoupled Access Control Register
7726 + *
7727 + ******************************************************************************/
7728 +enum {
7729 + PCIDAC_den_b = 0,
7730 + PCIDAC_den_m = 0x00000001,
7731 +} ;
7732 +
7733 +/*******************************************************************************
7734 + *
7735 + * PCI Decoupled Access Status Register
7736 + *
7737 + ******************************************************************************/
7738 +enum {
7739 + PCIDAS_d_b = 0,
7740 + PCIDAS_d_m = 0x00000001,
7741 + PCIDAS_b_b = 1,
7742 + PCIDAS_b_m = 0x00000002,
7743 + PCIDAS_e_b = 2,
7744 + PCIDAS_e_m = 0x00000004,
7745 + PCIDAS_ofe_b = 3,
7746 + PCIDAS_ofe_m = 0x00000008,
7747 + PCIDAS_off_b = 4,
7748 + PCIDAS_off_m = 0x00000010,
7749 + PCIDAS_ife_b = 5,
7750 + PCIDAS_ife_m = 0x00000020,
7751 + PCIDAS_iff_b = 6,
7752 + PCIDAS_iff_m = 0x00000040,
7753 +} ;
7754 +
7755 +/*******************************************************************************
7756 + *
7757 + * PCI DMA Channel 8 Configuration Register
7758 + *
7759 + ******************************************************************************/
7760 +enum
7761 +{
7762 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
7763 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
7764 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
7765 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
7766 +} ;
7767 +
7768 +/*******************************************************************************
7769 + *
7770 + * PCI DMA Channel 9 Configuration Register
7771 + *
7772 + ******************************************************************************/
7773 +enum
7774 +{
7775 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
7776 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
7777 +} ;
7778 +
7779 +/*******************************************************************************
7780 + *
7781 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
7782 + *
7783 + ******************************************************************************/
7784 +enum {
7785 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
7786 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
7787 + // These are for reads (DMA channel 8)
7788 + PCIDMAD_devcmd_mr_v = 0, //memory read
7789 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
7790 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
7791 + PCIDMAD_devcmd_ior_v = 3, //I/O read
7792 + // These are for writes (DMA channel 9)
7793 + PCIDMAD_devcmd_mw_v = 0, //memory write
7794 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
7795 + PCIDMAD_devcmd_iow_v = 3, //I/O write
7796 +
7797 + // Swap byte field applies to both DMA channel 8 and 9
7798 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
7799 + PCIDMAD_sb_m = 0x01000000, // swap byte field
7800 +} ;
7801 +
7802 +
7803 +/*******************************************************************************
7804 + *
7805 + * PCI Target Control Register
7806 + *
7807 + ******************************************************************************/
7808 +enum
7809 +{
7810 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
7811 + PCITC_rtimer_m = 0x000000ff,
7812 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
7813 + PCITC_dtimer_m = 0x0000ff00,
7814 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
7815 + PCITC_rdr_m = 0x00040000,
7816 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
7817 + PCITC_ddt_m = 0x00080000,
7818 +} ;
7819 +/*******************************************************************************
7820 + *
7821 + * PCI messaging unit [applies to both inbound and outbound registers ]
7822 + *
7823 + ******************************************************************************/
7824 +enum
7825 +{
7826 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7827 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
7828 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7829 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
7830 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
7831 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
7832 +};
7833 +
7834 +
7835 +
7836 +
7837 +
7838 +
7839 +#define PCI_MSG_VirtualAddress 0xB8088010
7840 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
7841 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
7842 +
7843 +#define PCIM_SHFT 0x6
7844 +#define PCIM_BIT_LEN 0x7
7845 +#define PCIM_H_EA 0x3
7846 +#define PCIM_H_IA_FIX 0x4
7847 +#define PCIM_H_IA_RR 0x5
7848 +#if 0
7849 +#define PCI_ADDR_START 0x13000000
7850 +#endif
7851 +
7852 +#define PCI_ADDR_START 0x50000000
7853 +
7854 +#define CPUTOPCI_MEM_WIN 0x02000000
7855 +#define CPUTOPCI_IO_WIN 0x00100000
7856 +#define PCILBA_SIZE_SHFT 2
7857 +#define PCILBA_SIZE_MASK 0x1F
7858 +#define SIZE_256MB 0x1C
7859 +#define SIZE_128MB 0x1B
7860 +#define SIZE_64MB 0x1A
7861 +#define SIZE_32MB 0x19
7862 +#define SIZE_16MB 0x18
7863 +#define SIZE_4MB 0x16
7864 +#define SIZE_2MB 0x15
7865 +#define SIZE_1MB 0x14
7866 +#define KORINA_CONFIG0_ADDR 0x80000000
7867 +#define KORINA_CONFIG1_ADDR 0x80000004
7868 +#define KORINA_CONFIG2_ADDR 0x80000008
7869 +#define KORINA_CONFIG3_ADDR 0x8000000C
7870 +#define KORINA_CONFIG4_ADDR 0x80000010
7871 +#define KORINA_CONFIG5_ADDR 0x80000014
7872 +#define KORINA_CONFIG6_ADDR 0x80000018
7873 +#define KORINA_CONFIG7_ADDR 0x8000001C
7874 +#define KORINA_CONFIG8_ADDR 0x80000020
7875 +#define KORINA_CONFIG9_ADDR 0x80000024
7876 +#define KORINA_CONFIG10_ADDR 0x80000028
7877 +#define KORINA_CONFIG11_ADDR 0x8000002C
7878 +#define KORINA_CONFIG12_ADDR 0x80000030
7879 +#define KORINA_CONFIG13_ADDR 0x80000034
7880 +#define KORINA_CONFIG14_ADDR 0x80000038
7881 +#define KORINA_CONFIG15_ADDR 0x8000003C
7882 +#define KORINA_CONFIG16_ADDR 0x80000040
7883 +#define KORINA_CONFIG17_ADDR 0x80000044
7884 +#define KORINA_CONFIG18_ADDR 0x80000048
7885 +#define KORINA_CONFIG19_ADDR 0x8000004C
7886 +#define KORINA_CONFIG20_ADDR 0x80000050
7887 +#define KORINA_CONFIG21_ADDR 0x80000054
7888 +#define KORINA_CONFIG22_ADDR 0x80000058
7889 +#define KORINA_CONFIG23_ADDR 0x8000005C
7890 +#define KORINA_CONFIG24_ADDR 0x80000060
7891 +#define KORINA_CONFIG25_ADDR 0x80000064
7892 +#define KORINA_CMD (PCFG04_command_ioena_m | \
7893 + PCFG04_command_memena_m | \
7894 + PCFG04_command_bmena_m | \
7895 + PCFG04_command_mwinv_m | \
7896 + PCFG04_command_parena_m | \
7897 + PCFG04_command_serrena_m )
7898 +
7899 +#define KORINA_STAT (PCFG04_status_mdpe_m | \
7900 + PCFG04_status_sta_m | \
7901 + PCFG04_status_rta_m | \
7902 + PCFG04_status_rma_m | \
7903 + PCFG04_status_sse_m | \
7904 + PCFG04_status_pe_m)
7905 +
7906 +#define KORINA_CNFG1 ((KORINA_STAT<<16)|KORINA_CMD)
7907 +
7908 +#define KORINA_REVID 0
7909 +#define KORINA_CLASS_CODE 0
7910 +#define KORINA_CNFG2 ((KORINA_CLASS_CODE<<8) | \
7911 + KORINA_REVID)
7912 +
7913 +#define KORINA_CACHE_LINE_SIZE 4
7914 +#define KORINA_MASTER_LAT 0x3c
7915 +#define KORINA_HEADER_TYPE 0
7916 +#define KORINA_BIST 0
7917 +
7918 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
7919 + (KORINA_HEADER_TYPE<<16) | \
7920 + (KORINA_MASTER_LAT<<8) | \
7921 + KORINA_CACHE_LINE_SIZE )
7922 +
7923 +#define KORINA_BAR0 0x00000008 /* 128 MB Memory */
7924 +#define KORINA_BAR1 0x18800001 /* 1 MB IO */
7925 +#define KORINA_BAR2 0x18000001 /* 2 MB IO window for Korina
7926 + internal Registers */
7927 +#define KORINA_BAR3 0x48000008 /* Spare 128 MB Memory */
7928 +
7929 +#define KORINA_CNFG4 KORINA_BAR0
7930 +#define KORINA_CNFG5 KORINA_BAR1
7931 +#define KORINA_CNFG6 KORINA_BAR2
7932 +#define KORINA_CNFG7 KORINA_BAR3
7933 +
7934 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
7935 +#define KORINA_SUBSYSTEM_ID 0x0214
7936 +#define KORINA_CNFG8 0
7937 +#define KORINA_CNFG9 0
7938 +#define KORINA_CNFG10 0
7939 +#define KORINA_CNFG11 ((KORINA_SUBSYS_VENDOR_ID<<16) | \
7940 + KORINA_SUBSYSTEM_ID)
7941 +#define KORINA_INT_LINE 1
7942 +#define KORINA_INT_PIN 1
7943 +#define KORINA_MIN_GNT 8
7944 +#define KORINA_MAX_LAT 0x38
7945 +#define KORINA_CNFG12 0
7946 +#define KORINA_CNFG13 0
7947 +#define KORINA_CNFG14 0
7948 +#define KORINA_CNFG15 ((KORINA_MAX_LAT<<24) | \
7949 + (KORINA_MIN_GNT<<16) | \
7950 + (KORINA_INT_PIN<<8) | \
7951 + KORINA_INT_LINE)
7952 +#define KORINA_RETRY_LIMIT 0x80
7953 +#define KORINA_TRDY_LIMIT 0x80
7954 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
7955 + KORINA_TRDY_LIMIT)
7956 +#define PCI_PBAxC_R 0x0
7957 +#define PCI_PBAxC_RL 0x1
7958 +#define PCI_PBAxC_RM 0x2
7959 +#define SIZE_SHFT 2
7960 +
7961 +#if defined(__MIPSEB__)
7962 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
7963 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7964 + PCIPBAC_pp_m | \
7965 + (SIZE_128MB<<SIZE_SHFT) | \
7966 + PCIPBAC_p_m)
7967 +#else
7968 +#define KORINA_PBA0C ( PCIPBAC_mrl_m | \
7969 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
7970 + PCIPBAC_pp_m | \
7971 + (SIZE_128MB<<SIZE_SHFT) | \
7972 + PCIPBAC_p_m)
7973 +#endif
7974 +#define KORINA_CNFG17 KORINA_PBA0C
7975 +#define KORINA_PBA0M 0x0
7976 +#define KORINA_CNFG18 KORINA_PBA0M
7977 +
7978 +#if defined(__MIPSEB__)
7979 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7980 + PCIPBAC_msi_m)
7981 +#else
7982 +#define KORINA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | \
7983 + PCIPBAC_msi_m)
7984 +#endif
7985 +#define KORINA_CNFG19 KORINA_PBA1C
7986 +#define KORINA_PBA1M 0x0
7987 +#define KORINA_CNFG20 KORINA_PBA1M
7988 +
7989 +#if defined(__MIPSEB__)
7990 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
7991 + PCIPBAC_msi_m)
7992 +#else
7993 +#define KORINA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | \
7994 + PCIPBAC_msi_m)
7995 +#endif
7996 +#define KORINA_CNFG21 KORINA_PBA2C
7997 +#define KORINA_PBA2M 0x18000000
7998 +#define KORINA_CNFG22 KORINA_PBA2M
7999 +#define KORINA_PBA3C 0
8000 +#define KORINA_CNFG23 KORINA_PBA3C
8001 +#define KORINA_PBA3M 0
8002 +#define KORINA_CNFG24 KORINA_PBA3M
8003 +
8004 +
8005 +
8006 +#define PCITC_DTIMER_VAL 8
8007 +#define PCITC_RTIMER_VAL 0x10
8008 +
8009 +
8010 +
8011 +
8012 +#endif // __IDT_PCI_H__
8013 +
8014 +
8015 +
8016 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h
8017 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 1970-01-01 01:00:00.000000000 +0100
8018 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_rst.h 2006-06-18 12:44:28.000000000 +0200
8019 @@ -0,0 +1,119 @@
8020 +/**************************************************************************
8021 + *
8022 + * BRIEF MODULE DESCRIPTION
8023 + * Reset register definitions.
8024 + *
8025 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8026 + *
8027 + * This program is free software; you can redistribute it and/or modify it
8028 + * under the terms of the GNU General Public License as published by the
8029 + * Free Software Foundation; either version 2 of the License, or (at your
8030 + * option) any later version.
8031 + *
8032 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8033 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8034 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8035 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8036 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8037 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8038 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8039 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8040 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8041 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8042 + *
8043 + * You should have received a copy of the GNU General Public License along
8044 + * with this program; if not, write to the Free Software Foundation, Inc.,
8045 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8046 + *
8047 + *
8048 + **************************************************************************
8049 + * May 2004 rkt, neb.
8050 + *
8051 + * Initial Release
8052 + *
8053 + *
8054 + *
8055 + **************************************************************************
8056 + */
8057 +
8058 +#ifndef __IDT_RST_H__
8059 +#define __IDT_RST_H__
8060 +
8061 +enum
8062 +{
8063 + RST0_PhysicalAddress = 0x18000000,
8064 + RST_PhysicalAddress = RST0_PhysicalAddress, // Default
8065 +
8066 + RST0_VirtualAddress = 0xb8000000,
8067 + RST_VirtualAddress = RST0_VirtualAddress, // Default
8068 +} ;
8069 +
8070 +typedef struct RST_s
8071 +{
8072 + u32 filler [0x0006] ;
8073 + u32 sysid ;
8074 + u32 filler2 [0x2000-8] ; // Pad out to offset 0x8000
8075 + u32 reset ;
8076 + u32 bcv ;
8077 + u32 cea ;
8078 +} volatile * RST_t ;
8079 +
8080 +enum
8081 +{
8082 + SYSID_rev_b = 0,
8083 + SYSID_rev_m = 0x000000ff,
8084 + SYSID_imp_b = 8,
8085 + SYSID_imp_m = 0x000fff00,
8086 + SYSID_vendor_b = 8,
8087 + SYSID_vendor_m = 0xfff00000,
8088 +
8089 + BCV_pll_b = 0,
8090 + BCV_pll_m = 0x0000000f,
8091 + BCV_pll_PLLBypass_v = 0x0, // PCLK=1*CLK.
8092 + BCV_pll_Mul3_v = 0x1, // PCLK=3*CLK.
8093 + BCV_pll_Mul4_v = 0x2, // PCLK=4*CLK.
8094 + BCV_pll_SlowMul5_v = 0x3, // PCLK=5*CLK.
8095 + BCV_pll_Mul5_v = 0x4, // PCLK=5*CLK.
8096 + BCV_pll_SlowMul6_v = 0x5, // PCLK=6*CLK.
8097 + BCV_pll_Mul6_v = 0x6, // PCLK=6*CLK.
8098 + BCV_pll_Mul8_v = 0x7, // PCLK=8*CLK.
8099 + BCV_pll_Mul10_v = 0x8, // PCLK=10*CLK.
8100 + BCV_pll_Res9_v = 0x9,
8101 + BCV_pll_Res10_v = 0xa,
8102 + BCV_pll_Res11_v = 0xb,
8103 + BCV_pll_Res12_v = 0xc,
8104 + BCV_pll_Res13_v = 0xd,
8105 + BCV_pll_Res14_v = 0xe,
8106 + BCV_pll_Res15_v = 0xf,
8107 + BCV_clkDiv_b = 4,
8108 + BCV_clkDiv_m = 0x00000030,
8109 + BCV_clkDiv_Div1_v = 0x0,
8110 + BCV_clkDiv_Div2_v = 0x1,
8111 + BCV_clkDiv_Div4_v = 0x2,
8112 + BCV_clkDiv_Res3_v = 0x3,
8113 + BCV_bigEndian_b = 6,
8114 + BCV_bigEndian_m = 0x00000040,
8115 + BCV_resetFast_b = 7,
8116 + BCV_resetFast_m = 0x00000080,
8117 + BCV_pciMode_b = 8,
8118 + BCV_pciMode_m = 0x00000700,
8119 + BCV_pciMode_disabled_v = 0, // PCI is disabled.
8120 + BCV_pciMode_tnr_v = 1, // satellite Target Not Ready.
8121 + BCV_pciMode_suspended_v = 2, // satellite with suspended CPU.
8122 + BCV_pciMode_external_v = 3, // host, external arbiter.
8123 + BCV_pciMode_fixed_v = 4, // host, fixed priority arbiter.
8124 + BCV_pciMode_roundRobin_v= 5, // host, round robin arbiter.
8125 + BCV_pciMode_res6_v = 6,
8126 + BCV_pciMode_res7_v = 7,
8127 + BCV_watchDisable_b = 11,
8128 + BCV_watchDisable_m = 0x00000800,
8129 + BCV_res12_b = 12,
8130 + BCV_res12_m = 0x00001000,
8131 + BCV_res13_b = 13,
8132 + BCV_res13_m = 0x00002000,
8133 + BCV_res14_b = 14,
8134 + BCV_res14_m = 0x00004000,
8135 + BCV_res15_b = 15,
8136 + BCV_res15_m = 0x00008000,
8137 +} ;
8138 +#endif // __IDT_RST_H__
8139 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h
8140 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 1970-01-01 01:00:00.000000000 +0100
8141 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_spi.h 2006-06-18 12:44:28.000000000 +0200
8142 @@ -0,0 +1,120 @@
8143 +/**************************************************************************
8144 + *
8145 + * BRIEF MODULE DESCRIPTION
8146 + * Serial Peripheral Interface register definitions.
8147 + *
8148 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8149 + *
8150 + * This program is free software; you can redistribute it and/or modify it
8151 + * under the terms of the GNU General Public License as published by the
8152 + * Free Software Foundation; either version 2 of the License, or (at your
8153 + * option) any later version.
8154 + *
8155 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8156 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8157 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8158 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8159 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8160 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8161 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8162 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8163 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8164 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8165 + *
8166 + * You should have received a copy of the GNU General Public License along
8167 + * with this program; if not, write to the Free Software Foundation, Inc.,
8168 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8169 + *
8170 + *
8171 + **************************************************************************
8172 + * May 2004 rkt, neb.
8173 + *
8174 + * Initial Release
8175 + *
8176 + *
8177 + *
8178 + **************************************************************************
8179 + */
8180 +
8181 +#ifndef __IDT_SPI_H__
8182 +#define __IDT_SPI_H__
8183 +
8184 +enum
8185 +{
8186 + SPI0_PhysicalAddress = 0x18070000,
8187 + SPI_PhysicalAddress = SPI0_PhysicalAddress,
8188 +
8189 + SPI0_VirtualAddress = 0xB8070000,
8190 + SPI_VirtualAddress = SPI0_VirtualAddress,
8191 +} ;
8192 +
8193 +typedef struct
8194 +{
8195 + u32 spcp ; // prescalar. 0=off, * spiClk = sysClk/(2*(spcp+1)*SPR)
8196 + u32 spc ; // spi control reg use SPC_
8197 + u32 sps ; // spi status reg use SPS_
8198 + u32 spd ; // spi data reg use SPD_
8199 + u32 siofunc ; // serial IO function use SIOFUNC_
8200 + u32 siocfg ; // serial IO config use SIOCFG_
8201 + u32 siod; // serial IO data use SIOD_
8202 +} volatile *SPI_t ;
8203 +
8204 +enum
8205 +{
8206 + SPCP_div_b = 0,
8207 + SPCP_div_m = 0x000000ff,
8208 + SPC_spr_b = 0,
8209 + SPC_spr_m = 0x00000003,
8210 + SPC_spr_div2_v = 0,
8211 + SPC_spr_div4_v = 1,
8212 + SPC_spr_div16_v = 2,
8213 + SPC_spr_div32_v = 3,
8214 + SPC_cpha_b = 2,
8215 + SPC_cpha_m = 0x00000004,
8216 + SPC_cpol_b = 3,
8217 + SPC_cpol_m = 0x00000008,
8218 + SPC_mstr_b = 4,
8219 + SPC_mstr_m = 0x00000010,
8220 + SPC_spe_b = 6,
8221 + SPC_spe_m = 0x00000040,
8222 + SPC_spie_b = 7,
8223 + SPC_spie_m = 0x00000080,
8224 +
8225 + SPS_modf_b = 4,
8226 + SPS_modf_m = 0x00000010,
8227 + SPS_wcol_b = 6,
8228 + SPS_wcol_m = 0x00000040,
8229 + SPS_spif_b = 7,
8230 + SPS_spif_m = 0x00000070,
8231 +
8232 + SPD_data_b = 0,
8233 + SPD_data_m = 0x000000ff,
8234 +
8235 + SIOFUNC_sdo_b = 0,
8236 + SIOFUNC_sdo_m = 0x00000001,
8237 + SIOFUNC_sdi_b = 1,
8238 + SIOFUNC_sdi_m = 0x00000002,
8239 + SIOFUNC_sck_b = 2,
8240 + SIOFUNC_sck_m = 0x00000004,
8241 + SIOFUNC_pci_b = 3,
8242 + SIOFUNC_pci_m = 0x00000008,
8243 +
8244 + SIOCFG_sdo_b = 0,
8245 + SIOCFG_sdo_m = 0x00000001,
8246 + SIOCFG_sdi_b = 1,
8247 + SIOCFG_sdi_m = 0x00000002,
8248 + SIOCFG_sck_b = 2,
8249 + SIOCFG_sck_m = 0x00000004,
8250 + SIOCFG_pci_b = 3,
8251 + SIOCFG_pci_m = 0x00000008,
8252 +
8253 + SIOD_sdo_b = 0,
8254 + SIOD_sdo_m = 0x00000001,
8255 + SIOD_sdi_b = 1,
8256 + SIOD_sdi_m = 0x00000002,
8257 + SIOD_sck_b = 2,
8258 + SIOD_sck_m = 0x00000004,
8259 + SIOD_pci_b = 3,
8260 + SIOD_pci_m = 0x00000008,
8261 +} ;
8262 +#endif // __IDT_SPI_H__
8263 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h
8264 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 1970-01-01 01:00:00.000000000 +0100
8265 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_timer.h 2006-06-18 12:44:28.000000000 +0200
8266 @@ -0,0 +1,91 @@
8267 +/**************************************************************************
8268 + *
8269 + * BRIEF MODULE DESCRIPTION
8270 + * Definitions for timer registers
8271 + *
8272 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8273 + *
8274 + * This program is free software; you can redistribute it and/or modify it
8275 + * under the terms of the GNU General Public License as published by the
8276 + * Free Software Foundation; either version 2 of the License, or (at your
8277 + * option) any later version.
8278 + *
8279 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8280 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8281 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8282 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8283 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8284 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8285 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8286 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8287 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8288 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8289 + *
8290 + * You should have received a copy of the GNU General Public License along
8291 + * with this program; if not, write to the Free Software Foundation, Inc.,
8292 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8293 + *
8294 + *
8295 + **************************************************************************
8296 + * May 2004 rkt,neb.
8297 + *
8298 + * Initial Release
8299 + *
8300 + *
8301 + *
8302 + **************************************************************************
8303 + */
8304 +
8305 +#ifndef __IDT_TIM_H__
8306 +#define __IDT_TIM_H__
8307 +
8308 +enum
8309 +{
8310 + TIM0_PhysicalAddress = 0x18028000,
8311 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
8312 +
8313 + TIM0_VirtualAddress = 0xb8028000,
8314 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
8315 +} ;
8316 +
8317 +enum
8318 +{
8319 + TIM_Count = 3,
8320 +} ;
8321 +
8322 +struct TIM_CNTR_s
8323 +{
8324 + u32 count ;
8325 + u32 compare ;
8326 + u32 ctc ; //use CTC_
8327 +} ;
8328 +
8329 +typedef struct TIM_s
8330 +{
8331 + struct TIM_CNTR_s tim [TIM_Count] ;
8332 + u32 rcount ; //use RCOUNT_
8333 + u32 rcompare ; //use RCOMPARE_
8334 + u32 rtc ; //use RTC_
8335 +} volatile * TIM_t ;
8336 +
8337 +enum
8338 +{
8339 + CTC_en_b = 0,
8340 + CTC_en_m = 0x00000001,
8341 + CTC_to_b = 1,
8342 + CTC_to_m = 0x00000002,
8343 +
8344 + RCOUNT_count_b = 0,
8345 + RCOUNT_count_m = 0x0000ffff,
8346 + RCOMPARE_compare_b = 0,
8347 + RCOMPARE_compare_m = 0x0000ffff,
8348 + RTC_ce_b = 0,
8349 + RTC_ce_m = 0x00000001,
8350 + RTC_to_b = 1,
8351 + RTC_to_m = 0x00000002,
8352 + RTC_rqe_b = 2,
8353 + RTC_rqe_m = 0x00000004,
8354 +
8355 +} ;
8356 +#endif // __IDT_TIM_H__
8357 +
8358 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h
8359 --- linux-2.6.17/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 1970-01-01 01:00:00.000000000 +0100
8360 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32434/rc32434_uart.h 2006-06-18 12:44:28.000000000 +0200
8361 @@ -0,0 +1,189 @@
8362 +/**************************************************************************
8363 + *
8364 + * BRIEF MODULE DESCRIPTION
8365 + * UART register definitions
8366 + *
8367 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8368 + *
8369 + * This program is free software; you can redistribute it and/or modify it
8370 + * under the terms of the GNU General Public License as published by the
8371 + * Free Software Foundation; either version 2 of the License, or (at your
8372 + * option) any later version.
8373 + *
8374 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8375 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8376 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8377 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8378 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8379 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8380 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8381 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8382 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8383 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8384 + *
8385 + * You should have received a copy of the GNU General Public License along
8386 + * with this program; if not, write to the Free Software Foundation, Inc.,
8387 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8388 + *
8389 + *
8390 + **************************************************************************
8391 + * May 2004 rkt, neb.
8392 + *
8393 + * Initial Release
8394 + *
8395 + *
8396 + *
8397 + **************************************************************************
8398 + */
8399 +
8400 +#ifndef __IDT_UART_H__
8401 +#define __IDT_UART_H__
8402 +
8403 +enum
8404 +{
8405 + UART0_PhysicalAddress = 0x1c000000,
8406 + UART_PhysicalAddress = UART0_PhysicalAddress, // Default
8407 +
8408 + UART0_VirtualAddress = 0xbc000000,
8409 + UART_VirtualAddress = UART0_VirtualAddress, // Default
8410 +} ;
8411 +
8412 +/*
8413 + * Register definitions are in bytes so we can handle endian problems.
8414 + */
8415 +
8416 +typedef struct UART_s
8417 +{
8418 + union
8419 + {
8420 + u32 const uartrb ; // 0x00 - DLAB=0, read.
8421 + u32 uartth ; // 0x00 - DLAB=0, write.
8422 + u32 uartdll ; // 0x00 - DLAB=1, read/write.
8423 + } ;
8424 +
8425 + union
8426 + {
8427 + u32 uartie ; // 0x04 - DLAB=0, read/write.
8428 + u32 uartdlh ; // 0x04 - DLAB=1, read/write.
8429 + } ;
8430 + union
8431 + {
8432 + u32 const uartii ; // 0x08 - DLAB=0, read.
8433 + u32 uartfc ; // 0x08 - DLAB=0, write.
8434 + } ;
8435 +
8436 + u32 uartlc ; // 0x0c
8437 + u32 uartmc ; // 0x10
8438 + u32 uartls ; // 0x14
8439 + u32 uartms ; // 0x18
8440 + u32 uarts ; // 0x1c
8441 +} volatile *UART_t ;
8442 +
8443 +// Reset registers.
8444 +typedef u32 volatile *UARTRR_t ;
8445 +
8446 +enum
8447 +{
8448 + UARTIE_rda_b = 0,
8449 + UARTIE_rda_m = 0x00000001,
8450 + UARTIE_the_b = 1,
8451 + UARTIE_the_m = 0x00000002,
8452 + UARTIE_rls_b = 2,
8453 + UARTIE_rls_m = 0x00000004,
8454 + UARTIE_ems_b = 3,
8455 + UARTIE_ems_m = 0x00000008,
8456 +
8457 + UARTII_pi_b = 0,
8458 + UARTII_pi_m = 0x00000001,
8459 + UARTII_iid_b = 1,
8460 + UARTII_iid_m = 0x0000000e,
8461 + UARTII_iid_ms_v = 0, // Modem stat-CTS,DSR,RI or DCD.
8462 + UARTII_iid_thre_v = 1, // Trans. Holding Reg. empty.
8463 + UARTII_iid_rda_v = 2, // Receive data available
8464 + UARTII_iid_rls_v = 3, // Overrun, parity, etc, error.
8465 + UARTII_iid_res4_v = 4, // reserved.
8466 + UARTII_iid_res5_v = 5, // reserved.
8467 + UARTII_iid_cto_v = 6, // Character timeout.
8468 + UARTII_iid_res7_v = 7, // reserved.
8469 +
8470 + UARTFC_en_b = 0,
8471 + UARTFC_en_m = 0x00000001,
8472 + UARTFC_rr_b = 1,
8473 + UARTFC_rr_m = 0x00000002,
8474 + UARTFC_tr_b = 2,
8475 + UARTFC_tr_m = 0x00000004,
8476 + UARTFC_dms_b = 3,
8477 + UARTFC_dms_m = 0x00000008,
8478 + UARTFC_rt_b = 6,
8479 + UARTFC_rt_m = 0x000000c0,
8480 + UARTFC_rt_1Byte_v = 0,
8481 + UARTFC_rt_4Byte_v = 1,
8482 + UARTFC_rt_8Byte_v = 2,
8483 + UARTFC_rt_14Byte_v = 3,
8484 +
8485 + UARTLC_wls_b = 0,
8486 + UARTLC_wls_m = 0x00000003,
8487 + UARTLC_wls_5Bits_v = 0,
8488 + UARTLC_wls_6Bits_v = 1,
8489 + UARTLC_wls_7Bits_v = 2,
8490 + UARTLC_wls_8Bits_v = 3,
8491 + UARTLC_stb_b = 2,
8492 + UARTLC_stb_m = 0x00000004,
8493 + UARTLC_pen_b = 3,
8494 + UARTLC_pen_m = 0x00000008,
8495 + UARTLC_eps_b = 4,
8496 + UARTLC_eps_m = 0x00000010,
8497 + UARTLC_sp_b = 5,
8498 + UARTLC_sp_m = 0x00000020,
8499 + UARTLC_sb_b = 6,
8500 + UARTLC_sb_m = 0x00000040,
8501 + UARTLC_dlab_b = 7,
8502 + UARTLC_dlab_m = 0x00000080,
8503 +
8504 + UARTMC_dtr_b = 0,
8505 + UARTMC_dtr_m = 0x00000001,
8506 + UARTMC_rts_b = 1,
8507 + UARTMC_rts_m = 0x00000002,
8508 + UARTMC_o1_b = 2,
8509 + UARTMC_o1_m = 0x00000004,
8510 + UARTMC_o2_b = 3,
8511 + UARTMC_o2_m = 0x00000008,
8512 + UARTMC_lp_b = 4,
8513 + UARTMC_lp_m = 0x00000010,
8514 +
8515 + UARTLS_dr_b = 0,
8516 + UARTLS_dr_m = 0x00000001,
8517 + UARTLS_oe_b = 1,
8518 + UARTLS_oe_m = 0x00000002,
8519 + UARTLS_pe_b = 2,
8520 + UARTLS_pe_m = 0x00000004,
8521 + UARTLS_fe_b = 3,
8522 + UARTLS_fe_m = 0x00000008,
8523 + UARTLS_bi_b = 4,
8524 + UARTLS_bi_m = 0x00000010,
8525 + UARTLS_thr_b = 5,
8526 + UARTLS_thr_m = 0x00000020,
8527 + UARTLS_te_b = 6,
8528 + UARTLS_te_m = 0x00000040,
8529 + UARTLS_rfe_b = 7,
8530 + UARTLS_rfe_m = 0x00000080,
8531 +
8532 + UARTMS_dcts_b = 0,
8533 + UARTMS_dcts_m = 0x00000001,
8534 + UARTMS_ddsr_b = 1,
8535 + UARTMS_ddsr_m = 0x00000002,
8536 + UARTMS_teri_b = 2,
8537 + UARTMS_teri_m = 0x00000004,
8538 + UARTMS_ddcd_b = 3,
8539 + UARTMS_ddcd_m = 0x00000008,
8540 + UARTMS_cts_b = 4,
8541 + UARTMS_cts_m = 0x00000010,
8542 + UARTMS_dsr_b = 5,
8543 + UARTMS_dsr_m = 0x00000020,
8544 + UARTMS_ri_b = 6,
8545 + UARTMS_ri_m = 0x00000040,
8546 + UARTMS_dcd_b = 7,
8547 + UARTMS_dcd_m = 0x00000080,
8548 +} ;
8549 +
8550 +#endif // __IDT_UART_H__
8551 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h
8552 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 1970-01-01 01:00:00.000000000 +0100
8553 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma.h 2006-06-18 12:44:28.000000000 +0200
8554 @@ -0,0 +1,231 @@
8555 +/**************************************************************************
8556 + *
8557 + * BRIEF MODULE DESCRIPTION
8558 + * Register definitions for IDT RC32438 DMA.
8559 + *
8560 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8561 + *
8562 + * This program is free software; you can redistribute it and/or modify it
8563 + * under the terms of the GNU General Public License as published by the
8564 + * Free Software Foundation; either version 2 of the License, or (at your
8565 + * option) any later version.
8566 + *
8567 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8568 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8569 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8570 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8571 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8572 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8573 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8574 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8575 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8576 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8577 + *
8578 + * You should have received a copy of the GNU General Public License along
8579 + * with this program; if not, write to the Free Software Foundation, Inc.,
8580 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8581 + *
8582 + *
8583 + **************************************************************************
8584 + * May 2004 P. Sadik.
8585 + *
8586 + * Initial Release
8587 + *
8588 + *
8589 + *
8590 + **************************************************************************
8591 + */
8592 +#ifndef __IDT_RC32438_DMA_H__
8593 +#define __IDT_RC32438_DMA_H__
8594 +enum
8595 +{
8596 + DMA0_PhysicalAddress = 0x18040000,
8597 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
8598 +
8599 + DMA0_VirtualAddress = 0xb8040000,
8600 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
8601 +} ;
8602 +
8603 +/*
8604 + * DMA descriptor (in physical memory).
8605 + */
8606 +
8607 +typedef struct DMAD_s
8608 +{
8609 + u32 control ; // Control. use DMAD_*
8610 + u32 ca ; // Current Address.
8611 + u32 devcs ; // Device control and status.
8612 + u32 link ; // Next descriptor in chain.
8613 +} volatile *DMAD_t ;
8614 +
8615 +enum
8616 +{
8617 + DMAD_size = sizeof (struct DMAD_s),
8618 + DMAD_count_b = 0, // in DMAD_t -> control
8619 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
8620 + DMAD_ds_b = 20, // in DMAD_t -> control
8621 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
8622 + DMAD_ds_extToMem0_v = 0,
8623 + DMAD_ds_memToExt0_v = 1,
8624 + DMAD_ds_extToMem1_v = 0,
8625 + DMAD_ds_memToExt1_v = 1,
8626 + DMAD_ds_ethRcv0_v = 0,
8627 + DMAD_ds_ethXmt0_v = 0,
8628 + DMAD_ds_ethRcv1_v = 0,
8629 + DMAD_ds_ethXmt2_v = 0,
8630 + DMAD_ds_memToFifo_v = 0,
8631 + DMAD_ds_fifoToMem_v = 0,
8632 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
8633 + DMAD_ds_pciToMem_v = 0,
8634 + DMAD_ds_memToPci_v = 0,
8635 + DMAD_ds_securityInput_v = 0,
8636 + DMAD_ds_securityOutput_v = 0,
8637 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
8638 +
8639 + DMAD_devcmd_b = 22, // in DMAD_t -> control
8640 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
8641 + DMAD_devcmd_byte_v = 0, //memory-to-memory
8642 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
8643 + DMAD_devcmd_word_v = 2, //memory-to-memory
8644 + DMAD_devcmd_2words_v = 3, //memory-to-memory
8645 + DMAD_devcmd_4words_v = 4, //memory-to-memory
8646 + DMAD_devcmd_6words_v = 5, //memory-to-memory
8647 + DMAD_devcmd_8words_v = 6, //memory-to-memory
8648 + DMAD_devcmd_16words_v = 7, //memory-to-memory
8649 + DMAD_cof_b = 25, // chain on finished
8650 + DMAD_cof_m = 0x02000000, //
8651 + DMAD_cod_b = 26, // chain on done
8652 + DMAD_cod_m = 0x04000000, //
8653 + DMAD_iof_b = 27, // interrupt on finished
8654 + DMAD_iof_m = 0x08000000, //
8655 + DMAD_iod_b = 28, // interrupt on done
8656 + DMAD_iod_m = 0x10000000, //
8657 + DMAD_t_b = 29, // terminated
8658 + DMAD_t_m = 0x20000000, //
8659 + DMAD_d_b = 30, // done
8660 + DMAD_d_m = 0x40000000, //
8661 + DMAD_f_b = 31, // finished
8662 + DMAD_f_m = 0x80000000, //
8663 +} ;
8664 +
8665 +/*
8666 + * DMA register (within Internal Register Map).
8667 + */
8668 +
8669 +struct DMA_Chan_s
8670 +{
8671 + u32 dmac ; // Control.
8672 + u32 dmas ; // Status.
8673 + u32 dmasm ; // Mask.
8674 + u32 dmadptr ; // Descriptor pointer.
8675 + u32 dmandptr ; // Next descriptor pointer.
8676 +};
8677 +
8678 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
8679 +
8680 +//DMA_Channels use DMACH_count instead
8681 +
8682 +enum
8683 +{
8684 + DMAC_run_b = 0, //
8685 + DMAC_run_m = 0x00000001, //
8686 + DMAC_dm_b = 1, // done mask
8687 + DMAC_dm_m = 0x00000002, //
8688 + DMAC_mode_b = 2, //
8689 + DMAC_mode_m = 0x0000000c, //
8690 + DMAC_mode_auto_v = 0,
8691 + DMAC_mode_burst_v = 1,
8692 + DMAC_mode_transfer_v = 2, //usually used
8693 + DMAC_mode_reserved_v = 3,
8694 + DMAC_a_b = 4, //
8695 + DMAC_a_m = 0x00000010, //
8696 +
8697 + DMAS_f_b = 0, // finished (sticky)
8698 + DMAS_f_m = 0x00000001, //
8699 + DMAS_d_b = 1, // done (sticky)
8700 + DMAS_d_m = 0x00000002, //
8701 + DMAS_c_b = 2, // chain (sticky)
8702 + DMAS_c_m = 0x00000004, //
8703 + DMAS_e_b = 3, // error (sticky)
8704 + DMAS_e_m = 0x00000008, //
8705 + DMAS_h_b = 4, // halt (sticky)
8706 + DMAS_h_m = 0x00000010, //
8707 +
8708 + DMASM_f_b = 0, // finished (1=mask)
8709 + DMASM_f_m = 0x00000001, //
8710 + DMASM_d_b = 1, // done (1=mask)
8711 + DMASM_d_m = 0x00000002, //
8712 + DMASM_c_b = 2, // chain (1=mask)
8713 + DMASM_c_m = 0x00000004, //
8714 + DMASM_e_b = 3, // error (1=mask)
8715 + DMASM_e_m = 0x00000008, //
8716 + DMASM_h_b = 4, // halt (1=mask)
8717 + DMASM_h_m = 0x00000010, //
8718 +} ;
8719 +
8720 +/*
8721 + * DMA channel definitions
8722 + */
8723 +
8724 +enum
8725 +{
8726 + DMACH_extToMem0 = 0,
8727 + DMACH_memToExt0 = 0,
8728 + DMACH_extToMem1 = 1,
8729 + DMACH_memToExt1 = 1,
8730 + DMACH_ethRcv0 = 2,
8731 + DMACH_ethXmt0 = 3,
8732 + DMACH_ethRcv1 = 4,
8733 + DMACH_ethXmt2 = 5,
8734 + DMACH_memToFifo = 6,
8735 + DMACH_fifoToMem = 7,
8736 + DMACH_rng_de = 7,//randomNumberGenerator on LC/DE
8737 + DMACH_pciToMem = 8,
8738 + DMACH_memToPci = 9,
8739 + DMACH_securityInput = 10,
8740 + DMACH_securityOutput = 11,
8741 + DMACH_rng_se = 12, //randomNumberGenerator on SE
8742 +
8743 + DMACH_count //must be last
8744 +};
8745 +
8746 +
8747 +typedef struct DMAC_s
8748 +{
8749 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
8750 +} volatile *DMA_t ;
8751 +
8752 +
8753 +/*
8754 + * External DMA parameters
8755 +*/
8756 +
8757 +enum
8758 +{
8759 + DMADEVCMD_ts_b = 0, // ts field in devcmd
8760 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
8761 + DMADEVCMD_ts_byte_v = 0,
8762 + DMADEVCMD_ts_halfword_v = 1,
8763 + DMADEVCMD_ts_word_v = 2,
8764 + DMADEVCMD_ts_2word_v = 3,
8765 + DMADEVCMD_ts_4word_v = 4,
8766 + DMADEVCMD_ts_6word_v = 5,
8767 + DMADEVCMD_ts_8word_v = 6,
8768 + DMADEVCMD_ts_16word_v = 7
8769 +};
8770 +
8771 +
8772 +#if 1 // aws - Compatibility.
8773 +# define EXTDMA_ts_b DMADEVCMD_ts_b
8774 +# define EXTDMA_ts_m DMADEVCMD_ts_m
8775 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
8776 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
8777 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
8778 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
8779 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
8780 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
8781 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
8782 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
8783 +#endif // aws - Compatibility.
8784 +
8785 +#endif //__IDT_RC32438_DMA_H__
8786 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h
8787 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 1970-01-01 01:00:00.000000000 +0100
8788 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_dma_v.h 2006-06-18 12:44:28.000000000 +0200
8789 @@ -0,0 +1,82 @@
8790 +/**************************************************************************
8791 + *
8792 + * BRIEF MODULE DESCRIPTION
8793 + * DMA operations for IDT RC32438.
8794 + *
8795 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8796 + *
8797 + * This program is free software; you can redistribute it and/or modify it
8798 + * under the terms of the GNU General Public License as published by the
8799 + * Free Software Foundation; either version 2 of the License, or (at your
8800 + * option) any later version.
8801 + *
8802 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8803 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8804 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8805 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8806 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8807 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8808 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8809 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8810 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8811 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8812 + *
8813 + * You should have received a copy of the GNU General Public License along
8814 + * with this program; if not, write to the Free Software Foundation, Inc.,
8815 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8816 + *
8817 + *
8818 + **************************************************************************
8819 + * May 2004 P. Sadik.
8820 + *
8821 + * Initial Release
8822 + *
8823 + *
8824 + *
8825 + **************************************************************************
8826 + */
8827 +
8828 +#ifndef __IDT_RC32438_DMA_V_H__
8829 +#define __IDT_RC32438_DMA_V_H__
8830 +#include <asm/idt-boards/rc32438/rc32438_dma.h>
8831 +
8832 +#define DMA_CHAN_OFFSET 0x14
8833 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
8834 +#define DMA_COUNT(count) \
8835 + ((count) & DMAD_count_m)
8836 +
8837 +#define DMA_HALT_TIMEOUT 500
8838 +
8839 +
8840 +static inline int rc32438_halt_dma(DMA_Chan_t ch)
8841 +{
8842 + int timeout=1;
8843 + if (rc32438_readl(&ch->dmac) & DMAC_run_m) {
8844 + rc32438_writel(0, &ch->dmac);
8845 +
8846 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
8847 + if (rc32438_readl(&ch->dmas) & DMAS_h_m) {
8848 + rc32438_writel(0, &ch->dmas);
8849 + break;
8850 + }
8851 + }
8852 +
8853 + }
8854 +
8855 + return timeout ? 0 : 1;
8856 +}
8857 +
8858 +
8859 +
8860 +
8861 +static inline void rc32438_start_dma(DMA_Chan_t ch, u32 dma_addr)
8862 +{
8863 + rc32438_writel(0, &ch->dmandptr);
8864 + rc32438_writel(dma_addr, &ch->dmadptr);
8865 +}
8866 +
8867 +static inline void rc32438_chain_dma(DMA_Chan_t ch, u32 dma_addr)
8868 +{
8869 + rc32438_writel(dma_addr, &ch->dmandptr);
8870 +}
8871 +#endif //__IDT_RC32438_DMA_V_H__
8872 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h
8873 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 1970-01-01 01:00:00.000000000 +0100
8874 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth.h 2006-06-18 12:44:28.000000000 +0200
8875 @@ -0,0 +1,328 @@
8876 +/**************************************************************************
8877 + *
8878 + * BRIEF MODULE DESCRIPTION
8879 + * Definitions for IDT EB438 ethernet
8880 + *
8881 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
8882 + *
8883 + * This program is free software; you can redistribute it and/or modify it
8884 + * under the terms of the GNU General Public License as published by the
8885 + * Free Software Foundation; either version 2 of the License, or (at your
8886 + * option) any later version.
8887 + *
8888 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
8889 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
8890 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
8891 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
8892 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
8893 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
8894 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
8895 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
8896 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
8897 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
8898 + *
8899 + * You should have received a copy of the GNU General Public License along
8900 + * with this program; if not, write to the Free Software Foundation, Inc.,
8901 + * 675 Mass Ave, Cambridge, MA 02139, USA.
8902 + *
8903 + *
8904 + **************************************************************************
8905 + * May 2004 P. Sadik.
8906 + *
8907 + * Initial Release
8908 + *
8909 + *
8910 + *
8911 + **************************************************************************
8912 + */
8913 +
8914 +#ifndef __IDT_RC32438_ETH_H__
8915 +#define __IDT_RC32438_ETH_H__
8916 +enum
8917 +{
8918 + ETH0_PhysicalAddress = 0x18058000,
8919 + ETH_PhysicalAddress = ETH0_PhysicalAddress, // Default
8920 +
8921 + ETH0_VirtualAddress = 0xb8058000,
8922 + ETH_VirtualAddress = ETH0_VirtualAddress, // Default
8923 + ETH1_PhysicalAddress = 0x18060000,
8924 + ETH1_VirtualAddress = 0xb8060000, // Default
8925 +} ;
8926 +
8927 +typedef struct
8928 +{
8929 + u32 ethintfc ;
8930 + u32 ethfifott ;
8931 + u32 etharc ;
8932 + u32 ethhash0 ;
8933 + u32 ethhash1 ;
8934 + u32 ethu0 [4] ; // Reserved.
8935 + u32 ethpfs ;
8936 + u32 ethmcp ;
8937 + u32 eth_u1 [10] ; // Reserved.
8938 + u32 ethspare ;
8939 + u32 eth_u2 [42] ; // Reserved.
8940 + u32 ethsal0 ;
8941 + u32 ethsah0 ;
8942 + u32 ethsal1 ;
8943 + u32 ethsah1 ;
8944 + u32 ethsal2 ;
8945 + u32 ethsah2 ;
8946 + u32 ethsal3 ;
8947 + u32 ethsah3 ;
8948 + u32 ethrbc ;
8949 + u32 ethrpc ;
8950 + u32 ethrupc ;
8951 + u32 ethrfc ;
8952 + u32 ethtbc ;
8953 + u32 ethgpf ;
8954 + u32 eth_u9 [50] ; // Reserved.
8955 + u32 ethmac1 ;
8956 + u32 ethmac2 ;
8957 + u32 ethipgt ;
8958 + u32 ethipgr ;
8959 + u32 ethclrt ;
8960 + u32 ethmaxf ;
8961 + u32 eth_u10 ; // Reserved.
8962 + u32 ethmtest ;
8963 + u32 miimcfg ;
8964 + u32 miimcmd ;
8965 + u32 miimaddr ;
8966 + u32 miimwtd ;
8967 + u32 miimrdd ;
8968 + u32 miimind ;
8969 + u32 eth_u11 ; // Reserved.
8970 + u32 eth_u12 ; // Reserved.
8971 + u32 ethcfsa0 ;
8972 + u32 ethcfsa1 ;
8973 + u32 ethcfsa2 ;
8974 +} volatile *ETH_t;
8975 +
8976 +enum
8977 +{
8978 + ETHINTFC_en_b = 0,
8979 + ETHINTFC_en_m = 0x00000001,
8980 + ETHINTFC_its_b = 1,
8981 + ETHINTFC_its_m = 0x00000002,
8982 + ETHINTFC_rip_b = 2,
8983 + ETHINTFC_rip_m = 0x00000004,
8984 + ETHINTFC_jam_b = 3,
8985 + ETHINTFC_jam_m = 0x00000008,
8986 + ETHINTFC_ovr_b = 4,
8987 + ETHINTFC_ovr_m = 0x00000010,
8988 + ETHINTFC_und_b = 5,
8989 + ETHINTFC_und_m = 0x00000020,
8990 +
8991 + ETHFIFOTT_tth_b = 0,
8992 + ETHFIFOTT_tth_m = 0x0000007f,
8993 +
8994 + ETHARC_pro_b = 0,
8995 + ETHARC_pro_m = 0x00000001,
8996 + ETHARC_am_b = 1,
8997 + ETHARC_am_m = 0x00000002,
8998 + ETHARC_afm_b = 2,
8999 + ETHARC_afm_m = 0x00000004,
9000 + ETHARC_ab_b = 3,
9001 + ETHARC_ab_m = 0x00000008,
9002 +
9003 + ETHSAL_byte5_b = 0,
9004 + ETHSAL_byte5_m = 0x000000ff,
9005 + ETHSAL_byte4_b = 8,
9006 + ETHSAL_byte4_m = 0x0000ff00,
9007 + ETHSAL_byte3_b = 16,
9008 + ETHSAL_byte3_m = 0x00ff0000,
9009 + ETHSAL_byte2_b = 24,
9010 + ETHSAL_byte2_m = 0xff000000,
9011 +
9012 + ETHSAH_byte1_b = 0,
9013 + ETHSAH_byte1_m = 0x000000ff,
9014 + ETHSAH_byte0_b = 8,
9015 + ETHSAH_byte0_m = 0x0000ff00,
9016 +
9017 + ETHGPF_ptv_b = 0,
9018 + ETHGPF_ptv_m = 0x0000ffff,
9019 +
9020 + ETHPFS_pfd_b = 0,
9021 + ETHPFS_pfd_m = 0x00000001,
9022 +
9023 + ETHCFSA0_cfsa4_b = 0,
9024 + ETHCFSA0_cfsa4_m = 0x000000ff,
9025 + ETHCFSA0_cfsa5_b = 8,
9026 + ETHCFSA0_cfsa5_m = 0x0000ff00,
9027 +
9028 + ETHCFSA1_cfsa2_b = 0,
9029 + ETHCFSA1_cfsa2_m = 0x000000ff,
9030 + ETHCFSA1_cfsa3_b = 8,
9031 + ETHCFSA1_cfsa3_m = 0x0000ff00,
9032 +
9033 + ETHCFSA2_cfsa0_b = 0,
9034 + ETHCFSA2_cfsa0_m = 0x000000ff,
9035 + ETHCFSA2_cfsa1_b = 8,
9036 + ETHCFSA2_cfsa1_m = 0x0000ff00,
9037 +
9038 + ETHMAC1_re_b = 0,
9039 + ETHMAC1_re_m = 0x00000001,
9040 + ETHMAC1_paf_b = 1,
9041 + ETHMAC1_paf_m = 0x00000002,
9042 + ETHMAC1_rfc_b = 2,
9043 + ETHMAC1_rfc_m = 0x00000004,
9044 + ETHMAC1_tfc_b = 3,
9045 + ETHMAC1_tfc_m = 0x00000008,
9046 + ETHMAC1_lb_b = 4,
9047 + ETHMAC1_lb_m = 0x00000010,
9048 + ETHMAC1_mr_b = 31,
9049 + ETHMAC1_mr_m = 0x80000000,
9050 +
9051 + ETHMAC2_fd_b = 0,
9052 + ETHMAC2_fd_m = 0x00000001,
9053 + ETHMAC2_flc_b = 1,
9054 + ETHMAC2_flc_m = 0x00000002,
9055 + ETHMAC2_hfe_b = 2,
9056 + ETHMAC2_hfe_m = 0x00000004,
9057 + ETHMAC2_dc_b = 3,
9058 + ETHMAC2_dc_m = 0x00000008,
9059 + ETHMAC2_cen_b = 4,
9060 + ETHMAC2_cen_m = 0x00000010,
9061 + ETHMAC2_pe_b = 5,
9062 + ETHMAC2_pe_m = 0x00000020,
9063 + ETHMAC2_vpe_b = 6,
9064 + ETHMAC2_vpe_m = 0x00000040,
9065 + ETHMAC2_ape_b = 7,
9066 + ETHMAC2_ape_m = 0x00000080,
9067 + ETHMAC2_ppe_b = 8,
9068 + ETHMAC2_ppe_m = 0x00000100,
9069 + ETHMAC2_lpe_b = 9,
9070 + ETHMAC2_lpe_m = 0x00000200,
9071 + ETHMAC2_nb_b = 12,
9072 + ETHMAC2_nb_m = 0x00001000,
9073 + ETHMAC2_bp_b = 13,
9074 + ETHMAC2_bp_m = 0x00002000,
9075 + ETHMAC2_ed_b = 14,
9076 + ETHMAC2_ed_m = 0x00004000,
9077 +
9078 + ETHIPGT_ipgt_b = 0,
9079 + ETHIPGT_ipgt_m = 0x0000007f,
9080 +
9081 + ETHIPGR_ipgr2_b = 0,
9082 + ETHIPGR_ipgr2_m = 0x0000007f,
9083 + ETHIPGR_ipgr1_b = 8,
9084 + ETHIPGR_ipgr1_m = 0x00007f00,
9085 +
9086 + ETHCLRT_maxret_b = 0,
9087 + ETHCLRT_maxret_m = 0x0000000f,
9088 + ETHCLRT_colwin_b = 8,
9089 + ETHCLRT_colwin_m = 0x00003f00,
9090 +
9091 + ETHMAXF_maxf_b = 0,
9092 + ETHMAXF_maxf_m = 0x0000ffff,
9093 +
9094 + ETHMTEST_tb_b = 2,
9095 + ETHMTEST_tb_m = 0x00000004,
9096 +
9097 + ETHMCP_div_b = 0,
9098 + ETHMCP_div_m = 0x000000ff,
9099 +
9100 + MIIMCFG_rsv_b = 0,
9101 + MIIMCFG_rsv_m = 0x0000000c,
9102 +
9103 + MIIMCMD_rd_b = 0,
9104 + MIIMCMD_rd_m = 0x00000001,
9105 + MIIMCMD_scn_b = 1,
9106 + MIIMCMD_scn_m = 0x00000002,
9107 +
9108 + MIIMADDR_regaddr_b = 0,
9109 + MIIMADDR_regaddr_m = 0x0000001f,
9110 + MIIMADDR_phyaddr_b = 8,
9111 + MIIMADDR_phyaddr_m = 0x00001f00,
9112 +
9113 + MIIMWTD_wdata_b = 0,
9114 + MIIMWTD_wdata_m = 0x0000ffff,
9115 +
9116 + MIIMRDD_rdata_b = 0,
9117 + MIIMRDD_rdata_m = 0x0000ffff,
9118 +
9119 + MIIMIND_bsy_b = 0,
9120 + MIIMIND_bsy_m = 0x00000001,
9121 + MIIMIND_scn_b = 1,
9122 + MIIMIND_scn_m = 0x00000002,
9123 + MIIMIND_nv_b = 2,
9124 + MIIMIND_nv_m = 0x00000004,
9125 +
9126 +} ;
9127 +
9128 +/*
9129 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
9130 + */
9131 +enum
9132 +{
9133 + ETHRX_fd_b = 0,
9134 + ETHRX_fd_m = 0x00000001,
9135 + ETHRX_ld_b = 1,
9136 + ETHRX_ld_m = 0x00000002,
9137 + ETHRX_rok_b = 2,
9138 + ETHRX_rok_m = 0x00000004,
9139 + ETHRX_fm_b = 3,
9140 + ETHRX_fm_m = 0x00000008,
9141 + ETHRX_mp_b = 4,
9142 + ETHRX_mp_m = 0x00000010,
9143 + ETHRX_bp_b = 5,
9144 + ETHRX_bp_m = 0x00000020,
9145 + ETHRX_vlt_b = 6,
9146 + ETHRX_vlt_m = 0x00000040,
9147 + ETHRX_cf_b = 7,
9148 + ETHRX_cf_m = 0x00000080,
9149 + ETHRX_ovr_b = 8,
9150 + ETHRX_ovr_m = 0x00000100,
9151 + ETHRX_crc_b = 9,
9152 + ETHRX_crc_m = 0x00000200,
9153 + ETHRX_cv_b = 10,
9154 + ETHRX_cv_m = 0x00000400,
9155 + ETHRX_db_b = 11,
9156 + ETHRX_db_m = 0x00000800,
9157 + ETHRX_le_b = 12,
9158 + ETHRX_le_m = 0x00001000,
9159 + ETHRX_lor_b = 13,
9160 + ETHRX_lor_m = 0x00002000,
9161 + ETHRX_ces_b = 14,
9162 + ETHRX_ces_m = 0x00004000,
9163 + ETHRX_length_b = 16,
9164 + ETHRX_length_m = 0xffff0000,
9165 +
9166 + ETHTX_fd_b = 0,
9167 + ETHTX_fd_m = 0x00000001,
9168 + ETHTX_ld_b = 1,
9169 + ETHTX_ld_m = 0x00000002,
9170 + ETHTX_oen_b = 2,
9171 + ETHTX_oen_m = 0x00000004,
9172 + ETHTX_pen_b = 3,
9173 + ETHTX_pen_m = 0x00000008,
9174 + ETHTX_cen_b = 4,
9175 + ETHTX_cen_m = 0x00000010,
9176 + ETHTX_hen_b = 5,
9177 + ETHTX_hen_m = 0x00000020,
9178 + ETHTX_tok_b = 6,
9179 + ETHTX_tok_m = 0x00000040,
9180 + ETHTX_mp_b = 7,
9181 + ETHTX_mp_m = 0x00000080,
9182 + ETHTX_bp_b = 8,
9183 + ETHTX_bp_m = 0x00000100,
9184 + ETHTX_und_b = 9,
9185 + ETHTX_und_m = 0x00000200,
9186 + ETHTX_of_b = 10,
9187 + ETHTX_of_m = 0x00000400,
9188 + ETHTX_ed_b = 11,
9189 + ETHTX_ed_m = 0x00000800,
9190 + ETHTX_ec_b = 12,
9191 + ETHTX_ec_m = 0x00001000,
9192 + ETHTX_lc_b = 13,
9193 + ETHTX_lc_m = 0x00002000,
9194 + ETHTX_td_b = 14,
9195 + ETHTX_td_m = 0x00004000,
9196 + ETHTX_crc_b = 15,
9197 + ETHTX_crc_m = 0x00008000,
9198 + ETHTX_le_b = 16,
9199 + ETHTX_le_m = 0x00010000,
9200 + ETHTX_cc_b = 17,
9201 + ETHTX_cc_m = 0x001E0000,
9202 +} ;
9203 +#endif //__IDT_RC32438_ETH_H__
9204 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h
9205 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 1970-01-01 01:00:00.000000000 +0100
9206 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_eth_v.h 2006-06-18 12:44:28.000000000 +0200
9207 @@ -0,0 +1,72 @@
9208 +/**************************************************************************
9209 + *
9210 + * BRIEF MODULE DESCRIPTION
9211 + * macros for IDT EB438 ethernet
9212 + *
9213 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9214 + *
9215 + * This program is free software; you can redistribute it and/or modify it
9216 + * under the terms of the GNU General Public License as published by the
9217 + * Free Software Foundation; either version 2 of the License, or (at your
9218 + * option) any later version.
9219 + *
9220 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9221 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9222 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9223 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9224 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9225 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9226 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9227 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9228 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9229 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9230 + *
9231 + * You should have received a copy of the GNU General Public License along
9232 + * with this program; if not, write to the Free Software Foundation, Inc.,
9233 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9234 + *
9235 + *
9236 + **************************************************************************
9237 + * May 2004 P. Sadik.
9238 + *
9239 + * Initial Release
9240 + *
9241 + *
9242 + *
9243 + **************************************************************************
9244 + */
9245 +
9246 +#ifndef __IDT_RC32438_ETH_V_H__
9247 +#define __IDT_RC32438_ETH_V_H__
9248 +#include <asm/idt-boards/rc32438/rc32438_eth.h>
9249 +
9250 +#define IS_TX_TOK(X) (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b ) /* Transmit Okay */
9251 +#define IS_TX_MP(X) (((X) & (1<<ETHTX_mp_b)) >> ETHTX_mp_b ) /* Multicast */
9252 +#define IS_TX_BP(X) (((X) & (1<<ETHTX_bp_b)) >> ETHTX_bp_b ) /* Broadcast */
9253 +#define IS_TX_UND_ERR(X) (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b ) /* Transmit FIFO Underflow */
9254 +#define IS_TX_OF_ERR(X) (((X) & (1<<ETHTX_of_b)) >> ETHTX_of_b ) /* Oversized frame */
9255 +#define IS_TX_ED_ERR(X) (((X) & (1<<ETHTX_ed_b)) >> ETHTX_ed_b ) /* Excessive deferral */
9256 +#define IS_TX_EC_ERR(X) (((X) & (1<<ETHTX_ec_b)) >> ETHTX_ec_b) /* Excessive collisions */
9257 +#define IS_TX_LC_ERR(X) (((X) & (1<<ETHTX_lc_b)) >> ETHTX_lc_b ) /* Late Collision */
9258 +#define IS_TX_TD_ERR(X) (((X) & (1<<ETHTX_td_b)) >> ETHTX_td_b ) /* Transmit deferred*/
9259 +#define IS_TX_CRC_ERR(X) (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b ) /* CRC Error */
9260 +#define IS_TX_LE_ERR(X) (((X) & (1<<ETHTX_le_b)) >> ETHTX_le_b ) /* Length Error */
9261 +
9262 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b) /* Collision Count */
9263 +
9264 +#define IS_RCV_ROK(X) (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b) /* Receive Okay */
9265 +#define IS_RCV_FM(X) (((X) & (1<<ETHRX_fm_b)) >> ETHRX_fm_b) /* Is Filter Match */
9266 +#define IS_RCV_MP(X) (((X) & (1<<ETHRX_mp_b)) >> ETHRX_mp_b) /* Is it MP */
9267 +#define IS_RCV_BP(X) (((X) & (1<<ETHRX_bp_b)) >> ETHRX_bp_b) /* Is it BP */
9268 +#define IS_RCV_VLT(X) (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b) /* VLAN Tag Detect */
9269 +#define IS_RCV_CF(X) (((X) & (1<<ETHRX_cf_b)) >> ETHRX_cf_b) /* Control Frame */
9270 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b) /* Receive Overflow */
9271 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b) /* CRC Error */
9272 +#define IS_RCV_CV_ERR(X) (((X) & (1<<ETHRX_cv_b)) >> ETHRX_cv_b) /* Code Violation */
9273 +#define IS_RCV_DB_ERR(X) (((X) & (1<<ETHRX_db_b)) >> ETHRX_db_b) /* Dribble Bits */
9274 +#define IS_RCV_LE_ERR(X) (((X) & (1<<ETHRX_le_b)) >> ETHRX_le_b) /* Length error */
9275 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b) /* Length Out of Range */
9276 +#define IS_RCV_CES_ERR(X) (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b) /* Preamble error */
9277 +#define RCVPKT_LENGTH(X) (((X) & ETHRX_length_m) >> ETHRX_length_b) /* Length of the received packet */
9278 +
9279 +#endif //__IDT_RC32438_ETH_V_H__
9280 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h
9281 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 1970-01-01 01:00:00.000000000 +0100
9282 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_gpio.h 2006-06-18 12:44:28.000000000 +0200
9283 @@ -0,0 +1,257 @@
9284 +/**************************************************************************
9285 + *
9286 + * BRIEF MODULE DESCRIPTION
9287 + * Definitions for IDT RC32438 GPIO.
9288 + *
9289 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9290 + *
9291 + * This program is free software; you can redistribute it and/or modify it
9292 + * under the terms of the GNU General Public License as published by the
9293 + * Free Software Foundation; either version 2 of the License, or (at your
9294 + * option) any later version.
9295 + *
9296 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9297 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9298 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9299 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9300 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9301 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9302 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9303 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9304 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9305 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9306 + *
9307 + * You should have received a copy of the GNU General Public License along
9308 + * with this program; if not, write to the Free Software Foundation, Inc.,
9309 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9310 + *
9311 + *
9312 + **************************************************************************
9313 + * May 2004 P. Sadik.
9314 + *
9315 + * Initial Release
9316 + *
9317 + *
9318 + *
9319 + **************************************************************************
9320 + */
9321 +#ifndef __IDT_RC32438_GPIO_H__
9322 +#define __IDT_RC32438_GPIO_H__
9323 +enum
9324 +{
9325 + GPIO0_PhysicalAddress = 0x18048000,
9326 + GPIO_PhysicalAddress = GPIO0_PhysicalAddress, // Default
9327 +
9328 + GPIO0_VirtualAddress = 0xb8048000,
9329 + GPIO_VirtualAddress = GPIO0_VirtualAddress, // Default
9330 +} ;
9331 +
9332 +typedef struct
9333 +{
9334 + u32 gpiofunc; /* GPIO Function Register
9335 + * gpiofunc[x]==0 bit = gpio
9336 + * func[x]==1 bit = altfunc
9337 + */
9338 + u32 gpiocfg; /* GPIO Configuration Register
9339 + * gpiocfg[x]==0 bit = input
9340 + * gpiocfg[x]==1 bit = output
9341 + */
9342 + u32 gpiod; /* GPIO Data Register
9343 + * gpiod[x] read/write gpio pinX status
9344 + */
9345 + u32 gpioilevel; /* GPIO Interrupt Status Register
9346 + * interrupt level (see gpioistat)
9347 + */
9348 + u32 gpioistat; /* Gpio Interrupt Status Register
9349 + * istat[x] = (gpiod[x] == level[x])
9350 + * cleared in ISR (STICKY bits)
9351 + */
9352 + u32 gpionmien; /* GPIO Non-maskable Interrupt Enable Register */
9353 +} volatile * GPIO_t ;
9354 +
9355 +typedef enum
9356 +{
9357 + GPIO_gpio_v = 0, // gpiofunc use pin as GPIO.
9358 + GPIO_alt_v = 1, // gpiofunc use pin as alt.
9359 + GPIO_input_v = 0, // gpiocfg use pin as input.
9360 + GPIO_output_v = 1, // gpiocfg use pin as output.
9361 + GPIO_pin0_b = 0,
9362 + GPIO_pin0_m = 0x00000001,
9363 + GPIO_pin1_b = 1,
9364 + GPIO_pin1_m = 0x00000002,
9365 + GPIO_pin2_b = 2,
9366 + GPIO_pin2_m = 0x00000004,
9367 + GPIO_pin3_b = 3,
9368 + GPIO_pin3_m = 0x00000008,
9369 + GPIO_pin4_b = 4,
9370 + GPIO_pin4_m = 0x00000010,
9371 + GPIO_pin5_b = 5,
9372 + GPIO_pin5_m = 0x00000020,
9373 + GPIO_pin6_b = 6,
9374 + GPIO_pin6_m = 0x00000040,
9375 + GPIO_pin7_b = 7,
9376 + GPIO_pin7_m = 0x00000080,
9377 + GPIO_pin8_b = 8,
9378 + GPIO_pin8_m = 0x00000100,
9379 + GPIO_pin9_b = 9,
9380 + GPIO_pin9_m = 0x00000200,
9381 + GPIO_pin10_b = 10,
9382 + GPIO_pin10_m = 0x00000400,
9383 + GPIO_pin11_b = 11,
9384 + GPIO_pin11_m = 0x00000800,
9385 + GPIO_pin12_b = 12,
9386 + GPIO_pin12_m = 0x00001000,
9387 + GPIO_pin13_b = 13,
9388 + GPIO_pin13_m = 0x00002000,
9389 + GPIO_pin14_b = 14,
9390 + GPIO_pin14_m = 0x00004000,
9391 + GPIO_pin15_b = 15,
9392 + GPIO_pin15_m = 0x00008000,
9393 + GPIO_pin16_b = 16,
9394 + GPIO_pin16_m = 0x00010000,
9395 + GPIO_pin17_b = 17,
9396 + GPIO_pin17_m = 0x00020000,
9397 + GPIO_pin18_b = 18,
9398 + GPIO_pin18_m = 0x00040000,
9399 + GPIO_pin19_b = 19,
9400 + GPIO_pin19_m = 0x00080000,
9401 + GPIO_pin20_b = 20,
9402 + GPIO_pin20_m = 0x00100000,
9403 + GPIO_pin21_b = 21,
9404 + GPIO_pin21_m = 0x00200000,
9405 + GPIO_pin22_b = 22,
9406 + GPIO_pin22_m = 0x00400000,
9407 + GPIO_pin23_b = 23,
9408 + GPIO_pin23_m = 0x00800000,
9409 + GPIO_pin24_b = 24,
9410 + GPIO_pin24_m = 0x01000000,
9411 + GPIO_pin25_b = 25,
9412 + GPIO_pin25_m = 0x02000000,
9413 + GPIO_pin26_b = 26,
9414 + GPIO_pin26_m = 0x04000000,
9415 + GPIO_pin27_b = 27,
9416 + GPIO_pin27_m = 0x08000000,
9417 + GPIO_pin28_b = 28,
9418 + GPIO_pin28_m = 0x10000000,
9419 + GPIO_pin29_b = 29,
9420 + GPIO_pin29_m = 0x20000000,
9421 + GPIO_pin30_b = 30,
9422 + GPIO_pin30_m = 0x40000000,
9423 + GPIO_pin31_b = 31,
9424 + GPIO_pin31_m = 0x80000000,
9425 +
9426 +// Alternate function pins. Corrsponding gpiofunc bit set to GPIO_alt_v.
9427 +
9428 + GPIO_u0sout_b = GPIO_pin0_b, // UART 0 serial out.
9429 + GPIO_u0sout_m = GPIO_pin0_m,
9430 + GPIO_u0sout_cfg_v = GPIO_output_v,
9431 + GPIO_u0sinp_b = GPIO_pin1_b, // UART 0 serial in.
9432 + GPIO_u0sinp_m = GPIO_pin1_m,
9433 + GPIO_u0sinp_cfg_v = GPIO_input_v,
9434 + GPIO_u0rin_b = GPIO_pin2_b, // UART 0 ring indic.
9435 + GPIO_u0rin_m = GPIO_pin2_m,
9436 + GPIO_u0rin_cfg_v = GPIO_input_v,
9437 + GPIO_u0dcdn_b = GPIO_pin3_b, // UART 0 data carr.det.
9438 + GPIO_u0dcdn_m = GPIO_pin3_m,
9439 + GPIO_u0dcdn_cfg_v = GPIO_input_v,
9440 + GPIO_u0dtrn_b = GPIO_pin4_b, // UART 0 data term rdy.
9441 + GPIO_u0dtrn_m = GPIO_pin4_m,
9442 + GPIO_u0dtrn_cfg_v = GPIO_output_v,
9443 + GPIO_u0dsrn_b = GPIO_pin5_b, // UART 0 data set rdy.
9444 + GPIO_u0dsrn_m = GPIO_pin5_m,
9445 + GPIO_u0dsrn_cfg_v = GPIO_input_v,
9446 + GPIO_u0rtsn_b = GPIO_pin6_b, // UART 0 req. to send.
9447 + GPIO_u0rtsn_m = GPIO_pin6_m,
9448 + GPIO_u0rtsn_cfg_v = GPIO_output_v,
9449 + GPIO_u0ctsn_b = GPIO_pin7_b, // UART 0 clear to send.
9450 + GPIO_u0ctsn_m = GPIO_pin7_m,
9451 + GPIO_u0ctsn_cfg_v = GPIO_input_v,
9452 +
9453 + GPIO_u1sout_b = GPIO_pin8_b, // UART 1 serial out.
9454 + GPIO_u1sout_m = GPIO_pin8_m,
9455 + GPIO_u1sout_cfg_v = GPIO_output_v,
9456 + GPIO_u1sinp_b = GPIO_pin9_b, // UART 1 serial in.
9457 + GPIO_u1sinp_m = GPIO_pin9_m,
9458 + GPIO_u1sinp_cfg_v = GPIO_input_v,
9459 + GPIO_u1dtrn_b = GPIO_pin10_b, // UART 1 data term rdy.
9460 + GPIO_u1dtrn_m = GPIO_pin10_m,
9461 + GPIO_u1dtrn_cfg_v = GPIO_output_v,
9462 + GPIO_u1dsrn_b = GPIO_pin11_b, // UART 1 data set rdy.
9463 + GPIO_u1dsrn_m = GPIO_pin11_m,
9464 + GPIO_u1dsrn_cfg_v = GPIO_input_v,
9465 + GPIO_u1rtsn_b = GPIO_pin12_b, // UART 1 req. to send.
9466 + GPIO_u1rtsn_m = GPIO_pin12_m,
9467 + GPIO_u1rtsn_cfg_v = GPIO_output_v,
9468 + GPIO_u1ctsn_b = GPIO_pin13_b, // UART 1 clear to send.
9469 + GPIO_u1ctsn_m = GPIO_pin13_m,
9470 + GPIO_u1ctsn_cfg_v = GPIO_input_v,
9471 +
9472 + GPIO_dmareqn0_b = GPIO_pin14_b, // Ext. DMA 0 request
9473 + GPIO_dmareqn0_m = GPIO_pin14_m,
9474 + GPIO_dmareqn0_cfg_v = GPIO_input_v,
9475 +
9476 + GPIO_dmareqn1_b = GPIO_pin15_b, // Ext. DMA 1 request
9477 + GPIO_dmareqn1_m = GPIO_pin15_m,
9478 + GPIO_dmareqn1_cfg_v = GPIO_input_v,
9479 +
9480 + GPIO_dmadonen0_b = GPIO_pin16_b, // Ext. DMA 0 done
9481 + GPIO_dmadonen0_m = GPIO_pin16_m,
9482 + GPIO_dmadonen0_cfg_v = GPIO_input_v,
9483 +
9484 + GPIO_dmadonen1_b = GPIO_pin17_b, // Ext. DMA 1 done
9485 + GPIO_dmadonen1_m = GPIO_pin17_m,
9486 + GPIO_dmadonen1_cfg_v = GPIO_input_v,
9487 +
9488 + GPIO_dmafinn0_b = GPIO_pin18_b, // Ext. DMA 0 finished
9489 + GPIO_dmafinn0_m = GPIO_pin18_m,
9490 + GPIO_dmafinn0_cfg_v = GPIO_output_v,
9491 +
9492 + GPIO_dmafinn1_b = GPIO_pin19_b, // Ext. DMA 1 finished
9493 + GPIO_dmafinn1_m = GPIO_pin19_m,
9494 + GPIO_dmafinn1_cfg_v = GPIO_output_v,
9495 +
9496 + GPIO_maddr22_b = GPIO_pin20_b, // M&P bus bit 22.
9497 + GPIO_maddr22_m = GPIO_pin20_m,
9498 + GPIO_maddr22_cfg_v = GPIO_output_v,
9499 +
9500 + GPIO_maddr23_b = GPIO_pin21_b, // M&P bus bit 23.
9501 + GPIO_maddr23_m = GPIO_pin21_m,
9502 + GPIO_maddr23_cfg_v = GPIO_output_v,
9503 +
9504 + GPIO_maddr24_b = GPIO_pin22_b, // M&P bus bit 24.
9505 + GPIO_maddr24_m = GPIO_pin22_m,
9506 + GPIO_maddr24_cfg_v = GPIO_output_v,
9507 +
9508 + GPIO_maddr25_b = GPIO_pin23_b, // M&P bus bit 25.
9509 + GPIO_maddr25_m = GPIO_pin23_m,
9510 + GPIO_maddr25_cfg_v = GPIO_output_v,
9511 +
9512 + GPIO_afspare6_b = GPIO_pin24_b, // reserved.
9513 + GPIO_afspare6_m = GPIO_pin24_m,
9514 + GPIO_afspare6_cfg_v = GPIO_input_v,
9515 + GPIO_afspare5_b = GPIO_pin25_b, // reserved.
9516 + GPIO_afspare5_m = GPIO_pin25_m,
9517 + GPIO_afspare5_cfg_v = GPIO_input_v,
9518 + GPIO_afspare4_b = GPIO_pin26_b, // reserved.
9519 + GPIO_afspare4_m = GPIO_pin26_m,
9520 + GPIO_afspare4_cfg_v = GPIO_input_v,
9521 + GPIO_afspare3_b = GPIO_pin27_b, // reserved.
9522 + GPIO_afspare3_m = GPIO_pin27_m,
9523 + GPIO_afspare3_cfg_v = GPIO_input_v,
9524 + GPIO_afspare2_b = GPIO_pin28_b, // reserved.
9525 + GPIO_afspare2_m = GPIO_pin28_m,
9526 + GPIO_afspare2_cfg_v = GPIO_input_v,
9527 + GPIO_afspare1_b = GPIO_pin29_b, // reserved.
9528 + GPIO_afspare1_m = GPIO_pin29_m,
9529 + GPIO_afspare1_cfg_v = GPIO_input_v,
9530 +
9531 + GPIO_pcimuintn_b = GPIO_pin30_b, // PCI messaging int.
9532 + GPIO_pcimuintn_m = GPIO_pin30_m,
9533 + GPIO_pcimuintn_cfg_v = GPIO_output_v,
9534 +
9535 + GPIO_rngclk_b = GPIO_pin31_b, // RNG external clock
9536 + GPIO_rngclk_m = GPIO_pin31_m,
9537 + GPIO_rncclk_cfg_v = GPIO_input_v,
9538 +} GPIO_DEFS_t;
9539 +
9540 +#endif //__IDT_RC32438_GPIO_H__
9541 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h
9542 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438.h 1970-01-01 01:00:00.000000000 +0100
9543 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438.h 2006-06-18 12:44:28.000000000 +0200
9544 @@ -0,0 +1,152 @@
9545 +/**************************************************************************
9546 + *
9547 + * BRIEF MODULE DESCRIPTION
9548 + * Definitions for IDT RC32438 CPU.
9549 + *
9550 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9551 + *
9552 + * This program is free software; you can redistribute it and/or modify it
9553 + * under the terms of the GNU General Public License as published by the
9554 + * Free Software Foundation; either version 2 of the License, or (at your
9555 + * option) any later version.
9556 + *
9557 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9558 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9559 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9560 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9561 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9562 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9563 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9564 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9565 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9566 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9567 + *
9568 + * You should have received a copy of the GNU General Public License along
9569 + * with this program; if not, write to the Free Software Foundation, Inc.,
9570 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9571 + *
9572 + *
9573 + **************************************************************************
9574 + * May 2004 P. Sadik.
9575 + *
9576 + * Initial Release
9577 + *
9578 + *
9579 + *
9580 + **************************************************************************
9581 + */
9582 +
9583 +#ifndef __IDT_RC32438_H__
9584 +#define __IDT_RC32438_H__
9585 +#include <linux/config.h>
9586 +#include <linux/delay.h>
9587 +#include <asm/io.h>
9588 +#include <asm/idt-boards/rc32438/rc32438_timer.h>
9589 +
9590 +#define RC32438_REG_BASE 0x18000000
9591 +
9592 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
9593 +#define idttimer ((volatile TIM_t) TIM0_VirtualAddress)
9594 +#define idt_gpio ((volatile GPIO_t) GPIO0_VirtualAddress)
9595 +
9596 +#define IDT_CLOCK_MULT 2
9597 +#define MIPS_CPU_TIMER_IRQ 7
9598 +/* Interrupt Controller */
9599 +#define IC_GROUP0_PEND (RC32438_REG_BASE + 0x38000)
9600 +#define IC_GROUP0_MASK (RC32438_REG_BASE + 0x38008)
9601 +#define IC_GROUP_OFFSET 0x0C
9602 +#define RTC_BASE 0xAC0801FF0
9603 +
9604 +#define NUM_INTR_GROUPS 5
9605 +/* 16550 UARTs */
9606 +
9607 +#define GROUP0_IRQ_BASE 8 /* GRP2 IRQ numbers start here */
9608 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
9609 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
9610 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
9611 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
9612 +
9613 +#ifdef __MIPSEB__
9614 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50003)
9615 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50023)
9616 +#else
9617 +#define RC32438_UART0_BASE (RC32438_REG_BASE + 0x50000)
9618 +#define RC32438_UART1_BASE (RC32438_REG_BASE + 0x50020)
9619 +#endif
9620 +
9621 +#define RC32438_UART0_IRQ GROUP3_IRQ_BASE + 0
9622 +#define RC32438_UART1_IRQ GROUP3_IRQ_BASE + 3
9623 +
9624 +#define RC32438_NR_IRQS (GROUP4_IRQ_BASE + 32)
9625 +
9626 +
9627 +
9628 +/* cpu pipeline flush */
9629 +static inline void rc32438_sync(void)
9630 +{
9631 + __asm__ volatile ("sync");
9632 +}
9633 +
9634 +static inline void rc32438_sync_udelay(int us)
9635 +{
9636 + __asm__ volatile ("sync");
9637 + udelay(us);
9638 +}
9639 +
9640 +static inline void rc32438_sync_delay(int ms)
9641 +{
9642 + __asm__ volatile ("sync");
9643 + mdelay(ms);
9644 +}
9645 +
9646 +/*
9647 + * Macros to access internal RC32438 registers. No byte
9648 + * swapping should be done when accessing the internal
9649 + * registers.
9650 + */
9651 +
9652 +#define rc32438_readb __raw_readb
9653 +#define rc32438_readw __raw_readw
9654 +#define rc32438_readl __raw_readl
9655 +
9656 +#define rc32438_writeb __raw_writeb
9657 +#define rc32438_writew __raw_writew
9658 +#define rc32438_writel __raw_writel
9659 +
9660 +/*
9661 + * C access to CLZ and CLO instructions
9662 + * (count leading zeroes/ones).
9663 + */
9664 +static inline int rc32438_clz(unsigned long val)
9665 +{
9666 + int ret;
9667 + __asm__ volatile (
9668 + ".set\tnoreorder\n\t"
9669 + ".set\tnoat\n\t"
9670 + ".set\tmips32\n\t"
9671 + "clz\t%0,%1\n\t"
9672 + ".set\tmips0\n\t"
9673 + ".set\tat\n\t"
9674 + ".set\treorder"
9675 + : "=r" (ret)
9676 + : "r" (val));
9677 +
9678 + return ret;
9679 +}
9680 +static inline int rc32438_clo(unsigned long val)
9681 +{
9682 + int ret;
9683 + __asm__ volatile (
9684 + ".set\tnoreorder\n\t"
9685 + ".set\tnoat\n\t"
9686 + ".set\tmips32\n\t"
9687 + "clo\t%0,%1\n\t"
9688 + ".set\tmips0\n\t"
9689 + ".set\tat\n\t"
9690 + ".set\treorder"
9691 + : "=r" (ret)
9692 + : "r" (val));
9693 +
9694 + return ret;
9695 +}
9696 +#endif //__IDT_RC32438_H__
9697 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h
9698 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 1970-01-01 01:00:00.000000000 +0100
9699 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci.h 2006-06-18 12:44:28.000000000 +0200
9700 @@ -0,0 +1,510 @@
9701 +/**************************************************************************
9702 + *
9703 + * BRIEF MODULE DESCRIPTION
9704 + * Definitions for IDT RC32438 PCI.
9705 + *
9706 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
9707 + *
9708 + * This program is free software; you can redistribute it and/or modify it
9709 + * under the terms of the GNU General Public License as published by the
9710 + * Free Software Foundation; either version 2 of the License, or (at your
9711 + * option) any later version.
9712 + *
9713 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
9714 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
9715 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
9716 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
9717 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
9718 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
9719 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
9720 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
9721 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
9722 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
9723 + *
9724 + * You should have received a copy of the GNU General Public License along
9725 + * with this program; if not, write to the Free Software Foundation, Inc.,
9726 + * 675 Mass Ave, Cambridge, MA 02139, USA.
9727 + *
9728 + *
9729 + **************************************************************************
9730 + * May 2004 P. Sadik
9731 + *
9732 + * Initial Release
9733 + *
9734 + *
9735 + *
9736 + **************************************************************************
9737 + */
9738 +
9739 +enum
9740 +{
9741 + PCI0_PhysicalAddress = 0x18080000,
9742 + PCI_PhysicalAddress = PCI0_PhysicalAddress,
9743 +
9744 + PCI0_VirtualAddress = 0xb8080000,
9745 + PCI_VirtualAddress = PCI0_VirtualAddress,
9746 +} ;
9747 +
9748 +enum
9749 +{
9750 + PCI_LbaCount = 4, // Local base addresses.
9751 +} ;
9752 +
9753 +typedef struct
9754 +{
9755 + u32 a ; // Address.
9756 + u32 c ; // Control.
9757 + u32 m ; // mapping.
9758 +} PCI_Map_s ;
9759 +
9760 +typedef struct
9761 +{
9762 + u32 pcic ;
9763 + u32 pcis ;
9764 + u32 pcism ;
9765 + u32 pcicfga ;
9766 + u32 pcicfgd ;
9767 + PCI_Map_s pcilba [PCI_LbaCount] ;
9768 + u32 pcidac ;
9769 + u32 pcidas ;
9770 + u32 pcidasm ;
9771 + u32 pcidad ;
9772 + u32 pcidma8c ;
9773 + u32 pcidma9c ;
9774 + u32 pcitc ;
9775 +} volatile *PCI_t ;
9776 +
9777 +// PCI messaging unit.
9778 +enum
9779 +{
9780 + PCIM_Count = 2,
9781 +} ;
9782 +typedef struct
9783 +{
9784 + u32 pciim [PCIM_Count] ;
9785 + u32 pciom [PCIM_Count] ;
9786 + u32 pciid ;
9787 + u32 pciiic ;
9788 + u32 pciiim ;
9789 + u32 pciiod ;
9790 + u32 pciioic ;
9791 + u32 pciioim ;
9792 +} volatile *PCIM_t ;
9793 +
9794 +/*******************************************************************************
9795 + *
9796 + * PCI Control Register
9797 + *
9798 + ******************************************************************************/
9799 +enum
9800 +{
9801 + PCIC_en_b = 0,
9802 + PCIC_en_m = 0x00000001,
9803 + PCIC_tnr_b = 1,
9804 + PCIC_tnr_m = 0x00000002,
9805 + PCIC_sce_b = 2,
9806 + PCIC_sce_m = 0x00000004,
9807 + PCIC_ien_b = 3,
9808 + PCIC_ien_m = 0x00000008,
9809 + PCIC_aaa_b = 4,
9810 + PCIC_aaa_m = 0x00000010,
9811 + PCIC_eap_b = 5,
9812 + PCIC_eap_m = 0x00000020,
9813 + PCIC_pcim_b = 6,
9814 + PCIC_pcim_m = 0x000001c0,
9815 + PCIC_pcim_disabled_v = 0,
9816 + PCIC_pcim_tnr_v = 1, // Satellite - target not ready
9817 + PCIC_pcim_suspend_v = 2, // Satellite - suspended CPU.
9818 + PCIC_pcim_extern_v = 3, // Host - external arbiter.
9819 + PCIC_pcim_fixed_v = 4, // Host - fixed priority arb.
9820 + PCIC_pcim_roundrobin_v = 5, // Host - round robin priority.
9821 + PCIC_pcim_reserved6_v = 6,
9822 + PCIC_pcim_reserved7_v = 7,
9823 + PCIC_igm_b = 9,
9824 + PCIC_igm_m = 0x00000200,
9825 +} ;
9826 +
9827 +/*******************************************************************************
9828 + *
9829 + * PCI Status Register
9830 + *
9831 + ******************************************************************************/
9832 +enum {
9833 + PCIS_eed_b = 0,
9834 + PCIS_eed_m = 0x00000001,
9835 + PCIS_wr_b = 1,
9836 + PCIS_wr_m = 0x00000002,
9837 + PCIS_nmi_b = 2,
9838 + PCIS_nmi_m = 0x00000004,
9839 + PCIS_ii_b = 3,
9840 + PCIS_ii_m = 0x00000008,
9841 + PCIS_cwe_b = 4,
9842 + PCIS_cwe_m = 0x00000010,
9843 + PCIS_cre_b = 5,
9844 + PCIS_cre_m = 0x00000020,
9845 + PCIS_mdpe_b = 6,
9846 + PCIS_mdpe_m = 0x00000040,
9847 + PCIS_sta_b = 7,
9848 + PCIS_sta_m = 0x00000080,
9849 + PCIS_rta_b = 8,
9850 + PCIS_rta_m = 0x00000100,
9851 + PCIS_rma_b = 9,
9852 + PCIS_rma_m = 0x00000200,
9853 + PCIS_sse_b = 10,
9854 + PCIS_sse_m = 0x00000400,
9855 + PCIS_ose_b = 11,
9856 + PCIS_ose_m = 0x00000800,
9857 + PCIS_pe_b = 12,
9858 + PCIS_pe_m = 0x00001000,
9859 + PCIS_tae_b = 13,
9860 + PCIS_tae_m = 0x00002000,
9861 + PCIS_rle_b = 14,
9862 + PCIS_rle_m = 0x00004000,
9863 + PCIS_bme_b = 15,
9864 + PCIS_bme_m = 0x00008000,
9865 + PCIS_prd_b = 16,
9866 + PCIS_prd_m = 0x00010000,
9867 + PCIS_rip_b = 17,
9868 + PCIS_rip_m = 0x00020000,
9869 +} ;
9870 +
9871 +/*******************************************************************************
9872 + *
9873 + * PCI Status Mask Register
9874 + *
9875 + ******************************************************************************/
9876 +enum {
9877 + PCISM_eed_b = 0,
9878 + PCISM_eed_m = 0x00000001,
9879 + PCISM_wr_b = 1,
9880 + PCISM_wr_m = 0x00000002,
9881 + PCISM_nmi_b = 2,
9882 + PCISM_nmi_m = 0x00000004,
9883 + PCISM_ii_b = 3,
9884 + PCISM_ii_m = 0x00000008,
9885 + PCISM_cwe_b = 4,
9886 + PCISM_cwe_m = 0x00000010,
9887 + PCISM_cre_b = 5,
9888 + PCISM_cre_m = 0x00000020,
9889 + PCISM_mdpe_b = 6,
9890 + PCISM_mdpe_m = 0x00000040,
9891 + PCISM_sta_b = 7,
9892 + PCISM_sta_m = 0x00000080,
9893 + PCISM_rta_b = 8,
9894 + PCISM_rta_m = 0x00000100,
9895 + PCISM_rma_b = 9,
9896 + PCISM_rma_m = 0x00000200,
9897 + PCISM_sse_b = 10,
9898 + PCISM_sse_m = 0x00000400,
9899 + PCISM_ose_b = 11,
9900 + PCISM_ose_m = 0x00000800,
9901 + PCISM_pe_b = 12,
9902 + PCISM_pe_m = 0x00001000,
9903 + PCISM_tae_b = 13,
9904 + PCISM_tae_m = 0x00002000,
9905 + PCISM_rle_b = 14,
9906 + PCISM_rle_m = 0x00004000,
9907 + PCISM_bme_b = 15,
9908 + PCISM_bme_m = 0x00008000,
9909 + PCISM_prd_b = 16,
9910 + PCISM_prd_m = 0x00010000,
9911 + PCISM_rip_b = 17,
9912 + PCISM_rip_m = 0x00020000,
9913 +} ;
9914 +
9915 +/*******************************************************************************
9916 + *
9917 + * PCI Configuration Address Register
9918 + *
9919 + ******************************************************************************/
9920 +enum {
9921 + PCICFGA_reg_b = 2,
9922 + PCICFGA_reg_m = 0x000000fc,
9923 + PCICFGA_reg_id_v = 0x00>>2, //use PCFGID_
9924 + PCICFGA_reg_04_v = 0x04>>2, //use PCFG04_
9925 + PCICFGA_reg_08_v = 0x08>>2, //use PCFG08_
9926 + PCICFGA_reg_0C_v = 0x0C>>2, //use PCFG0C_
9927 + PCICFGA_reg_pba0_v = 0x10>>2, //use PCIPBA_
9928 + PCICFGA_reg_pba1_v = 0x14>>2, //use PCIPBA_
9929 + PCICFGA_reg_pba2_v = 0x18>>2, //use PCIPBA_
9930 + PCICFGA_reg_pba3_v = 0x1c>>2, //use PCIPBA_
9931 + PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
9932 + PCICFGA_reg_3C_v = 0x3C>>2, //use PCFG3C_
9933 + PCICFGA_reg_pba0c_v = 0x44>>2, //use PCIPBAC_
9934 + PCICFGA_reg_pba0m_v = 0x48>>2,
9935 + PCICFGA_reg_pba1c_v = 0x4c>>2, //use PCIPBAC_
9936 + PCICFGA_reg_pba1m_v = 0x50>>2,
9937 + PCICFGA_reg_pba2c_v = 0x54>>2, //use PCIPBAC_
9938 + PCICFGA_reg_pba2m_v = 0x58>>2,
9939 + PCICFGA_reg_pba3c_v = 0x5c>>2, //use PCIPBAC_
9940 + PCICFGA_reg_pba3m_v = 0x60>>2,
9941 + PCICFGA_reg_pmgt_v = 0x64>>2,
9942 + PCICFGA_func_b = 8,
9943 + PCICFGA_func_m = 0x00000700,
9944 + PCICFGA_dev_b = 11,
9945 + PCICFGA_dev_m = 0x0000f800,
9946 + PCICFGA_dev_internal_v = 0,
9947 + PCICFGA_bus_b = 16,
9948 + PCICFGA_bus_m = 0x00ff0000,
9949 + PCICFGA_bus_type0_v = 0, //local bus
9950 + PCICFGA_en_b = 31, // read only
9951 + PCICFGA_en_m = 0x80000000,
9952 +} ;
9953 +
9954 +enum {
9955 + PCFGID_vendor_b = 0,
9956 + PCFGID_vendor_m = 0x0000ffff,
9957 + PCFGID_vendor_IDT_v = 0x111d,
9958 + PCFGID_device_b = 16,
9959 + PCFGID_device_m = 0xffff0000,
9960 + PCFGID_device_Acaciade_v = 0x0207,
9961 +
9962 + PCFG04_command_ioena_b = 1,
9963 + PCFG04_command_ioena_m = 0x00000001,
9964 + PCFG04_command_memena_b = 2,
9965 + PCFG04_command_memena_m = 0x00000002,
9966 + PCFG04_command_bmena_b = 3,
9967 + PCFG04_command_bmena_m = 0x00000004,
9968 + PCFG04_command_mwinv_b = 5,
9969 + PCFG04_command_mwinv_m = 0x00000010,
9970 + PCFG04_command_parena_b = 7,
9971 + PCFG04_command_parena_m = 0x00000040,
9972 + PCFG04_command_serrena_b = 9,
9973 + PCFG04_command_serrena_m = 0x00000100,
9974 + PCFG04_command_fastbbena_b = 10,
9975 + PCFG04_command_fastbbena_m = 0x00000200,
9976 + PCFG04_status_b = 16,
9977 + PCFG04_status_m = 0xffff0000,
9978 + PCFG04_status_66MHz_b = 21, // 66 MHz enable
9979 + PCFG04_status_66MHz_m = 0x00200000,
9980 + PCFG04_status_fbb_b = 23,
9981 + PCFG04_status_fbb_m = 0x00800000,
9982 + PCFG04_status_mdpe_b = 24,
9983 + PCFG04_status_mdpe_m = 0x01000000,
9984 + PCFG04_status_dst_b = 25,
9985 + PCFG04_status_dst_m = 0x06000000,
9986 + PCFG04_status_sta_b = 27,
9987 + PCFG04_status_sta_m = 0x08000000,
9988 + PCFG04_status_rta_b = 28,
9989 + PCFG04_status_rta_m = 0x10000000,
9990 + PCFG04_status_rma_b = 29,
9991 + PCFG04_status_rma_m = 0x20000000,
9992 + PCFG04_status_sse_b = 30,
9993 + PCFG04_status_sse_m = 0x40000000,
9994 + PCFG04_status_pe_b = 31,
9995 + PCFG04_status_pe_m = 0x40000000,
9996 +
9997 + PCFG08_revId_b = 0,
9998 + PCFG08_revId_m = 0x000000ff,
9999 + PCFG08_classCode_b = 0,
10000 + PCFG08_classCode_m = 0xffffff00,
10001 + PCFG08_classCode_bridge_v = 06,
10002 + PCFG08_classCode_proc_v = 0x0b3000, // processor-MIPS
10003 + PCFG0C_cacheline_b = 0,
10004 + PCFG0C_cacheline_m = 0x000000ff,
10005 + PCFG0C_masterLatency_b = 8,
10006 + PCFG0C_masterLatency_m = 0x0000ff00,
10007 + PCFG0C_headerType_b = 16,
10008 + PCFG0C_headerType_m = 0x00ff0000,
10009 + PCFG0C_bist_b = 24,
10010 + PCFG0C_bist_m = 0xff000000,
10011 +
10012 + PCIPBA_msi_b = 0,
10013 + PCIPBA_msi_m = 0x00000001,
10014 + PCIPBA_p_b = 3,
10015 + PCIPBA_p_m = 0x00000004,
10016 + PCIPBA_baddr_b = 8,
10017 + PCIPBA_baddr_m = 0xffffff00,
10018 +
10019 + PCFGSS_vendorId_b = 0,
10020 + PCFGSS_vendorId_m = 0x0000ffff,
10021 + PCFGSS_id_b = 16,
10022 + PCFGSS_id_m = 0xffff0000,
10023 +
10024 + PCFG3C_interruptLine_b = 0,
10025 + PCFG3C_interruptLine_m = 0x000000ff,
10026 + PCFG3C_interruptPin_b = 8,
10027 + PCFG3C_interruptPin_m = 0x0000ff00,
10028 + PCFG3C_minGrant_b = 16,
10029 + PCFG3C_minGrant_m = 0x00ff0000,
10030 + PCFG3C_maxLat_b = 24,
10031 + PCFG3C_maxLat_m = 0xff000000,
10032 +
10033 + PCIPBAC_msi_b = 0,
10034 + PCIPBAC_msi_m = 0x00000001,
10035 + PCIPBAC_p_b = 1,
10036 + PCIPBAC_p_m = 0x00000002,
10037 + PCIPBAC_size_b = 2,
10038 + PCIPBAC_size_m = 0x0000007c,
10039 + PCIPBAC_sb_b = 7,
10040 + PCIPBAC_sb_m = 0x00000080,
10041 + PCIPBAC_pp_b = 8,
10042 + PCIPBAC_pp_m = 0x00000100,
10043 + PCIPBAC_mr_b = 9,
10044 + PCIPBAC_mr_m = 0x00000600,
10045 + PCIPBAC_mr_read_v =0, //no prefetching
10046 + PCIPBAC_mr_readLine_v =1,
10047 + PCIPBAC_mr_readMult_v =2,
10048 + PCIPBAC_mrl_b = 11,
10049 + PCIPBAC_mrl_m = 0x00000800,
10050 + PCIPBAC_mrm_b = 12,
10051 + PCIPBAC_mrm_m = 0x00001000,
10052 + PCIPBAC_trp_b = 13,
10053 + PCIPBAC_trp_m = 0x00002000,
10054 +
10055 + PCFG40_trdyTimeout_b = 0,
10056 + PCFG40_trdyTimeout_m = 0x000000ff,
10057 + PCFG40_retryLim_b = 8,
10058 + PCFG40_retryLim_m = 0x0000ff00,
10059 +};
10060 +
10061 +/*******************************************************************************
10062 + *
10063 + * PCI Local Base Address [0|1|2|3] Register
10064 + *
10065 + ******************************************************************************/
10066 +enum {
10067 + PCILBA_baddr_b = 0, // In PCI_t -> pcilba [] .a
10068 + PCILBA_baddr_m = 0xffffff00,
10069 +} ;
10070 +/*******************************************************************************
10071 + *
10072 + * PCI Local Base Address Control Register
10073 + *
10074 + ******************************************************************************/
10075 +enum {
10076 + PCILBAC_msi_b = 0, // In pPci->pcilba[i].c
10077 + PCILBAC_msi_m = 0x00000001,
10078 + PCILBAC_msi_mem_v = 0,
10079 + PCILBAC_msi_io_v = 1,
10080 + PCILBAC_size_b = 2, // In pPci->pcilba[i].c
10081 + PCILBAC_size_m = 0x0000007c,
10082 + PCILBAC_sb_b = 7, // In pPci->pcilba[i].c
10083 + PCILBAC_sb_m = 0x00000080,
10084 + PCILBAC_rt_b = 8, // In pPci->pcilba[i].c
10085 + PCILBAC_rt_m = 0x00000100,
10086 + PCILBAC_rt_noprefetch_v = 0, // mem read
10087 + PCILBAC_rt_prefetch_v = 1, // mem readline
10088 +} ;
10089 +
10090 +/*******************************************************************************
10091 + *
10092 + * PCI Local Base Address [0|1|2|3] Mapping Register
10093 + *
10094 + ******************************************************************************/
10095 +enum {
10096 + PCILBAM_maddr_b = 8,
10097 + PCILBAM_maddr_m = 0xffffff00,
10098 +} ;
10099 +
10100 +/*******************************************************************************
10101 + *
10102 + * PCI Decoupled Access Control Register
10103 + *
10104 + ******************************************************************************/
10105 +enum {
10106 + PCIDAC_den_b = 0,
10107 + PCIDAC_den_m = 0x00000001,
10108 +} ;
10109 +
10110 +/*******************************************************************************
10111 + *
10112 + * PCI Decoupled Access Status Register
10113 + *
10114 + ******************************************************************************/
10115 +enum {
10116 + PCIDAS_d_b = 0,
10117 + PCIDAS_d_m = 0x00000001,
10118 + PCIDAS_b_b = 1,
10119 + PCIDAS_b_m = 0x00000002,
10120 + PCIDAS_e_b = 2,
10121 + PCIDAS_e_m = 0x00000004,
10122 + PCIDAS_ofe_b = 3,
10123 + PCIDAS_ofe_m = 0x00000008,
10124 + PCIDAS_off_b = 4,
10125 + PCIDAS_off_m = 0x00000010,
10126 + PCIDAS_ife_b = 5,
10127 + PCIDAS_ife_m = 0x00000020,
10128 + PCIDAS_iff_b = 6,
10129 + PCIDAS_iff_m = 0x00000040,
10130 +} ;
10131 +
10132 +/*******************************************************************************
10133 + *
10134 + * PCI DMA Channel 8 Configuration Register
10135 + *
10136 + ******************************************************************************/
10137 +enum
10138 +{
10139 + PCIDMA8C_mbs_b = 0, // Maximum Burst Size.
10140 + PCIDMA8C_mbs_m = 0x00000fff, // { pcidma8c }
10141 + PCIDMA8C_our_b = 12, // Optimize Unaligned Burst Reads.
10142 + PCIDMA8C_our_m = 0x00001000, // { pcidma8c }
10143 +} ;
10144 +
10145 +/*******************************************************************************
10146 + *
10147 + * PCI DMA Channel 9 Configuration Register
10148 + *
10149 + ******************************************************************************/
10150 +enum
10151 +{
10152 + PCIDMA9C_mbs_b = 0, // Maximum Burst Size.
10153 + PCIDMA9C_mbs_m = 0x00000fff, // { pcidma9c }
10154 +} ;
10155 +
10156 +/*******************************************************************************
10157 + *
10158 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
10159 + *
10160 + ******************************************************************************/
10161 +enum {
10162 + PCIDMAD_pt_b = 22, // in DEVCMD field (descriptor)
10163 + PCIDMAD_pt_m = 0x00c00000, // preferred transaction field
10164 + // These are for reads (DMA channel 8)
10165 + PCIDMAD_devcmd_mr_v = 0, //memory read
10166 + PCIDMAD_devcmd_mrl_v = 1, //memory read line
10167 + PCIDMAD_devcmd_mrm_v = 2, //memory read multiple
10168 + PCIDMAD_devcmd_ior_v = 3, //I/O read
10169 + // These are for writes (DMA channel 9)
10170 + PCIDMAD_devcmd_mw_v = 0, //memory write
10171 + PCIDMAD_devcmd_mwi_v = 1, //memory write invalidate
10172 + PCIDMAD_devcmd_iow_v = 3, //I/O write
10173 +
10174 + // Swap byte field applies to both DMA channel 8 and 9
10175 + PCIDMAD_sb_b = 24, // in DEVCMD field (descriptor)
10176 + PCIDMAD_sb_m = 0x01000000, // swap byte field
10177 +} ;
10178 +
10179 +
10180 +/*******************************************************************************
10181 + *
10182 + * PCI Target Control Register
10183 + *
10184 + ******************************************************************************/
10185 +enum
10186 +{
10187 + PCITC_rtimer_b = 0, // In PCITC_t -> pcitc
10188 + PCITC_rtimer_m = 0x000000ff,
10189 + PCITC_dtimer_b = 8, // In PCITC_t -> pcitc
10190 + PCITC_dtimer_m = 0x0000ff00,
10191 + PCITC_rdr_b = 18, // In PCITC_t -> pcitc
10192 + PCITC_rdr_m = 0x00040000,
10193 + PCITC_ddt_b = 19, // In PCITC_t -> pcitc
10194 + PCITC_ddt_m = 0x00080000,
10195 +} ;
10196 +/*******************************************************************************
10197 + *
10198 + * PCI messaging unit [applies to both inbound and outbound registers ]
10199 + *
10200 + ******************************************************************************/
10201 +enum
10202 +{
10203 + PCIM_m0_b = 0, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10204 + PCIM_m0_m = 0x00000001, // inbound or outbound message 0
10205 + PCIM_m1_b = 1, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10206 + PCIM_m1_m = 0x00000002, // inbound or outbound message 1
10207 + PCIM_db_b = 2, // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
10208 + PCIM_db_m = 0x00000004, // inbound or outbound doorbell
10209 +};
10210 +
10211 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h
10212 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 1970-01-01 01:00:00.000000000 +0100
10213 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_pci_v.h 2006-06-18 12:44:28.000000000 +0200
10214 @@ -0,0 +1,190 @@
10215 +/**************************************************************************
10216 + *
10217 + * BRIEF MODULE DESCRIPTION
10218 + * Definitions for IDT RC32438 PCI setup.
10219 + *
10220 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10221 + *
10222 + * This program is free software; you can redistribute it and/or modify it
10223 + * under the terms of the GNU General Public License as published by the
10224 + * Free Software Foundation; either version 2 of the License, or (at your
10225 + * option) any later version.
10226 + *
10227 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10228 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10229 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10230 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10231 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10232 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10233 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10234 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10235 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10236 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10237 + *
10238 + * You should have received a copy of the GNU General Public License along
10239 + * with this program; if not, write to the Free Software Foundation, Inc.,
10240 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10241 + *
10242 + *
10243 + **************************************************************************
10244 + * May 2004 P. Sadik
10245 + *
10246 + * Initial Release
10247 + *
10248 + *
10249 + *
10250 + **************************************************************************
10251 + */
10252 +
10253 +#define PCI_MSG_VirtualAddress 0xB8088010
10254 +#define rc32438_pci ((volatile PCI_t) PCI0_VirtualAddress)
10255 +#define rc32438_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
10256 +
10257 +#define PCIM_SHFT 0x6
10258 +#define PCIM_BIT_LEN 0x7
10259 +#define PCIM_H_EA 0x3
10260 +#define PCIM_H_IA_FIX 0x4
10261 +#define PCIM_H_IA_RR 0x5
10262 +
10263 +#define PCI_ADDR_START 0x50000000
10264 +
10265 +#define CPUTOPCI_MEM_WIN 0x02000000
10266 +#define CPUTOPCI_IO_WIN 0x00100000
10267 +#define PCILBA_SIZE_SHFT 2
10268 +#define PCILBA_SIZE_MASK 0x1F
10269 +#define SIZE_256MB 0x1C
10270 +#define SIZE_128MB 0x1B
10271 +#define SIZE_64MB 0x1A
10272 +#define SIZE_32MB 0x19
10273 +#define SIZE_16MB 0x18
10274 +#define SIZE_4MB 0x16
10275 +#define SIZE_2MB 0x15
10276 +#define SIZE_1MB 0x14
10277 +#define ACACIA_CONFIG0_ADDR 0x80000000
10278 +#define ACACIA_CONFIG1_ADDR 0x80000004
10279 +#define ACACIA_CONFIG2_ADDR 0x80000008
10280 +#define ACACIA_CONFIG3_ADDR 0x8000000C
10281 +#define ACACIA_CONFIG4_ADDR 0x80000010
10282 +#define ACACIA_CONFIG5_ADDR 0x80000014
10283 +#define ACACIA_CONFIG6_ADDR 0x80000018
10284 +#define ACACIA_CONFIG7_ADDR 0x8000001C
10285 +#define ACACIA_CONFIG8_ADDR 0x80000020
10286 +#define ACACIA_CONFIG9_ADDR 0x80000024
10287 +#define ACACIA_CONFIG10_ADDR 0x80000028
10288 +#define ACACIA_CONFIG11_ADDR 0x8000002C
10289 +#define ACACIA_CONFIG12_ADDR 0x80000030
10290 +#define ACACIA_CONFIG13_ADDR 0x80000034
10291 +#define ACACIA_CONFIG14_ADDR 0x80000038
10292 +#define ACACIA_CONFIG15_ADDR 0x8000003C
10293 +#define ACACIA_CONFIG16_ADDR 0x80000040
10294 +#define ACACIA_CONFIG17_ADDR 0x80000044
10295 +#define ACACIA_CONFIG18_ADDR 0x80000048
10296 +#define ACACIA_CONFIG19_ADDR 0x8000004C
10297 +#define ACACIA_CONFIG20_ADDR 0x80000050
10298 +#define ACACIA_CONFIG21_ADDR 0x80000054
10299 +#define ACACIA_CONFIG22_ADDR 0x80000058
10300 +#define ACACIA_CONFIG23_ADDR 0x8000005C
10301 +#define ACACIA_CONFIG24_ADDR 0x80000060
10302 +#define ACACIA_CONFIG25_ADDR 0x80000064
10303 +#define ACACIA_CMD (PCFG04_command_ioena_m | \
10304 + PCFG04_command_memena_m | \
10305 + PCFG04_command_bmena_m | \
10306 + PCFG04_command_mwinv_m | \
10307 + PCFG04_command_parena_m | \
10308 + PCFG04_command_serrena_m )
10309 +
10310 +#define ACACIA_STAT (PCFG04_status_mdpe_m | \
10311 + PCFG04_status_sta_m | \
10312 + PCFG04_status_rta_m | \
10313 + PCFG04_status_rma_m | \
10314 + PCFG04_status_sse_m | \
10315 + PCFG04_status_pe_m)
10316 +
10317 +#define ACACIA_CNFG1 ((ACACIA_STAT<<16)|ACACIA_CMD)
10318 +
10319 +#define ACACIA_REVID 0
10320 +#define ACACIA_CLASS_CODE 0
10321 +#define ACACIA_CNFG2 ((ACACIA_CLASS_CODE<<8) | \
10322 + ACACIA_REVID)
10323 +
10324 +#define ACACIA_CACHE_LINE_SIZE 4
10325 +#define ACACIA_MASTER_LAT 0x3c
10326 +#define ACACIA_HEADER_TYPE 0
10327 +#define ACACIA_BIST 0
10328 +
10329 +#define ACACIA_CNFG3 ((ACACIA_BIST << 24) | \
10330 + (ACACIA_HEADER_TYPE<<16) | \
10331 + (ACACIA_MASTER_LAT<<8) | \
10332 + ACACIA_CACHE_LINE_SIZE )
10333 +
10334 +#define ACACIA_BAR0 0x00000008 /* 128 MB Memory */
10335 +#define ACACIA_BAR1 0x18800001 /* 1 MB IO */
10336 +#define ACACIA_BAR2 0x18000001 /* 2 MB IO window for Acacia
10337 + internal Registers */
10338 +#define ACACIA_BAR3 0x48000008 /* Spare 128 MB Memory */
10339 +
10340 +#define ACACIA_CNFG4 ACACIA_BAR0
10341 +#define ACACIA_CNFG5 ACACIA_BAR1
10342 +#define ACACIA_CNFG6 ACACIA_BAR2
10343 +#define ACACIA_CNFG7 ACACIA_BAR3
10344 +
10345 +#define ACACIA_SUBSYS_VENDOR_ID 0
10346 +#define ACACIA_SUBSYSTEM_ID 0
10347 +#define ACACIA_CNFG8 0
10348 +#define ACACIA_CNFG9 0
10349 +#define ACACIA_CNFG10 0
10350 +#define ACACIA_CNFG11 ((ACACIA_SUBSYS_VENDOR_ID<<16) | \
10351 + ACACIA_SUBSYSTEM_ID)
10352 +#define ACACIA_INT_LINE 1
10353 +#define ACACIA_INT_PIN 1
10354 +#define ACACIA_MIN_GNT 8
10355 +#define ACACIA_MAX_LAT 0x38
10356 +#define ACACIA_CNFG12 0
10357 +#define ACACIA_CNFG13 0
10358 +#define ACACIA_CNFG14 0
10359 +#define ACACIA_CNFG15 ((ACACIA_MAX_LAT<<24) | \
10360 + (ACACIA_MIN_GNT<<16) | \
10361 + (ACACIA_INT_PIN<<8) | \
10362 + ACACIA_INT_LINE)
10363 +#define ACACIA_RETRY_LIMIT 0x80
10364 +#define ACACIA_TRDY_LIMIT 0x80
10365 +#define ACACIA_CNFG16 ((ACACIA_RETRY_LIMIT<<8) | \
10366 + ACACIA_TRDY_LIMIT)
10367 +#define PCI_PBAxC_R 0x0
10368 +#define PCI_PBAxC_RL 0x1
10369 +#define PCI_PBAxC_RM 0x2
10370 +#define SIZE_SHFT 2
10371 +
10372 +#define ACACIA_PBA0C ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
10373 + ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
10374 + PCIPBAC_pp_m | \
10375 + (SIZE_128MB<<SIZE_SHFT) | \
10376 + PCIPBAC_p_m)
10377 +
10378 +#define ACACIA_CNFG17 ACACIA_PBA0C
10379 +#define ACACIA_PBA0M 0x0
10380 +#define ACACIA_CNFG18 ACACIA_PBA0M
10381 +
10382 +#define ACACIA_PBA1C ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10383 + PCIPBAC_msi_m)
10384 +
10385 +#define ACACIA_CNFG19 ACACIA_PBA1C
10386 +#define ACACIA_PBA1M 0x0
10387 +#define ACACIA_CNFG20 ACACIA_PBA1M
10388 +
10389 +#define ACACIA_PBA2C ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
10390 + PCIPBAC_msi_m)
10391 +
10392 +#define ACACIA_CNFG21 ACACIA_PBA2C
10393 +#define ACACIA_PBA2M 0x18000000
10394 +#define ACACIA_CNFG22 ACACIA_PBA2M
10395 +#define ACACIA_PBA3C 0
10396 +#define ACACIA_CNFG23 ACACIA_PBA3C
10397 +#define ACACIA_PBA3M 0
10398 +#define ACACIA_CNFG24 ACACIA_PBA3M
10399 +
10400 +
10401 +
10402 +#define PCITC_DTIMER_VAL 8
10403 +#define PCITC_RTIMER_VAL 0x10
10404 +
10405 diff -Nur linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h
10406 --- linux-2.6.17/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 1970-01-01 01:00:00.000000000 +0100
10407 +++ linux-2.6.17-owrt/include/asm-mips/idt-boards/rc32438/rc32438_timer.h 2006-06-18 12:44:28.000000000 +0200
10408 @@ -0,0 +1,91 @@
10409 +/**************************************************************************
10410 + *
10411 + * BRIEF MODULE DESCRIPTION
10412 + * Timer register definition IDT RC32438 CPU.
10413 + *
10414 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
10415 + *
10416 + * This program is free software; you can redistribute it and/or modify it
10417 + * under the terms of the GNU General Public License as published by the
10418 + * Free Software Foundation; either version 2 of the License, or (at your
10419 + * option) any later version.
10420 + *
10421 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10422 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10423 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10424 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10425 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10426 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10427 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10428 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10429 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10430 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10431 + *
10432 + * You should have received a copy of the GNU General Public License along
10433 + * with this program; if not, write to the Free Software Foundation, Inc.,
10434 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10435 + *
10436 + *
10437 + **************************************************************************
10438 + * May 2004 P. Sadik.
10439 + *
10440 + * Initial Release
10441 + *
10442 + *
10443 + *
10444 + **************************************************************************
10445 + */
10446 +
10447 +#ifndef __IDT_RC32438_TIM_H__
10448 +#define __IDT_RC32438_TIM_H__
10449 +
10450 +enum
10451 +{
10452 + TIM0_PhysicalAddress = 0x18028000,
10453 + TIM_PhysicalAddress = TIM0_PhysicalAddress, // Default
10454 +
10455 + TIM0_VirtualAddress = 0xb8028000,
10456 + TIM_VirtualAddress = TIM0_VirtualAddress, // Default
10457 +} ;
10458 +
10459 +enum
10460 +{
10461 + TIM_Count = 3,
10462 +} ;
10463 +
10464 +struct TIM_CNTR_s
10465 +{
10466 + u32 count ;
10467 + u32 compare ;
10468 + u32 ctc ; //use CTC_
10469 +} ;
10470 +
10471 +typedef struct TIM_s
10472 +{
10473 + struct TIM_CNTR_s tim [TIM_Count] ;
10474 + u32 rcount ; //use RCOUNT_
10475 + u32 rcompare ; //use RCOMPARE_
10476 + u32 rtc ; //use RTC_
10477 +} volatile * TIM_t ;
10478 +
10479 +enum
10480 +{
10481 + CTC_en_b = 0,
10482 + CTC_en_m = 0x00000001,
10483 + CTC_to_b = 1,
10484 + CTC_to_m = 0x00000002,
10485 +
10486 + RCOUNT_count_b = 0,
10487 + RCOUNT_count_m = 0x0000ffff,
10488 + RCOMPARE_compare_b = 0,
10489 + RCOMPARE_compare_m = 0x0000ffff,
10490 + RTC_ce_b = 0,
10491 + RTC_ce_m = 0x00000001,
10492 + RTC_to_b = 1,
10493 + RTC_to_m = 0x00000002,
10494 + RTC_rqe_b = 2,
10495 + RTC_rqe_m = 0x00000004,
10496 +
10497 +} ;
10498 +#endif //__IDT_RC32438_TIM_H__
10499 +
10500 diff -Nur linux-2.6.17/include/asm-mips/mach-generic/irq.h linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h
10501 --- linux-2.6.17/include/asm-mips/mach-generic/irq.h 2006-06-18 03:49:35.000000000 +0200
10502 +++ linux-2.6.17-owrt/include/asm-mips/mach-generic/irq.h 2006-06-18 12:44:28.000000000 +0200
10503 @@ -8,6 +8,6 @@
10504 #ifndef __ASM_MACH_GENERIC_IRQ_H
10505 #define __ASM_MACH_GENERIC_IRQ_H
10506
10507 -#define NR_IRQS 128
10508 +#define NR_IRQS 256
10509
10510 #endif /* __ASM_MACH_GENERIC_IRQ_H */
10511 diff -Nur linux-2.6.17/include/linux/kernel.h linux-2.6.17-owrt/include/linux/kernel.h
10512 --- linux-2.6.17/include/linux/kernel.h 2006-06-18 03:49:35.000000000 +0200
10513 +++ linux-2.6.17-owrt/include/linux/kernel.h 2006-06-18 12:44:28.000000000 +0200
10514 @@ -329,6 +329,7 @@
10515 };
10516
10517 /* Force a compilation error if condition is true */
10518 +extern void BUILD_BUG(void);
10519 #define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)]))
10520
10521 /* Trap pasters of __FUNCTION__ at compile-time */
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