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add new broadcom system code and new wlan driver (old driver still used by default)
[openwrt.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 001-bcm47xx.patch
1 diff -urN linux.old/Makefile linux.dev/Makefile
2 --- linux.old/Makefile 2005-08-26 13:41:41.689634168 +0200
3 +++ linux.dev/Makefile 2005-08-26 13:44:34.233403528 +0200
4 @@ -17,9 +17,9 @@
5 FINDHPATH = $(HPATH)/asm $(HPATH)/linux $(HPATH)/scsi $(HPATH)/net $(HPATH)/math-emu
6
7 HOSTCC = gcc
8 -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
9 +HOSTCFLAGS = -Wall -Wstrict-prototypes -Os -fomit-frame-pointer
10
11 -CROSS_COMPILE =
12 +CROSS_COMPILE=
13
14 #
15 # Include the make variables (CC, etc...)
16 @@ -91,8 +91,10 @@
17
18 CPPFLAGS := -D__KERNEL__ -I$(HPATH)
19
20 -CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -O2 \
21 +CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes -Wno-trigraphs -Os \
22 -fno-strict-aliasing -fno-common
23 +
24 +
25 ifndef CONFIG_FRAME_POINTER
26 CFLAGS += -fomit-frame-pointer
27 endif
28 @@ -354,7 +356,7 @@
29 @rm -f .ver1
30
31 include/linux/version.h: ./Makefile
32 - @expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
33 + @-expr length "$(KERNELRELEASE)" \<= $(uts_len) > /dev/null || \
34 (echo KERNELRELEASE \"$(KERNELRELEASE)\" exceeds $(uts_len) characters >&2; false)
35 @echo \#define UTS_RELEASE \"$(KERNELRELEASE)\" > .ver
36 @echo \#define LINUX_VERSION_CODE `expr $(VERSION) \\* 65536 + $(PATCHLEVEL) \\* 256 + $(SUBLEVEL)` >> .ver
37 @@ -501,7 +503,7 @@
38 ifdef CONFIG_MODVERSIONS
39 $(MAKE) update-modverfile
40 endif
41 - scripts/mkdep -- `find $(FINDHPATH) \( -name SCCS -o -name .svn \) -prune -o -follow -name \*.h ! -name modversions.h -print` > .hdepend
42 + (find $(FINDHPATH) \( -name SCCS -o -name .svn \) -prune -o -follow -name \*.h ! -name modversions.h -print | xargs -r scripts/mkdep -- ) > .hdepend
43 scripts/mkdep -- init/*.c > .depend
44
45 ifdef CONFIG_MODVERSIONS
46 diff -urN linux.old/Rules.make linux.dev/Rules.make
47 --- linux.old/Rules.make 2005-11-07 23:12:50.538884250 +0100
48 +++ linux.dev/Rules.make 2005-11-07 21:57:07.837585250 +0100
49 @@ -176,7 +176,14 @@
50 _modinst__: dummy
51 ifneq "$(strip $(ALL_MOBJS))" ""
52 mkdir -p $(MODLIB)/kernel/$(MOD_DESTDIR)
53 - cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
54 + #@cp $(sort $(ALL_MOBJS)) $(MODLIB)/kernel/$(MOD_DESTDIR)
55 + for f in $(ALL_MOBJS) ; do \
56 + $(OBJCOPY) -R __ksymtab -R .comment -R .note -x \
57 + `$(NM) $$f | cut -f3- -d' ' | sed -n \
58 + -e 's/__module_parm_\(.*\)/-K \1/p' \
59 + -e 's/__ks..tab_\(.*\)/-K \1/p'` \
60 + $$f $(MODLIB)/kernel/$(MOD_DESTDIR)$(MOD_TARGET)$$f; \
61 + done
62 endif
63
64 .PHONY: modules_install
65 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
66 --- linux.old/arch/mips/Makefile 2005-11-07 23:12:50.582887000 +0100
67 +++ linux.dev/arch/mips/Makefile 2005-11-07 21:57:08.537629000 +0100
68 @@ -46,10 +46,10 @@
69 GCCFLAGS := -I $(TOPDIR)/include/asm/gcc
70 GCCFLAGS += -G 0 -mno-abicalls -fno-pic -pipe
71 GCCFLAGS += $(call check_gcc, -finline-limit=100000,)
72 -LINKFLAGS += -G 0 -static -n
73 -MODFLAGS += -mlong-calls
74 +LINKFLAGS += -G 0 -static -n -nostdlib
75 +MODFLAGS += -mlong-calls -fno-common
76
77 -ifdef CONFIG_DEBUG_INFO
78 +ifdef CONFIG_REMOTE_DEBUG
79 GCCFLAGS += -g
80 ifdef CONFIG_SB1XXX_CORELIS
81 GCCFLAGS += -mno-sched-prolog -fno-omit-frame-pointer
82 @@ -71,13 +71,13 @@
83 set_gccflags = $(shell \
84 while :; do \
85 cpu=$(1); isa=-$(2); \
86 - for gcc_opt in -march= -mcpu=; do \
87 + for gcc_opt in -march= -mtune=; do \
88 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
89 -xc /dev/null > /dev/null 2>&1 && \
90 break 2; \
91 done; \
92 cpu=$(3); isa=-$(4); \
93 - for gcc_opt in -march= -mcpu=; do \
94 + for gcc_opt in -march= -mtune=; do \
95 $(CC) $$gcc_opt$$cpu $$isa -S -o /dev/null \
96 -xc /dev/null > /dev/null 2>&1 && \
97 break 2; \
98 @@ -92,7 +92,7 @@
99 fi; \
100 gas_abi=-Wa,-32; gas_cpu=$$cpu; gas_isa=-Wa,$$isa; \
101 while :; do \
102 - for gas_opt in -Wa,-march= -Wa,-mcpu=; do \
103 + for gas_opt in -Wa,-march= -Wa,-mtune=; do \
104 $(CC) $$gas_abi $$gas_opt$$cpu $$gas_isa -Wa,-Z -c \
105 -o /dev/null -xassembler /dev/null > /dev/null 2>&1 && \
106 break 2; \
107 @@ -174,6 +174,7 @@
108 endif
109
110 AFLAGS += $(GCCFLAGS)
111 +ASFLAGS += $(GCCFLAGS)
112 CFLAGS += $(GCCFLAGS)
113
114 LD += -m $(ld-emul)
115 @@ -727,6 +728,19 @@
116 endif
117
118 #
119 +# Broadcom BCM947XX variants
120 +#
121 +ifdef CONFIG_BCM947XX
122 +LIBS += arch/mips/bcm947xx/generic/brcm.o arch/mips/bcm947xx/bcm947xx.o
123 +SUBDIRS += arch/mips/bcm947xx/generic arch/mips/bcm947xx
124 +LOADADDR := 0x80001000
125 +
126 +zImage: vmlinux
127 + $(MAKE) -C arch/$(ARCH)/bcm947xx/compressed
128 +export LOADADDR
129 +endif
130 +
131 +#
132 # Choosing incompatible machines durings configuration will result in
133 # error messages during linking. Select a default linkscript if
134 # none has been choosen above.
135 @@ -779,6 +793,7 @@
136 $(MAKE) -C arch/$(ARCH)/tools clean
137 $(MAKE) -C arch/mips/baget clean
138 $(MAKE) -C arch/mips/lasat clean
139 + $(MAKE) -C arch/mips/bcm947xx/compressed clean
140
141 archmrproper:
142 @$(MAKEBOOT) mrproper
143 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
144 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
145 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-11-08 00:55:04.392074500 +0100
146 @@ -0,0 +1,15 @@
147 +#
148 +# Makefile for the BCM947xx specific kernel interface routines
149 +# under Linux.
150 +#
151 +
152 +EXTRA_CFLAGS+=-I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
153 +
154 +O_TARGET := bcm947xx.o
155 +
156 +export-objs := nvram_linux.o setup.o
157 +obj-y := prom.o setup.o time.o sbmips.o gpio.o
158 +obj-y += nvram.o nvram_linux.o sflash.o
159 +obj-$(CONFIG_PCI) += sbpci.o pcibios.o
160 +
161 +include $(TOPDIR)/Rules.make
162 diff -urN linux.old/arch/mips/bcm947xx/compressed/Makefile linux.dev/arch/mips/bcm947xx/compressed/Makefile
163 --- linux.old/arch/mips/bcm947xx/compressed/Makefile 1970-01-01 01:00:00.000000000 +0100
164 +++ linux.dev/arch/mips/bcm947xx/compressed/Makefile 2005-11-07 21:57:07.841585500 +0100
165 @@ -0,0 +1,33 @@
166 +#
167 +# Makefile for Broadcom BCM947XX boards
168 +#
169 +# Copyright 2001-2003, Broadcom Corporation
170 +# All Rights Reserved.
171 +#
172 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
173 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
174 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
175 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
176 +#
177 +# $Id: Makefile,v 1.2 2005/04/02 12:12:57 wbx Exp $
178 +#
179 +
180 +OBJCOPY_ARGS = -O binary -R .reginfo -R .note -R .comment -R .mdebug -S
181 +SYSTEM ?= $(TOPDIR)/vmlinux
182 +
183 +all: vmlinuz
184 +
185 +# Don't build dependencies, this may die if $(CC) isn't gcc
186 +dep:
187 +
188 +# Create a gzipped version named vmlinuz for compatibility
189 +vmlinuz: piggy
190 + gzip -c9 $< > $@
191 +
192 +piggy: $(SYSTEM)
193 + $(OBJCOPY) $(OBJCOPY_ARGS) $< $@
194 +
195 +mrproper: clean
196 +
197 +clean:
198 + rm -f vmlinuz piggy
199 diff -urN linux.old/arch/mips/bcm947xx/generic/Makefile linux.dev/arch/mips/bcm947xx/generic/Makefile
200 --- linux.old/arch/mips/bcm947xx/generic/Makefile 1970-01-01 01:00:00.000000000 +0100
201 +++ linux.dev/arch/mips/bcm947xx/generic/Makefile 2005-11-07 21:57:07.841585500 +0100
202 @@ -0,0 +1,15 @@
203 +#
204 +# Makefile for the BCM947xx specific kernel interface routines
205 +# under Linux.
206 +#
207 +
208 +.S.s:
209 + $(CPP) $(AFLAGS) $< -o $*.s
210 +.S.o:
211 + $(CC) $(AFLAGS) -c $< -o $*.o
212 +
213 +O_TARGET := brcm.o
214 +
215 +obj-y := int-handler.o irq.o
216 +
217 +include $(TOPDIR)/Rules.make
218 diff -urN linux.old/arch/mips/bcm947xx/generic/int-handler.S linux.dev/arch/mips/bcm947xx/generic/int-handler.S
219 --- linux.old/arch/mips/bcm947xx/generic/int-handler.S 1970-01-01 01:00:00.000000000 +0100
220 +++ linux.dev/arch/mips/bcm947xx/generic/int-handler.S 2005-11-07 21:57:07.841585500 +0100
221 @@ -0,0 +1,51 @@
222 +/*
223 + * Generic interrupt handler for Broadcom MIPS boards
224 + *
225 + * Copyright 2004, Broadcom Corporation
226 + * All Rights Reserved.
227 + *
228 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
229 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
230 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
231 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
232 + *
233 + * $Id: int-handler.S,v 1.1 2005/03/16 13:50:00 wbx Exp $
234 + */
235 +
236 +#include <linux/config.h>
237 +
238 +#include <asm/asm.h>
239 +#include <asm/mipsregs.h>
240 +#include <asm/regdef.h>
241 +#include <asm/stackframe.h>
242 +
243 +/*
244 + * MIPS IRQ Source
245 + * -------- ------
246 + * 0 Software (ignored)
247 + * 1 Software (ignored)
248 + * 2 Combined hardware interrupt (hw0)
249 + * 3 Hardware
250 + * 4 Hardware
251 + * 5 Hardware
252 + * 6 Hardware
253 + * 7 R4k timer
254 + */
255 +
256 + .text
257 + .set noreorder
258 + .set noat
259 + .align 5
260 + NESTED(brcmIRQ, PT_SIZE, sp)
261 + SAVE_ALL
262 + CLI
263 + .set at
264 + .set noreorder
265 +
266 + jal brcm_irq_dispatch
267 + move a0, sp
268 +
269 + j ret_from_irq
270 + nop
271 +
272 + END(brcmIRQ)
273 diff -urN linux.old/arch/mips/bcm947xx/generic/irq.c linux.dev/arch/mips/bcm947xx/generic/irq.c
274 --- linux.old/arch/mips/bcm947xx/generic/irq.c 1970-01-01 01:00:00.000000000 +0100
275 +++ linux.dev/arch/mips/bcm947xx/generic/irq.c 2005-11-07 21:57:07.841585500 +0100
276 @@ -0,0 +1,130 @@
277 +/*
278 + * Generic interrupt control functions for Broadcom MIPS boards
279 + *
280 + * Copyright 2004, Broadcom Corporation
281 + * All Rights Reserved.
282 + *
283 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
284 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
285 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
286 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
287 + *
288 + * $Id: irq.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
289 + */
290 +
291 +#include <linux/config.h>
292 +#include <linux/init.h>
293 +#include <linux/kernel.h>
294 +#include <linux/types.h>
295 +#include <linux/interrupt.h>
296 +#include <linux/irq.h>
297 +
298 +#include <asm/irq.h>
299 +#include <asm/mipsregs.h>
300 +#include <asm/gdb-stub.h>
301 +
302 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
303 +
304 +extern asmlinkage void brcmIRQ(void);
305 +extern asmlinkage unsigned int do_IRQ(int irq, struct pt_regs *regs);
306 +
307 +void
308 +brcm_irq_dispatch(struct pt_regs *regs)
309 +{
310 + u32 cause;
311 +
312 + cause = read_c0_cause() &
313 + read_c0_status() &
314 + CAUSEF_IP;
315 +
316 +#ifdef CONFIG_KERNPROF
317 + change_c0_status(cause | 1, 1);
318 +#else
319 + clear_c0_status(cause);
320 +#endif
321 +
322 + if (cause & CAUSEF_IP7)
323 + do_IRQ(7, regs);
324 + if (cause & CAUSEF_IP2)
325 + do_IRQ(2, regs);
326 + if (cause & CAUSEF_IP3)
327 + do_IRQ(3, regs);
328 + if (cause & CAUSEF_IP4)
329 + do_IRQ(4, regs);
330 + if (cause & CAUSEF_IP5)
331 + do_IRQ(5, regs);
332 + if (cause & CAUSEF_IP6)
333 + do_IRQ(6, regs);
334 +}
335 +
336 +static void
337 +enable_brcm_irq(unsigned int irq)
338 +{
339 + if (irq < 8)
340 + set_c0_status(1 << (irq + 8));
341 + else
342 + set_c0_status(IE_IRQ0);
343 +}
344 +
345 +static void
346 +disable_brcm_irq(unsigned int irq)
347 +{
348 + if (irq < 8)
349 + clear_c0_status(1 << (irq + 8));
350 + else
351 + clear_c0_status(IE_IRQ0);
352 +}
353 +
354 +static void
355 +ack_brcm_irq(unsigned int irq)
356 +{
357 + /* Already done in brcm_irq_dispatch */
358 +}
359 +
360 +static unsigned int
361 +startup_brcm_irq(unsigned int irq)
362 +{
363 + enable_brcm_irq(irq);
364 +
365 + return 0; /* never anything pending */
366 +}
367 +
368 +static void
369 +end_brcm_irq(unsigned int irq)
370 +{
371 + if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
372 + enable_brcm_irq(irq);
373 +}
374 +
375 +static struct hw_interrupt_type brcm_irq_type = {
376 + typename: "MIPS",
377 + startup: startup_brcm_irq,
378 + shutdown: disable_brcm_irq,
379 + enable: enable_brcm_irq,
380 + disable: disable_brcm_irq,
381 + ack: ack_brcm_irq,
382 + end: end_brcm_irq,
383 + NULL
384 +};
385 +
386 +void __init
387 +init_IRQ(void)
388 +{
389 + int i;
390 +
391 + for (i = 0; i < NR_IRQS; i++) {
392 + irq_desc[i].status = IRQ_DISABLED;
393 + irq_desc[i].action = 0;
394 + irq_desc[i].depth = 1;
395 + irq_desc[i].handler = &brcm_irq_type;
396 + }
397 +
398 + set_except_vector(0, brcmIRQ);
399 + change_c0_status(ST0_IM, ALLINTS);
400 +
401 +#ifdef CONFIG_REMOTE_DEBUG
402 + printk("Breaking into debugger...\n");
403 + set_debug_traps();
404 + breakpoint();
405 +#endif
406 +}
407 diff -urN linux.old/arch/mips/bcm947xx/gpio.c linux.dev/arch/mips/bcm947xx/gpio.c
408 --- linux.old/arch/mips/bcm947xx/gpio.c 1970-01-01 01:00:00.000000000 +0100
409 +++ linux.dev/arch/mips/bcm947xx/gpio.c 2005-11-07 23:58:34.968754500 +0100
410 @@ -0,0 +1,158 @@
411 +/*
412 + * GPIO char driver
413 + *
414 + * Copyright 2005, Broadcom Corporation
415 + * All Rights Reserved.
416 + *
417 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
418 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
419 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
420 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
421 + *
422 + * $Id$
423 + */
424 +
425 +#include <linux/module.h>
426 +#include <linux/init.h>
427 +#include <linux/fs.h>
428 +#include <linux/miscdevice.h>
429 +#include <asm/uaccess.h>
430 +
431 +#include <typedefs.h>
432 +#include <bcmutils.h>
433 +#include <sbutils.h>
434 +#include <bcmdevs.h>
435 +
436 +static sb_t *gpio_sbh;
437 +static int gpio_major;
438 +static devfs_handle_t gpio_dir;
439 +static struct {
440 + char *name;
441 + devfs_handle_t handle;
442 +} gpio_file[] = {
443 + { "in", NULL },
444 + { "out", NULL },
445 + { "outen", NULL },
446 + { "control", NULL }
447 +};
448 +
449 +static int
450 +gpio_open(struct inode *inode, struct file * file)
451 +{
452 + if (MINOR(inode->i_rdev) > ARRAYSIZE(gpio_file))
453 + return -ENODEV;
454 +
455 + MOD_INC_USE_COUNT;
456 + return 0;
457 +}
458 +
459 +static int
460 +gpio_release(struct inode *inode, struct file * file)
461 +{
462 + MOD_DEC_USE_COUNT;
463 + return 0;
464 +}
465 +
466 +static ssize_t
467 +gpio_read(struct file *file, char *buf, size_t count, loff_t *ppos)
468 +{
469 + u32 val;
470 +
471 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
472 + case 0:
473 + val = sb_gpioin(gpio_sbh);
474 + break;
475 + case 1:
476 + val = sb_gpioout(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
477 + break;
478 + case 2:
479 + val = sb_gpioouten(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
480 + break;
481 + case 3:
482 + val = sb_gpiocontrol(gpio_sbh, 0, 0, GPIO_DRV_PRIORITY);
483 + break;
484 + default:
485 + return -ENODEV;
486 + }
487 +
488 + if (put_user(val, (u32 *) buf))
489 + return -EFAULT;
490 +
491 + return sizeof(val);
492 +}
493 +
494 +static ssize_t
495 +gpio_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
496 +{
497 + u32 val;
498 +
499 + if (get_user(val, (u32 *) buf))
500 + return -EFAULT;
501 +
502 + switch (MINOR(file->f_dentry->d_inode->i_rdev)) {
503 + case 0:
504 + return -EACCES;
505 + case 1:
506 + sb_gpioout(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
507 + break;
508 + case 2:
509 + sb_gpioouten(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
510 + break;
511 + case 3:
512 + sb_gpiocontrol(gpio_sbh, ~0, val, GPIO_DRV_PRIORITY);
513 + break;
514 + default:
515 + return -ENODEV;
516 + }
517 +
518 + return sizeof(val);
519 +}
520 +
521 +static struct file_operations gpio_fops = {
522 + owner: THIS_MODULE,
523 + open: gpio_open,
524 + release: gpio_release,
525 + read: gpio_read,
526 + write: gpio_write,
527 +};
528 +
529 +static int __init
530 +gpio_init(void)
531 +{
532 + int i;
533 +
534 + if (!(gpio_sbh = sb_kattach()))
535 + return -ENODEV;
536 +
537 + sb_gpiosetcore(gpio_sbh);
538 +
539 + if ((gpio_major = devfs_register_chrdev(0, "gpio", &gpio_fops)) < 0)
540 + return gpio_major;
541 +
542 + gpio_dir = devfs_mk_dir(NULL, "gpio", NULL);
543 +
544 + for (i = 0; i < ARRAYSIZE(gpio_file); i++) {
545 + gpio_file[i].handle = devfs_register(gpio_dir,
546 + gpio_file[i].name,
547 + DEVFS_FL_DEFAULT, gpio_major, i,
548 + S_IFCHR | S_IRUGO | S_IWUGO,
549 + &gpio_fops, NULL);
550 + }
551 +
552 + return 0;
553 +}
554 +
555 +static void __exit
556 +gpio_exit(void)
557 +{
558 + int i;
559 +
560 + for (i = 0; i < ARRAYSIZE(gpio_file); i++)
561 + devfs_unregister(gpio_file[i].handle);
562 + devfs_unregister(gpio_dir);
563 + devfs_unregister_chrdev(gpio_major, "gpio");
564 + sb_detach(gpio_sbh);
565 +}
566 +
567 +module_init(gpio_init);
568 +module_exit(gpio_exit);
569 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
570 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
571 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-11-07 22:51:38.772725750 +0100
572 @@ -0,0 +1,391 @@
573 +/*
574 + * Broadcom device-specific manifest constants.
575 + *
576 + * Copyright 2005, Broadcom Corporation
577 + * All Rights Reserved.
578 + *
579 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
580 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
581 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
582 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
583 + * $Id$
584 + */
585 +
586 +#ifndef _BCMDEVS_H
587 +#define _BCMDEVS_H
588 +
589 +
590 +/* Known PCI vendor Id's */
591 +#define VENDOR_EPIGRAM 0xfeda
592 +#define VENDOR_BROADCOM 0x14e4
593 +#define VENDOR_3COM 0x10b7
594 +#define VENDOR_NETGEAR 0x1385
595 +#define VENDOR_DIAMOND 0x1092
596 +#define VENDOR_DELL 0x1028
597 +#define VENDOR_HP 0x0e11
598 +#define VENDOR_APPLE 0x106b
599 +
600 +/* PCI Device Id's */
601 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
602 +#define BCM4211_DEVICE_ID 0x4211
603 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
604 +#define BCM4231_DEVICE_ID 0x4231
605 +
606 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
607 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
608 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
609 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
610 +
611 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
612 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
613 +
614 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
615 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
616 +
617 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
618 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
619 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
620 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
621 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
622 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
623 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
624 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
625 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
626 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
627 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
628 +
629 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
630 +
631 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
632 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
633 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
634 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
635 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
636 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
637 +
638 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
639 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
640 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
641 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
642 +
643 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
644 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
645 +
646 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
647 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
648 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
649 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
650 +
651 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
652 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
653 +#define BCM4306_D11G_ID2 0x4325
654 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
655 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
656 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
657 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
658 +
659 +#define BCM4309_PKG_ID 1 /* 4309 package id */
660 +
661 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
662 +#define BCM4303_PKG_ID 2 /* 4303 package id */
663 +
664 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
665 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
666 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
667 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
668 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
669 +
670 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
671 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
672 +
673 +
674 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
675 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
676 +
677 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
678 +
679 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
680 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
681 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
682 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
683 +
684 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
685 +
686 +/* Address map */
687 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
688 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
689 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
690 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
691 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
692 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
693 +
694 +/* Core register space */
695 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
696 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
697 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
698 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
699 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
700 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
701 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
702 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
703 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
704 +
705 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
706 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
707 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
708 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
709 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
710 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
711 +
712 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
713 +
714 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
715 +
716 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
717 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
718 +
719 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
720 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
721 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
722 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
723 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
724 +
725 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
726 +
727 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
728 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
729 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
730 +
731 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
732 +
733 +/* PCMCIA vendor Id's */
734 +
735 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
736 +
737 +/* SDIO vendor Id's */
738 +#define VENDOR_BROADCOM_SDIO 0x00BF
739 +
740 +
741 +/* boardflags */
742 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
743 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
744 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
745 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
746 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
747 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
748 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
749 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
750 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
751 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
752 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
753 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
754 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
755 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
756 +
757 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
758 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
759 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
760 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
761 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
762 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
763 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
764 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
765 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
766 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
767 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
768 +
769 +/* Bus types */
770 +#define SB_BUS 0 /* Silicon Backplane */
771 +#define PCI_BUS 1 /* PCI target */
772 +#define PCMCIA_BUS 2 /* PCMCIA target */
773 +#define SDIO_BUS 3 /* SDIO target */
774 +#define JTAG_BUS 4 /* JTAG */
775 +
776 +/* Allows optimization for single-bus support */
777 +#ifdef BCMBUSTYPE
778 +#define BUSTYPE(bus) (BCMBUSTYPE)
779 +#else
780 +#define BUSTYPE(bus) (bus)
781 +#endif
782 +
783 +/* power control defines */
784 +#define PLL_DELAY 150 /* us pll on delay */
785 +#define FREF_DELAY 200 /* us fref change delay */
786 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
787 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
788 +
789 +/* Reference Board Types */
790 +
791 +#define BU4710_BOARD 0x0400
792 +#define VSIM4710_BOARD 0x0401
793 +#define QT4710_BOARD 0x0402
794 +
795 +#define BU4610_BOARD 0x0403
796 +#define VSIM4610_BOARD 0x0404
797 +
798 +#define BU4307_BOARD 0x0405
799 +#define BCM94301CB_BOARD 0x0406
800 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
801 +#define BCM94301MP_BOARD 0x0407
802 +#define BCM94307MP_BOARD 0x0408
803 +#define BCMAP4307_BOARD 0x0409
804 +
805 +#define BU4309_BOARD 0x040a
806 +#define BCM94309CB_BOARD 0x040b
807 +#define BCM94309MP_BOARD 0x040c
808 +#define BCM4309AP_BOARD 0x040d
809 +
810 +#define BCM94302MP_BOARD 0x040e
811 +
812 +#define VSIM4310_BOARD 0x040f
813 +#define BU4711_BOARD 0x0410
814 +#define BCM94310U_BOARD 0x0411
815 +#define BCM94310AP_BOARD 0x0412
816 +#define BCM94310MP_BOARD 0x0414
817 +
818 +#define BU4306_BOARD 0x0416
819 +#define BCM94306CB_BOARD 0x0417
820 +#define BCM94306MP_BOARD 0x0418
821 +
822 +#define BCM94710D_BOARD 0x041a
823 +#define BCM94710R1_BOARD 0x041b
824 +#define BCM94710R4_BOARD 0x041c
825 +#define BCM94710AP_BOARD 0x041d
826 +
827 +
828 +#define BU2050_BOARD 0x041f
829 +
830 +
831 +#define BCM94309G_BOARD 0x0421
832 +
833 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
834 +
835 +#define BU4704_BOARD 0x0423
836 +#define BU4702_BOARD 0x0424
837 +
838 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
839 +
840 +#define BU4317_BOARD 0x0426
841 +
842 +
843 +#define BCM94702MN_BOARD 0x0428
844 +
845 +/* BCM4702 1U CompactPCI Board */
846 +#define BCM94702CPCI_BOARD 0x0429
847 +
848 +/* BCM4702 with BCM95380 VLAN Router */
849 +#define BCM95380RR_BOARD 0x042a
850 +
851 +/* cb4306 with SiGe PA */
852 +#define BCM94306CBSG_BOARD 0x042b
853 +
854 +/* mp4301 with 2050 radio */
855 +#define BCM94301MPL_BOARD 0x042c
856 +
857 +/* cb4306 with SiGe PA */
858 +#define PCSG94306_BOARD 0x042d
859 +
860 +/* bu4704 with sdram */
861 +#define BU4704SD_BOARD 0x042e
862 +
863 +/* Dual 11a/11g Router */
864 +#define BCM94704AGR_BOARD 0x042f
865 +
866 +/* 11a-only minipci */
867 +#define BCM94308MP_BOARD 0x0430
868 +
869 +
870 +
871 +/* BCM94317 boards */
872 +#define BCM94317CB_BOARD 0x0440
873 +#define BCM94317MP_BOARD 0x0441
874 +#define BCM94317PCMCIA_BOARD 0x0442
875 +#define BCM94317SDIO_BOARD 0x0443
876 +
877 +#define BU4712_BOARD 0x0444
878 +#define BU4712SD_BOARD 0x045d
879 +#define BU4712L_BOARD 0x045f
880 +
881 +/* BCM4712 boards */
882 +#define BCM94712AP_BOARD 0x0445
883 +#define BCM94712P_BOARD 0x0446
884 +
885 +/* BCM4318 boards */
886 +#define BU4318_BOARD 0x0447
887 +#define CB4318_BOARD 0x0448
888 +#define MPG4318_BOARD 0x0449
889 +#define MP4318_BOARD 0x044a
890 +#define SD4318_BOARD 0x044b
891 +
892 +/* BCM63XX boards */
893 +#define BCM96338_BOARD 0x6338
894 +#define BCM96345_BOARD 0x6345
895 +#define BCM96348_BOARD 0x6348
896 +
897 +/* Another mp4306 with SiGe */
898 +#define BCM94306P_BOARD 0x044c
899 +
900 +/* CF-like 4317 modules */
901 +#define BCM94317CF_BOARD 0x044d
902 +
903 +/* mp4303 */
904 +#define BCM94303MP_BOARD 0x044e
905 +
906 +/* mpsgh4306 */
907 +#define BCM94306MPSGH_BOARD 0x044f
908 +
909 +/* BRCM 4306 w/ Front End Modules */
910 +#define BCM94306MPM 0x0450
911 +#define BCM94306MPL 0x0453
912 +
913 +/* 4712agr */
914 +#define BCM94712AGR_BOARD 0x0451
915 +
916 +/* The real CF 4317 board */
917 +#define CFI4317_BOARD 0x0452
918 +
919 +/* pcmcia 4303 */
920 +#define PC4303_BOARD 0x0454
921 +
922 +/* 5350K */
923 +#define BCM95350K_BOARD 0x0455
924 +
925 +/* 5350R */
926 +#define BCM95350R_BOARD 0x0456
927 +
928 +/* 4306mplna */
929 +#define BCM94306MPLNA_BOARD 0x0457
930 +
931 +/* 4320 boards */
932 +#define BU4320_BOARD 0x0458
933 +#define BU4320S_BOARD 0x0459
934 +#define BCM94320PH_BOARD 0x045a
935 +
936 +/* 4306mph */
937 +#define BCM94306MPH_BOARD 0x045b
938 +
939 +/* 4306pciv */
940 +#define BCM94306PCIV_BOARD 0x045c
941 +
942 +#define BU4712SD_BOARD 0x045d
943 +
944 +#define BCM94320PFLSH_BOARD 0x045e
945 +
946 +#define BU4712L_BOARD 0x045f
947 +#define BCM94712LGR_BOARD 0x0460
948 +#define BCM94320R_BOARD 0x0461
949 +
950 +#define BU5352_BOARD 0x0462
951 +
952 +#define BCM94318MPGH_BOARD 0x0463
953 +
954 +
955 +#define BCM95352GR_BOARD 0x0467
956 +
957 +/* bcm95351agr */
958 +#define BCM95351AGR_BOARD 0x0470
959 +
960 +/* # of GPIO pins */
961 +#define GPIO_NUMPINS 16
962 +
963 +#endif /* _BCMDEVS_H */
964 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
965 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
966 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-11-07 22:51:38.772725750 +0100
967 @@ -0,0 +1,152 @@
968 +/*
969 + * local version of endian.h - byte order defines
970 + *
971 + * Copyright 2005, Broadcom Corporation
972 + * All Rights Reserved.
973 + *
974 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
975 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
976 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
977 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
978 + *
979 + * $Id$
980 +*/
981 +
982 +#ifndef _BCMENDIAN_H_
983 +#define _BCMENDIAN_H_
984 +
985 +#include <typedefs.h>
986 +
987 +/* Byte swap a 16 bit value */
988 +#define BCMSWAP16(val) \
989 + ((uint16)( \
990 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
991 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
992 +
993 +/* Byte swap a 32 bit value */
994 +#define BCMSWAP32(val) \
995 + ((uint32)( \
996 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
997 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
998 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
999 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
1000 +
1001 +/* 2 Byte swap a 32 bit value */
1002 +#define BCMSWAP32BY16(val) \
1003 + ((uint32)( \
1004 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
1005 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
1006 +
1007 +
1008 +static INLINE uint16
1009 +bcmswap16(uint16 val)
1010 +{
1011 + return BCMSWAP16(val);
1012 +}
1013 +
1014 +static INLINE uint32
1015 +bcmswap32(uint32 val)
1016 +{
1017 + return BCMSWAP32(val);
1018 +}
1019 +
1020 +static INLINE uint32
1021 +bcmswap32by16(uint32 val)
1022 +{
1023 + return BCMSWAP32BY16(val);
1024 +}
1025 +
1026 +/* buf - start of buffer of shorts to swap */
1027 +/* len - byte length of buffer */
1028 +static INLINE void
1029 +bcmswap16_buf(uint16 *buf, uint len)
1030 +{
1031 + len = len/2;
1032 +
1033 + while(len--){
1034 + *buf = bcmswap16(*buf);
1035 + buf++;
1036 + }
1037 +}
1038 +
1039 +#ifndef hton16
1040 +#ifndef IL_BIGENDIAN
1041 +#define HTON16(i) BCMSWAP16(i)
1042 +#define hton16(i) bcmswap16(i)
1043 +#define hton32(i) bcmswap32(i)
1044 +#define ntoh16(i) bcmswap16(i)
1045 +#define ntoh32(i) bcmswap32(i)
1046 +#define ltoh16(i) (i)
1047 +#define ltoh32(i) (i)
1048 +#define htol16(i) (i)
1049 +#define htol32(i) (i)
1050 +#else
1051 +#define HTON16(i) (i)
1052 +#define hton16(i) (i)
1053 +#define hton32(i) (i)
1054 +#define ntoh16(i) (i)
1055 +#define ntoh32(i) (i)
1056 +#define ltoh16(i) bcmswap16(i)
1057 +#define ltoh32(i) bcmswap32(i)
1058 +#define htol16(i) bcmswap16(i)
1059 +#define htol32(i) bcmswap32(i)
1060 +#endif
1061 +#endif
1062 +
1063 +#ifndef IL_BIGENDIAN
1064 +#define ltoh16_buf(buf, i)
1065 +#define htol16_buf(buf, i)
1066 +#else
1067 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1068 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
1069 +#endif
1070 +
1071 +/*
1072 +* load 16-bit value from unaligned little endian byte array.
1073 +*/
1074 +static INLINE uint16
1075 +ltoh16_ua(uint8 *bytes)
1076 +{
1077 + return (bytes[1]<<8)+bytes[0];
1078 +}
1079 +
1080 +/*
1081 +* load 32-bit value from unaligned little endian byte array.
1082 +*/
1083 +static INLINE uint32
1084 +ltoh32_ua(uint8 *bytes)
1085 +{
1086 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
1087 +}
1088 +
1089 +/*
1090 +* load 16-bit value from unaligned big(network) endian byte array.
1091 +*/
1092 +static INLINE uint16
1093 +ntoh16_ua(uint8 *bytes)
1094 +{
1095 + return (bytes[0]<<8)+bytes[1];
1096 +}
1097 +
1098 +/*
1099 +* load 32-bit value from unaligned big(network) endian byte array.
1100 +*/
1101 +static INLINE uint32
1102 +ntoh32_ua(uint8 *bytes)
1103 +{
1104 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
1105 +}
1106 +
1107 +#define ltoh_ua(ptr) ( \
1108 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1109 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
1110 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
1111 +)
1112 +
1113 +#define ntoh_ua(ptr) ( \
1114 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
1115 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
1116 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
1117 +)
1118 +
1119 +#endif /* _BCMENDIAN_H_ */
1120 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h
1121 --- linux.old/arch/mips/bcm947xx/include/bcmenet47xx.h 1970-01-01 01:00:00.000000000 +0100
1122 +++ linux.dev/arch/mips/bcm947xx/include/bcmenet47xx.h 2005-11-07 22:51:38.772725750 +0100
1123 @@ -0,0 +1,229 @@
1124 +/*
1125 + * Hardware-specific definitions for
1126 + * Broadcom BCM47XX 10/100 Mbps Ethernet cores.
1127 + *
1128 + * Copyright 2005, Broadcom Corporation
1129 + * All Rights Reserved.
1130 + *
1131 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1132 + * the contents of this file may not be disclosed to third parties, copied
1133 + * or duplicated in any form, in whole or in part, without the prior
1134 + * written permission of Broadcom Corporation.
1135 + * $Id$
1136 + */
1137 +
1138 +#ifndef _bcmenet_47xx_h_
1139 +#define _bcmenet_47xx_h_
1140 +
1141 +#include <bcmenetmib.h>
1142 +#include <bcmenetrxh.h>
1143 +#include <bcmenetphy.h>
1144 +
1145 +#define BCMENET_NFILTERS 64 /* # ethernet address filter entries */
1146 +#define BCMENET_MCHASHBASE 0x200 /* multicast hash filter base address */
1147 +#define BCMENET_MCHASHSIZE 256 /* multicast hash filter size in bytes */
1148 +#define BCMENET_MAX_DMA 4096 /* chip has 12 bits of DMA addressing */
1149 +
1150 +/* power management event wakeup pattern constants */
1151 +#define BCMENET_NPMP 4 /* chip supports 4 wakeup patterns */
1152 +#define BCMENET_PMPBASE 0x400 /* wakeup pattern base address */
1153 +#define BCMENET_PMPSIZE 0x80 /* 128bytes each pattern */
1154 +#define BCMENET_PMMBASE 0x600 /* wakeup mask base address */
1155 +#define BCMENET_PMMSIZE 0x10 /* 128bits each mask */
1156 +
1157 +/* cpp contortions to concatenate w/arg prescan */
1158 +#ifndef PAD
1159 +#define _PADLINE(line) pad ## line
1160 +#define _XSTR(line) _PADLINE(line)
1161 +#define PAD _XSTR(__LINE__)
1162 +#endif /* PAD */
1163 +
1164 +/*
1165 + * Host Interface Registers
1166 + */
1167 +typedef volatile struct _bcmenettregs {
1168 + /* Device and Power Control */
1169 + uint32 devcontrol;
1170 + uint32 PAD[2];
1171 + uint32 biststatus;
1172 + uint32 wakeuplength;
1173 + uint32 PAD[3];
1174 +
1175 + /* Interrupt Control */
1176 + uint32 intstatus;
1177 + uint32 intmask;
1178 + uint32 gptimer;
1179 + uint32 PAD[23];
1180 +
1181 + /* Ethernet MAC Address Filtering Control */
1182 + uint32 PAD[2];
1183 + uint32 enetftaddr;
1184 + uint32 enetftdata;
1185 + uint32 PAD[2];
1186 +
1187 + /* Ethernet MAC Control */
1188 + uint32 emactxmaxburstlen;
1189 + uint32 emacrxmaxburstlen;
1190 + uint32 emaccontrol;
1191 + uint32 emacflowcontrol;
1192 +
1193 + uint32 PAD[20];
1194 +
1195 + /* DMA Lazy Interrupt Control */
1196 + uint32 intrecvlazy;
1197 + uint32 PAD[63];
1198 +
1199 + /* DMA engine */
1200 + dma32regp_t dmaregs;
1201 + dma32diag_t dmafifo;
1202 + uint32 PAD[116];
1203 +
1204 + /* EMAC Registers */
1205 + uint32 rxconfig;
1206 + uint32 rxmaxlength;
1207 + uint32 txmaxlength;
1208 + uint32 PAD;
1209 + uint32 mdiocontrol;
1210 + uint32 mdiodata;
1211 + uint32 emacintmask;
1212 + uint32 emacintstatus;
1213 + uint32 camdatalo;
1214 + uint32 camdatahi;
1215 + uint32 camcontrol;
1216 + uint32 enetcontrol;
1217 + uint32 txcontrol;
1218 + uint32 txwatermark;
1219 + uint32 mibcontrol;
1220 + uint32 PAD[49];
1221 +
1222 + /* EMAC MIB counters */
1223 + bcmenetmib_t mib;
1224 +
1225 + uint32 PAD[585];
1226 +
1227 + /* Sonics SiliconBackplane config registers */
1228 + sbconfig_t sbconfig;
1229 +} bcmenetregs_t;
1230 +
1231 +/* device control */
1232 +#define DC_PM ((uint32)1 << 7) /* pattern filtering enable */
1233 +#define DC_IP ((uint32)1 << 10) /* internal ephy present (rev >= 1) */
1234 +#define DC_ER ((uint32)1 << 15) /* ephy reset */
1235 +#define DC_MP ((uint32)1 << 16) /* mii phy mode enable */
1236 +#define DC_CO ((uint32)1 << 17) /* mii phy mode: enable clocks */
1237 +#define DC_PA_MASK 0x7c0000 /* mii phy mode: mdc/mdio phy address */
1238 +#define DC_PA_SHIFT 18
1239 +#define DC_FS_MASK 0x03800000 /* fifo size (rev >= 8) */
1240 +#define DC_FS_SHIFT 23
1241 +#define DC_FS_4K 0 /* 4Kbytes */
1242 +#define DC_FS_512 1 /* 512bytes */
1243 +
1244 +/* wakeup length */
1245 +#define WL_P0_MASK 0x7f /* pattern 0 */
1246 +#define WL_D0 ((uint32)1 << 7)
1247 +#define WL_P1_MASK 0x7f00 /* pattern 1 */
1248 +#define WL_P1_SHIFT 8
1249 +#define WL_D1 ((uint32)1 << 15)
1250 +#define WL_P2_MASK 0x7f0000 /* pattern 2 */
1251 +#define WL_P2_SHIFT 16
1252 +#define WL_D2 ((uint32)1 << 23)
1253 +#define WL_P3_MASK 0x7f000000 /* pattern 3 */
1254 +#define WL_P3_SHIFT 24
1255 +#define WL_D3 ((uint32)1 << 31)
1256 +
1257 +/* intstatus and intmask */
1258 +#define I_PME ((uint32)1 << 6) /* power management event */
1259 +#define I_TO ((uint32)1 << 7) /* general purpose timeout */
1260 +#define I_PC ((uint32)1 << 10) /* descriptor error */
1261 +#define I_PD ((uint32)1 << 11) /* data error */
1262 +#define I_DE ((uint32)1 << 12) /* descriptor protocol error */
1263 +#define I_RU ((uint32)1 << 13) /* receive descriptor underflow */
1264 +#define I_RO ((uint32)1 << 14) /* receive fifo overflow */
1265 +#define I_XU ((uint32)1 << 15) /* transmit fifo underflow */
1266 +#define I_RI ((uint32)1 << 16) /* receive interrupt */
1267 +#define I_XI ((uint32)1 << 24) /* transmit interrupt */
1268 +#define I_EM ((uint32)1 << 26) /* emac interrupt */
1269 +#define I_MW ((uint32)1 << 27) /* mii write */
1270 +#define I_MR ((uint32)1 << 28) /* mii read */
1271 +
1272 +/* emaccontrol */
1273 +#define EMC_CG ((uint32)1 << 0) /* crc32 generation enable */
1274 +#define EMC_EP ((uint32)1 << 2) /* onchip ephy: powerdown (rev >= 1) */
1275 +#define EMC_ED ((uint32)1 << 3) /* onchip ephy: energy detected (rev >= 1) */
1276 +#define EMC_LC_MASK 0xe0 /* onchip ephy: led control (rev >= 1) */
1277 +#define EMC_LC_SHIFT 5
1278 +
1279 +/* emacflowcontrol */
1280 +#define EMF_RFH_MASK 0xff /* rx fifo hi water mark */
1281 +#define EMF_PG ((uint32)1 << 15) /* enable pause frame generation */
1282 +
1283 +/* interrupt receive lazy */
1284 +#define IRL_TO_MASK 0x00ffffff /* timeout */
1285 +#define IRL_FC_MASK 0xff000000 /* frame count */
1286 +#define IRL_FC_SHIFT 24 /* frame count */
1287 +
1288 +/* emac receive config */
1289 +#define ERC_DB ((uint32)1 << 0) /* disable broadcast */
1290 +#define ERC_AM ((uint32)1 << 1) /* accept all multicast */
1291 +#define ERC_RDT ((uint32)1 << 2) /* receive disable while transmitting */
1292 +#define ERC_PE ((uint32)1 << 3) /* promiscuous enable */
1293 +#define ERC_LE ((uint32)1 << 4) /* loopback enable */
1294 +#define ERC_FE ((uint32)1 << 5) /* enable flow control */
1295 +#define ERC_UF ((uint32)1 << 6) /* accept unicast flow control frame */
1296 +#define ERC_RF ((uint32)1 << 7) /* reject filter */
1297 +#define ERC_CA ((uint32)1 << 8) /* cam absent */
1298 +
1299 +/* emac mdio control */
1300 +#define MC_MF_MASK 0x7f /* mdc frequency */
1301 +#define MC_PE ((uint32)1 << 7) /* mii preamble enable */
1302 +
1303 +/* emac mdio data */
1304 +#define MD_DATA_MASK 0xffff /* r/w data */
1305 +#define MD_TA_MASK 0x30000 /* turnaround value */
1306 +#define MD_TA_SHIFT 16
1307 +#define MD_TA_VALID (2 << MD_TA_SHIFT) /* valid ta */
1308 +#define MD_RA_MASK 0x7c0000 /* register address */
1309 +#define MD_RA_SHIFT 18
1310 +#define MD_PMD_MASK 0xf800000 /* physical media device */
1311 +#define MD_PMD_SHIFT 23
1312 +#define MD_OP_MASK 0x30000000 /* opcode */
1313 +#define MD_OP_SHIFT 28
1314 +#define MD_OP_WRITE (1 << MD_OP_SHIFT) /* write op */
1315 +#define MD_OP_READ (2 << MD_OP_SHIFT) /* read op */
1316 +#define MD_SB_MASK 0xc0000000 /* start bits */
1317 +#define MD_SB_SHIFT 30
1318 +#define MD_SB_START (0x1 << MD_SB_SHIFT) /* start of frame */
1319 +
1320 +/* emac intstatus and intmask */
1321 +#define EI_MII ((uint32)1 << 0) /* mii mdio interrupt */
1322 +#define EI_MIB ((uint32)1 << 1) /* mib interrupt */
1323 +#define EI_FLOW ((uint32)1 << 2) /* flow control interrupt */
1324 +
1325 +/* emac cam data high */
1326 +#define CD_V ((uint32)1 << 16) /* valid bit */
1327 +
1328 +/* emac cam control */
1329 +#define CC_CE ((uint32)1 << 0) /* cam enable */
1330 +#define CC_MS ((uint32)1 << 1) /* mask select */
1331 +#define CC_RD ((uint32)1 << 2) /* read */
1332 +#define CC_WR ((uint32)1 << 3) /* write */
1333 +#define CC_INDEX_MASK 0x3f0000 /* index */
1334 +#define CC_INDEX_SHIFT 16
1335 +#define CC_CB ((uint32)1 << 31) /* cam busy */
1336 +
1337 +/* emac ethernet control */
1338 +#define EC_EE ((uint32)1 << 0) /* emac enable */
1339 +#define EC_ED ((uint32)1 << 1) /* emac disable */
1340 +#define EC_ES ((uint32)1 << 2) /* emac soft reset */
1341 +#define EC_EP ((uint32)1 << 3) /* external phy select */
1342 +
1343 +/* emac transmit control */
1344 +#define EXC_FD ((uint32)1 << 0) /* full duplex */
1345 +#define EXC_FM ((uint32)1 << 1) /* flowmode */
1346 +#define EXC_SB ((uint32)1 << 2) /* single backoff enable */
1347 +#define EXC_SS ((uint32)1 << 3) /* small slottime */
1348 +
1349 +/* emac mib control */
1350 +#define EMC_RZ ((uint32)1 << 0) /* autoclear on read */
1351 +
1352 +#endif /* _bcmenet_47xx_h_ */
1353 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetmib.h linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h
1354 --- linux.old/arch/mips/bcm947xx/include/bcmenetmib.h 1970-01-01 01:00:00.000000000 +0100
1355 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetmib.h 2005-11-07 21:57:07.845585750 +0100
1356 @@ -0,0 +1,81 @@
1357 +/*
1358 + * Hardware-specific MIB definition for
1359 + * Broadcom Home Networking Division
1360 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1361 + *
1362 + * Copyright 2005, Broadcom Corporation
1363 + * All Rights Reserved.
1364 + *
1365 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1366 + * the contents of this file may not be disclosed to third parties, copied
1367 + * or duplicated in any form, in whole or in part, without the prior
1368 + * written permission of Broadcom Corporation.
1369 + * $Id$
1370 + */
1371 +
1372 +#ifndef _bcmenetmib_h_
1373 +#define _bcmenetmib_h_
1374 +
1375 +/* cpp contortions to concatenate w/arg prescan */
1376 +#ifndef PAD
1377 +#define _PADLINE(line) pad ## line
1378 +#define _XSTR(line) _PADLINE(line)
1379 +#define PAD _XSTR(__LINE__)
1380 +#endif /* PAD */
1381 +
1382 +/*
1383 + * EMAC MIB Registers
1384 + */
1385 +typedef volatile struct {
1386 + uint32 tx_good_octets;
1387 + uint32 tx_good_pkts;
1388 + uint32 tx_octets;
1389 + uint32 tx_pkts;
1390 + uint32 tx_broadcast_pkts;
1391 + uint32 tx_multicast_pkts;
1392 + uint32 tx_len_64;
1393 + uint32 tx_len_65_to_127;
1394 + uint32 tx_len_128_to_255;
1395 + uint32 tx_len_256_to_511;
1396 + uint32 tx_len_512_to_1023;
1397 + uint32 tx_len_1024_to_max;
1398 + uint32 tx_jabber_pkts;
1399 + uint32 tx_oversize_pkts;
1400 + uint32 tx_fragment_pkts;
1401 + uint32 tx_underruns;
1402 + uint32 tx_total_cols;
1403 + uint32 tx_single_cols;
1404 + uint32 tx_multiple_cols;
1405 + uint32 tx_excessive_cols;
1406 + uint32 tx_late_cols;
1407 + uint32 tx_defered;
1408 + uint32 tx_carrier_lost;
1409 + uint32 tx_pause_pkts;
1410 + uint32 PAD[8];
1411 +
1412 + uint32 rx_good_octets;
1413 + uint32 rx_good_pkts;
1414 + uint32 rx_octets;
1415 + uint32 rx_pkts;
1416 + uint32 rx_broadcast_pkts;
1417 + uint32 rx_multicast_pkts;
1418 + uint32 rx_len_64;
1419 + uint32 rx_len_65_to_127;
1420 + uint32 rx_len_128_to_255;
1421 + uint32 rx_len_256_to_511;
1422 + uint32 rx_len_512_to_1023;
1423 + uint32 rx_len_1024_to_max;
1424 + uint32 rx_jabber_pkts;
1425 + uint32 rx_oversize_pkts;
1426 + uint32 rx_fragment_pkts;
1427 + uint32 rx_missed_pkts;
1428 + uint32 rx_crc_align_errs;
1429 + uint32 rx_undersize;
1430 + uint32 rx_crc_errs;
1431 + uint32 rx_align_errs;
1432 + uint32 rx_symbol_errs;
1433 + uint32 rx_pause_pkts;
1434 + uint32 rx_nonpause_pkts;
1435 +} bcmenetmib_t;
1436 +
1437 +#endif /* _bcmenetmib_h_ */
1438 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetphy.h linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h
1439 --- linux.old/arch/mips/bcm947xx/include/bcmenetphy.h 1970-01-01 01:00:00.000000000 +0100
1440 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetphy.h 2005-11-07 21:57:07.845585750 +0100
1441 @@ -0,0 +1,58 @@
1442 +/*
1443 + * Misc Broadcom BCM47XX MDC/MDIO enet phy definitions.
1444 + *
1445 + * Copyright 2005, Broadcom Corporation
1446 + * All Rights Reserved.
1447 + *
1448 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1449 + * the contents of this file may not be disclosed to third parties, copied
1450 + * or duplicated in any form, in whole or in part, without the prior
1451 + * written permission of Broadcom Corporation.
1452 + * $Id$
1453 + */
1454 +
1455 +#ifndef _bcmenetphy_h_
1456 +#define _bcmenetphy_h_
1457 +
1458 +/* phy address */
1459 +#define MAXEPHY 32 /* mdio phy addresses are 5bit quantities */
1460 +#define EPHY_MASK 0x1f
1461 +#define EPHY_NONE 31 /* nvram: no phy present at all */
1462 +#define EPHY_NOREG 30 /* nvram: no local phy regs */
1463 +
1464 +/* just a few phy registers */
1465 +#define CTL_RESET (1 << 15) /* reset */
1466 +#define CTL_LOOP (1 << 14) /* loopback */
1467 +#define CTL_SPEED (1 << 13) /* speed selection 0=10, 1=100 */
1468 +#define CTL_ANENAB (1 << 12) /* autonegotiation enable */
1469 +#define CTL_RESTART (1 << 9) /* restart autonegotiation */
1470 +#define CTL_DUPLEX (1 << 8) /* duplex mode 0=half, 1=full */
1471 +
1472 +#define ADV_10FULL (1 << 6) /* autonegotiate advertise 10full */
1473 +#define ADV_10HALF (1 << 5) /* autonegotiate advertise 10half */
1474 +#define ADV_100FULL (1 << 8) /* autonegotiate advertise 100full */
1475 +#define ADV_100HALF (1 << 7) /* autonegotiate advertise 100half */
1476 +
1477 +/* link partner ability register */
1478 +#define LPA_SLCT 0x001f /* same as advertise selector */
1479 +#define LPA_10HALF 0x0020 /* can do 10mbps half-duplex */
1480 +#define LPA_10FULL 0x0040 /* can do 10mbps full-duplex */
1481 +#define LPA_100HALF 0x0080 /* can do 100mbps half-duplex */
1482 +#define LPA_100FULL 0x0100 /* can do 100mbps full-duplex */
1483 +#define LPA_100BASE4 0x0200 /* can do 100mbps 4k packets */
1484 +#define LPA_RESV 0x1c00 /* unused */
1485 +#define LPA_RFAULT 0x2000 /* link partner faulted */
1486 +#define LPA_LPACK 0x4000 /* link partner acked us */
1487 +#define LPA_NPAGE 0x8000 /* next page bit */
1488 +
1489 +#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
1490 +#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
1491 +
1492 +#define STAT_REMFAULT (1 << 4) /* remote fault */
1493 +#define STAT_LINK (1 << 2) /* link status */
1494 +#define STAT_JAB (1 << 1) /* jabber detected */
1495 +#define AUX_FORCED (1 << 2) /* forced 10/100 */
1496 +#define AUX_SPEED (1 << 1) /* speed 0=10mbps 1=100mbps */
1497 +#define AUX_DUPLEX (1 << 0) /* duplex 0=half 1=full */
1498 +
1499 +#endif /* _bcmenetphy_h_ */
1500 diff -urN linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h
1501 --- linux.old/arch/mips/bcm947xx/include/bcmenetrxh.h 1970-01-01 01:00:00.000000000 +0100
1502 +++ linux.dev/arch/mips/bcm947xx/include/bcmenetrxh.h 2005-11-07 21:57:07.845585750 +0100
1503 @@ -0,0 +1,43 @@
1504 +/*
1505 + * Hardware-specific Receive Data Header for the
1506 + * Broadcom Home Networking Division
1507 + * BCM44XX and BCM47XX 10/100 Mbps Ethernet cores.
1508 + *
1509 + * Copyright 2005, Broadcom Corporation
1510 + * All Rights Reserved.
1511 + *
1512 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
1513 + * the contents of this file may not be disclosed to third parties, copied
1514 + * or duplicated in any form, in whole or in part, without the prior
1515 + * written permission of Broadcom Corporation.
1516 + * $Id$
1517 + */
1518 +
1519 +#ifndef _bcmenetrxh_h_
1520 +#define _bcmenetrxh_h_
1521 +
1522 +/*
1523 + * The Ethernet MAC core returns an 8-byte Receive Frame Data Header
1524 + * with every frame consisting of
1525 + * 16bits of frame length, followed by
1526 + * 16bits of EMAC rx descriptor info, followed by 32bits of undefined.
1527 + */
1528 +typedef volatile struct {
1529 + uint16 len;
1530 + uint16 flags;
1531 + uint16 pad[12];
1532 +} bcmenetrxh_t;
1533 +
1534 +#define RXHDR_LEN 28
1535 +
1536 +#define RXF_L ((uint16)1 << 11) /* last buffer in a frame */
1537 +#define RXF_MISS ((uint16)1 << 7) /* received due to promisc mode */
1538 +#define RXF_BRDCAST ((uint16)1 << 6) /* dest is broadcast address */
1539 +#define RXF_MULT ((uint16)1 << 5) /* dest is multicast address */
1540 +#define RXF_LG ((uint16)1 << 4) /* frame length > rxmaxlength */
1541 +#define RXF_NO ((uint16)1 << 3) /* odd number of nibbles */
1542 +#define RXF_RXER ((uint16)1 << 2) /* receive symbol error */
1543 +#define RXF_CRC ((uint16)1 << 1) /* crc error */
1544 +#define RXF_OV ((uint16)1 << 0) /* fifo overflow */
1545 +
1546 +#endif /* _bcmenetrxh_h_ */
1547 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
1548 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
1549 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-11-07 22:51:38.772725750 +0100
1550 @@ -0,0 +1,141 @@
1551 +/*
1552 + * NVRAM variable manipulation
1553 + *
1554 + * Copyright 2005, Broadcom Corporation
1555 + * All Rights Reserved.
1556 + *
1557 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1558 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1559 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1560 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1561 + *
1562 + * $Id$
1563 + */
1564 +
1565 +#ifndef _bcmnvram_h_
1566 +#define _bcmnvram_h_
1567 +
1568 +#ifndef _LANGUAGE_ASSEMBLY
1569 +
1570 +#include <typedefs.h>
1571 +
1572 +struct nvram_header {
1573 + uint32 magic;
1574 + uint32 len;
1575 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
1576 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
1577 + uint32 config_ncdl; /* ncdl values for memc */
1578 +};
1579 +
1580 +struct nvram_tuple {
1581 + char *name;
1582 + char *value;
1583 + struct nvram_tuple *next;
1584 +};
1585 +
1586 +/*
1587 + * Initialize NVRAM access. May be unnecessary or undefined on certain
1588 + * platforms.
1589 + */
1590 +extern int BCMINIT(nvram_init)(void *sbh);
1591 +
1592 +/*
1593 + * Disable NVRAM access. May be unnecessary or undefined on certain
1594 + * platforms.
1595 + */
1596 +extern void BCMINIT(nvram_exit)(void *sbh);
1597 +
1598 +/*
1599 + * Get the value of an NVRAM variable. The pointer returned may be
1600 + * invalid after a set.
1601 + * @param name name of variable to get
1602 + * @return value of variable or NULL if undefined
1603 + */
1604 +extern char * BCMINIT(nvram_get)(const char *name);
1605 +
1606 +/*
1607 + * Read the reset GPIO value from the nvram and set the GPIO
1608 + * as input
1609 + */
1610 +extern int BCMINITFN(nvram_resetgpio_init)(void *sbh);
1611 +
1612 +/*
1613 + * Get the value of an NVRAM variable.
1614 + * @param name name of variable to get
1615 + * @return value of variable or NUL if undefined
1616 + */
1617 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
1618 +
1619 +/*
1620 + * Match an NVRAM variable.
1621 + * @param name name of variable to match
1622 + * @param match value to compare against value of variable
1623 + * @return TRUE if variable is defined and its value is string equal
1624 + * to match or FALSE otherwise
1625 + */
1626 +static INLINE int
1627 +nvram_match(char *name, char *match) {
1628 + const char *value = BCMINIT(nvram_get)(name);
1629 + return (value && !strcmp(value, match));
1630 +}
1631 +
1632 +/*
1633 + * Inversely match an NVRAM variable.
1634 + * @param name name of variable to match
1635 + * @param match value to compare against value of variable
1636 + * @return TRUE if variable is defined and its value is not string
1637 + * equal to invmatch or FALSE otherwise
1638 + */
1639 +static INLINE int
1640 +nvram_invmatch(char *name, char *invmatch) {
1641 + const char *value = BCMINIT(nvram_get)(name);
1642 + return (value && strcmp(value, invmatch));
1643 +}
1644 +
1645 +/*
1646 + * Set the value of an NVRAM variable. The name and value strings are
1647 + * copied into private storage. Pointers to previously set values
1648 + * may become invalid. The new value may be immediately
1649 + * retrieved but will not be permanently stored until a commit.
1650 + * @param name name of variable to set
1651 + * @param value value of variable
1652 + * @return 0 on success and errno on failure
1653 + */
1654 +extern int BCMINIT(nvram_set)(const char *name, const char *value);
1655 +
1656 +/*
1657 + * Unset an NVRAM variable. Pointers to previously set values
1658 + * remain valid until a set.
1659 + * @param name name of variable to unset
1660 + * @return 0 on success and errno on failure
1661 + * NOTE: use nvram_commit to commit this change to flash.
1662 + */
1663 +extern int BCMINIT(nvram_unset)(const char *name);
1664 +
1665 +/*
1666 + * Commit NVRAM variables to permanent storage. All pointers to values
1667 + * may be invalid after a commit.
1668 + * NVRAM values are undefined after a commit.
1669 + * @return 0 on success and errno on failure
1670 + */
1671 +extern int BCMINIT(nvram_commit)(void);
1672 +
1673 +/*
1674 + * Get all NVRAM variables (format name=value\0 ... \0\0).
1675 + * @param buf buffer to store variables
1676 + * @param count size of buffer in bytes
1677 + * @return 0 on success and errno on failure
1678 + */
1679 +extern int BCMINIT(nvram_getall)(char *buf, int count);
1680 +
1681 +#endif /* _LANGUAGE_ASSEMBLY */
1682 +
1683 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
1684 +#define NVRAM_VERSION 1
1685 +#define NVRAM_HEADER_SIZE 20
1686 +#define NVRAM_SPACE 0x8000
1687 +
1688 +#define NVRAM_MAX_VALUE_LEN 255
1689 +#define NVRAM_MAX_PARAM_LEN 64
1690 +
1691 +#endif /* _bcmnvram_h_ */
1692 diff -urN linux.old/arch/mips/bcm947xx/include/bcmparams.h linux.dev/arch/mips/bcm947xx/include/bcmparams.h
1693 --- linux.old/arch/mips/bcm947xx/include/bcmparams.h 1970-01-01 01:00:00.000000000 +0100
1694 +++ linux.dev/arch/mips/bcm947xx/include/bcmparams.h 2005-11-07 22:51:38.776726000 +0100
1695 @@ -0,0 +1,25 @@
1696 +/*
1697 + * Misc system wide parameters.
1698 + *
1699 + * Copyright 2005, Broadcom Corporation
1700 + * All Rights Reserved.
1701 + *
1702 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1703 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1704 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1705 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1706 + * $Id$
1707 + */
1708 +
1709 +#ifndef _bcmparams_h_
1710 +#define _bcmparams_h_
1711 +
1712 +#define VLAN_MAXVID 15 /* Max. VLAN ID supported/allowed */
1713 +
1714 +#define VLAN_NUMPRIS 8 /* # of prio, start from 0 */
1715 +
1716 +#define DEV_NUMIFS 16 /* Max. # of devices/interfaces supported */
1717 +
1718 +#define WL_MAXBSSCFG 16 /* maximum number of BSS Configs we can configure */
1719 +
1720 +#endif
1721 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
1722 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
1723 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-11-07 22:51:38.776726000 +0100
1724 @@ -0,0 +1,23 @@
1725 +/*
1726 + * Misc useful routines to access NIC local SROM/OTP .
1727 + *
1728 + * Copyright 2005, Broadcom Corporation
1729 + * All Rights Reserved.
1730 + *
1731 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1732 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1733 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1734 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1735 + *
1736 + * $Id$
1737 + */
1738 +
1739 +#ifndef _bcmsrom_h_
1740 +#define _bcmsrom_h_
1741 +
1742 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
1743 +
1744 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1745 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
1746 +
1747 +#endif /* _bcmsrom_h_ */
1748 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
1749 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
1750 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-11-07 22:51:38.776726000 +0100
1751 @@ -0,0 +1,313 @@
1752 +/*
1753 + * Misc useful os-independent macros and functions.
1754 + *
1755 + * Copyright 2005, Broadcom Corporation
1756 + * All Rights Reserved.
1757 + *
1758 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1759 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1760 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1761 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1762 + * $Id$
1763 + */
1764 +
1765 +#ifndef _bcmutils_h_
1766 +#define _bcmutils_h_
1767 +
1768 +/*** driver-only section ***/
1769 +#ifdef BCMDRIVER
1770 +#include <osl.h>
1771 +
1772 +#define _BCM_U 0x01 /* upper */
1773 +#define _BCM_L 0x02 /* lower */
1774 +#define _BCM_D 0x04 /* digit */
1775 +#define _BCM_C 0x08 /* cntrl */
1776 +#define _BCM_P 0x10 /* punct */
1777 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
1778 +#define _BCM_X 0x40 /* hex digit */
1779 +#define _BCM_SP 0x80 /* hard space (0x20) */
1780 +
1781 +#define GPIO_PIN_NOTDEFINED 0x20
1782 +
1783 +extern unsigned char bcm_ctype[];
1784 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
1785 +
1786 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
1787 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
1788 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
1789 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
1790 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
1791 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
1792 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
1793 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
1794 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
1795 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
1796 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
1797 +
1798 +/*
1799 + * Spin at most 'us' microseconds while 'exp' is true.
1800 + * Caller should explicitly test 'exp' when this completes
1801 + * and take appropriate error action if 'exp' is still true.
1802 + */
1803 +#define SPINWAIT(exp, us) { \
1804 + uint countdown = (us) + 9; \
1805 + while ((exp) && (countdown >= 10)) {\
1806 + OSL_DELAY(10); \
1807 + countdown -= 10; \
1808 + } \
1809 +}
1810 +
1811 +/* generic osl packet queue */
1812 +struct pktq {
1813 + void *head; /* first packet to dequeue */
1814 + void *tail; /* last packet to dequeue */
1815 + uint len; /* number of queued packets */
1816 + uint maxlen; /* maximum number of queued packets */
1817 + bool priority; /* enqueue by packet priority */
1818 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
1819 +};
1820 +#define DEFAULT_QLEN 128
1821 +
1822 +#define pktq_len(q) ((q)->len)
1823 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
1824 +#define pktq_head(q) ((q)->head)
1825 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
1826 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
1827 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
1828 +
1829 +/* externs */
1830 +/* packet */
1831 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
1832 +extern uint pkttotlen(osl_t *osh, void *);
1833 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
1834 +extern void pktenq(struct pktq *q, void *p, bool lifo);
1835 +extern void *pktdeq(struct pktq *q);
1836 +extern void *pktdeqtail(struct pktq *q);
1837 +/* string */
1838 +extern uint bcm_atoi(char *s);
1839 +extern uchar bcm_toupper(uchar c);
1840 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
1841 +extern char *bcmstrstr(char *haystack, char *needle);
1842 +extern char *bcmstrcat(char *dest, const char *src);
1843 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
1844 +/* ethernet address */
1845 +extern char *bcm_ether_ntoa(char *ea, char *buf);
1846 +extern int bcm_ether_atoe(char *p, char *ea);
1847 +/* delay */
1848 +extern void bcm_mdelay(uint ms);
1849 +/* variable access */
1850 +extern char *getvar(char *vars, char *name);
1851 +extern int getintvar(char *vars, char *name);
1852 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
1853 +#define bcmlog(fmt, a1, a2)
1854 +#define bcmdumplog(buf, size) *buf = '\0'
1855 +#define bcmdumplogent(buf, idx) -1
1856 +
1857 +#endif /* #ifdef BCMDRIVER */
1858 +
1859 +/*** driver/apps-shared section ***/
1860 +
1861 +#define BCME_STRLEN 64
1862 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
1863 +
1864 +
1865 +/*
1866 + * error codes could be added but the defined ones shouldn't be changed/deleted
1867 + * these error codes are exposed to the user code
1868 + * when ever a new error code is added to this list
1869 + * please update errorstring table with the related error string and
1870 + * update osl files with os specific errorcode map
1871 +*/
1872 +
1873 +#define BCME_ERROR -1 /* Error generic */
1874 +#define BCME_BADARG -2 /* Bad Argument */
1875 +#define BCME_BADOPTION -3 /* Bad option */
1876 +#define BCME_NOTUP -4 /* Not up */
1877 +#define BCME_NOTDOWN -5 /* Not down */
1878 +#define BCME_NOTAP -6 /* Not AP */
1879 +#define BCME_NOTSTA -7 /* Not STA */
1880 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
1881 +#define BCME_RADIOOFF -9 /* Radio Off */
1882 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
1883 +#define BCME_NOCLK -11 /* No Clock*/
1884 +#define BCME_BADRATESET -12 /* BAD RateSet*/
1885 +#define BCME_BADBAND -13 /* BAD Band */
1886 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
1887 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
1888 +#define BCME_BUSY -16 /* Busy*/
1889 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
1890 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
1891 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
1892 +#define BCME_BADCHAN -20 /* BAD Channel */
1893 +#define BCME_BADADDR -21 /* BAD Address*/
1894 +#define BCME_NORESOURCE -22 /* No resources*/
1895 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
1896 +#define BCME_BADLEN -24 /* Bad Length*/
1897 +#define BCME_NOTREADY -25 /* Not ready Yet*/
1898 +#define BCME_EPERM -26 /* Not Permitted */
1899 +#define BCME_NOMEM -27 /* No Memory */
1900 +#define BCME_ASSOCIATED -28 /* Associated */
1901 +#define BCME_RANGE -29 /* Range Error*/
1902 +#define BCME_NOTFOUND -30 /* Not found */
1903 +#define BCME_LAST BCME_NOTFOUND
1904 +
1905 +#ifndef ABS
1906 +#define ABS(a) (((a)<0)?-(a):(a))
1907 +#endif
1908 +
1909 +#ifndef MIN
1910 +#define MIN(a, b) (((a)<(b))?(a):(b))
1911 +#endif
1912 +
1913 +#ifndef MAX
1914 +#define MAX(a, b) (((a)>(b))?(a):(b))
1915 +#endif
1916 +
1917 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
1918 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
1919 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
1920 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
1921 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
1922 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
1923 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
1924 +
1925 +/* bit map related macros */
1926 +#ifndef setbit
1927 +#define NBBY 8 /* 8 bits per byte */
1928 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
1929 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
1930 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
1931 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
1932 +#endif
1933 +
1934 +#define NBITS(type) (sizeof(type) * 8)
1935 +#define NBITVAL(bits) (1 << (bits))
1936 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
1937 +
1938 +/* crc defines */
1939 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
1940 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
1941 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
1942 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
1943 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
1944 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
1945 +
1946 +/* bcm_format_flags() bit description structure */
1947 +typedef struct bcm_bit_desc {
1948 + uint32 bit;
1949 + char* name;
1950 +} bcm_bit_desc_t;
1951 +
1952 +/* tag_ID/length/value_buffer tuple */
1953 +typedef struct bcm_tlv {
1954 + uint8 id;
1955 + uint8 len;
1956 + uint8 data[1];
1957 +} bcm_tlv_t;
1958 +
1959 +/* Check that bcm_tlv_t fits into the given buflen */
1960 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
1961 +
1962 +/* buffer length for ethernet address from bcm_ether_ntoa() */
1963 +#define ETHER_ADDR_STR_LEN 18
1964 +
1965 +/* unaligned load and store macros */
1966 +#ifdef IL_BIGENDIAN
1967 +static INLINE uint32
1968 +load32_ua(uint8 *a)
1969 +{
1970 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
1971 +}
1972 +
1973 +static INLINE void
1974 +store32_ua(uint8 *a, uint32 v)
1975 +{
1976 + a[0] = (v >> 24) & 0xff;
1977 + a[1] = (v >> 16) & 0xff;
1978 + a[2] = (v >> 8) & 0xff;
1979 + a[3] = v & 0xff;
1980 +}
1981 +
1982 +static INLINE uint16
1983 +load16_ua(uint8 *a)
1984 +{
1985 + return ((a[0] << 8) | a[1]);
1986 +}
1987 +
1988 +static INLINE void
1989 +store16_ua(uint8 *a, uint16 v)
1990 +{
1991 + a[0] = (v >> 8) & 0xff;
1992 + a[1] = v & 0xff;
1993 +}
1994 +
1995 +#else
1996 +
1997 +static INLINE uint32
1998 +load32_ua(uint8 *a)
1999 +{
2000 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
2001 +}
2002 +
2003 +static INLINE void
2004 +store32_ua(uint8 *a, uint32 v)
2005 +{
2006 + a[3] = (v >> 24) & 0xff;
2007 + a[2] = (v >> 16) & 0xff;
2008 + a[1] = (v >> 8) & 0xff;
2009 + a[0] = v & 0xff;
2010 +}
2011 +
2012 +static INLINE uint16
2013 +load16_ua(uint8 *a)
2014 +{
2015 + return ((a[1] << 8) | a[0]);
2016 +}
2017 +
2018 +static INLINE void
2019 +store16_ua(uint8 *a, uint16 v)
2020 +{
2021 + a[1] = (v >> 8) & 0xff;
2022 + a[0] = v & 0xff;
2023 +}
2024 +
2025 +#endif
2026 +
2027 +/* externs */
2028 +/* crc */
2029 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
2030 +extern uint16 hndcrc16(uint8 *p, uint nbytes, uint16 crc);
2031 +extern uint32 hndcrc32(uint8 *p, uint nbytes, uint32 crc);
2032 +/* format/print */
2033 +/* IE parsing */
2034 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
2035 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
2036 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
2037 +
2038 +/* bcmerror*/
2039 +extern const char *bcmerrorstr(int bcmerror);
2040 +
2041 +/* multi-bool data type: set of bools, mbool is true if any is set */
2042 +typedef uint32 mbool;
2043 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
2044 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
2045 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
2046 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
2047 +
2048 +/* power conversion */
2049 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
2050 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
2051 +
2052 +/* generic datastruct to help dump routines */
2053 +struct fielddesc {
2054 + char *nameandfmt;
2055 + uint32 offset;
2056 + uint32 len;
2057 +};
2058 +
2059 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
2060 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
2061 +
2062 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
2063 +
2064 +#endif /* _bcmutils_h_ */
2065 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
2066 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
2067 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-11-07 21:57:07.849586000 +0100
2068 @@ -0,0 +1,85 @@
2069 +/*
2070 + * bit manipulation utility functions
2071 + *
2072 + * Copyright 2005, Broadcom Corporation
2073 + * All Rights Reserved.
2074 + *
2075 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2076 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2077 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2078 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2079 + * $Id$
2080 + */
2081 +
2082 +#ifndef _BITFUNCS_H
2083 +#define _BITFUNCS_H
2084 +
2085 +#include <typedefs.h>
2086 +
2087 +/* local prototypes */
2088 +static INLINE uint32 find_msbit(uint32 x);
2089 +
2090 +
2091 +/*
2092 + * find_msbit: returns index of most significant set bit in x, with index
2093 + * range defined as 0-31. NOTE: returns zero if input is zero.
2094 + */
2095 +
2096 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
2097 +
2098 +/*
2099 + * Implementation for Pentium processors and gcc. Note that this
2100 + * instruction is actually very slow on some processors (e.g., family 5,
2101 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
2102 + * implementation instead.
2103 + */
2104 +static INLINE uint32 find_msbit(uint32 x)
2105 +{
2106 + uint msbit;
2107 + __asm__("bsrl %1,%0"
2108 + :"=r" (msbit)
2109 + :"r" (x));
2110 + return msbit;
2111 +}
2112 +
2113 +#else
2114 +
2115 +/*
2116 + * Generic Implementation
2117 + */
2118 +
2119 +#define DB_POW_MASK16 0xffff0000
2120 +#define DB_POW_MASK8 0x0000ff00
2121 +#define DB_POW_MASK4 0x000000f0
2122 +#define DB_POW_MASK2 0x0000000c
2123 +#define DB_POW_MASK1 0x00000002
2124 +
2125 +static INLINE uint32 find_msbit(uint32 x)
2126 +{
2127 + uint32 temp_x = x;
2128 + uint msbit = 0;
2129 + if (temp_x & DB_POW_MASK16) {
2130 + temp_x >>= 16;
2131 + msbit = 16;
2132 + }
2133 + if (temp_x & DB_POW_MASK8) {
2134 + temp_x >>= 8;
2135 + msbit += 8;
2136 + }
2137 + if (temp_x & DB_POW_MASK4) {
2138 + temp_x >>= 4;
2139 + msbit += 4;
2140 + }
2141 + if (temp_x & DB_POW_MASK2) {
2142 + temp_x >>= 2;
2143 + msbit += 2;
2144 + }
2145 + if (temp_x & DB_POW_MASK1) {
2146 + msbit += 1;
2147 + }
2148 + return(msbit);
2149 +}
2150 +
2151 +#endif
2152 +
2153 +#endif /* _BITFUNCS_H */
2154 diff -urN linux.old/arch/mips/bcm947xx/include/cfe_osl.h linux.dev/arch/mips/bcm947xx/include/cfe_osl.h
2155 --- linux.old/arch/mips/bcm947xx/include/cfe_osl.h 1970-01-01 01:00:00.000000000 +0100
2156 +++ linux.dev/arch/mips/bcm947xx/include/cfe_osl.h 2005-11-07 22:51:38.776726000 +0100
2157 @@ -0,0 +1,191 @@
2158 +/*
2159 + * CFE boot loader OS Abstraction Layer.
2160 + *
2161 + * Copyright 2005, Broadcom Corporation
2162 + * All Rights Reserved.
2163 + *
2164 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
2165 + * the contents of this file may not be disclosed to third parties, copied
2166 + * or duplicated in any form, in whole or in part, without the prior
2167 + * written permission of Broadcom Corporation.
2168 + *
2169 + * $Id$
2170 + */
2171 +
2172 +#ifndef _cfe_osl_h_
2173 +#define _cfe_osl_h_
2174 +
2175 +#include <lib_types.h>
2176 +#include <lib_string.h>
2177 +#include <lib_printf.h>
2178 +#include <lib_malloc.h>
2179 +#include <cpu_config.h>
2180 +#include <cfe_timer.h>
2181 +#include <cfe_iocb.h>
2182 +#include <cfe_devfuncs.h>
2183 +#include <addrspace.h>
2184 +
2185 +#include <typedefs.h>
2186 +
2187 +/* dump string */
2188 +extern int (*xprinthook)(const char *str);
2189 +#define puts(str) do { if (xprinthook) xprinthook(str); } while (0)
2190 +
2191 +/* assert and panic */
2192 +#define ASSERT(exp) do {} while (0)
2193 +
2194 +/* PCMCIA attribute space access macros */
2195 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2196 + bzero(buf, size)
2197 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2198 + do {} while (0)
2199 +
2200 +/* PCI configuration space access macros */
2201 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
2202 + (offset == 8 ? 0 : 0xffffffff)
2203 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
2204 + do {} while (0)
2205 +
2206 +/* PCI device bus # and slot # */
2207 +#define OSL_PCI_BUS(osh) (0)
2208 +#define OSL_PCI_SLOT(osh) (0)
2209 +
2210 +/* register access macros */
2211 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
2212 +#define rreg32(r) (*(volatile uint32*)(r))
2213 +#ifdef IL_BIGENDIAN
2214 +#define wreg16(r, v) (*(volatile uint16*)((ulong)(r)^2) = (uint16)(v))
2215 +#define rreg16(r) (*(volatile uint16*)((ulong)(r)^2))
2216 +#define wreg8(r, v) (*(volatile uint8*)((ulong)(r)^3) = (uint8)(v))
2217 +#define rreg8(r) (*(volatile uint8*)((ulong)(r)^3))
2218 +#else
2219 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
2220 +#define rreg16(r) (*(volatile uint16*)(r))
2221 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
2222 +#define rreg8(r) (*(volatile uint8*)(r))
2223 +#endif
2224 +#define R_REG(r) ({ \
2225 + __typeof(*(r)) __osl_v; \
2226 + switch (sizeof(*(r))) { \
2227 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
2228 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
2229 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
2230 + } \
2231 + __osl_v; \
2232 +})
2233 +#define W_REG(r, v) do { \
2234 + switch (sizeof(*(r))) { \
2235 + case sizeof(uint8): wreg8((r), (v)); break; \
2236 + case sizeof(uint16): wreg16((r), (v)); break; \
2237 + case sizeof(uint32): wreg32((r), (v)); break; \
2238 + } \
2239 +} while (0)
2240 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
2241 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
2242 +
2243 +/* bcopy, bcmp, and bzero */
2244 +#define bcmp(b1, b2, len) lib_memcmp((b1), (b2), (len))
2245 +
2246 +#define osl_attach(pdev) ((osl_t*)pdev)
2247 +#define osl_detach(osh)
2248 +
2249 +/* general purpose memory allocation */
2250 +#define MALLOC(osh, size) KMALLOC((size),0)
2251 +#define MFREE(osh, addr, size) KFREE((addr))
2252 +#define MALLOCED(osh) (0)
2253 +#define MALLOC_DUMP(osh, buf, sz)
2254 +#define MALLOC_FAILED(osh) (0)
2255 +
2256 +/* uncached virtual address */
2257 +#define OSL_UNCACHED(va) ((void*)UNCADDR((ulong)(va)))
2258 +
2259 +/* host/bus architecture-specific address byte swap */
2260 +#define BUS_SWAP32(v) (v)
2261 +
2262 +/* get processor cycle count */
2263 +#define OSL_GETCYCLES(x) ((x) = 0)
2264 +
2265 +/* microsecond delay */
2266 +#define OSL_DELAY(usec) cfe_usleep((cfe_cpu_speed/CPUCFG_CYCLESPERCPUTICK/1000000*(usec)))
2267 +
2268 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
2269 +
2270 +/* map/unmap physical to virtual I/O */
2271 +#define REG_MAP(pa, size) ((void*)UNCADDR((ulong)(pa)))
2272 +#define REG_UNMAP(va) do {} while (0)
2273 +
2274 +/* dereference an address that may cause a bus exception */
2275 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (uint32)(addr))
2276 +extern int osl_busprobe(uint32 *val, uint32 addr);
2277 +
2278 +/* allocate/free shared (dma-able) consistent (uncached) memory */
2279 +#define DMA_CONSISTENT_ALIGN 4096
2280 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2281 + osl_dma_alloc_consistent((size), (pap))
2282 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2283 + osl_dma_free_consistent((void*)(va))
2284 +extern void *osl_dma_alloc_consistent(uint size, ulong *pap);
2285 +extern void osl_dma_free_consistent(void *va);
2286 +
2287 +/* map/unmap direction */
2288 +#define DMA_TX 1
2289 +#define DMA_RX 2
2290 +
2291 +/* map/unmap shared (dma-able) memory */
2292 +#define DMA_MAP(osh, va, size, direction, lb) ({ \
2293 + cfe_flushcache(CFE_CACHE_FLUSH_D); \
2294 + PHYSADDR((ulong)(va)); \
2295 +})
2296 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2297 + do {} while (0)
2298 +
2299 +/* shared (dma-able) memory access macros */
2300 +#define R_SM(r) *(r)
2301 +#define W_SM(r, v) (*(r) = (v))
2302 +#define BZERO_SM(r, len) lib_memset((r), '\0', (len))
2303 +
2304 +/* generic packet structure */
2305 +#define LBUFSZ 4096
2306 +#define LBDATASZ (LBUFSZ - sizeof(struct lbuf))
2307 +struct lbuf {
2308 + struct lbuf *next; /* pointer to next lbuf if in a chain */
2309 + struct lbuf *link; /* pointer to next lbuf if in a list */
2310 + uchar *head; /* start of buffer */
2311 + uchar *end; /* end of buffer */
2312 + uchar *data; /* start of data */
2313 + uchar *tail; /* end of data */
2314 + uint len; /* nbytes of data */
2315 + void *cookie; /* generic cookie */
2316 +};
2317 +
2318 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
2319 +#define PKTBUFSZ 2048
2320 +
2321 +/* packet primitives */
2322 +#define PKTGET(osh, len, send) ((void*)osl_pktget((len)))
2323 +#define PKTFREE(osh, lb, send) osl_pktfree((struct lbuf*)(lb))
2324 +#define PKTDATA(osh, lb) (((struct lbuf*)(lb))->data)
2325 +#define PKTLEN(osh, lb) (((struct lbuf*)(lb))->len)
2326 +#define PKTHEADROOM(osh, lb) (PKTDATA(osh,lb)-(((struct lbuf*)(lb))->head))
2327 +#define PKTTAILROOM(osh, lb) ((((struct lbuf*)(lb))->end)-(((struct lbuf*)(lb))->tail))
2328 +#define PKTNEXT(osh, lb) (((struct lbuf*)(lb))->next)
2329 +#define PKTSETNEXT(lb, x) (((struct lbuf*)(lb))->next = (struct lbuf*)(x))
2330 +#define PKTSETLEN(osh, lb, len) osl_pktsetlen((struct lbuf*)(lb), (len))
2331 +#define PKTPUSH(osh, lb, bytes) osl_pktpush((struct lbuf*)(lb), (bytes))
2332 +#define PKTPULL(osh, lb, bytes) osl_pktpull((struct lbuf*)(lb), (bytes))
2333 +#define PKTDUP(osh, lb) osl_pktdup((struct lbuf*)(lb))
2334 +#define PKTCOOKIE(lb) (((struct lbuf*)(lb))->cookie)
2335 +#define PKTSETCOOKIE(lb, x) (((struct lbuf*)(lb))->cookie = (void*)(x))
2336 +#define PKTLINK(lb) (((struct lbuf*)(lb))->link)
2337 +#define PKTSETLINK(lb, x) (((struct lbuf*)(lb))->link = (struct lbuf*)(x))
2338 +#define PKTPRIO(lb) (0)
2339 +#define PKTSETPRIO(lb, x) do {} while (0)
2340 +extern struct lbuf *osl_pktget(uint len);
2341 +extern void osl_pktfree(struct lbuf *lb);
2342 +extern void osl_pktsetlen(struct lbuf *lb, uint len);
2343 +extern uchar *osl_pktpush(struct lbuf *lb, uint bytes);
2344 +extern uchar *osl_pktpull(struct lbuf *lb, uint bytes);
2345 +extern struct lbuf *osl_pktdup(struct lbuf *lb);
2346 +extern int osl_error(int bcmerror);
2347 +
2348 +#endif /* _cfe_osl_h_ */
2349 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h linux.dev/arch/mips/bcm947xx/include/epivers.h
2350 --- linux.old/arch/mips/bcm947xx/include/epivers.h 1970-01-01 01:00:00.000000000 +0100
2351 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h 2005-11-07 22:51:38.776726000 +0100
2352 @@ -0,0 +1,69 @@
2353 +/*
2354 + * Copyright 2005, Broadcom Corporation
2355 + * All Rights Reserved.
2356 + *
2357 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2358 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2359 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2360 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2361 + *
2362 + * $Id$
2363 + *
2364 +*/
2365 +
2366 +#ifndef _epivers_h_
2367 +#define _epivers_h_
2368 +
2369 +#ifdef linux
2370 +#include <linux/config.h>
2371 +#endif
2372 +
2373 +/* Vendor Name, ASCII, 32 chars max */
2374 +#ifdef COMPANYNAME
2375 +#define HPNA_VENDOR COMPANYNAME
2376 +#else
2377 +#define HPNA_VENDOR "Broadcom Corporation"
2378 +#endif
2379 +
2380 +/* Driver Date, ASCII, 32 chars max */
2381 +#define HPNA_DRV_BUILD_DATE __DATE__
2382 +
2383 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2384 +#define HPNA_HW_MFG_DATE "Not Specified"
2385 +
2386 +/* See documentation for Device Type values, 32 values max */
2387 +#ifndef HPNA_DEV_TYPE
2388 +
2389 +#if defined(CONFIG_BRCM_VJ)
2390 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2391 +
2392 +#elif defined(CONFIG_BCRM_93725)
2393 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2394 +
2395 +#else
2396 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2397 +
2398 +#endif
2399 +
2400 +#endif /* !HPNA_DEV_TYPE */
2401 +
2402 +
2403 +#define EPI_MAJOR_VERSION 3
2404 +
2405 +#define EPI_MINOR_VERSION 130
2406 +
2407 +#define EPI_RC_NUMBER 20
2408 +
2409 +#define EPI_INCREMENTAL_NUMBER 0
2410 +
2411 +#define EPI_BUILD_NUMBER 0
2412 +
2413 +#define EPI_VERSION 3,130,20,0
2414 +
2415 +#define EPI_VERSION_NUM 0x03821400
2416 +
2417 +/* Driver Version String, ASCII, 32 chars max */
2418 +#define EPI_VERSION_STR "3.130.20.0"
2419 +#define EPI_ROUTER_VERSION_STR "3.131.20.0"
2420 +
2421 +#endif /* _epivers_h_ */
2422 diff -urN linux.old/arch/mips/bcm947xx/include/epivers.h.in linux.dev/arch/mips/bcm947xx/include/epivers.h.in
2423 --- linux.old/arch/mips/bcm947xx/include/epivers.h.in 1970-01-01 01:00:00.000000000 +0100
2424 +++ linux.dev/arch/mips/bcm947xx/include/epivers.h.in 2005-11-07 21:57:07.849586000 +0100
2425 @@ -0,0 +1,69 @@
2426 +/*
2427 + * Copyright 2005, Broadcom Corporation
2428 + * All Rights Reserved.
2429 + *
2430 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2431 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2432 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2433 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2434 + *
2435 + * $Id$
2436 + *
2437 +*/
2438 +
2439 +#ifndef _epivers_h_
2440 +#define _epivers_h_
2441 +
2442 +#ifdef linux
2443 +#include <linux/config.h>
2444 +#endif
2445 +
2446 +/* Vendor Name, ASCII, 32 chars max */
2447 +#ifdef COMPANYNAME
2448 +#define HPNA_VENDOR COMPANYNAME
2449 +#else
2450 +#define HPNA_VENDOR "Broadcom Corporation"
2451 +#endif
2452 +
2453 +/* Driver Date, ASCII, 32 chars max */
2454 +#define HPNA_DRV_BUILD_DATE __DATE__
2455 +
2456 +/* Hardware Manufacture Date, ASCII, 32 chars max */
2457 +#define HPNA_HW_MFG_DATE "Not Specified"
2458 +
2459 +/* See documentation for Device Type values, 32 values max */
2460 +#ifndef HPNA_DEV_TYPE
2461 +
2462 +#if defined(CONFIG_BRCM_VJ)
2463 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_DISPLAY }
2464 +
2465 +#elif defined(CONFIG_BCRM_93725)
2466 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_CM_BRIDGE, CDCF_V0_DEVICE_DISPLAY }
2467 +
2468 +#else
2469 +#define HPNA_DEV_TYPE { CDCF_V0_DEVICE_PCINIC }
2470 +
2471 +#endif
2472 +
2473 +#endif /* !HPNA_DEV_TYPE */
2474 +
2475 +
2476 +#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
2477 +
2478 +#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
2479 +
2480 +#define EPI_RC_NUMBER @EPI_RC_NUMBER@
2481 +
2482 +#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
2483 +
2484 +#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
2485 +
2486 +#define EPI_VERSION @EPI_VERSION@
2487 +
2488 +#define EPI_VERSION_NUM @EPI_VERSION_NUM@
2489 +
2490 +/* Driver Version String, ASCII, 32 chars max */
2491 +#define EPI_VERSION_STR "@EPI_VERSION_STR@"
2492 +#define EPI_ROUTER_VERSION_STR "@EPI_ROUTER_VERSION_STR@"
2493 +
2494 +#endif /* _epivers_h_ */
2495 diff -urN linux.old/arch/mips/bcm947xx/include/etsockio.h linux.dev/arch/mips/bcm947xx/include/etsockio.h
2496 --- linux.old/arch/mips/bcm947xx/include/etsockio.h 1970-01-01 01:00:00.000000000 +0100
2497 +++ linux.dev/arch/mips/bcm947xx/include/etsockio.h 2005-11-07 21:57:07.861586750 +0100
2498 @@ -0,0 +1,59 @@
2499 +/*
2500 + * Driver-specific socket ioctls
2501 + * used by BSD, Linux, and PSOS
2502 + * Broadcom BCM44XX 10/100Mbps Ethernet Device Driver
2503 + *
2504 + * Copyright 2005, Broadcom Corporation
2505 + * All Rights Reserved.
2506 + *
2507 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2508 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2509 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2510 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2511 + *
2512 + * $Id$
2513 + */
2514 +
2515 +#ifndef _etsockio_h_
2516 +#define _etsockio_h_
2517 +
2518 +/* THESE MUST BE CONTIGUOUS AND CONSISTENT WITH VALUES IN ETC.H */
2519 +
2520 +
2521 +#if defined(linux)
2522 +#define SIOCSETCUP (SIOCDEVPRIVATE + 0)
2523 +#define SIOCSETCDOWN (SIOCDEVPRIVATE + 1)
2524 +#define SIOCSETCLOOP (SIOCDEVPRIVATE + 2)
2525 +#define SIOCGETCDUMP (SIOCDEVPRIVATE + 3)
2526 +#define SIOCSETCSETMSGLEVEL (SIOCDEVPRIVATE + 4)
2527 +#define SIOCSETCPROMISC (SIOCDEVPRIVATE + 5)
2528 +#define SIOCSETCTXDOWN (SIOCDEVPRIVATE + 6) /* obsolete */
2529 +#define SIOCSETCSPEED (SIOCDEVPRIVATE + 7)
2530 +#define SIOCTXGEN (SIOCDEVPRIVATE + 8)
2531 +#define SIOCGETCPHYRD (SIOCDEVPRIVATE + 9)
2532 +#define SIOCSETCPHYWR (SIOCDEVPRIVATE + 10)
2533 +#define SIOCSETCQOS (SIOCDEVPRIVATE + 11)
2534 +
2535 +#else /* !linux */
2536 +
2537 +#define SIOCSETCUP _IOWR('e', 130 + 0, struct ifreq)
2538 +#define SIOCSETCDOWN _IOWR('e', 130 + 1, struct ifreq)
2539 +#define SIOCSETCLOOP _IOWR('e', 130 + 2, struct ifreq)
2540 +#define SIOCGETCDUMP _IOWR('e', 130 + 3, struct ifreq)
2541 +#define SIOCSETCSETMSGLEVEL _IOWR('e', 130 + 4, struct ifreq)
2542 +#define SIOCSETCPROMISC _IOWR('e', 130 + 5, struct ifreq)
2543 +#define SIOCSETCTXDOWN _IOWR('e', 130 + 6, struct ifreq) /* obsolete */
2544 +#define SIOCSETCSPEED _IOWR('e', 130 + 7, struct ifreq)
2545 +#define SIOCTXGEN _IOWR('e', 130 + 8, struct ifreq)
2546 +
2547 +#endif
2548 +
2549 +/* arg to SIOCTXGEN */
2550 +struct txg {
2551 + uint32 num; /* number of frames to send */
2552 + uint32 delay; /* delay in microseconds between sending each */
2553 + uint32 size; /* size of ether frame to send */
2554 + uchar buf[1514]; /* starting ether frame data */
2555 +};
2556 +
2557 +#endif
2558 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
2559 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
2560 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-11-07 21:57:07.861586750 +0100
2561 @@ -0,0 +1,188 @@
2562 +/*
2563 + * flash.h: Common definitions for flash access.
2564 + *
2565 + * Copyright 2005, Broadcom Corporation
2566 + * All Rights Reserved.
2567 + *
2568 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2569 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2570 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2571 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2572 + *
2573 + * $Id$
2574 + */
2575 +
2576 +/* Types of flashes we know about */
2577 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
2578 +
2579 +/* Commands to write/erase the flases */
2580 +typedef struct _flash_cmds{
2581 + flash_type_t type;
2582 + bool need_unlock;
2583 + uint16 pre_erase;
2584 + uint16 erase_block;
2585 + uint16 erase_chip;
2586 + uint16 write_word;
2587 + uint16 write_buf;
2588 + uint16 clear_csr;
2589 + uint16 read_csr;
2590 + uint16 read_id;
2591 + uint16 confirm;
2592 + uint16 read_array;
2593 +} flash_cmds_t;
2594 +
2595 +#define UNLOCK_CMD_WORDS 2
2596 +
2597 +typedef struct _unlock_cmd {
2598 + uint addr[UNLOCK_CMD_WORDS];
2599 + uint16 cmd[UNLOCK_CMD_WORDS];
2600 +} unlock_cmd_t;
2601 +
2602 +/* Flash descriptors */
2603 +typedef struct _flash_desc {
2604 + uint16 mfgid; /* Manufacturer Id */
2605 + uint16 devid; /* Device Id */
2606 + uint size; /* Total size in bytes */
2607 + uint width; /* Device width in bytes */
2608 + flash_type_t type; /* Device type old, S, J */
2609 + uint bsize; /* Block size */
2610 + uint nb; /* Number of blocks */
2611 + uint ff; /* First full block */
2612 + uint lf; /* Last full block */
2613 + uint nsub; /* Number of subblocks */
2614 + uint *subblocks; /* Offsets for subblocks */
2615 + char *desc; /* Description */
2616 +} flash_desc_t;
2617 +
2618 +
2619 +#ifdef DECLARE_FLASHES
2620 +flash_cmds_t sflash_cmd_t =
2621 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
2622 +
2623 +flash_cmds_t flash_cmds[] = {
2624 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
2625 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
2626 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
2627 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2628 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
2629 + { 0 }
2630 +};
2631 +
2632 +unlock_cmd_t unlock_cmd_amd = {
2633 +#ifdef MIPSEB
2634 +/* addr: */ { 0x0aa8, 0x0556},
2635 +#else
2636 +/* addr: */ { 0x0aaa, 0x0554},
2637 +#endif
2638 +/* data: */ { 0xaa, 0x55}
2639 +};
2640 +
2641 +unlock_cmd_t unlock_cmd_sst = {
2642 +#ifdef MIPSEB
2643 +/* addr: */ { 0xaaa8, 0x5556},
2644 +#else
2645 +/* addr: */ { 0xaaaa, 0x5554},
2646 +#endif
2647 +/* data: */ { 0xaa, 0x55}
2648 +};
2649 +
2650 +#define AMD_CMD 0xaaa
2651 +#define SST_CMD 0xaaaa
2652 +
2653 +/* intel unlock block cmds */
2654 +#define INTEL_UNLOCK1 0x60
2655 +#define INTEL_UNLOCK2 0xD0
2656 +
2657 +/* Just eight blocks of 8KB byte each */
2658 +
2659 +uint blk8x8k[] = { 0x00000000,
2660 + 0x00002000,
2661 + 0x00004000,
2662 + 0x00006000,
2663 + 0x00008000,
2664 + 0x0000a000,
2665 + 0x0000c000,
2666 + 0x0000e000,
2667 + 0x00010000
2668 +};
2669 +
2670 +/* Funky AMD arrangement for 29xx800's */
2671 +uint amd800[] = { 0x00000000, /* 16KB */
2672 + 0x00004000, /* 32KB */
2673 + 0x0000c000, /* 8KB */
2674 + 0x0000e000, /* 8KB */
2675 + 0x00010000, /* 8KB */
2676 + 0x00012000, /* 8KB */
2677 + 0x00014000, /* 32KB */
2678 + 0x0001c000, /* 16KB */
2679 + 0x00020000
2680 +};
2681 +
2682 +/* AMD arrangement for 29xx160's */
2683 +uint amd4112[] = { 0x00000000, /* 32KB */
2684 + 0x00008000, /* 8KB */
2685 + 0x0000a000, /* 8KB */
2686 + 0x0000c000, /* 16KB */
2687 + 0x00010000
2688 +};
2689 +uint amd2114[] = { 0x00000000, /* 16KB */
2690 + 0x00004000, /* 8KB */
2691 + 0x00006000, /* 8KB */
2692 + 0x00008000, /* 32KB */
2693 + 0x00010000
2694 +};
2695 +
2696 +
2697 +flash_desc_t sflash_desc =
2698 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
2699 +
2700 +flash_desc_t flashes[] = {
2701 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
2702 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
2703 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
2704 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
2705 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
2706 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
2707 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
2708 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
2709 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
2710 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
2711 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
2712 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
2713 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
2714 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
2715 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
2716 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
2717 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
2718 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
2719 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
2720 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
2721 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
2722 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
2723 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
2724 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
2725 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
2726 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
2727 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
2728 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
2729 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
2730 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
2731 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2732 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2733 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
2734 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
2735 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
2736 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
2737 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
2738 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
2739 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
2740 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
2741 +};
2742 +
2743 +#else
2744 +
2745 +extern flash_cmds_t flash_cmds[];
2746 +extern unlock_cmd_t unlock_cmd;
2747 +extern flash_desc_t flashes[];
2748 +
2749 +#endif
2750 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
2751 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
2752 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-11-07 21:57:07.861586750 +0100
2753 @@ -0,0 +1,27 @@
2754 +/*
2755 + * BCM47XX FLASH driver interface
2756 + *
2757 + * Copyright 2005, Broadcom Corporation
2758 + * All Rights Reserved.
2759 + *
2760 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2761 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2762 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2763 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2764 + * $Id$
2765 + */
2766 +
2767 +#ifndef _flashutl_h_
2768 +#define _flashutl_h_
2769 +
2770 +
2771 +#ifndef _LANGUAGE_ASSEMBLY
2772 +
2773 +int sysFlashInit(char *flash_str);
2774 +int sysFlashRead(uint off, uchar *dst, uint bytes);
2775 +int sysFlashWrite(uint off, uchar *src, uint bytes);
2776 +void nvWrite(unsigned short *data, unsigned int len);
2777 +
2778 +#endif /* _LANGUAGE_ASSEMBLY */
2779 +
2780 +#endif /* _flashutl_h_ */
2781 diff -urN linux.old/arch/mips/bcm947xx/include/hnddma.h linux.dev/arch/mips/bcm947xx/include/hnddma.h
2782 --- linux.old/arch/mips/bcm947xx/include/hnddma.h 1970-01-01 01:00:00.000000000 +0100
2783 +++ linux.dev/arch/mips/bcm947xx/include/hnddma.h 2005-11-07 22:51:38.776726000 +0100
2784 @@ -0,0 +1,71 @@
2785 +/*
2786 + * Generic Broadcom Home Networking Division (HND) DMA engine SW interface
2787 + * This supports the following chips: BCM42xx, 44xx, 47xx .
2788 + *
2789 + * Copyright 2005, Broadcom Corporation
2790 + * All Rights Reserved.
2791 + *
2792 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2793 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2794 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2795 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2796 + * $Id$
2797 + */
2798 +
2799 +#ifndef _hnddma_h_
2800 +#define _hnddma_h_
2801 +
2802 +/* export structure */
2803 +typedef volatile struct {
2804 + /* rx error counters */
2805 + uint rxgiants; /* rx giant frames */
2806 + uint rxnobuf; /* rx out of dma descriptors */
2807 + /* tx error counters */
2808 + uint txnobuf; /* tx out of dma descriptors */
2809 +} hnddma_t;
2810 +
2811 +#ifndef di_t
2812 +#define di_t void
2813 +#endif
2814 +
2815 +#ifndef osl_t
2816 +#define osl_t void
2817 +#endif
2818 +
2819 +/* externs */
2820 +extern void * dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
2821 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level);
2822 +extern void dma_detach(di_t *di);
2823 +extern void dma_txreset(di_t *di);
2824 +extern void dma_rxreset(di_t *di);
2825 +extern void dma_txinit(di_t *di);
2826 +extern bool dma_txenabled(di_t *di);
2827 +extern void dma_rxinit(di_t *di);
2828 +extern void dma_rxenable(di_t *di);
2829 +extern bool dma_rxenabled(di_t *di);
2830 +extern void dma_txsuspend(di_t *di);
2831 +extern void dma_txresume(di_t *di);
2832 +extern bool dma_txsuspended(di_t *di);
2833 +extern bool dma_txsuspendedidle(di_t *di);
2834 +extern bool dma_txstopped(di_t *di);
2835 +extern bool dma_rxstopped(di_t *di);
2836 +extern int dma_txfast(di_t *di, void *p, uint32 coreflags);
2837 +extern void dma_fifoloopbackenable(di_t *di);
2838 +extern void *dma_rx(di_t *di);
2839 +extern void dma_rxfill(di_t *di);
2840 +extern void dma_txreclaim(di_t *di, bool forceall);
2841 +extern void dma_rxreclaim(di_t *di);
2842 +extern uintptr dma_getvar(di_t *di, char *name);
2843 +extern void *dma_getnexttxp(di_t *di, bool forceall);
2844 +extern void *dma_peeknexttxp(di_t *di);
2845 +extern void *dma_getnextrxp(di_t *di, bool forceall);
2846 +extern void dma_txblock(di_t *di);
2847 +extern void dma_txunblock(di_t *di);
2848 +extern uint dma_txactive(di_t *di);
2849 +extern void dma_txrotate(di_t *di);
2850 +
2851 +extern void dma_rxpiomode(dma32regs_t *);
2852 +extern void dma_txpioloopback(dma32regs_t *);
2853 +
2854 +
2855 +#endif /* _hnddma_h_ */
2856 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
2857 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
2858 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-11-07 21:57:07.861586750 +0100
2859 @@ -0,0 +1,16 @@
2860 +/*
2861 + * Alternate include file for HND sbmips.h since CFE also ships with
2862 + * a sbmips.h.
2863 + *
2864 + * Copyright 2005, Broadcom Corporation
2865 + * All Rights Reserved.
2866 + *
2867 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2868 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2869 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2870 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2871 + *
2872 + * $Id$
2873 + */
2874 +
2875 +#include "sbmips.h"
2876 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
2877 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
2878 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-11-07 22:51:38.776726000 +0100
2879 @@ -0,0 +1,371 @@
2880 +/*
2881 + * Linux OS Independent Layer
2882 + *
2883 + * Copyright 2005, Broadcom Corporation
2884 + * All Rights Reserved.
2885 + *
2886 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2887 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2888 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2889 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2890 + *
2891 + * $Id$
2892 + */
2893 +
2894 +#ifndef _linux_osl_h_
2895 +#define _linux_osl_h_
2896 +
2897 +#include <typedefs.h>
2898 +
2899 +/* use current 2.4.x calling conventions */
2900 +#include <linuxver.h>
2901 +
2902 +/* assert and panic */
2903 +#ifdef __GNUC__
2904 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
2905 +#if GCC_VERSION > 30100
2906 +#define ASSERT(exp) do {} while (0)
2907 +#else
2908 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
2909 +#define ASSERT(exp)
2910 +#endif
2911 +#endif
2912 +
2913 +/* microsecond delay */
2914 +#define OSL_DELAY(usec) osl_delay(usec)
2915 +extern void osl_delay(uint usec);
2916 +
2917 +/* PCMCIA attribute space access macros */
2918 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
2919 +struct pcmcia_dev {
2920 + dev_link_t link; /* PCMCIA device pointer */
2921 + dev_node_t node; /* PCMCIA node structure */
2922 + void *base; /* Mapped attribute memory window */
2923 + size_t size; /* Size of window */
2924 + void *drv; /* Driver data */
2925 +};
2926 +#endif
2927 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
2928 + osl_pcmcia_read_attr((osh), (offset), (buf), (size))
2929 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
2930 + osl_pcmcia_write_attr((osh), (offset), (buf), (size))
2931 +extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
2932 +extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
2933 +
2934 +/* PCI configuration space access macros */
2935 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
2936 + osl_pci_read_config((osh), (offset), (size))
2937 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
2938 + osl_pci_write_config((osh), (offset), (size), (val))
2939 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
2940 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
2941 +
2942 +/* PCI device bus # and slot # */
2943 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
2944 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
2945 +extern uint osl_pci_bus(osl_t *osh);
2946 +extern uint osl_pci_slot(osl_t *osh);
2947 +
2948 +/* OSL initialization */
2949 +extern osl_t *osl_attach(void *pdev);
2950 +extern void osl_detach(osl_t *osh);
2951 +
2952 +/* host/bus architecture-specific byte swap */
2953 +#define BUS_SWAP32(v) (v)
2954 +
2955 +/* general purpose memory allocation */
2956 +
2957 +#if defined(BCMDBG_MEM)
2958 +
2959 +#define MALLOC(osh, size) osl_debug_malloc((osh), (size), __LINE__, __FILE__)
2960 +#define MFREE(osh, addr, size) osl_debug_mfree((osh), (addr), (size), __LINE__, __FILE__)
2961 +#define MALLOCED(osh) osl_malloced((osh))
2962 +#define MALLOC_DUMP(osh, buf, sz) osl_debug_memdump((osh), (buf), (sz))
2963 +extern void *osl_debug_malloc(osl_t *osh, uint size, int line, char* file);
2964 +extern void osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file);
2965 +extern char *osl_debug_memdump(osl_t *osh, char *buf, uint sz);
2966 +
2967 +#else
2968 +
2969 +#define MALLOC(osh, size) osl_malloc((osh), (size))
2970 +#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
2971 +#define MALLOCED(osh) osl_malloced((osh))
2972 +
2973 +#endif /* BCMDBG_MEM */
2974 +
2975 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
2976 +
2977 +extern void *osl_malloc(osl_t *osh, uint size);
2978 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
2979 +extern uint osl_malloced(osl_t *osh);
2980 +extern uint osl_malloc_failed(osl_t *osh);
2981 +
2982 +/* allocate/free shared (dma-able) consistent memory */
2983 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
2984 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
2985 + osl_dma_alloc_consistent((osh), (size), (pap))
2986 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
2987 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
2988 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
2989 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
2990 +
2991 +/* map/unmap direction */
2992 +#define DMA_TX 1
2993 +#define DMA_RX 2
2994 +
2995 +/* map/unmap shared (dma-able) memory */
2996 +#define DMA_MAP(osh, va, size, direction, p) \
2997 + osl_dma_map((osh), (va), (size), (direction))
2998 +#define DMA_UNMAP(osh, pa, size, direction, p) \
2999 + osl_dma_unmap((osh), (pa), (size), (direction))
3000 +extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction);
3001 +extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
3002 +
3003 +/* register access macros */
3004 +#if defined(BCMJTAG)
3005 +#include <bcmjtag.h>
3006 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
3007 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
3008 +#endif
3009 +
3010 +/*
3011 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
3012 + * Macros expand to calls to functions defined in linux_osl.c .
3013 + */
3014 +#ifndef BINOSL
3015 +
3016 +/* string library, kernel mode */
3017 +#define printf(fmt, args...) printk(fmt, ## args)
3018 +#include <linux/kernel.h>
3019 +#include <linux/string.h>
3020 +
3021 +/* register access macros */
3022 +#if !defined(BCMJTAG)
3023 +#ifndef IL_BIGENDIAN
3024 +#define R_REG(r) ( \
3025 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
3026 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
3027 + readl((volatile uint32*)(r)) \
3028 +)
3029 +#define W_REG(r, v) do { \
3030 + switch (sizeof(*(r))) { \
3031 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
3032 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
3033 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3034 + } \
3035 +} while (0)
3036 +#else /* IL_BIGENDIAN */
3037 +#define R_REG(r) ({ \
3038 + __typeof(*(r)) __osl_v; \
3039 + switch (sizeof(*(r))) { \
3040 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
3041 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
3042 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
3043 + } \
3044 + __osl_v; \
3045 +})
3046 +#define W_REG(r, v) do { \
3047 + switch (sizeof(*(r))) { \
3048 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
3049 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
3050 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
3051 + } \
3052 +} while (0)
3053 +#endif
3054 +#endif
3055 +
3056 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3057 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3058 +
3059 +/* bcopy, bcmp, and bzero */
3060 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3061 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3062 +#define bzero(b, len) memset((b), '\0', (len))
3063 +
3064 +/* uncached virtual address */
3065 +#ifdef mips
3066 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
3067 +#include <asm/addrspace.h>
3068 +#else
3069 +#define OSL_UNCACHED(va) (va)
3070 +#endif
3071 +
3072 +/* get processor cycle count */
3073 +#if defined(mips)
3074 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
3075 +#elif defined(__i386__)
3076 +#define OSL_GETCYCLES(x) rdtscl((x))
3077 +#else
3078 +#define OSL_GETCYCLES(x) ((x) = 0)
3079 +#endif
3080 +
3081 +/* dereference an address that may cause a bus exception */
3082 +#ifdef mips
3083 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
3084 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
3085 +#else
3086 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
3087 +#include <asm/paccess.h>
3088 +#endif
3089 +#else
3090 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
3091 +#endif
3092 +
3093 +/* map/unmap physical to virtual I/O */
3094 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
3095 +#define REG_UNMAP(va) iounmap((void *)(va))
3096 +
3097 +/* shared (dma-able) memory access macros */
3098 +#define R_SM(r) *(r)
3099 +#define W_SM(r, v) (*(r) = (v))
3100 +#define BZERO_SM(r, len) memset((r), '\0', (len))
3101 +
3102 +/* packet primitives */
3103 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3104 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3105 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
3106 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
3107 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
3108 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
3109 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
3110 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
3111 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
3112 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
3113 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
3114 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
3115 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
3116 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
3117 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
3118 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
3119 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
3120 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
3121 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3122 +extern void osl_pktfree(void *skb);
3123 +
3124 +#else /* BINOSL */
3125 +
3126 +/* string library */
3127 +#ifndef LINUX_OSL
3128 +#undef printf
3129 +#define printf(fmt, args...) osl_printf((fmt), ## args)
3130 +#undef sprintf
3131 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
3132 +#undef strcmp
3133 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
3134 +#undef strncmp
3135 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
3136 +#undef strlen
3137 +#define strlen(s) osl_strlen((s))
3138 +#undef strcpy
3139 +#define strcpy(d, s) osl_strcpy((d), (s))
3140 +#undef strncpy
3141 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
3142 +#endif
3143 +extern int osl_printf(const char *format, ...);
3144 +extern int osl_sprintf(char *buf, const char *format, ...);
3145 +extern int osl_strcmp(const char *s1, const char *s2);
3146 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
3147 +extern int osl_strlen(const char *s);
3148 +extern char* osl_strcpy(char *d, const char *s);
3149 +extern char* osl_strncpy(char *d, const char *s, uint n);
3150 +
3151 +/* register access macros */
3152 +#if !defined(BCMJTAG)
3153 +#define R_REG(r) ( \
3154 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
3155 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
3156 + osl_readl((volatile uint32*)(r)) \
3157 +)
3158 +#define W_REG(r, v) do { \
3159 + switch (sizeof(*(r))) { \
3160 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
3161 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
3162 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
3163 + } \
3164 +} while (0)
3165 +#endif
3166 +
3167 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3168 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3169 +extern uint8 osl_readb(volatile uint8 *r);
3170 +extern uint16 osl_readw(volatile uint16 *r);
3171 +extern uint32 osl_readl(volatile uint32 *r);
3172 +extern void osl_writeb(uint8 v, volatile uint8 *r);
3173 +extern void osl_writew(uint16 v, volatile uint16 *r);
3174 +extern void osl_writel(uint32 v, volatile uint32 *r);
3175 +
3176 +/* bcopy, bcmp, and bzero */
3177 +extern void bcopy(const void *src, void *dst, int len);
3178 +extern int bcmp(const void *b1, const void *b2, int len);
3179 +extern void bzero(void *b, int len);
3180 +
3181 +/* uncached virtual address */
3182 +#define OSL_UNCACHED(va) osl_uncached((va))
3183 +extern void *osl_uncached(void *va);
3184 +
3185 +/* get processor cycle count */
3186 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
3187 +extern uint osl_getcycles(void);
3188 +
3189 +/* dereference an address that may target abort */
3190 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
3191 +extern int osl_busprobe(uint32 *val, uint32 addr);
3192 +
3193 +/* map/unmap physical to virtual */
3194 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
3195 +#define REG_UNMAP(va) osl_reg_unmap((va))
3196 +extern void *osl_reg_map(uint32 pa, uint size);
3197 +extern void osl_reg_unmap(void *va);
3198 +
3199 +/* shared (dma-able) memory access macros */
3200 +#define R_SM(r) *(r)
3201 +#define W_SM(r, v) (*(r) = (v))
3202 +#define BZERO_SM(r, len) bzero((r), (len))
3203 +
3204 +/* packet primitives */
3205 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
3206 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
3207 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
3208 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
3209 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
3210 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
3211 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
3212 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
3213 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
3214 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
3215 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
3216 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
3217 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
3218 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
3219 +#define PKTLINK(skb) osl_pktlink((skb))
3220 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
3221 +#define PKTPRIO(skb) osl_pktprio((skb))
3222 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
3223 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
3224 +extern void osl_pktfree(void *skb);
3225 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
3226 +extern uint osl_pktlen(osl_t *osh, void *skb);
3227 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
3228 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
3229 +extern void *osl_pktnext(osl_t *osh, void *skb);
3230 +extern void osl_pktsetnext(void *skb, void *x);
3231 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
3232 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
3233 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
3234 +extern void *osl_pktdup(osl_t *osh, void *skb);
3235 +extern void *osl_pktcookie(void *skb);
3236 +extern void osl_pktsetcookie(void *skb, void *x);
3237 +extern void *osl_pktlink(void *skb);
3238 +extern void osl_pktsetlink(void *skb, void *x);
3239 +extern uint osl_pktprio(void *skb);
3240 +extern void osl_pktsetprio(void *skb, uint x);
3241 +
3242 +#endif /* BINOSL */
3243 +
3244 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3245 +extern int osl_error(int bcmerror);
3246 +
3247 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
3248 +#define PKTBUFSZ 2048
3249 +
3250 +#endif /* _linux_osl_h_ */
3251 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
3252 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
3253 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-11-07 22:51:38.780726250 +0100
3254 @@ -0,0 +1,411 @@
3255 +/*
3256 + * Linux-specific abstractions to gain some independence from linux kernel versions.
3257 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
3258 + *
3259 + * Copyright 2005, Broadcom Corporation
3260 + * All Rights Reserved.
3261 + *
3262 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3263 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3264 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3265 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3266 + *
3267 + * $Id$
3268 + */
3269 +
3270 +#ifndef _linuxver_h_
3271 +#define _linuxver_h_
3272 +
3273 +#include <linux/config.h>
3274 +#include <linux/version.h>
3275 +
3276 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
3277 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
3278 +#ifdef __UNDEF_NO_VERSION__
3279 +#undef __NO_VERSION__
3280 +#else
3281 +#define __NO_VERSION__
3282 +#endif
3283 +#endif
3284 +
3285 +#if defined(MODULE) && defined(MODVERSIONS)
3286 +#include <linux/modversions.h>
3287 +#endif
3288 +
3289 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
3290 +#include <linux/moduleparam.h>
3291 +#endif
3292 +
3293 +
3294 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
3295 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
3296 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
3297 +#endif
3298 +
3299 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
3300 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
3301 +#include <linux/malloc.h>
3302 +#else
3303 +#include <linux/slab.h>
3304 +#endif
3305 +
3306 +#include <linux/types.h>
3307 +#include <linux/init.h>
3308 +#include <linux/mm.h>
3309 +#include <linux/string.h>
3310 +#include <linux/pci.h>
3311 +#include <linux/interrupt.h>
3312 +#include <linux/netdevice.h>
3313 +#include <asm/io.h>
3314 +
3315 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
3316 +#include <linux/workqueue.h>
3317 +#else
3318 +#include <linux/tqueue.h>
3319 +#ifndef work_struct
3320 +#define work_struct tq_struct
3321 +#endif
3322 +#ifndef INIT_WORK
3323 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
3324 +#endif
3325 +#ifndef schedule_work
3326 +#define schedule_work(_work) schedule_task((_work))
3327 +#endif
3328 +#ifndef flush_scheduled_work
3329 +#define flush_scheduled_work() flush_scheduled_tasks()
3330 +#endif
3331 +#endif
3332 +
3333 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3334 +/* Some distributions have their own 2.6.x compatibility layers */
3335 +#ifndef IRQ_NONE
3336 +typedef void irqreturn_t;
3337 +#define IRQ_NONE
3338 +#define IRQ_HANDLED
3339 +#define IRQ_RETVAL(x)
3340 +#endif
3341 +#else
3342 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
3343 +#endif
3344 +
3345 +#if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
3346 +
3347 +#include <pcmcia/version.h>
3348 +#include <pcmcia/cs_types.h>
3349 +#include <pcmcia/cs.h>
3350 +#include <pcmcia/cistpl.h>
3351 +#include <pcmcia/cisreg.h>
3352 +#include <pcmcia/ds.h>
3353 +
3354 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,69))
3355 +/* In 2.5 (as of 2.5.69 at least) there is a cs_error exported which
3356 + * does this, but it's not in 2.4 so we do our own for now. */
3357 +static inline void
3358 +cs_error(client_handle_t handle, int func, int ret)
3359 +{
3360 + error_info_t err = { func, ret };
3361 + CardServices(ReportError, handle, &err);
3362 +}
3363 +#endif
3364 +
3365 +#endif /* CONFIG_PCMCIA */
3366 +
3367 +#ifndef __exit
3368 +#define __exit
3369 +#endif
3370 +#ifndef __devexit
3371 +#define __devexit
3372 +#endif
3373 +#ifndef __devinit
3374 +#define __devinit __init
3375 +#endif
3376 +#ifndef __devinitdata
3377 +#define __devinitdata
3378 +#endif
3379 +#ifndef __devexit_p
3380 +#define __devexit_p(x) x
3381 +#endif
3382 +
3383 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
3384 +
3385 +#define pci_get_drvdata(dev) (dev)->sysdata
3386 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
3387 +
3388 +/*
3389 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
3390 + */
3391 +
3392 +struct pci_device_id {
3393 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
3394 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
3395 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
3396 + unsigned long driver_data; /* Data private to the driver */
3397 +};
3398 +
3399 +struct pci_driver {
3400 + struct list_head node;
3401 + char *name;
3402 + const struct pci_device_id *id_table; /* NULL if wants all devices */
3403 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
3404 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
3405 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
3406 + void (*resume)(struct pci_dev *dev); /* Device woken up */
3407 +};
3408 +
3409 +#define MODULE_DEVICE_TABLE(type, name)
3410 +#define PCI_ANY_ID (~0)
3411 +
3412 +/* compatpci.c */
3413 +#define pci_module_init pci_register_driver
3414 +extern int pci_register_driver(struct pci_driver *drv);
3415 +extern void pci_unregister_driver(struct pci_driver *drv);
3416 +
3417 +#endif /* PCI registration */
3418 +
3419 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
3420 +#ifdef MODULE
3421 +#define module_init(x) int init_module(void) { return x(); }
3422 +#define module_exit(x) void cleanup_module(void) { x(); }
3423 +#else
3424 +#define module_init(x) __initcall(x);
3425 +#define module_exit(x) __exitcall(x);
3426 +#endif
3427 +#endif
3428 +
3429 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
3430 +#define list_for_each(pos, head) \
3431 + for (pos = (head)->next; pos != (head); pos = pos->next)
3432 +#endif
3433 +
3434 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
3435 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
3436 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
3437 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
3438 +#endif
3439 +
3440 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
3441 +#define pci_enable_device(dev) do { } while (0)
3442 +#endif
3443 +
3444 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
3445 +#define net_device device
3446 +#endif
3447 +
3448 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
3449 +
3450 +/*
3451 + * DMA mapping
3452 + *
3453 + * See linux/Documentation/DMA-mapping.txt
3454 + */
3455 +
3456 +#ifndef PCI_DMA_TODEVICE
3457 +#define PCI_DMA_TODEVICE 1
3458 +#define PCI_DMA_FROMDEVICE 2
3459 +#endif
3460 +
3461 +typedef u32 dma_addr_t;
3462 +
3463 +/* Pure 2^n version of get_order */
3464 +static inline int get_order(unsigned long size)
3465 +{
3466 + int order;
3467 +
3468 + size = (size-1) >> (PAGE_SHIFT-1);
3469 + order = -1;
3470 + do {
3471 + size >>= 1;
3472 + order++;
3473 + } while (size);
3474 + return order;
3475 +}
3476 +
3477 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
3478 + dma_addr_t *dma_handle)
3479 +{
3480 + void *ret;
3481 + int gfp = GFP_ATOMIC | GFP_DMA;
3482 +
3483 + ret = (void *)__get_free_pages(gfp, get_order(size));
3484 +
3485 + if (ret != NULL) {
3486 + memset(ret, 0, size);
3487 + *dma_handle = virt_to_bus(ret);
3488 + }
3489 + return ret;
3490 +}
3491 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
3492 + void *vaddr, dma_addr_t dma_handle)
3493 +{
3494 + free_pages((unsigned long)vaddr, get_order(size));
3495 +}
3496 +#ifdef ILSIM
3497 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
3498 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
3499 +#else
3500 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
3501 +#define pci_unmap_single(cookie, address, size, dir)
3502 +#endif
3503 +
3504 +#endif /* DMA mapping */
3505 +
3506 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
3507 +
3508 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
3509 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
3510 +
3511 +/* pcmcia-cs provides its own netdevice compatibility layer */
3512 +#ifndef _COMPAT_NETDEVICE_H
3513 +
3514 +/*
3515 + * SoftNet
3516 + *
3517 + * For pre-softnet kernels we need to tell the upper layer not to
3518 + * re-enter start_xmit() while we are in there. However softnet
3519 + * guarantees not to enter while we are in there so there is no need
3520 + * to do the netif_stop_queue() dance unless the transmit queue really
3521 + * gets stuck. This should also improve performance according to tests
3522 + * done by Aman Singla.
3523 + */
3524 +
3525 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
3526 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
3527 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
3528 +
3529 +static inline void netif_start_queue(struct net_device *dev)
3530 +{
3531 + dev->tbusy = 0;
3532 + dev->interrupt = 0;
3533 + dev->start = 1;
3534 +}
3535 +
3536 +#define netif_queue_stopped(dev) (dev)->tbusy
3537 +#define netif_running(dev) (dev)->start
3538 +
3539 +#endif /* _COMPAT_NETDEVICE_H */
3540 +
3541 +#define netif_device_attach(dev) netif_start_queue(dev)
3542 +#define netif_device_detach(dev) netif_stop_queue(dev)
3543 +
3544 +/* 2.4.x renamed bottom halves to tasklets */
3545 +#define tasklet_struct tq_struct
3546 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
3547 +{
3548 + queue_task(tasklet, &tq_immediate);
3549 + mark_bh(IMMEDIATE_BH);
3550 +}
3551 +
3552 +static inline void tasklet_init(struct tasklet_struct *tasklet,
3553 + void (*func)(unsigned long),
3554 + unsigned long data)
3555 +{
3556 + tasklet->next = NULL;
3557 + tasklet->sync = 0;
3558 + tasklet->routine = (void (*)(void *))func;
3559 + tasklet->data = (void *)data;
3560 +}
3561 +#define tasklet_kill(tasklet) {do{} while(0);}
3562 +
3563 +/* 2.4.x introduced del_timer_sync() */
3564 +#define del_timer_sync(timer) del_timer(timer)
3565 +
3566 +#else
3567 +
3568 +#define netif_down(dev)
3569 +
3570 +#endif /* SoftNet */
3571 +
3572 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
3573 +
3574 +/*
3575 + * Emit code to initialise a tq_struct's routine and data pointers
3576 + */
3577 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
3578 + do { \
3579 + (_tq)->routine = _routine; \
3580 + (_tq)->data = _data; \
3581 + } while (0)
3582 +
3583 +/*
3584 + * Emit code to initialise all of a tq_struct
3585 + */
3586 +#define INIT_TQUEUE(_tq, _routine, _data) \
3587 + do { \
3588 + INIT_LIST_HEAD(&(_tq)->list); \
3589 + (_tq)->sync = 0; \
3590 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
3591 + } while (0)
3592 +
3593 +#endif
3594 +
3595 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
3596 +
3597 +/* Power management related routines */
3598 +
3599 +static inline int
3600 +pci_save_state(struct pci_dev *dev, u32 *buffer)
3601 +{
3602 + int i;
3603 + if (buffer) {
3604 + for (i = 0; i < 16; i++)
3605 + pci_read_config_dword(dev, i * 4,&buffer[i]);
3606 + }
3607 + return 0;
3608 +}
3609 +
3610 +static inline int
3611 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
3612 +{
3613 + int i;
3614 +
3615 + if (buffer) {
3616 + for (i = 0; i < 16; i++)
3617 + pci_write_config_dword(dev,i * 4, buffer[i]);
3618 + }
3619 + /*
3620 + * otherwise, write the context information we know from bootup.
3621 + * This works around a problem where warm-booting from Windows
3622 + * combined with a D3(hot)->D0 transition causes PCI config
3623 + * header data to be forgotten.
3624 + */
3625 + else {
3626 + for (i = 0; i < 6; i ++)
3627 + pci_write_config_dword(dev,
3628 + PCI_BASE_ADDRESS_0 + (i * 4),
3629 + pci_resource_start(dev, i));
3630 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
3631 + }
3632 + return 0;
3633 +}
3634 +
3635 +#endif /* PCI power management */
3636 +
3637 +/* Old cp0 access macros deprecated in 2.4.19 */
3638 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
3639 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
3640 +#endif
3641 +
3642 +/* Module refcount handled internally in 2.6.x */
3643 +#ifndef SET_MODULE_OWNER
3644 +#define SET_MODULE_OWNER(dev) do {} while (0)
3645 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
3646 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
3647 +#else
3648 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
3649 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
3650 +#endif
3651 +
3652 +#ifndef SET_NETDEV_DEV
3653 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
3654 +#endif
3655 +
3656 +#ifndef HAVE_FREE_NETDEV
3657 +#define free_netdev(dev) kfree(dev)
3658 +#endif
3659 +
3660 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
3661 +/* struct packet_type redefined in 2.6.x */
3662 +#define af_packet_priv data
3663 +#endif
3664 +
3665 +#endif /* _linuxver_h_ */
3666 diff -urN linux.old/arch/mips/bcm947xx/include/min_osl.h linux.dev/arch/mips/bcm947xx/include/min_osl.h
3667 --- linux.old/arch/mips/bcm947xx/include/min_osl.h 1970-01-01 01:00:00.000000000 +0100
3668 +++ linux.dev/arch/mips/bcm947xx/include/min_osl.h 2005-11-07 22:51:38.780726250 +0100
3669 @@ -0,0 +1,126 @@
3670 +/*
3671 + * HND Minimal OS Abstraction Layer.
3672 + *
3673 + * Copyright 2005, Broadcom Corporation
3674 + * All Rights Reserved.
3675 + *
3676 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3677 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3678 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3679 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3680 + *
3681 + * $Id$
3682 + */
3683 +
3684 +#ifndef _min_osl_h_
3685 +#define _min_osl_h_
3686 +
3687 +#include <typedefs.h>
3688 +#include <sbconfig.h>
3689 +#include <mipsinc.h>
3690 +
3691 +/* Cache support */
3692 +extern void caches_on(void);
3693 +extern void blast_dcache(void);
3694 +extern void blast_icache(void);
3695 +
3696 +/* uart output */
3697 +extern void putc(int c);
3698 +
3699 +/* lib functions */
3700 +extern int printf(const char *fmt, ...);
3701 +extern int sprintf(char *buf, const char *fmt, ...);
3702 +extern int strcmp(const char *s1, const char *s2);
3703 +extern int strncmp(const char *s1, const char *s2, uint n);
3704 +extern char *strcpy(char *dest, const char *src);
3705 +extern char *strncpy(char *dest, const char *src, uint n);
3706 +extern uint strlen(const char *s);
3707 +extern char *strchr(const char *str,int c);
3708 +extern char *strrchr(const char *str, int c);
3709 +extern char *strcat(char *d, const char *s);
3710 +extern void *memset(void *dest, int c, uint n);
3711 +extern void *memcpy(void *dest, const void *src, uint n);
3712 +extern int memcmp(const void *s1, const void *s2, uint n);
3713 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
3714 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
3715 +#define bzero(b, len) memset((b), '\0', (len))
3716 +
3717 +/* assert & debugging */
3718 +#define ASSERT(exp) do {} while (0)
3719 +
3720 +/* PCMCIA attribute space access macros */
3721 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
3722 + ASSERT(0)
3723 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
3724 + ASSERT(0)
3725 +
3726 +/* PCI configuration space access macros */
3727 +#define OSL_PCI_READ_CONFIG(loc, offset, size) \
3728 + (offset == 8 ? 0 : 0xffffffff)
3729 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) \
3730 + do {} while (0)
3731 +
3732 +/* PCI device bus # and slot # */
3733 +#define OSL_PCI_BUS(osh) (0)
3734 +#define OSL_PCI_SLOT(osh) (0)
3735 +
3736 +/* register access macros */
3737 +#define wreg32(r, v) (*(volatile uint32*)(r) = (uint32)(v))
3738 +#define rreg32(r) (*(volatile uint32*)(r))
3739 +#define wreg16(r, v) (*(volatile uint16*)(r) = (uint16)(v))
3740 +#define rreg16(r) (*(volatile uint16*)(r))
3741 +#define wreg8(r, v) (*(volatile uint8*)(r) = (uint8)(v))
3742 +#define rreg8(r) (*(volatile uint8*)(r))
3743 +#define R_REG(r) ({ \
3744 + __typeof(*(r)) __osl_v; \
3745 + switch (sizeof(*(r))) { \
3746 + case sizeof(uint8): __osl_v = rreg8((r)); break; \
3747 + case sizeof(uint16): __osl_v = rreg16((r)); break; \
3748 + case sizeof(uint32): __osl_v = rreg32((r)); break; \
3749 + } \
3750 + __osl_v; \
3751 +})
3752 +#define W_REG(r, v) do { \
3753 + switch (sizeof(*(r))) { \
3754 + case sizeof(uint8): wreg8((r), (v)); break; \
3755 + case sizeof(uint16): wreg16((r), (v)); break; \
3756 + case sizeof(uint32): wreg32((r), (v)); break; \
3757 + } \
3758 +} while (0)
3759 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
3760 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
3761 +
3762 +/* general purpose memory allocation */
3763 +#define MALLOC(osh, size) malloc(size)
3764 +#define MFREE(osh, addr, size) free(addr)
3765 +#define MALLOCED(osh) 0
3766 +#define MALLOC_FAILED(osh) 0
3767 +#define MALLOC_DUMP(osh, buf, sz)
3768 +extern int free(void *ptr);
3769 +extern void *malloc(uint size);
3770 +
3771 +/* uncached virtual address */
3772 +#define OSL_UNCACHED(va) ((void*)KSEG1ADDR((ulong)(va)))
3773 +
3774 +/* host/bus architecture-specific address byte swap */
3775 +#define BUS_SWAP32(v) (v)
3776 +
3777 +/* microsecond delay */
3778 +#define OSL_DELAY(usec) udelay(usec)
3779 +extern void udelay(uint32 usec);
3780 +
3781 +/* map/unmap physical to virtual I/O */
3782 +#define REG_MAP(pa, size) ((void*)KSEG1ADDR((ulong)(pa)))
3783 +#define REG_UNMAP(va) do {} while (0)
3784 +
3785 +/* dereference an address that may cause a bus exception */
3786 +#define BUSPROBE(val, addr) (uint32 *)(addr) = (val)
3787 +
3788 +/* Misc stubs */
3789 +#define osl_attach(pdev) ((osl_t*)pdev)
3790 +#define osl_detach(osh)
3791 +extern void *osl_init(void);
3792 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
3793 +extern int osl_error(int);
3794 +
3795 +#endif /* _min_osl_h_ */
3796 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
3797 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
3798 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-11-07 22:51:38.780726250 +0100
3799 @@ -0,0 +1,552 @@
3800 +/*
3801 + * HND Run Time Environment for standalone MIPS programs.
3802 + *
3803 + * Copyright 2005, Broadcom Corporation
3804 + * All Rights Reserved.
3805 + *
3806 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3807 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3808 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3809 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3810 + *
3811 + * $Id$
3812 + */
3813 +
3814 +#ifndef _MISPINC_H
3815 +#define _MISPINC_H
3816 +
3817 +
3818 +/* MIPS defines */
3819 +
3820 +#ifdef _LANGUAGE_ASSEMBLY
3821 +
3822 +/*
3823 + * Symbolic register names for 32 bit ABI
3824 + */
3825 +#define zero $0 /* wired zero */
3826 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
3827 +#define v0 $2 /* return value */
3828 +#define v1 $3
3829 +#define a0 $4 /* argument registers */
3830 +#define a1 $5
3831 +#define a2 $6
3832 +#define a3 $7
3833 +#define t0 $8 /* caller saved */
3834 +#define t1 $9
3835 +#define t2 $10
3836 +#define t3 $11
3837 +#define t4 $12
3838 +#define t5 $13
3839 +#define t6 $14
3840 +#define t7 $15
3841 +#define s0 $16 /* callee saved */
3842 +#define s1 $17
3843 +#define s2 $18
3844 +#define s3 $19
3845 +#define s4 $20
3846 +#define s5 $21
3847 +#define s6 $22
3848 +#define s7 $23
3849 +#define t8 $24 /* caller saved */
3850 +#define t9 $25
3851 +#define jp $25 /* PIC jump register */
3852 +#define k0 $26 /* kernel scratch */
3853 +#define k1 $27
3854 +#define gp $28 /* global pointer */
3855 +#define sp $29 /* stack pointer */
3856 +#define fp $30 /* frame pointer */
3857 +#define s8 $30 /* same like fp! */
3858 +#define ra $31 /* return address */
3859 +
3860 +
3861 +/*
3862 + * CP0 Registers
3863 + */
3864 +
3865 +#define C0_INX $0
3866 +#define C0_RAND $1
3867 +#define C0_TLBLO0 $2
3868 +#define C0_TLBLO C0_TLBLO0
3869 +#define C0_TLBLO1 $3
3870 +#define C0_CTEXT $4
3871 +#define C0_PGMASK $5
3872 +#define C0_WIRED $6
3873 +#define C0_BADVADDR $8
3874 +#define C0_COUNT $9
3875 +#define C0_TLBHI $10
3876 +#define C0_COMPARE $11
3877 +#define C0_SR $12
3878 +#define C0_STATUS C0_SR
3879 +#define C0_CAUSE $13
3880 +#define C0_EPC $14
3881 +#define C0_PRID $15
3882 +#define C0_CONFIG $16
3883 +#define C0_LLADDR $17
3884 +#define C0_WATCHLO $18
3885 +#define C0_WATCHHI $19
3886 +#define C0_XCTEXT $20
3887 +#define C0_DIAGNOSTIC $22
3888 +#define C0_BROADCOM C0_DIAGNOSTIC
3889 +#define C0_PERFORMANCE $25
3890 +#define C0_ECC $26
3891 +#define C0_CACHEERR $27
3892 +#define C0_TAGLO $28
3893 +#define C0_TAGHI $29
3894 +#define C0_ERREPC $30
3895 +#define C0_DESAVE $31
3896 +
3897 +/*
3898 + * LEAF - declare leaf routine
3899 + */
3900 +#define LEAF(symbol) \
3901 + .globl symbol; \
3902 + .align 2; \
3903 + .type symbol,@function; \
3904 + .ent symbol,0; \
3905 +symbol: .frame sp,0,ra
3906 +
3907 +/*
3908 + * END - mark end of function
3909 + */
3910 +#define END(function) \
3911 + .end function; \
3912 + .size function,.-function
3913 +
3914 +#define _ULCAST_
3915 +
3916 +#else
3917 +
3918 +/*
3919 + * The following macros are especially useful for __asm__
3920 + * inline assembler.
3921 + */
3922 +#ifndef __STR
3923 +#define __STR(x) #x
3924 +#endif
3925 +#ifndef STR
3926 +#define STR(x) __STR(x)
3927 +#endif
3928 +
3929 +#define _ULCAST_ (unsigned long)
3930 +
3931 +
3932 +/*
3933 + * CP0 Registers
3934 + */
3935 +
3936 +#define C0_INX 0 /* CP0: TLB Index */
3937 +#define C0_RAND 1 /* CP0: TLB Random */
3938 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
3939 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
3940 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
3941 +#define C0_CTEXT 4 /* CP0: Context */
3942 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
3943 +#define C0_WIRED 6 /* CP0: TLB Wired */
3944 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
3945 +#define C0_COUNT 9 /* CP0: Count */
3946 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
3947 +#define C0_COMPARE 11 /* CP0: Compare */
3948 +#define C0_SR 12 /* CP0: Processor Status */
3949 +#define C0_STATUS C0_SR /* CP0: Processor Status */
3950 +#define C0_CAUSE 13 /* CP0: Exception Cause */
3951 +#define C0_EPC 14 /* CP0: Exception PC */
3952 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
3953 +#define C0_CONFIG 16 /* CP0: Config */
3954 +#define C0_LLADDR 17 /* CP0: LLAddr */
3955 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
3956 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
3957 +#define C0_XCTEXT 20 /* CP0: XContext */
3958 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
3959 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
3960 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
3961 +#define C0_ECC 26 /* CP0: ECC */
3962 +#define C0_CACHEERR 27 /* CP0: CacheErr */
3963 +#define C0_TAGLO 28 /* CP0: TagLo */
3964 +#define C0_TAGHI 29 /* CP0: TagHi */
3965 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
3966 +#define C0_DESAVE 31 /* CP0: DebugSave */
3967 +
3968 +#endif /* _LANGUAGE_ASSEMBLY */
3969 +
3970 +/*
3971 + * Memory segments (32bit kernel mode addresses)
3972 + */
3973 +#undef KUSEG
3974 +#undef KSEG0
3975 +#undef KSEG1
3976 +#undef KSEG2
3977 +#undef KSEG3
3978 +#define KUSEG 0x00000000
3979 +#define KSEG0 0x80000000
3980 +#define KSEG1 0xa0000000
3981 +#define KSEG2 0xc0000000
3982 +#define KSEG3 0xe0000000
3983 +#define PHYSADDR_MASK 0x1fffffff
3984 +
3985 +/*
3986 + * Map an address to a certain kernel segment
3987 + */
3988 +#undef PHYSADDR
3989 +#undef KSEG0ADDR
3990 +#undef KSEG1ADDR
3991 +#undef KSEG2ADDR
3992 +#undef KSEG3ADDR
3993 +
3994 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
3995 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
3996 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
3997 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
3998 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
3999 +
4000 +
4001 +#ifndef Index_Invalidate_I
4002 +/*
4003 + * Cache Operations
4004 + */
4005 +#define Index_Invalidate_I 0x00
4006 +#define Index_Writeback_Inv_D 0x01
4007 +#define Index_Invalidate_SI 0x02
4008 +#define Index_Writeback_Inv_SD 0x03
4009 +#define Index_Load_Tag_I 0x04
4010 +#define Index_Load_Tag_D 0x05
4011 +#define Index_Load_Tag_SI 0x06
4012 +#define Index_Load_Tag_SD 0x07
4013 +#define Index_Store_Tag_I 0x08
4014 +#define Index_Store_Tag_D 0x09
4015 +#define Index_Store_Tag_SI 0x0A
4016 +#define Index_Store_Tag_SD 0x0B
4017 +#define Create_Dirty_Excl_D 0x0d
4018 +#define Create_Dirty_Excl_SD 0x0f
4019 +#define Hit_Invalidate_I 0x10
4020 +#define Hit_Invalidate_D 0x11
4021 +#define Hit_Invalidate_SI 0x12
4022 +#define Hit_Invalidate_SD 0x13
4023 +#define Fill_I 0x14
4024 +#define Hit_Writeback_Inv_D 0x15
4025 + /* 0x16 is unused */
4026 +#define Hit_Writeback_Inv_SD 0x17
4027 +#define R5K_Page_Invalidate_S 0x17
4028 +#define Hit_Writeback_I 0x18
4029 +#define Hit_Writeback_D 0x19
4030 + /* 0x1a is unused */
4031 +#define Hit_Writeback_SD 0x1b
4032 + /* 0x1c is unused */
4033 + /* 0x1e is unused */
4034 +#define Hit_Set_Virtual_SI 0x1e
4035 +#define Hit_Set_Virtual_SD 0x1f
4036 +#endif
4037 +
4038 +
4039 +/*
4040 + * R4x00 interrupt enable / cause bits
4041 + */
4042 +#define IE_SW0 (_ULCAST_(1) << 8)
4043 +#define IE_SW1 (_ULCAST_(1) << 9)
4044 +#define IE_IRQ0 (_ULCAST_(1) << 10)
4045 +#define IE_IRQ1 (_ULCAST_(1) << 11)
4046 +#define IE_IRQ2 (_ULCAST_(1) << 12)
4047 +#define IE_IRQ3 (_ULCAST_(1) << 13)
4048 +#define IE_IRQ4 (_ULCAST_(1) << 14)
4049 +#define IE_IRQ5 (_ULCAST_(1) << 15)
4050 +
4051 +#ifndef ST0_UM
4052 +/*
4053 + * Bitfields in the mips32 cp0 status register
4054 + */
4055 +#define ST0_IE 0x00000001
4056 +#define ST0_EXL 0x00000002
4057 +#define ST0_ERL 0x00000004
4058 +#define ST0_UM 0x00000010
4059 +#define ST0_SWINT0 0x00000100
4060 +#define ST0_SWINT1 0x00000200
4061 +#define ST0_HWINT0 0x00000400
4062 +#define ST0_HWINT1 0x00000800
4063 +#define ST0_HWINT2 0x00001000
4064 +#define ST0_HWINT3 0x00002000
4065 +#define ST0_HWINT4 0x00004000
4066 +#define ST0_HWINT5 0x00008000
4067 +#define ST0_IM 0x0000ff00
4068 +#define ST0_NMI 0x00080000
4069 +#define ST0_SR 0x00100000
4070 +#define ST0_TS 0x00200000
4071 +#define ST0_BEV 0x00400000
4072 +#define ST0_RE 0x02000000
4073 +#define ST0_RP 0x08000000
4074 +#define ST0_CU 0xf0000000
4075 +#define ST0_CU0 0x10000000
4076 +#define ST0_CU1 0x20000000
4077 +#define ST0_CU2 0x40000000
4078 +#define ST0_CU3 0x80000000
4079 +#endif
4080 +
4081 +
4082 +/*
4083 + * Bitfields in the mips32 cp0 cause register
4084 + */
4085 +#define C_EXC 0x0000007c
4086 +#define C_EXC_SHIFT 2
4087 +#define C_INT 0x0000ff00
4088 +#define C_INT_SHIFT 8
4089 +#define C_SW0 (_ULCAST_(1) << 8)
4090 +#define C_SW1 (_ULCAST_(1) << 9)
4091 +#define C_IRQ0 (_ULCAST_(1) << 10)
4092 +#define C_IRQ1 (_ULCAST_(1) << 11)
4093 +#define C_IRQ2 (_ULCAST_(1) << 12)
4094 +#define C_IRQ3 (_ULCAST_(1) << 13)
4095 +#define C_IRQ4 (_ULCAST_(1) << 14)
4096 +#define C_IRQ5 (_ULCAST_(1) << 15)
4097 +#define C_WP 0x00400000
4098 +#define C_IV 0x00800000
4099 +#define C_CE 0x30000000
4100 +#define C_CE_SHIFT 28
4101 +#define C_BD 0x80000000
4102 +
4103 +/* Values in C_EXC */
4104 +#define EXC_INT 0
4105 +#define EXC_TLBM 1
4106 +#define EXC_TLBL 2
4107 +#define EXC_TLBS 3
4108 +#define EXC_AEL 4
4109 +#define EXC_AES 5
4110 +#define EXC_IBE 6
4111 +#define EXC_DBE 7
4112 +#define EXC_SYS 8
4113 +#define EXC_BPT 9
4114 +#define EXC_RI 10
4115 +#define EXC_CU 11
4116 +#define EXC_OV 12
4117 +#define EXC_TR 13
4118 +#define EXC_WATCH 23
4119 +#define EXC_MCHK 24
4120 +
4121 +
4122 +/*
4123 + * Bits in the cp0 config register.
4124 + */
4125 +#define CONF_CM_CACHABLE_NO_WA 0
4126 +#define CONF_CM_CACHABLE_WA 1
4127 +#define CONF_CM_UNCACHED 2
4128 +#define CONF_CM_CACHABLE_NONCOHERENT 3
4129 +#define CONF_CM_CACHABLE_CE 4
4130 +#define CONF_CM_CACHABLE_COW 5
4131 +#define CONF_CM_CACHABLE_CUW 6
4132 +#define CONF_CM_CACHABLE_ACCELERATED 7
4133 +#define CONF_CM_CMASK 7
4134 +#define CONF_CU (_ULCAST_(1) << 3)
4135 +#define CONF_DB (_ULCAST_(1) << 4)
4136 +#define CONF_IB (_ULCAST_(1) << 5)
4137 +#define CONF_SE (_ULCAST_(1) << 12)
4138 +#define CONF_SC (_ULCAST_(1) << 17)
4139 +#define CONF_AC (_ULCAST_(1) << 23)
4140 +#define CONF_HALT (_ULCAST_(1) << 25)
4141 +
4142 +
4143 +/*
4144 + * Bits in the cp0 config register select 1.
4145 + */
4146 +#define CONF1_FP 0x00000001 /* FPU present */
4147 +#define CONF1_EP 0x00000002 /* EJTAG present */
4148 +#define CONF1_CA 0x00000004 /* mips16 implemented */
4149 +#define CONF1_WR 0x00000008 /* Watch registers present */
4150 +#define CONF1_PC 0x00000010 /* Performance counters present */
4151 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
4152 +#define CONF1_DA_MASK 0x00000380
4153 +#define CONF1_DA_BASE 1
4154 +#define CONF1_DL_SHIFT 10 /* D$ line size */
4155 +#define CONF1_DL_MASK 0x00001c00
4156 +#define CONF1_DL_BASE 2
4157 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
4158 +#define CONF1_DS_MASK 0x0000e000
4159 +#define CONF1_DS_BASE 64
4160 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
4161 +#define CONF1_IA_MASK 0x00070000
4162 +#define CONF1_IA_BASE 1
4163 +#define CONF1_IL_SHIFT 19 /* I$ line size */
4164 +#define CONF1_IL_MASK 0x00380000
4165 +#define CONF1_IL_BASE 2
4166 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
4167 +#define CONF1_IS_MASK 0x01c00000
4168 +#define CONF1_IS_BASE 64
4169 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
4170 +#define CONF1_MS_SHIFT 25
4171 +
4172 +/* PRID register */
4173 +#define PRID_COPT_MASK 0xff000000
4174 +#define PRID_COMP_MASK 0x00ff0000
4175 +#define PRID_IMP_MASK 0x0000ff00
4176 +#define PRID_REV_MASK 0x000000ff
4177 +
4178 +#define PRID_COMP_LEGACY 0x000000
4179 +#define PRID_COMP_MIPS 0x010000
4180 +#define PRID_COMP_BROADCOM 0x020000
4181 +#define PRID_COMP_ALCHEMY 0x030000
4182 +#define PRID_COMP_SIBYTE 0x040000
4183 +#define PRID_IMP_BCM4710 0x4000
4184 +#define PRID_IMP_BCM3302 0x9000
4185 +#define PRID_IMP_BCM3303 0x9100
4186 +
4187 +#define PRID_IMP_UNKNOWN 0xff00
4188 +
4189 +#define BCM330X(id) \
4190 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
4191 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
4192 +
4193 +/* Bits in C0_BROADCOM */
4194 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
4195 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
4196 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
4197 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
4198 +
4199 +/* PreFetch Cache aka Read Ahead Cache */
4200 +
4201 +#define PFC_CR0 0xff400000 /* control reg 0 */
4202 +#define PFC_CR1 0xff400004 /* control reg 1 */
4203 +
4204 +/* PFC operations */
4205 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
4206 +#define PFC_D 0x00000002 /* Enable PFC use for data */
4207 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
4208 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
4209 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
4210 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
4211 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
4212 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
4213 +#define PFC_BRR 0x40000000 /* Bus error indication */
4214 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
4215 +
4216 +/* Handy defaults */
4217 +#define PFC_DISABLED 0
4218 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
4219 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
4220 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
4221 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
4222 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
4223 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
4224 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
4225 +
4226 +
4227 +/*
4228 + * These are the UART port assignments, expressed as offsets from the base
4229 + * register. These assignments should hold for any serial port based on
4230 + * a 8250, 16450, or 16550(A).
4231 + */
4232 +
4233 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
4234 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
4235 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
4236 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
4237 +#define UART_LCR 3 /* Out: Line Control Register */
4238 +#define UART_MCR 4 /* Out: Modem Control Register */
4239 +#define UART_LSR 5 /* In: Line Status Register */
4240 +#define UART_MSR 6 /* In: Modem Status Register */
4241 +#define UART_SCR 7 /* I/O: Scratch Register */
4242 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
4243 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
4244 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
4245 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
4246 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
4247 +
4248 +
4249 +#ifndef _LANGUAGE_ASSEMBLY
4250 +
4251 +/*
4252 + * Macros to access the system control coprocessor
4253 + */
4254 +
4255 +#define MFC0(source, sel) \
4256 +({ \
4257 + int __res; \
4258 + __asm__ __volatile__( \
4259 + ".set\tnoreorder\n\t" \
4260 + ".set\tnoat\n\t" \
4261 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
4262 + "move\t%0,$1\n\t" \
4263 + ".set\tat\n\t" \
4264 + ".set\treorder" \
4265 + :"=r" (__res) \
4266 + : \
4267 + :"$1"); \
4268 + __res; \
4269 +})
4270 +
4271 +#define MTC0(source, sel, value) \
4272 +do { \
4273 + __asm__ __volatile__( \
4274 + ".set\tnoreorder\n\t" \
4275 + ".set\tnoat\n\t" \
4276 + "move\t$1,%z0\n\t" \
4277 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
4278 + ".set\tat\n\t" \
4279 + ".set\treorder" \
4280 + : \
4281 + :"jr" (value) \
4282 + :"$1"); \
4283 +} while (0)
4284 +
4285 +#define get_c0_count() \
4286 +({ \
4287 + int __res; \
4288 + __asm__ __volatile__( \
4289 + ".set\tnoreorder\n\t" \
4290 + ".set\tnoat\n\t" \
4291 + "mfc0\t%0,$9\n\t" \
4292 + ".set\tat\n\t" \
4293 + ".set\treorder" \
4294 + :"=r" (__res)); \
4295 + __res; \
4296 +})
4297 +
4298 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
4299 +{
4300 + uint lsz, sets, ways;
4301 +
4302 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
4303 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
4304 + lsz = CONF1_IL_BASE << lsz;
4305 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
4306 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
4307 + *size = lsz * sets * ways;
4308 + *lsize = lsz;
4309 +}
4310 +
4311 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
4312 +{
4313 + uint lsz, sets, ways;
4314 +
4315 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
4316 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
4317 + lsz = CONF1_DL_BASE << lsz;
4318 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
4319 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
4320 + *size = lsz * sets * ways;
4321 + *lsize = lsz;
4322 +}
4323 +
4324 +#define cache_op(base, op) \
4325 + __asm__ __volatile__(" \
4326 + .set noreorder; \
4327 + .set mips3; \
4328 + cache %1, (%0); \
4329 + .set mips0; \
4330 + .set reorder" \
4331 + : \
4332 + : "r" (base), \
4333 + "i" (op));
4334 +
4335 +#define cache_unroll4(base, delta, op) \
4336 + __asm__ __volatile__(" \
4337 + .set noreorder; \
4338 + .set mips3; \
4339 + cache %1,0(%0); \
4340 + cache %1,delta(%0); \
4341 + cache %1,(2 * delta)(%0); \
4342 + cache %1,(3 * delta)(%0); \
4343 + .set mips0; \
4344 + .set reorder" \
4345 + : \
4346 + : "r" (base), \
4347 + "i" (op));
4348 +
4349 +#endif /* !_LANGUAGE_ASSEMBLY */
4350 +
4351 +#endif /* _MISPINC_H */
4352 diff -urN linux.old/arch/mips/bcm947xx/include/nvports.h linux.dev/arch/mips/bcm947xx/include/nvports.h
4353 --- linux.old/arch/mips/bcm947xx/include/nvports.h 1970-01-01 01:00:00.000000000 +0100
4354 +++ linux.dev/arch/mips/bcm947xx/include/nvports.h 2005-11-07 21:57:07.865587000 +0100
4355 @@ -0,0 +1,55 @@
4356 +/*
4357 + * BCM53xx RoboSwitch utility functions
4358 + *
4359 + * Copyright (C) 2002 Broadcom Corporation
4360 + * $Id$
4361 + */
4362 +
4363 +#ifndef _nvports_h_
4364 +#define _nvports_h_
4365 +
4366 +#define uint32 unsigned long
4367 +#define uint16 unsigned short
4368 +#define uint unsigned int
4369 +#define uint8 unsigned char
4370 +#define uint64 unsigned long long
4371 +
4372 +enum FORCE_PORT {
4373 + FORCE_OFF,
4374 + FORCE_10H,
4375 + FORCE_10F,
4376 + FORCE_100H,
4377 + FORCE_100F,
4378 + FORCE_DOWN,
4379 + POWER_OFF
4380 +};
4381 +
4382 +typedef struct _PORT_ATTRIBS
4383 +{
4384 + uint autoneg;
4385 + uint force;
4386 + uint native;
4387 +} PORT_ATTRIBS;
4388 +
4389 +extern uint
4390 +nvExistsPortAttrib(char *attrib, uint portno);
4391 +
4392 +extern int
4393 +nvExistsAnyForcePortAttrib(uint portno);
4394 +
4395 +extern void
4396 +nvSetPortAttrib(char *attrib, uint portno);
4397 +
4398 +extern void
4399 +nvUnsetPortAttrib(char *attrib, uint portno);
4400 +
4401 +extern void
4402 +nvUnsetAllForcePortAttrib(uint portno);
4403 +
4404 +extern PORT_ATTRIBS
4405 +nvGetSwitchPortAttribs(uint portno);
4406 +
4407 +#endif /* _nvports_h_ */
4408 +
4409 +
4410 +
4411 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
4412 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
4413 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-11-07 22:51:38.780726250 +0100
4414 @@ -0,0 +1,42 @@
4415 +/*
4416 + * OS Abstraction Layer
4417 + *
4418 + * Copyright 2005, Broadcom Corporation
4419 + * All Rights Reserved.
4420 + *
4421 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4422 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4423 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4424 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4425 + * $Id$
4426 + */
4427 +
4428 +#ifndef _osl_h_
4429 +#define _osl_h_
4430 +
4431 +/* osl handle type forward declaration */
4432 +typedef struct os_handle osl_t;
4433 +
4434 +#if defined(linux)
4435 +#include <linux_osl.h>
4436 +#elif defined(NDIS)
4437 +#include <ndis_osl.h>
4438 +#elif defined(_CFE_)
4439 +#include <cfe_osl.h>
4440 +#elif defined(_HNDRTE_)
4441 +#include <hndrte_osl.h>
4442 +#elif defined(_MINOSL_)
4443 +#include <min_osl.h>
4444 +#elif PMON
4445 +#include <pmon_osl.h>
4446 +#elif defined(MACOSX)
4447 +#include <macosx_osl.h>
4448 +#else
4449 +#error "Unsupported OSL requested"
4450 +#endif
4451 +
4452 +/* handy */
4453 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
4454 +#define MAXPRIO 7 /* 0-7 */
4455 +
4456 +#endif /* _osl_h_ */
4457 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
4458 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
4459 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-11-07 22:51:38.780726250 +0100
4460 @@ -0,0 +1,451 @@
4461 +/*
4462 + * pcicfg.h: PCI configuration constants and structures.
4463 + *
4464 + * Copyright 2005, Broadcom Corporation
4465 + * All Rights Reserved.
4466 + *
4467 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
4468 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
4469 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
4470 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
4471 + *
4472 + * $Id$
4473 + */
4474 +
4475 +#ifndef _h_pci_
4476 +#define _h_pci_
4477 +
4478 +/* The following inside ifndef's so we don't collide with NTDDK.H */
4479 +#ifndef PCI_MAX_BUS
4480 +#define PCI_MAX_BUS 0x100
4481 +#endif
4482 +#ifndef PCI_MAX_DEVICES
4483 +#define PCI_MAX_DEVICES 0x20
4484 +#endif
4485 +#ifndef PCI_MAX_FUNCTION
4486 +#define PCI_MAX_FUNCTION 0x8
4487 +#endif
4488 +
4489 +#ifndef PCI_INVALID_VENDORID
4490 +#define PCI_INVALID_VENDORID 0xffff
4491 +#endif
4492 +#ifndef PCI_INVALID_DEVICEID
4493 +#define PCI_INVALID_DEVICEID 0xffff
4494 +#endif
4495 +
4496 +
4497 +/* Convert between bus-slot-function-register and config addresses */
4498 +
4499 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
4500 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
4501 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
4502 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
4503 +
4504 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
4505 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
4506 +#define PCICFG_FUN_MASK 7 /* Function mask */
4507 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
4508 +
4509 +#define PCI_CONFIG_ADDR(b, s, f, o) \
4510 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
4511 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
4512 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
4513 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
4514 +
4515 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
4516 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
4517 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
4518 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
4519 +
4520 +/* PCIE Config space accessing MACROS*/
4521 +
4522 +#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
4523 +#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
4524 +#define PCIECFG_FUN_SHIFT 16 /* Function shift */
4525 +#define PCIECFG_OFF_SHIFT 0 /* Register shift */
4526 +
4527 +#define PCIECFG_BUS_MASK 0xff /* Bus mask */
4528 +#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
4529 +#define PCIECFG_FUN_MASK 7 /* Function mask */
4530 +#define PCIECFG_OFF_MASK 0x3ff /* Register mask */
4531 +
4532 +#define PCIE_CONFIG_ADDR(b, s, f, o) \
4533 + ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
4534 + | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
4535 + | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
4536 + | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
4537 +
4538 +#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
4539 +#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
4540 +#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
4541 +#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
4542 +
4543 +
4544 +/* The actual config space */
4545 +
4546 +#define PCI_BAR_MAX 6
4547 +
4548 +#define PCI_ROM_BAR 8
4549 +
4550 +#define PCR_RSVDA_MAX 2
4551 +
4552 +/* pci config status reg has a bit to indicate that capability ptr is present*/
4553 +
4554 +#define PCI_CAPPTR_PRESENT 0x0010
4555 +
4556 +typedef struct _pci_config_regs {
4557 + unsigned short vendor;
4558 + unsigned short device;
4559 + unsigned short command;
4560 + unsigned short status;
4561 + unsigned char rev_id;
4562 + unsigned char prog_if;
4563 + unsigned char sub_class;
4564 + unsigned char base_class;
4565 + unsigned char cache_line_size;
4566 + unsigned char latency_timer;
4567 + unsigned char header_type;
4568 + unsigned char bist;
4569 + unsigned long base[PCI_BAR_MAX];
4570 + unsigned long cardbus_cis;
4571 + unsigned short subsys_vendor;
4572 + unsigned short subsys_id;
4573 + unsigned long baserom;
4574 + unsigned long rsvd_a[PCR_RSVDA_MAX];
4575 + unsigned char int_line;
4576 + unsigned char int_pin;
4577 + unsigned char min_gnt;
4578 + unsigned char max_lat;
4579 + unsigned char dev_dep[192];
4580 +} pci_config_regs;
4581 +
4582 +#define SZPCR (sizeof (pci_config_regs))
4583 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
4584 +
4585 +/* A structure for the config registers is nice, but in most
4586 + * systems the config space is not memory mapped, so we need
4587 + * filed offsetts. :-(
4588 + */
4589 +#define PCI_CFG_VID 0
4590 +#define PCI_CFG_DID 2
4591 +#define PCI_CFG_CMD 4
4592 +#define PCI_CFG_STAT 6
4593 +#define PCI_CFG_REV 8
4594 +#define PCI_CFG_PROGIF 9
4595 +#define PCI_CFG_SUBCL 0xa
4596 +#define PCI_CFG_BASECL 0xb
4597 +#define PCI_CFG_CLSZ 0xc
4598 +#define PCI_CFG_LATTIM 0xd
4599 +#define PCI_CFG_HDR 0xe
4600 +#define PCI_CFG_BIST 0xf
4601 +#define PCI_CFG_BAR0 0x10
4602 +#define PCI_CFG_BAR1 0x14
4603 +#define PCI_CFG_BAR2 0x18
4604 +#define PCI_CFG_BAR3 0x1c
4605 +#define PCI_CFG_BAR4 0x20
4606 +#define PCI_CFG_BAR5 0x24
4607 +#define PCI_CFG_CIS 0x28
4608 +#define PCI_CFG_SVID 0x2c
4609 +#define PCI_CFG_SSID 0x2e
4610 +#define PCI_CFG_ROMBAR 0x30
4611 +#define PCI_CFG_CAPPTR 0x34
4612 +#define PCI_CFG_INT 0x3c
4613 +#define PCI_CFG_PIN 0x3d
4614 +#define PCI_CFG_MINGNT 0x3e
4615 +#define PCI_CFG_MAXLAT 0x3f
4616 +
4617 +/* Classes and subclasses */
4618 +
4619 +typedef enum {
4620 + PCI_CLASS_OLD = 0,
4621 + PCI_CLASS_DASDI,
4622 + PCI_CLASS_NET,
4623 + PCI_CLASS_DISPLAY,
4624 + PCI_CLASS_MMEDIA,
4625 + PCI_CLASS_MEMORY,
4626 + PCI_CLASS_BRIDGE,
4627 + PCI_CLASS_COMM,
4628 + PCI_CLASS_BASE,
4629 + PCI_CLASS_INPUT,
4630 + PCI_CLASS_DOCK,
4631 + PCI_CLASS_CPU,
4632 + PCI_CLASS_SERIAL,
4633 + PCI_CLASS_INTELLIGENT = 0xe,
4634 + PCI_CLASS_SATELLITE,
4635 + PCI_CLASS_CRYPT,
4636 + PCI_CLASS_DSP,
4637 + PCI_CLASS_MAX
4638 +} pci_classes;
4639 +
4640 +typedef enum {
4641 + PCI_DASDI_SCSI,
4642 + PCI_DASDI_IDE,
4643 + PCI_DASDI_FLOPPY,
4644 + PCI_DASDI_IPI,
4645 + PCI_DASDI_RAID,
4646 + PCI_DASDI_OTHER = 0x80
4647 +} pci_dasdi_subclasses;
4648 +
4649 +typedef enum {
4650 + PCI_NET_ETHER,
4651 + PCI_NET_TOKEN,
4652 + PCI_NET_FDDI,
4653 + PCI_NET_ATM,
4654 + PCI_NET_OTHER = 0x80
4655 +} pci_net_subclasses;
4656 +
4657 +typedef enum {
4658 + PCI_DISPLAY_VGA,
4659 + PCI_DISPLAY_XGA,
4660 + PCI_DISPLAY_3D,
4661 + PCI_DISPLAY_OTHER = 0x80
4662 +} pci_display_subclasses;
4663 +
4664 +typedef enum {
4665 + PCI_MMEDIA_VIDEO,
4666 + PCI_MMEDIA_AUDIO,
4667 + PCI_MMEDIA_PHONE,
4668 + PCI_MEDIA_OTHER = 0x80
4669 +} pci_mmedia_subclasses;
4670 +
4671 +typedef enum {
4672 + PCI_MEMORY_RAM,
4673 + PCI_MEMORY_FLASH,
4674 + PCI_MEMORY_OTHER = 0x80
4675 +} pci_memory_subclasses;
4676 +
4677 +typedef enum {
4678 + PCI_BRIDGE_HOST,
4679 + PCI_BRIDGE_ISA,
4680 + PCI_BRIDGE_EISA,
4681 + PCI_BRIDGE_MC,
4682 + PCI_BRIDGE_PCI,
4683 + PCI_BRIDGE_PCMCIA,
4684 + PCI_BRIDGE_NUBUS,
4685 + PCI_BRIDGE_CARDBUS,
4686 + PCI_BRIDGE_RACEWAY,
4687 + PCI_BRIDGE_OTHER = 0x80
4688 +} pci_bridge_subclasses;
4689 +
4690 +typedef enum {
4691 + PCI_COMM_UART,
4692 + PCI_COMM_PARALLEL,
4693 + PCI_COMM_MULTIUART,
4694 + PCI_COMM_MODEM,
4695 + PCI_COMM_OTHER = 0x80
4696 +} pci_comm_subclasses;
4697 +
4698 +typedef enum {
4699 + PCI_BASE_PIC,
4700 + PCI_BASE_DMA,
4701 + PCI_BASE_TIMER,
4702 + PCI_BASE_RTC,
4703 + PCI_BASE_PCI_HOTPLUG,
4704 + PCI_BASE_OTHER = 0x80
4705 +} pci_base_subclasses;
4706 +
4707 +typedef enum {
4708 + PCI_INPUT_KBD,
4709 + PCI_INPUT_PEN,
4710 + PCI_INPUT_MOUSE,
4711 + PCI_INPUT_SCANNER,
4712 + PCI_INPUT_GAMEPORT,
4713 + PCI_INPUT_OTHER = 0x80
4714 +} pci_input_subclasses;
4715 +
4716 +typedef enum {
4717 + PCI_DOCK_GENERIC,
4718 + PCI_DOCK_OTHER = 0x80
4719 +} pci_dock_subclasses;
4720 +
4721 +typedef enum {
4722 + PCI_CPU_386,
4723 + PCI_CPU_486,
4724 + PCI_CPU_PENTIUM,
4725 + PCI_CPU_ALPHA = 0x10,
4726 + PCI_CPU_POWERPC = 0x20,
4727 + PCI_CPU_MIPS = 0x30,
4728 + PCI_CPU_COPROC = 0x40,
4729 + PCI_CPU_OTHER = 0x80
4730 +} pci_cpu_subclasses;
4731 +
4732 +typedef enum {
4733 + PCI_SERIAL_IEEE1394,
4734 + PCI_SERIAL_ACCESS,
4735 + PCI_SERIAL_SSA,
4736 + PCI_SERIAL_USB,
4737 + PCI_SERIAL_FIBER,
4738 + PCI_SERIAL_SMBUS,
4739 + PCI_SERIAL_OTHER = 0x80
4740 +} pci_serial_subclasses;
4741 +
4742 +typedef enum {
4743 + PCI_INTELLIGENT_I2O,
4744 +} pci_intelligent_subclasses;
4745 +
4746 +typedef enum {
4747 + PCI_SATELLITE_TV,
4748 + PCI_SATELLITE_AUDIO,
4749 + PCI_SATELLITE_VOICE,
4750 + PCI_SATELLITE_DATA,
4751 + PCI_SATELLITE_OTHER = 0x80
4752 +} pci_satellite_subclasses;
4753 +
4754 +typedef enum {
4755 + PCI_CRYPT_NETWORK,
4756 + PCI_CRYPT_ENTERTAINMENT,
4757 + PCI_CRYPT_OTHER = 0x80
4758 +} pci_crypt_subclasses;
4759 +
4760 +typedef enum {
4761 + PCI_DSP_DPIO,
4762 + PCI_DSP_OTHER = 0x80
4763 +} pci_dsp_subclasses;
4764 +
4765 +/* Header types */
4766 +typedef enum {
4767 + PCI_HEADER_NORMAL,
4768 + PCI_HEADER_BRIDGE,
4769 + PCI_HEADER_CARDBUS
4770 +} pci_header_types;
4771 +
4772 +
4773 +/* Overlay for a PCI-to-PCI bridge */
4774 +
4775 +#define PPB_RSVDA_MAX 2
4776 +#define PPB_RSVDD_MAX 8
4777 +
4778 +typedef struct _ppb_config_regs {
4779 + unsigned short vendor;
4780 + unsigned short device;
4781 + unsigned short command;
4782 + unsigned short status;
4783 + unsigned char rev_id;
4784 + unsigned char prog_if;
4785 + unsigned char sub_class;
4786 + unsigned char base_class;
4787 + unsigned char cache_line_size;
4788 + unsigned char latency_timer;
4789 + unsigned char header_type;
4790 + unsigned char bist;
4791 + unsigned long rsvd_a[PPB_RSVDA_MAX];
4792 + unsigned char prim_bus;
4793 + unsigned char sec_bus;
4794 + unsigned char sub_bus;
4795 + unsigned char sec_lat;
4796 + unsigned char io_base;
4797 + unsigned char io_lim;
4798 + unsigned short sec_status;
4799 + unsigned short mem_base;
4800 + unsigned short mem_lim;
4801 + unsigned short pf_mem_base;
4802 + unsigned short pf_mem_lim;
4803 + unsigned long pf_mem_base_hi;
4804 + unsigned long pf_mem_lim_hi;
4805 + unsigned short io_base_hi;
4806 + unsigned short io_lim_hi;
4807 + unsigned short subsys_vendor;
4808 + unsigned short subsys_id;
4809 + unsigned long rsvd_b;
4810 + unsigned char rsvd_c;
4811 + unsigned char int_pin;
4812 + unsigned short bridge_ctrl;
4813 + unsigned char chip_ctrl;
4814 + unsigned char diag_ctrl;
4815 + unsigned short arb_ctrl;
4816 + unsigned long rsvd_d[PPB_RSVDD_MAX];
4817 + unsigned char dev_dep[192];
4818 +} ppb_config_regs;
4819 +
4820 +
4821 +/* PCI CAPABILITY DEFINES */
4822 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
4823 +#define PCI_CAP_MSICAP_ID 0x05
4824 +#define PCI_CAP_PCIECAP_ID 0x10
4825 +
4826 +/* Data structure to define the Message Signalled Interrupt facility
4827 + * Valid for PCI and PCIE configurations */
4828 +typedef struct _pciconfig_cap_msi {
4829 + unsigned char capID;
4830 + unsigned char nextptr;
4831 + unsigned short msgctrl;
4832 + unsigned int msgaddr;
4833 +} pciconfig_cap_msi;
4834 +
4835 +/* Data structure to define the Power managment facility
4836 + * Valid for PCI and PCIE configurations */
4837 +typedef struct _pciconfig_cap_pwrmgmt {
4838 + unsigned char capID;
4839 + unsigned char nextptr;
4840 + unsigned short pme_cap;
4841 + unsigned short pme_sts_ctrl;
4842 + unsigned char pme_bridge_ext;
4843 + unsigned char data;
4844 +} pciconfig_cap_pwrmgmt;
4845 +
4846 +/* Data structure to define the PCIE capability */
4847 +typedef struct _pciconfig_cap_pcie {
4848 + unsigned char capID;
4849 + unsigned char nextptr;
4850 + unsigned short pcie_cap;
4851 + unsigned int dev_cap;
4852 + unsigned short dev_ctrl;
4853 + unsigned short dev_status;
4854 + unsigned int link_cap;
4855 + unsigned short link_ctrl;
4856 + unsigned short link_status;
4857 +} pciconfig_cap_pcie;
4858 +
4859 +/* PCIE Enhanced CAPABILITY DEFINES */
4860 +#define PCIE_EXTCFG_OFFSET 0x100
4861 +#define PCIE_ADVERRREP_CAPID 0x0001
4862 +#define PCIE_VC_CAPID 0x0002
4863 +#define PCIE_DEVSNUM_CAPID 0x0003
4864 +#define PCIE_PWRBUDGET_CAPID 0x0004
4865 +
4866 +/* Header to define the PCIE specific capabilities in the extended config space */
4867 +typedef struct _pcie_enhanced_caphdr {
4868 + unsigned short capID;
4869 + unsigned short cap_ver : 4;
4870 + unsigned short next_ptr : 12;
4871 +} pcie_enhanced_caphdr;
4872 +
4873 +
4874 +/* Everything below is BRCM HND proprietary */
4875 +
4876 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
4877 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
4878 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
4879 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
4880 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
4881 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
4882 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
4883 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
4884 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
4885 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
4886 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
4887 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
4888 +
4889 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
4890 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
4891 +
4892 +/* PCI_INT_STATUS */
4893 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
4894 +
4895 +/* PCI_INT_MASK */
4896 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
4897 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
4898 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
4899 +
4900 +/* PCI_SPROM_CONTROL */
4901 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
4902 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
4903 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
4904 +
4905 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
4906 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
4907 +
4908 +/* PCI_CFG_CMD_STAT */
4909 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
4910 +
4911 +#endif
4912 diff -urN linux.old/arch/mips/bcm947xx/include/pmon_osl.h linux.dev/arch/mips/bcm947xx/include/pmon_osl.h
4913 --- linux.old/arch/mips/bcm947xx/include/pmon_osl.h 1970-01-01 01:00:00.000000000 +0100
4914 +++ linux.dev/arch/mips/bcm947xx/include/pmon_osl.h 2005-11-07 21:57:07.869587250 +0100
4915 @@ -0,0 +1,126 @@
4916 +/*
4917 + * MIPS PMON boot loader OS Abstraction Layer.
4918 + *
4919 + * Copyright 2005, Broadcom Corporation
4920 + * All Rights Reserved.
4921 + *
4922 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
4923 + * the contents of this file may not be disclosed to third parties, copied
4924 + * or duplicated in any form, in whole or in part, without the prior
4925 + * written permission of Broadcom Corporation.
4926 + * $Id$
4927 + */
4928 +
4929 +#ifndef _pmon_osl_h_
4930 +#define _pmon_osl_h_
4931 +
4932 +#include <typedefs.h>
4933 +#include <mips.h>
4934 +#include <string.h>
4935 +#include <utypes.h>
4936 +
4937 +extern int printf(char *fmt,...);
4938 +extern int sprintf(char *dst,char *fmt,...);
4939 +
4940 +#define OSL_UNCACHED(va) phy2k1(log2phy((va)))
4941 +#define REG_MAP(pa, size) phy2k1((pa))
4942 +#define REG_UNMAP(va) /* nop */
4943 +
4944 +/* Common macros */
4945 +
4946 +#define BUSPROBE(val, addr) ((val) = *(addr))
4947 +
4948 +#define ASSERT(exp)
4949 +
4950 +#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) bzero(buf, size)
4951 +#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size)
4952 +
4953 +/* kludge */
4954 +#define OSL_PCI_READ_CONFIG(loc, offset, size) ((offset == 8)? 0: 0xffffffff)
4955 +#define OSL_PCI_WRITE_CONFIG(loc, offset, size, val) ASSERT(0)
4956 +
4957 +#define wreg32(r,v) (*(volatile uint32 *)(r) = (v))
4958 +#define rreg32(r) (*(volatile uint32 *)(r))
4959 +#ifdef IL_BIGENDIAN
4960 +#define wreg16(r,v) (*(volatile uint16 *)((uint32)r^2) = (v))
4961 +#define rreg16(r) (*(volatile uint16 *)((uint32)r^2))
4962 +#else
4963 +#define wreg16(r,v) (*(volatile uint16 *)(r) = (v))
4964 +#define rreg16(r) (*(volatile uint16 *)(r))
4965 +#endif
4966 +
4967 +#include <memory.h>
4968 +#define bcopy(src, dst, len) memcpy(dst, src, len)
4969 +#define bcmp(b1, b2, len) memcmp(b1, b2, len)
4970 +#define bzero(b, len) memset(b, '\0', len)
4971 +
4972 +/* register access macros */
4973 +#define R_REG(r) ((sizeof *(r) == sizeof (uint32))? rreg32(r): rreg16(r))
4974 +#define W_REG(r,v) ((sizeof *(r) == sizeof (uint32))? wreg32(r,(uint32)v): wreg16(r,(uint16)v))
4975 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
4976 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
4977 +
4978 +#define R_SM(r) *(r)
4979 +#define W_SM(r, v) (*(r) = (v))
4980 +#define BZERO_SM(r, len) memset(r, '\0', len)
4981 +
4982 +/* Host/Bus architecture specific swap. Noop for little endian systems, possible swap on big endian */
4983 +#define BUS_SWAP32(v) (v)
4984 +
4985 +#define OSL_DELAY(usec) delay_us(usec)
4986 +extern void delay_us(uint usec);
4987 +
4988 +#define OSL_GETCYCLES(x) ((x) = 0)
4989 +
4990 +#define osl_attach(pdev) (pdev)
4991 +#define osl_detach(osh)
4992 +
4993 +#define MALLOC(osh, size) malloc(size)
4994 +#define MFREE(osh, addr, size) free(addr)
4995 +#define MALLOCED(osh) (0)
4996 +#define MALLOC_DUMP(osh, buf, sz)
4997 +#define MALLOC_FAILED(osh)
4998 +extern void *malloc();
4999 +extern void free(void *addr);
5000 +
5001 +#define DMA_CONSISTENT_ALIGN sizeof (int)
5002 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) et_dma_alloc_consistent(osh, size, pap)
5003 +#define DMA_FREE_CONSISTENT(osh, va, size, pa)
5004 +extern void* et_dma_alloc_consistent(void *osh, uint size, ulong *pap);
5005 +#define DMA_TX 0
5006 +#define DMA_RX 1
5007 +
5008 +#define DMA_MAP(osh, va, size, direction, p) osl_dma_map(osh, (void*)va, size, direction)
5009 +#define DMA_UNMAP(osh, pa, size, direction, p) /* nop */
5010 +extern void* osl_dma_map(void *osh, void *va, uint size, uint direction);
5011 +
5012 +struct lbuf {
5013 + struct lbuf *next; /* pointer to next lbuf on freelist */
5014 + uchar *buf; /* pointer to buffer */
5015 + uint len; /* nbytes of data */
5016 +};
5017 +
5018 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
5019 +#define PKTBUFSZ 2048
5020 +
5021 +/* packet primitives */
5022 +#define PKTGET(drv, len, send) et_pktget(drv, len, send)
5023 +#define PKTFREE(drv, lb, send) et_pktfree(drv, (struct lbuf*)lb, send)
5024 +#define PKTDATA(drv, lb) ((uchar*)OSL_UNCACHED(((struct lbuf*)lb)->buf))
5025 +#define PKTLEN(drv, lb) ((struct lbuf*)lb)->len
5026 +#define PKTHEADROOM(drv, lb) (0)
5027 +#define PKTTAILROOM(drv, lb) (0)
5028 +#define PKTNEXT(drv, lb) NULL
5029 +#define PKTSETNEXT(lb, x) ASSERT(0)
5030 +#define PKTSETLEN(drv, lb, bytes) ((struct lbuf*)lb)->len = bytes
5031 +#define PKTPUSH(drv, lb, bytes) ASSERT(0)
5032 +#define PKTPULL(drv, lb, bytes) ASSERT(0)
5033 +#define PKTDUP(drv, lb) ASSERT(0)
5034 +#define PKTLINK(lb) ((struct lbuf*)lb)->next
5035 +#define PKTSETLINK(lb, x) ((struct lbuf*)lb)->next = (struct lbuf*)x
5036 +#define PKTPRIO(lb) (0)
5037 +#define PKTSETPRIO(lb, x) do {} while (0)
5038 +extern void *et_pktget(void *drv, uint len, bool send);
5039 +extern void et_pktfree(void *drv, struct lbuf *lb, bool send);
5040 +
5041 +#endif /* _pmon_osl_h_ */
5042 diff -urN linux.old/arch/mips/bcm947xx/include/proto/802.11.h linux.dev/arch/mips/bcm947xx/include/proto/802.11.h
5043 --- linux.old/arch/mips/bcm947xx/include/proto/802.11.h 1970-01-01 01:00:00.000000000 +0100
5044 +++ linux.dev/arch/mips/bcm947xx/include/proto/802.11.h 2005-11-07 22:51:38.784726500 +0100
5045 @@ -0,0 +1,930 @@
5046 +/*
5047 + * Copyright 2005, Broadcom Corporation
5048 + * All Rights Reserved.
5049 + *
5050 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5051 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5052 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5053 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5054 + *
5055 + * Fundamental types and constants relating to 802.11
5056 + *
5057 + * $Id$
5058 + */
5059 +
5060 +#ifndef _802_11_H_
5061 +#define _802_11_H_
5062 +
5063 +#ifndef _TYPEDEFS_H_
5064 +#include <typedefs.h>
5065 +#endif
5066 +
5067 +#ifndef _NET_ETHERNET_H_
5068 +#include <proto/ethernet.h>
5069 +#endif
5070 +
5071 +#include <proto/wpa.h>
5072 +
5073 +
5074 +/* enable structure packing */
5075 +#if defined(__GNUC__)
5076 +#define PACKED __attribute__((packed))
5077 +#else
5078 +#pragma pack(1)
5079 +#define PACKED
5080 +#endif
5081 +
5082 +#define DOT11_TU_TO_US 1024 /* 802.11 Time Unit is 1024 microseconds */
5083 +
5084 +/* Generic 802.11 frame constants */
5085 +#define DOT11_A3_HDR_LEN 24
5086 +#define DOT11_A4_HDR_LEN 30
5087 +#define DOT11_MAC_HDR_LEN DOT11_A3_HDR_LEN
5088 +#define DOT11_FCS_LEN 4
5089 +#define DOT11_ICV_LEN 4
5090 +#define DOT11_ICV_AES_LEN 8
5091 +#define DOT11_QOS_LEN 2
5092 +
5093 +#define DOT11_KEY_INDEX_SHIFT 6
5094 +#define DOT11_IV_LEN 4
5095 +#define DOT11_IV_TKIP_LEN 8
5096 +#define DOT11_IV_AES_OCB_LEN 4
5097 +#define DOT11_IV_AES_CCM_LEN 8
5098 +
5099 +/* Includes MIC */
5100 +#define DOT11_MAX_MPDU_BODY_LEN 2304
5101 +/* A4 header + QoS + CCMP + PDU + ICV + FCS = 2352 */
5102 +#define DOT11_MAX_MPDU_LEN (DOT11_A4_HDR_LEN + \
5103 + DOT11_QOS_LEN + \
5104 + DOT11_IV_AES_CCM_LEN + \
5105 + DOT11_MAX_MPDU_BODY_LEN + \
5106 + DOT11_ICV_LEN + \
5107 + DOT11_FCS_LEN)
5108 +
5109 +#define DOT11_MAX_SSID_LEN 32
5110 +
5111 +/* dot11RTSThreshold */
5112 +#define DOT11_DEFAULT_RTS_LEN 2347
5113 +#define DOT11_MAX_RTS_LEN 2347
5114 +
5115 +/* dot11FragmentationThreshold */
5116 +#define DOT11_MIN_FRAG_LEN 256
5117 +#define DOT11_MAX_FRAG_LEN 2346 /* Max frag is also limited by aMPDUMaxLength of the attached PHY */
5118 +#define DOT11_DEFAULT_FRAG_LEN 2346
5119 +
5120 +/* dot11BeaconPeriod */
5121 +#define DOT11_MIN_BEACON_PERIOD 1
5122 +#define DOT11_MAX_BEACON_PERIOD 0xFFFF
5123 +
5124 +/* dot11DTIMPeriod */
5125 +#define DOT11_MIN_DTIM_PERIOD 1
5126 +#define DOT11_MAX_DTIM_PERIOD 0xFF
5127 +
5128 +/* 802.2 LLC/SNAP header used by 802.11 per 802.1H */
5129 +#define DOT11_LLC_SNAP_HDR_LEN 8
5130 +#define DOT11_OUI_LEN 3
5131 +struct dot11_llc_snap_header {
5132 + uint8 dsap; /* always 0xAA */
5133 + uint8 ssap; /* always 0xAA */
5134 + uint8 ctl; /* always 0x03 */
5135 + uint8 oui[DOT11_OUI_LEN]; /* RFC1042: 0x00 0x00 0x00
5136 + Bridge-Tunnel: 0x00 0x00 0xF8 */
5137 + uint16 type; /* ethertype */
5138 +} PACKED;
5139 +
5140 +/* RFC1042 header used by 802.11 per 802.1H */
5141 +#define RFC1042_HDR_LEN (ETHER_HDR_LEN + DOT11_LLC_SNAP_HDR_LEN)
5142 +
5143 +/* Generic 802.11 MAC header */
5144 +/*
5145 + * N.B.: This struct reflects the full 4 address 802.11 MAC header.
5146 + * The fields are defined such that the shorter 1, 2, and 3
5147 + * address headers just use the first k fields.
5148 + */
5149 +struct dot11_header {
5150 + uint16 fc; /* frame control */
5151 + uint16 durid; /* duration/ID */
5152 + struct ether_addr a1; /* address 1 */
5153 + struct ether_addr a2; /* address 2 */
5154 + struct ether_addr a3; /* address 3 */
5155 + uint16 seq; /* sequence control */
5156 + struct ether_addr a4; /* address 4 */
5157 +} PACKED;
5158 +
5159 +/* Control frames */
5160 +
5161 +struct dot11_rts_frame {
5162 + uint16 fc; /* frame control */
5163 + uint16 durid; /* duration/ID */
5164 + struct ether_addr ra; /* receiver address */
5165 + struct ether_addr ta; /* transmitter address */
5166 +} PACKED;
5167 +#define DOT11_RTS_LEN 16
5168 +
5169 +struct dot11_cts_frame {
5170 + uint16 fc; /* frame control */
5171 + uint16 durid; /* duration/ID */
5172 + struct ether_addr ra; /* receiver address */
5173 +} PACKED;
5174 +#define DOT11_CTS_LEN 10
5175 +
5176 +struct dot11_ack_frame {
5177 + uint16 fc; /* frame control */
5178 + uint16 durid; /* duration/ID */
5179 + struct ether_addr ra; /* receiver address */
5180 +} PACKED;
5181 +#define DOT11_ACK_LEN 10
5182 +
5183 +struct dot11_ps_poll_frame {
5184 + uint16 fc; /* frame control */
5185 + uint16 durid; /* AID */
5186 + struct ether_addr bssid; /* receiver address, STA in AP */
5187 + struct ether_addr ta; /* transmitter address */
5188 +} PACKED;
5189 +#define DOT11_PS_POLL_LEN 16
5190 +
5191 +struct dot11_cf_end_frame {
5192 + uint16 fc; /* frame control */
5193 + uint16 durid; /* duration/ID */
5194 + struct ether_addr ra; /* receiver address */
5195 + struct ether_addr bssid; /* transmitter address, STA in AP */
5196 +} PACKED;
5197 +#define DOT11_CS_END_LEN 16
5198 +
5199 +/* Management frame header */
5200 +struct dot11_management_header {
5201 + uint16 fc; /* frame control */
5202 + uint16 durid; /* duration/ID */
5203 + struct ether_addr da; /* receiver address */
5204 + struct ether_addr sa; /* transmitter address */
5205 + struct ether_addr bssid; /* BSS ID */
5206 + uint16 seq; /* sequence control */
5207 +} PACKED;
5208 +#define DOT11_MGMT_HDR_LEN 24
5209 +
5210 +/* Management frame payloads */
5211 +
5212 +struct dot11_bcn_prb {
5213 + uint32 timestamp[2];
5214 + uint16 beacon_interval;
5215 + uint16 capability;
5216 +} PACKED;
5217 +#define DOT11_BCN_PRB_LEN 12
5218 +
5219 +struct dot11_auth {
5220 + uint16 alg; /* algorithm */
5221 + uint16 seq; /* sequence control */
5222 + uint16 status; /* status code */
5223 +} PACKED;
5224 +#define DOT11_AUTH_FIXED_LEN 6 /* length of auth frame without challenge info elt */
5225 +
5226 +struct dot11_assoc_req {
5227 + uint16 capability; /* capability information */
5228 + uint16 listen; /* listen interval */
5229 +} PACKED;
5230 +#define DOT11_ASSOC_REQ_FIXED_LEN 4 /* length of assoc frame without info elts */
5231 +
5232 +struct dot11_reassoc_req {
5233 + uint16 capability; /* capability information */
5234 + uint16 listen; /* listen interval */
5235 + struct ether_addr ap; /* Current AP address */
5236 +} PACKED;
5237 +#define DOT11_REASSOC_REQ_FIXED_LEN 10 /* length of assoc frame without info elts */
5238 +
5239 +struct dot11_assoc_resp {
5240 + uint16 capability; /* capability information */
5241 + uint16 status; /* status code */
5242 + uint16 aid; /* association ID */
5243 +} PACKED;
5244 +
5245 +struct dot11_action_measure {
5246 + uint8 category;
5247 + uint8 action;
5248 + uint8 token;
5249 + uint8 data[1];
5250 +} PACKED;
5251 +#define DOT11_ACTION_MEASURE_LEN 3
5252 +
5253 +struct dot11_action_switch_channel {
5254 + uint8 category;
5255 + uint8 action;
5256 + uint8 data[5]; /* for switch IE */
5257 +} PACKED;
5258 +
5259 +/**************
5260 + 802.11h related definitions.
5261 +**************/
5262 +typedef struct {
5263 + uint8 id;
5264 + uint8 len;
5265 + uint8 power;
5266 +} dot11_power_cnst_t;
5267 +
5268 +typedef struct {
5269 + uint8 min;
5270 + uint8 max;
5271 +} dot11_power_cap_t;
5272 +
5273 +typedef struct {
5274 + uint8 id;
5275 + uint8 len;
5276 + uint8 tx_pwr;
5277 + uint8 margin;
5278 +} dot11_tpc_rep_t;
5279 +#define DOT11_MNG_IE_TPC_REPORT_LEN 2 /* length of IE data, not including 2 byte header */
5280 +
5281 +typedef struct {
5282 + uint8 id;
5283 + uint8 len;
5284 + uint8 first_channel;
5285 + uint8 num_channels;
5286 +} dot11_supp_channels_t;
5287 +
5288 +/* csa mode type */
5289 +#define DOT11_CSA_MODE_ADVISORY 0
5290 +#define DOT11_CSA_MODE_NO_TX 1
5291 +struct dot11_channel_switch {
5292 + uint8 id;
5293 + uint8 len;
5294 + uint8 mode;
5295 + uint8 channel;
5296 + uint8 count;
5297 +} PACKED;
5298 +typedef struct dot11_channel_switch dot11_channel_switch_t;
5299 +
5300 +/* length of IE data, not including 2 byte header */
5301 +#define DOT11_SWITCH_IE_LEN 3
5302 +
5303 +/* 802.11h Measurement Request/Report IEs */
5304 +/* Measurement Type field */
5305 +#define DOT11_MEASURE_TYPE_BASIC 0
5306 +#define DOT11_MEASURE_TYPE_CCA 1
5307 +#define DOT11_MEASURE_TYPE_RPI 2
5308 +
5309 +/* Measurement Mode field */
5310 +
5311 +/* Measurement Request Modes */
5312 +#define DOT11_MEASURE_MODE_ENABLE (1<<1)
5313 +#define DOT11_MEASURE_MODE_REQUEST (1<<2)
5314 +#define DOT11_MEASURE_MODE_REPORT (1<<3)
5315 +/* Measurement Report Modes */
5316 +#define DOT11_MEASURE_MODE_LATE (1<<0)
5317 +#define DOT11_MEASURE_MODE_INCAPABLE (1<<1)
5318 +#define DOT11_MEASURE_MODE_REFUSED (1<<2)
5319 +/* Basic Measurement Map bits */
5320 +#define DOT11_MEASURE_BASIC_MAP_BSS ((uint8)(1<<0))
5321 +#define DOT11_MEASURE_BASIC_MAP_OFDM ((uint8)(1<<1))
5322 +#define DOT11_MEASURE_BASIC_MAP_UKNOWN ((uint8)(1<<2))
5323 +#define DOT11_MEASURE_BASIC_MAP_RADAR ((uint8)(1<<3))
5324 +#define DOT11_MEASURE_BASIC_MAP_UNMEAS ((uint8)(1<<4))
5325 +
5326 +typedef struct {
5327 + uint8 id;
5328 + uint8 len;
5329 + uint8 token;
5330 + uint8 mode;
5331 + uint8 type;
5332 + uint8 channel;
5333 + uint8 start_time[8];
5334 + uint16 duration;
5335 +} dot11_meas_req_t;
5336 +#define DOT11_MNG_IE_MREQ_LEN 14
5337 +/* length of Measure Request IE data not including variable len */
5338 +#define DOT11_MNG_IE_MREQ_FIXED_LEN 3
5339 +
5340 +struct dot11_meas_rep {
5341 + uint8 id;
5342 + uint8 len;
5343 + uint8 token;
5344 + uint8 mode;
5345 + uint8 type;
5346 + union
5347 + {
5348 + struct {
5349 + uint8 channel;
5350 + uint8 start_time[8];
5351 + uint16 duration;
5352 + uint8 map;
5353 + } PACKED basic;
5354 + uint8 data[1];
5355 + } PACKED rep;
5356 +} PACKED;
5357 +typedef struct dot11_meas_rep dot11_meas_rep_t;
5358 +
5359 +/* length of Measure Report IE data not including variable len */
5360 +#define DOT11_MNG_IE_MREP_FIXED_LEN 3
5361 +
5362 +struct dot11_meas_rep_basic {
5363 + uint8 channel;
5364 + uint8 start_time[8];
5365 + uint16 duration;
5366 + uint8 map;
5367 +} PACKED;
5368 +typedef struct dot11_meas_rep_basic dot11_meas_rep_basic_t;
5369 +#define DOT11_MEASURE_BASIC_REP_LEN 12
5370 +
5371 +struct dot11_quiet {
5372 + uint8 id;
5373 + uint8 len;
5374 + uint8 count; /* TBTTs until beacon interval in quiet starts */
5375 + uint8 period; /* Beacon intervals between periodic quiet periods ? */
5376 + uint16 duration;/* Length of quiet period, in TU's */
5377 + uint16 offset; /* TU's offset from TBTT in Count field */
5378 +} PACKED;
5379 +typedef struct dot11_quiet dot11_quiet_t;
5380 +
5381 +typedef struct {
5382 + uint8 channel;
5383 + uint8 map;
5384 +} chan_map_tuple_t;
5385 +
5386 +typedef struct {
5387 + uint8 id;
5388 + uint8 len;
5389 + uint8 eaddr[ETHER_ADDR_LEN];
5390 + uint8 interval;
5391 + chan_map_tuple_t map[1];
5392 +} dot11_ibss_dfs_t;
5393 +
5394 +/* WME Elements */
5395 +#define WME_OUI "\x00\x50\xf2"
5396 +#define WME_VER 1
5397 +#define WME_TYPE 2
5398 +#define WME_SUBTYPE_IE 0 /* Information Element */
5399 +#define WME_SUBTYPE_PARAM_IE 1 /* Parameter Element */
5400 +#define WME_SUBTYPE_TSPEC 2 /* Traffic Specification */
5401 +
5402 +/* WME Access Category Indices (ACIs) */
5403 +#define AC_BE 0 /* Best Effort */
5404 +#define AC_BK 1 /* Background */
5405 +#define AC_VI 2 /* Video */
5406 +#define AC_VO 3 /* Voice */
5407 +#define AC_MAX 4
5408 +
5409 +/* WME Information Element (IE) */
5410 +struct wme_ie {
5411 + uint8 oui[3];
5412 + uint8 type;
5413 + uint8 subtype;
5414 + uint8 version;
5415 + uint8 acinfo;
5416 +} PACKED;
5417 +typedef struct wme_ie wme_ie_t;
5418 +#define WME_IE_LEN 7
5419 +
5420 +struct wme_acparam {
5421 + uint8 ACI;
5422 + uint8 ECW;
5423 + uint16 TXOP; /* stored in network order (ls octet first) */
5424 +} PACKED;
5425 +typedef struct wme_acparam wme_acparam_t;
5426 +
5427 +/* WME Parameter Element (PE) */
5428 +struct wme_params {
5429 + uint8 oui[3];
5430 + uint8 type;
5431 + uint8 subtype;
5432 + uint8 version;
5433 + uint8 acinfo;
5434 + uint8 rsvd;
5435 + wme_acparam_t acparam[4];
5436 +} PACKED;
5437 +typedef struct wme_params wme_params_t;
5438 +#define WME_PARAMS_IE_LEN 24
5439 +
5440 +/* acinfo */
5441 +#define WME_COUNT_MASK 0x0f
5442 +/* ACI */
5443 +#define WME_AIFS_MASK 0x0f
5444 +#define WME_ACM_MASK 0x10
5445 +#define WME_ACI_MASK 0x60
5446 +#define WME_ACI_SHIFT 5
5447 +/* ECW */
5448 +#define WME_CWMIN_MASK 0x0f
5449 +#define WME_CWMAX_MASK 0xf0
5450 +#define WME_CWMAX_SHIFT 4
5451 +
5452 +#define WME_TXOP_UNITS 32
5453 +
5454 +/* AP: default params to be announced in the Beacon Frames/Probe Responses Table 12 WME Draft*/
5455 +/* AP: default params to be Used in the AP Side Table 14 WME Draft January 2004 802.11-03-504r5 */
5456 +#define WME_AC_BK_ACI_STA 0x27
5457 +#define WME_AC_BK_ECW_STA 0xA4
5458 +#define WME_AC_BK_TXOP_STA 0x0000
5459 +#define WME_AC_BE_ACI_STA 0x03
5460 +#define WME_AC_BE_ECW_STA 0xA4
5461 +#define WME_AC_BE_TXOP_STA 0x0000
5462 +#define WME_AC_VI_ACI_STA 0x42
5463 +#define WME_AC_VI_ECW_STA 0x43
5464 +#define WME_AC_VI_TXOP_STA 0x005e
5465 +#define WME_AC_VO_ACI_STA 0x62
5466 +#define WME_AC_VO_ECW_STA 0x32
5467 +#define WME_AC_VO_TXOP_STA 0x002f
5468 +
5469 +#define WME_AC_BK_ACI_AP 0x27
5470 +#define WME_AC_BK_ECW_AP 0xA4
5471 +#define WME_AC_BK_TXOP_AP 0x0000
5472 +#define WME_AC_BE_ACI_AP 0x03
5473 +#define WME_AC_BE_ECW_AP 0x64
5474 +#define WME_AC_BE_TXOP_AP 0x0000
5475 +#define WME_AC_VI_ACI_AP 0x41
5476 +#define WME_AC_VI_ECW_AP 0x43
5477 +#define WME_AC_VI_TXOP_AP 0x005e
5478 +#define WME_AC_VO_ACI_AP 0x61
5479 +#define WME_AC_VO_ECW_AP 0x32
5480 +#define WME_AC_VO_TXOP_AP 0x002f
5481 +
5482 +/* WME Traffic Specification (TSPEC) element */
5483 +#define WME_SUBTYPE_TSPEC 2
5484 +#define WME_TSPEC_HDR_LEN 2
5485 +#define WME_TSPEC_BODY_OFF 2
5486 +struct wme_tspec {
5487 + uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
5488 + uint8 type; /* WME_TYPE */
5489 + uint8 subtype; /* WME_SUBTYPE_TSPEC */
5490 + uint8 version; /* WME_VERSION */
5491 + uint16 ts_info; /* TS Info */
5492 + uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
5493 + uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
5494 + uint32 min_service_interval; /* Minimum Service Interval (us) */
5495 + uint32 max_service_interval; /* Maximum Service Interval (us) */
5496 + uint32 inactivity_interval; /* Inactivity Interval (us) */
5497 + uint32 service_start; /* Service Start Time (us) */
5498 + uint32 min_rate; /* Minimum Data Rate (bps) */
5499 + uint32 mean_rate; /* Mean Data Rate (bps) */
5500 + uint32 max_burst_size; /* Maximum Burst Size (bytes) */
5501 + uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
5502 + uint32 peak_rate; /* Peak Data Rate (bps) */
5503 + uint32 delay_bound; /* Delay Bound (us) */
5504 + uint16 surplus_bandwidth; /* Surplus Bandwidth Allowance Factor */
5505 + uint16 medium_time; /* Medium Time (32 us/s periods) */
5506 +} PACKED;
5507 +typedef struct wme_tspec wme_tspec_t;
5508 +#define WME_TSPEC_LEN 56 /* not including 2-byte header */
5509 +
5510 +/* ts_info */
5511 +/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
5512 +#define TS_INFO_PRIO_SHIFT_HI 11
5513 +#define TS_INFO_PRIO_MASK_HI (0x7 << TS_INFO_PRIO_SHIFT_HI)
5514 +#define TS_INFO_PRIO_SHIFT_LO 1
5515 +#define TS_INFO_PRIO_MASK_LO (0x7 << TS_INFO_PRIO_SHIFT_LO)
5516 +#define TS_INFO_CONTENTION_SHIFT 7
5517 +#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT)
5518 +#define TS_INFO_DIRECTION_SHIFT 5
5519 +#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT)
5520 +#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT)
5521 +#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT)
5522 +#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT)
5523 +
5524 +/* nom_msdu_size */
5525 +#define FIXED_MSDU_SIZE 0x8000 /* MSDU size is fixed */
5526 +#define MSDU_SIZE_MASK 0x7fff /* (Nominal or fixed) MSDU size */
5527 +
5528 +/* surplus_bandwidth */
5529 +/* Represented as 3 bits of integer, binary point, 13 bits fraction */
5530 +#define INTEGER_SHIFT 13
5531 +#define FRACTION_MASK 0x1FFF
5532 +
5533 +/* Management Notification Frame */
5534 +struct dot11_management_notification {
5535 + uint8 category; /* DOT11_ACTION_NOTIFICATION */
5536 + uint8 action;
5537 + uint8 token;
5538 + uint8 status;
5539 + uint8 data[1]; /* Elements */
5540 +} PACKED;
5541 +#define DOT11_MGMT_NOTIFICATION_LEN 4 /* Fixed length */
5542 +
5543 +/* WME Action Codes */
5544 +#define WME_SETUP_REQUEST 0
5545 +#define WME_SETUP_RESPONSE 1
5546 +#define WME_TEARDOWN 2
5547 +
5548 +/* WME Setup Response Status Codes */
5549 +#define WME_ADMISSION_ACCEPTED 0
5550 +#define WME_INVALID_PARAMETERS 1
5551 +#define WME_ADMISSION_REFUSED 3
5552 +
5553 +/* Macro to take a pointer to a beacon or probe response
5554 + * header and return the char* pointer to the SSID info element
5555 + */
5556 +#define BCN_PRB_SSID(hdr) ((char*)(hdr) + DOT11_MGMT_HDR_LEN + DOT11_BCN_PRB_LEN)
5557 +
5558 +/* Authentication frame payload constants */
5559 +#define DOT11_OPEN_SYSTEM 0
5560 +#define DOT11_SHARED_KEY 1
5561 +#define DOT11_CHALLENGE_LEN 128
5562 +
5563 +/* Frame control macros */
5564 +#define FC_PVER_MASK 0x3
5565 +#define FC_PVER_SHIFT 0
5566 +#define FC_TYPE_MASK 0xC
5567 +#define FC_TYPE_SHIFT 2
5568 +#define FC_SUBTYPE_MASK 0xF0
5569 +#define FC_SUBTYPE_SHIFT 4
5570 +#define FC_TODS 0x100
5571 +#define FC_TODS_SHIFT 8
5572 +#define FC_FROMDS 0x200
5573 +#define FC_FROMDS_SHIFT 9
5574 +#define FC_MOREFRAG 0x400
5575 +#define FC_MOREFRAG_SHIFT 10
5576 +#define FC_RETRY 0x800
5577 +#define FC_RETRY_SHIFT 11
5578 +#define FC_PM 0x1000
5579 +#define FC_PM_SHIFT 12
5580 +#define FC_MOREDATA 0x2000
5581 +#define FC_MOREDATA_SHIFT 13
5582 +#define FC_WEP 0x4000
5583 +#define FC_WEP_SHIFT 14
5584 +#define FC_ORDER 0x8000
5585 +#define FC_ORDER_SHIFT 15
5586 +
5587 +/* sequence control macros */
5588 +#define SEQNUM_SHIFT 4
5589 +#define FRAGNUM_MASK 0xF
5590 +
5591 +/* Frame Control type/subtype defs */
5592 +
5593 +/* FC Types */
5594 +#define FC_TYPE_MNG 0
5595 +#define FC_TYPE_CTL 1
5596 +#define FC_TYPE_DATA 2
5597 +
5598 +/* Management Subtypes */
5599 +#define FC_SUBTYPE_ASSOC_REQ 0
5600 +#define FC_SUBTYPE_ASSOC_RESP 1
5601 +#define FC_SUBTYPE_REASSOC_REQ 2
5602 +#define FC_SUBTYPE_REASSOC_RESP 3
5603 +#define FC_SUBTYPE_PROBE_REQ 4
5604 +#define FC_SUBTYPE_PROBE_RESP 5
5605 +#define FC_SUBTYPE_BEACON 8
5606 +#define FC_SUBTYPE_ATIM 9
5607 +#define FC_SUBTYPE_DISASSOC 10
5608 +#define FC_SUBTYPE_AUTH 11
5609 +#define FC_SUBTYPE_DEAUTH 12
5610 +#define FC_SUBTYPE_ACTION 13
5611 +
5612 +/* Control Subtypes */
5613 +#define FC_SUBTYPE_PS_POLL 10
5614 +#define FC_SUBTYPE_RTS 11
5615 +#define FC_SUBTYPE_CTS 12
5616 +#define FC_SUBTYPE_ACK 13
5617 +#define FC_SUBTYPE_CF_END 14
5618 +#define FC_SUBTYPE_CF_END_ACK 15
5619 +
5620 +/* Data Subtypes */
5621 +#define FC_SUBTYPE_DATA 0
5622 +#define FC_SUBTYPE_DATA_CF_ACK 1
5623 +#define FC_SUBTYPE_DATA_CF_POLL 2
5624 +#define FC_SUBTYPE_DATA_CF_ACK_POLL 3
5625 +#define FC_SUBTYPE_NULL 4
5626 +#define FC_SUBTYPE_CF_ACK 5
5627 +#define FC_SUBTYPE_CF_POLL 6
5628 +#define FC_SUBTYPE_CF_ACK_POLL 7
5629 +#define FC_SUBTYPE_QOS_DATA 8
5630 +#define FC_SUBTYPE_QOS_NULL 12
5631 +
5632 +/* type-subtype combos */
5633 +#define FC_KIND_MASK (FC_TYPE_MASK | FC_SUBTYPE_MASK)
5634 +
5635 +#define FC_KIND(t, s) (((t) << FC_TYPE_SHIFT) | ((s) << FC_SUBTYPE_SHIFT))
5636 +
5637 +#define FC_ASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_REQ)
5638 +#define FC_ASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ASSOC_RESP)
5639 +#define FC_REASSOC_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_REQ)
5640 +#define FC_REASSOC_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_REASSOC_RESP)
5641 +#define FC_PROBE_REQ FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_REQ)
5642 +#define FC_PROBE_RESP FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_PROBE_RESP)
5643 +#define FC_BEACON FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_BEACON)
5644 +#define FC_DISASSOC FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DISASSOC)
5645 +#define FC_AUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_AUTH)
5646 +#define FC_DEAUTH FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_DEAUTH)
5647 +#define FC_ACTION FC_KIND(FC_TYPE_MNG, FC_SUBTYPE_ACTION)
5648 +
5649 +#define FC_PS_POLL FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_PS_POLL)
5650 +#define FC_RTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_RTS)
5651 +#define FC_CTS FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CTS)
5652 +#define FC_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_ACK)
5653 +#define FC_CF_END FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END)
5654 +#define FC_CF_END_ACK FC_KIND(FC_TYPE_CTL, FC_SUBTYPE_CF_END_ACK)
5655 +
5656 +#define FC_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA)
5657 +#define FC_NULL_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_NULL)
5658 +#define FC_DATA_CF_ACK FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_DATA_CF_ACK)
5659 +#define FC_QOS_DATA FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_DATA)
5660 +#define FC_QOS_NULL FC_KIND(FC_TYPE_DATA, FC_SUBTYPE_QOS_NULL)
5661 +
5662 +/* QoS Control Field */
5663 +
5664 +/* 802.1D Tag */
5665 +#define QOS_PRIO_SHIFT 0
5666 +#define QOS_PRIO_MASK 0x0007
5667 +#define QOS_PRIO(qos) (((qos) & QOS_PRIO_MASK) >> QOS_PRIO_SHIFT)
5668 +
5669 +#define QOS_TID_SHIFT 0
5670 +#define QOS_TID_MASK 0x000f
5671 +#define QOS_TID(qos) (((qos) & QOS_TID_MASK) >> QOS_TID_SHIFT)
5672 +
5673 +/* Ack Policy (0 means Acknowledge) */
5674 +#define QOS_ACK_SHIFT 5
5675 +#define QOS_ACK_MASK 0x0060
5676 +#define QOS_ACK(qos) (((qos) & QOS_ACK_MASK) >> QOS_ACK_SHIFT)
5677 +
5678 +/* Management Frames */
5679 +
5680 +/* Management Frame Constants */
5681 +
5682 +/* Fixed fields */
5683 +#define DOT11_MNG_AUTH_ALGO_LEN 2
5684 +#define DOT11_MNG_AUTH_SEQ_LEN 2
5685 +#define DOT11_MNG_BEACON_INT_LEN 2
5686 +#define DOT11_MNG_CAP_LEN 2
5687 +#define DOT11_MNG_AP_ADDR_LEN 6
5688 +#define DOT11_MNG_LISTEN_INT_LEN 2
5689 +#define DOT11_MNG_REASON_LEN 2
5690 +#define DOT11_MNG_AID_LEN 2
5691 +#define DOT11_MNG_STATUS_LEN 2
5692 +#define DOT11_MNG_TIMESTAMP_LEN 8
5693 +
5694 +/* DUR/ID field in assoc resp is 0xc000 | AID */
5695 +#define DOT11_AID_MASK 0x3fff
5696 +
5697 +/* Reason Codes */
5698 +#define DOT11_RC_RESERVED 0
5699 +#define DOT11_RC_UNSPECIFIED 1 /* Unspecified reason */
5700 +#define DOT11_RC_AUTH_INVAL 2 /* Previous authentication no longer valid */
5701 +#define DOT11_RC_DEAUTH_LEAVING 3 /* Deauthenticated because sending station is
5702 + leaving (or has left) IBSS or ESS */
5703 +#define DOT11_RC_INACTIVITY 4 /* Disassociated due to inactivity */
5704 +#define DOT11_RC_BUSY 5 /* Disassociated because AP is unable to handle
5705 + all currently associated stations */
5706 +#define DOT11_RC_INVAL_CLASS_2 6 /* Class 2 frame received from
5707 + nonauthenticated station */
5708 +#define DOT11_RC_INVAL_CLASS_3 7 /* Class 3 frame received from
5709 + nonassociated station */
5710 +#define DOT11_RC_DISASSOC_LEAVING 8 /* Disassociated because sending station is
5711 + leaving (or has left) BSS */
5712 +#define DOT11_RC_NOT_AUTH 9 /* Station requesting (re)association is
5713 + not authenticated with responding station */
5714 +#define DOT11_RC_MAX 23 /* Reason codes > 23 are reserved */
5715 +
5716 +/* Status Codes */
5717 +#define DOT11_STATUS_SUCCESS 0 /* Successful */
5718 +#define DOT11_STATUS_FAILURE 1 /* Unspecified failure */
5719 +#define DOT11_STATUS_CAP_MISMATCH 10 /* Cannot support all requested capabilities
5720 + in the Capability Information field */
5721 +#define DOT11_STATUS_REASSOC_FAIL 11 /* Reassociation denied due to inability to
5722 + confirm that association exists */
5723 +#define DOT11_STATUS_ASSOC_FAIL 12 /* Association denied due to reason outside
5724 + the scope of this standard */
5725 +#define DOT11_STATUS_AUTH_MISMATCH 13 /* Responding station does not support the
5726 + specified authentication algorithm */
5727 +#define DOT11_STATUS_AUTH_SEQ 14 /* Received an Authentication frame with
5728 + authentication transaction sequence number
5729 + out of expected sequence */
5730 +#define DOT11_STATUS_AUTH_CHALLENGE_FAIL 15 /* Authentication rejected because of challenge failure */
5731 +#define DOT11_STATUS_AUTH_TIMEOUT 16 /* Authentication rejected due to timeout waiting
5732 + for next frame in sequence */
5733 +#define DOT11_STATUS_ASSOC_BUSY_FAIL 17 /* Association denied because AP is unable to
5734 + handle additional associated stations */
5735 +#define DOT11_STATUS_ASSOC_RATE_MISMATCH 18 /* Association denied due to requesting station
5736 + not supporting all of the data rates in the
5737 + BSSBasicRateSet parameter */
5738 +#define DOT11_STATUS_ASSOC_SHORT_REQUIRED 19 /* Association denied due to requesting station
5739 + not supporting the Short Preamble option */
5740 +#define DOT11_STATUS_ASSOC_PBCC_REQUIRED 20 /* Association denied due to requesting station
5741 + not supporting the PBCC Modulation option */
5742 +#define DOT11_STATUS_ASSOC_AGILITY_REQUIRED 21 /* Association denied due to requesting station
5743 + not supporting the Channel Agility option */
5744 +#define DOT11_STATUS_ASSOC_SPECTRUM_REQUIRED 22 /* Association denied because Spectrum Management
5745 + capability is required. */
5746 +#define DOT11_STATUS_ASSOC_BAD_POWER_CAP 23 /* Association denied because the info in the
5747 + Power Cap element is unacceptable. */
5748 +#define DOT11_STATUS_ASSOC_BAD_SUP_CHANNELS 24 /* Association denied because the info in the
5749 + Supported Channel element is unacceptable */
5750 +#define DOT11_STATUS_ASSOC_SHORTSLOT_REQUIRED 25 /* Association denied due to requesting station
5751 + not supporting the Short Slot Time option */
5752 +#define DOT11_STATUS_ASSOC_ERPBCC_REQUIRED 26 /* Association denied due to requesting station
5753 + not supporting the ER-PBCC Modulation option */
5754 +#define DOT11_STATUS_ASSOC_DSSOFDM_REQUIRED 27 /* Association denied due to requesting station
5755 + not supporting the DSS-OFDM option */
5756 +
5757 +/* Info Elts, length of INFORMATION portion of Info Elts */
5758 +#define DOT11_MNG_DS_PARAM_LEN 1
5759 +#define DOT11_MNG_IBSS_PARAM_LEN 2
5760 +
5761 +/* TIM Info element has 3 bytes fixed info in INFORMATION field,
5762 + * followed by 1 to 251 bytes of Partial Virtual Bitmap */
5763 +#define DOT11_MNG_TIM_FIXED_LEN 3
5764 +#define DOT11_MNG_TIM_DTIM_COUNT 0
5765 +#define DOT11_MNG_TIM_DTIM_PERIOD 1
5766 +#define DOT11_MNG_TIM_BITMAP_CTL 2
5767 +#define DOT11_MNG_TIM_PVB 3
5768 +
5769 +/* TLV defines */
5770 +#define TLV_TAG_OFF 0
5771 +#define TLV_LEN_OFF 1
5772 +#define TLV_HDR_LEN 2
5773 +#define TLV_BODY_OFF 2
5774 +
5775 +/* Management Frame Information Element IDs */
5776 +#define DOT11_MNG_SSID_ID 0
5777 +#define DOT11_MNG_RATES_ID 1
5778 +#define DOT11_MNG_FH_PARMS_ID 2
5779 +#define DOT11_MNG_DS_PARMS_ID 3
5780 +#define DOT11_MNG_CF_PARMS_ID 4
5781 +#define DOT11_MNG_TIM_ID 5
5782 +#define DOT11_MNG_IBSS_PARMS_ID 6
5783 +#define DOT11_MNG_COUNTRY_ID 7
5784 +#define DOT11_MNG_HOPPING_PARMS_ID 8
5785 +#define DOT11_MNG_HOPPING_TABLE_ID 9
5786 +#define DOT11_MNG_REQUEST_ID 10
5787 +#define DOT11_MNG_CHALLENGE_ID 16
5788 +#define DOT11_MNG_PWR_CONSTRAINT_ID 32 /* 11H PowerConstraint */
5789 +#define DOT11_MNG_PWR_CAP_ID 33 /* 11H PowerCapability */
5790 +#define DOT11_MNG_TPC_REQUEST_ID 34 /* 11H TPC Request */
5791 +#define DOT11_MNG_TPC_REPORT_ID 35 /* 11H TPC Report */
5792 +#define DOT11_MNG_SUPP_CHANNELS_ID 36 /* 11H Supported Channels */
5793 +#define DOT11_MNG_CHANNEL_SWITCH_ID 37 /* 11H ChannelSwitch Announcement*/
5794 +#define DOT11_MNG_MEASURE_REQUEST_ID 38 /* 11H MeasurementRequest */
5795 +#define DOT11_MNG_MEASURE_REPORT_ID 39 /* 11H MeasurementReport */
5796 +#define DOT11_MNG_QUIET_ID 40 /* 11H Quiet */
5797 +#define DOT11_MNG_IBSS_DFS_ID 41 /* 11H IBSS_DFS */
5798 +#define DOT11_MNG_ERP_ID 42
5799 +#define DOT11_MNG_NONERP_ID 47
5800 +#ifdef BCMWPA2
5801 +#define DOT11_MNG_RSN_ID 48
5802 +#endif /* BCMWPA2 */
5803 +#define DOT11_MNG_EXT_RATES_ID 50
5804 +#define DOT11_MNG_WPA_ID 221
5805 +#define DOT11_MNG_PROPR_ID 221
5806 +
5807 +/* ERP info element bit values */
5808 +#define DOT11_MNG_ERP_LEN 1 /* ERP is currently 1 byte long */
5809 +#define DOT11_MNG_NONERP_PRESENT 0x01 /* NonERP (802.11b) STAs are present in the BSS */
5810 +#define DOT11_MNG_USE_PROTECTION 0x02 /* Use protection mechanisms for ERP-OFDM frames */
5811 +#define DOT11_MNG_BARKER_PREAMBLE 0x04 /* Short Preambles: 0 == allowed, 1 == not allowed */
5812 +
5813 +/* Capability Information Field */
5814 +#define DOT11_CAP_ESS 0x0001
5815 +#define DOT11_CAP_IBSS 0x0002
5816 +#define DOT11_CAP_POLLABLE 0x0004
5817 +#define DOT11_CAP_POLL_RQ 0x0008
5818 +#define DOT11_CAP_PRIVACY 0x0010
5819 +#define DOT11_CAP_SHORT 0x0020
5820 +#define DOT11_CAP_PBCC 0x0040
5821 +#define DOT11_CAP_AGILITY 0x0080
5822 +#define DOT11_CAP_SPECTRUM 0x0100
5823 +#define DOT11_CAP_SHORTSLOT 0x0400
5824 +#define DOT11_CAP_CCK_OFDM 0x2000
5825 +
5826 +/* Action Frame Constants */
5827 +#define DOT11_ACTION_CAT_ERR_MASK 0x80
5828 +#define DOT11_ACTION_CAT_SPECT_MNG 0x00
5829 +#define DOT11_ACTION_NOTIFICATION 0x11 /* 17 */
5830 +
5831 +#define DOT11_ACTION_ID_M_REQ 0
5832 +#define DOT11_ACTION_ID_M_REP 1
5833 +#define DOT11_ACTION_ID_TPC_REQ 2
5834 +#define DOT11_ACTION_ID_TPC_REP 3
5835 +#define DOT11_ACTION_ID_CHANNEL_SWITCH 4
5836 +
5837 +/* MLME Enumerations */
5838 +#define DOT11_BSSTYPE_INFRASTRUCTURE 0
5839 +#define DOT11_BSSTYPE_INDEPENDENT 1
5840 +#define DOT11_BSSTYPE_ANY 2
5841 +#define DOT11_SCANTYPE_ACTIVE 0
5842 +#define DOT11_SCANTYPE_PASSIVE 1
5843 +
5844 +/* 802.11 A PHY constants */
5845 +#define APHY_SLOT_TIME 9
5846 +#define APHY_SIFS_TIME 16
5847 +#define APHY_DIFS_TIME (APHY_SIFS_TIME + (2 * APHY_SLOT_TIME))
5848 +#define APHY_PREAMBLE_TIME 16
5849 +#define APHY_SIGNAL_TIME 4
5850 +#define APHY_SYMBOL_TIME 4
5851 +#define APHY_SERVICE_NBITS 16
5852 +#define APHY_TAIL_NBITS 6
5853 +#define APHY_CWMIN 15
5854 +
5855 +/* 802.11 B PHY constants */
5856 +#define BPHY_SLOT_TIME 20
5857 +#define BPHY_SIFS_TIME 10
5858 +#define BPHY_DIFS_TIME 50
5859 +#define BPHY_PLCP_TIME 192
5860 +#define BPHY_PLCP_SHORT_TIME 96
5861 +#define BPHY_CWMIN 31
5862 +
5863 +/* 802.11 G constants */
5864 +#define DOT11_OFDM_SIGNAL_EXTENSION 6
5865 +
5866 +#define PHY_CWMAX 1023
5867 +
5868 +#define DOT11_MAXNUMFRAGS 16 /* max # fragments per MSDU */
5869 +
5870 +/* dot11Counters Table - 802.11 spec., Annex D */
5871 +typedef struct d11cnt {
5872 + uint32 txfrag; /* dot11TransmittedFragmentCount */
5873 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
5874 + uint32 txfail; /* dot11FailedCount */
5875 + uint32 txretry; /* dot11RetryCount */
5876 + uint32 txretrie; /* dot11MultipleRetryCount */
5877 + uint32 rxdup; /* dot11FrameduplicateCount */
5878 + uint32 txrts; /* dot11RTSSuccessCount */
5879 + uint32 txnocts; /* dot11RTSFailureCount */
5880 + uint32 txnoack; /* dot11ACKFailureCount */
5881 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
5882 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
5883 + uint32 rxcrc; /* dot11FCSErrorCount */
5884 + uint32 txfrmsnt; /* dot11TransmittedFrameCount */
5885 + uint32 rxundec; /* dot11WEPUndecryptableCount */
5886 +} d11cnt_t;
5887 +
5888 +/* BRCM OUI */
5889 +#define BRCM_OUI "\x00\x10\x18"
5890 +
5891 +/* BRCM info element */
5892 +struct brcm_ie {
5893 + uchar id; /* 221, DOT11_MNG_PROPR_ID */
5894 + uchar len;
5895 + uchar oui[3];
5896 + uchar ver;
5897 + uchar assoc; /* # of assoc STAs */
5898 + uchar flags; /* misc flags */
5899 +} PACKED;
5900 +#define BRCM_IE_LEN 8
5901 +typedef struct brcm_ie brcm_ie_t;
5902 +#define BRCM_IE_VER 2
5903 +#define BRCM_IE_LEGACY_AES_VER 1
5904 +
5905 +/* brcm_ie flags */
5906 +#define BRF_ABCAP 0x1 /* afterburner capable */
5907 +#define BRF_ABRQRD 0x2 /* afterburner requested */
5908 +#define BRF_LZWDS 0x4 /* lazy wds enabled */
5909 +#define BRF_ABCOUNTER_MASK 0xf0 /* afterburner wds "state" counter */
5910 +#define BRF_ABCOUNTER_SHIFT 4
5911 +
5912 +#define AB_WDS_TIMEOUT_MAX 15 /* afterburner wds Max count indicating not locally capable */
5913 +#define AB_WDS_TIMEOUT_MIN 1 /* afterburner wds, use zero count as indicating "downrev" */
5914 +
5915 +
5916 +/* OUI for BRCM proprietary IE */
5917 +#define BRCM_PROP_OUI "\x00\x90\x4C"
5918 +
5919 +/* Vendor IE structure */
5920 +struct vndr_ie {
5921 + uchar id;
5922 + uchar len;
5923 + uchar oui [3];
5924 + uchar data [1]; /* Variable size data */
5925 +}PACKED;
5926 +typedef struct vndr_ie vndr_ie_t;
5927 +
5928 +#define VNDR_IE_HDR_LEN 2 /* id + len field */
5929 +#define VNDR_IE_MIN_LEN 3 /* size of the oui field */
5930 +#define VNDR_IE_MAX_LEN 256
5931 +
5932 +/* WPA definitions */
5933 +#define WPA_VERSION 1
5934 +#define WPA_OUI "\x00\x50\xF2"
5935 +
5936 +#ifdef BCMWPA2
5937 +#define WPA2_VERSION 1
5938 +#define WPA2_VERSION_LEN 2
5939 +#define WPA2_OUI "\x00\x0F\xAC"
5940 +#endif /* BCMWPA2 */
5941 +
5942 +#define WPA_OUI_LEN 3
5943 +
5944 +/* RSN authenticated key managment suite */
5945 +#define RSN_AKM_NONE 0 /* None (IBSS) */
5946 +#define RSN_AKM_UNSPECIFIED 1 /* Over 802.1x */
5947 +#define RSN_AKM_PSK 2 /* Pre-shared Key */
5948 +
5949 +
5950 +/* Key related defines */
5951 +#define DOT11_MAX_DEFAULT_KEYS 4 /* number of default keys */
5952 +#define DOT11_MAX_KEY_SIZE 32 /* max size of any key */
5953 +#define DOT11_MAX_IV_SIZE 16 /* max size of any IV */
5954 +#define DOT11_EXT_IV_FLAG (1<<5) /* flag to indicate IV is > 4 bytes */
5955 +
5956 +#define WEP1_KEY_SIZE 5 /* max size of any WEP key */
5957 +#define WEP1_KEY_HEX_SIZE 10 /* size of WEP key in hex. */
5958 +#define WEP128_KEY_SIZE 13 /* max size of any WEP key */
5959 +#define WEP128_KEY_HEX_SIZE 26 /* size of WEP key in hex. */
5960 +#define TKIP_MIC_SIZE 8 /* size of TKIP MIC */
5961 +#define TKIP_EOM_SIZE 7 /* max size of TKIP EOM */
5962 +#define TKIP_EOM_FLAG 0x5a /* TKIP EOM flag byte */
5963 +#define TKIP_KEY_SIZE 32 /* size of any TKIP key */
5964 +#define TKIP_MIC_AUTH_TX 16 /* offset to Authenticator MIC TX key */
5965 +#define TKIP_MIC_AUTH_RX 24 /* offset to Authenticator MIC RX key */
5966 +#define TKIP_MIC_SUP_RX 16 /* offset to Supplicant MIC RX key */
5967 +#define TKIP_MIC_SUP_TX 24 /* offset to Supplicant MIC TX key */
5968 +#define AES_KEY_SIZE 16 /* size of AES key */
5969 +
5970 +#undef PACKED
5971 +#if !defined(__GNUC__)
5972 +#pragma pack()
5973 +#endif
5974 +
5975 +#endif /* _802_11_H_ */
5976 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h
5977 --- linux.old/arch/mips/bcm947xx/include/proto/bcmeth.h 1970-01-01 01:00:00.000000000 +0100
5978 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmeth.h 2005-11-07 22:51:38.784726500 +0100
5979 @@ -0,0 +1,103 @@
5980 +/*
5981 + * Broadcom Ethernettype protocol definitions
5982 + *
5983 + * Copyright 2005, Broadcom Corporation
5984 + * All Rights Reserved.
5985 + *
5986 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5987 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5988 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5989 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5990 + *
5991 + */
5992 +
5993 +/*
5994 + * Broadcom Ethernet protocol defines
5995 + *
5996 + */
5997 +
5998 +#ifndef _BCMETH_H_
5999 +#define _BCMETH_H_
6000 +
6001 +/* enable structure packing */
6002 +#if defined(__GNUC__)
6003 +#define PACKED __attribute__((packed))
6004 +#else
6005 +#pragma pack(1)
6006 +#define PACKED
6007 +#endif
6008 +
6009 +/* ETHER_TYPE_BRCM is defined in ethernet.h */
6010 +
6011 +/*
6012 + * Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
6013 + * in one of two formats: (only subtypes 32768-65535 are in use now)
6014 + *
6015 + * subtypes 0-32767:
6016 + * 8 bit subtype (0-127)
6017 + * 8 bit length in bytes (0-255)
6018 + *
6019 + * subtypes 32768-65535:
6020 + * 16 bit big-endian subtype
6021 + * 16 bit big-endian length in bytes (0-65535)
6022 + *
6023 + * length is the number of additional bytes beyond the 4 or 6 byte header
6024 + *
6025 + * Reserved values:
6026 + * 0 reserved
6027 + * 5-15 reserved for iLine protocol assignments
6028 + * 17-126 reserved, assignable
6029 + * 127 reserved
6030 + * 32768 reserved
6031 + * 32769-65534 reserved, assignable
6032 + * 65535 reserved
6033 + */
6034 +
6035 +/*
6036 + * While adding the subtypes and their specific processing code make sure
6037 + * bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
6038 + */
6039 +
6040 +#define BCMILCP_SUBTYPE_RATE 1
6041 +#define BCMILCP_SUBTYPE_LINK 2
6042 +#define BCMILCP_SUBTYPE_CSA 3
6043 +#define BCMILCP_SUBTYPE_LARQ 4
6044 +#define BCMILCP_SUBTYPE_VENDOR 5
6045 +#define BCMILCP_SUBTYPE_FLH 17
6046 +
6047 +#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
6048 +#define BCMILCP_SUBTYPE_CERT 32770
6049 +#define BCMILCP_SUBTYPE_SES 32771
6050 +
6051 +
6052 +#define BCMILCP_BCM_SUBTYPE_RESERVED 0
6053 +#define BCMILCP_BCM_SUBTYPE_EVENT 1
6054 +#define BCMILCP_BCM_SUBTYPE_SES 2
6055 +/*
6056 +The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
6057 +within BCMILCP_BCM_SUBTYPE_EVENT type messages
6058 +*/
6059 +/*#define BCMILCP_BCM_SUBTYPE_EAPOL 3*/
6060 +
6061 +#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
6062 +#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
6063 +
6064 +/* These fields are stored in network order */
6065 +typedef struct bcmeth_hdr
6066 +{
6067 + uint16 subtype; /* Vendor specific..32769*/
6068 + uint16 length;
6069 + uint8 version; /* Version is 0*/
6070 + uint8 oui[3]; /* Broadcom OUI*/
6071 + /* user specific Data */
6072 + uint16 usr_subtype;
6073 +} PACKED bcmeth_hdr_t;
6074 +
6075 +
6076 +
6077 +#undef PACKED
6078 +#if !defined(__GNUC__)
6079 +#pragma pack()
6080 +#endif
6081 +
6082 +#endif
6083 diff -urN linux.old/arch/mips/bcm947xx/include/proto/bcmip.h linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h
6084 --- linux.old/arch/mips/bcm947xx/include/proto/bcmip.h 1970-01-01 01:00:00.000000000 +0100
6085 +++ linux.dev/arch/mips/bcm947xx/include/proto/bcmip.h 2005-11-08 00:15:47.881307500 +0100
6086 @@ -0,0 +1,42 @@
6087 +/*
6088 + * Copyright 2005, Broadcom Corporation
6089 + * All Rights Reserved.
6090 + *
6091 + * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
6092 + * the contents of this file may not be disclosed to third parties, copied
6093 + * or duplicated in any form, in whole or in part, without the prior
6094 + * written permission of Broadcom Corporation.
6095 + *
6096 + * Fundamental constants relating to IP Protocol
6097 + *
6098 + * $Id$
6099 + */
6100 +
6101 +#ifndef _bcmip_h_
6102 +#define _bcmip_h_
6103 +
6104 +/* IP header */
6105 +#define IPV4_VERIHL_OFFSET 0 /* version and ihl byte offset */
6106 +#define IPV4_TOS_OFFSET 1 /* TOS offset */
6107 +#define IPV4_PROT_OFFSET 9 /* protocol type offset */
6108 +#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
6109 +#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
6110 +#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
6111 +
6112 +#define IPV4_VER_MASK 0xf0
6113 +#define IPV4_IHL_MASK 0x0f
6114 +
6115 +#define IPV4_PROT_UDP 17 /* UDP protocol type */
6116 +
6117 +#define IPV4_ADDR_LEN 4 /* IP v4 address length */
6118 +
6119 +#define IPV4_VER_NUM 0x40 /* IP v4 version number */
6120 +
6121 +/* NULL IP address check */
6122 +#define IPV4_ISNULLADDR(a) ((((uint8 *)(a))[0] + ((uint8 *)(a))[1] + \
6123 + ((uint8 *)(a))[2] + ((uint8 *)(a))[3]) == 0)
6124 +
6125 +#define IPV4_ADDR_STR_LEN 16
6126 +
6127 +#endif /* #ifndef _bcmip_h_ */
6128 +
6129 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
6130 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
6131 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-11-07 22:51:38.784726500 +0100
6132 @@ -0,0 +1,169 @@
6133 +/*******************************************************************************
6134 + * $Id$
6135 + * Copyright 2005, Broadcom Corporation
6136 + * All Rights Reserved.
6137 + *
6138 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6139 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6140 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6141 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6142 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
6143 + ******************************************************************************/
6144 +
6145 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
6146 +#define _NET_ETHERNET_H_
6147 +
6148 +#ifndef _TYPEDEFS_H_
6149 +#include "typedefs.h"
6150 +#endif
6151 +
6152 +/* enable structure packing */
6153 +#if defined(__GNUC__)
6154 +#define PACKED __attribute__((packed))
6155 +#else
6156 +#pragma pack(1)
6157 +#define PACKED
6158 +#endif
6159 +
6160 +/*
6161 + * The number of bytes in an ethernet (MAC) address.
6162 + */
6163 +#define ETHER_ADDR_LEN 6
6164 +
6165 +/*
6166 + * The number of bytes in the type field.
6167 + */
6168 +#define ETHER_TYPE_LEN 2
6169 +
6170 +/*
6171 + * The number of bytes in the trailing CRC field.
6172 + */
6173 +#define ETHER_CRC_LEN 4
6174 +
6175 +/*
6176 + * The length of the combined header.
6177 + */
6178 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
6179 +
6180 +/*
6181 + * The minimum packet length.
6182 + */
6183 +#define ETHER_MIN_LEN 64
6184 +
6185 +/*
6186 + * The minimum packet user data length.
6187 + */
6188 +#define ETHER_MIN_DATA 46
6189 +
6190 +/*
6191 + * The maximum packet length.
6192 + */
6193 +#define ETHER_MAX_LEN 1518
6194 +
6195 +/*
6196 + * The maximum packet user data length.
6197 + */
6198 +#define ETHER_MAX_DATA 1500
6199 +
6200 +/* ether types */
6201 +#define ETHER_TYPE_IP 0x0800 /* IP */
6202 +#define ETHER_TYPE_ARP 0x0806 /* ARP */
6203 +#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
6204 +#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
6205 +#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
6206 +#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication*/
6207 +
6208 +/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
6209 +#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
6210 +#define ETHER_BRCM_CRAM 0x1 /* Broadcom subtype cram protocol */
6211 +
6212 +/* ether header */
6213 +#define ETHER_DEST_OFFSET 0 /* dest address offset */
6214 +#define ETHER_SRC_OFFSET 6 /* src address offset */
6215 +#define ETHER_TYPE_OFFSET 12 /* ether type offset */
6216 +
6217 +/*
6218 + * A macro to validate a length with
6219 + */
6220 +#define ETHER_IS_VALID_LEN(foo) \
6221 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
6222 +
6223 +
6224 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
6225 +/*
6226 + * Structure of a 10Mb/s Ethernet header.
6227 + */
6228 +struct ether_header {
6229 + uint8 ether_dhost[ETHER_ADDR_LEN];
6230 + uint8 ether_shost[ETHER_ADDR_LEN];
6231 + uint16 ether_type;
6232 +} PACKED;
6233 +
6234 +/*
6235 + * Structure of a 48-bit Ethernet address.
6236 + */
6237 +struct ether_addr {
6238 + uint8 octet[ETHER_ADDR_LEN];
6239 +} PACKED;
6240 +#endif
6241 +
6242 +/*
6243 + * Takes a pointer, sets locally admininistered
6244 + * address bit in the 48-bit Ethernet address.
6245 + */
6246 +#define ETHER_SET_LOCALADDR(ea) ( ((uint8 *)(ea))[0] = \
6247 + (((uint8 *)(ea))[0] | 2) )
6248 +
6249 +/*
6250 + * Takes a pointer, returns true if a 48-bit multicast address
6251 + * (including broadcast, since it is all ones)
6252 + */
6253 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
6254 +
6255 +
6256 +/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
6257 +#define ether_cmp(a, b) ( \
6258 + !(((short*)a)[0] == ((short*)b)[0]) | \
6259 + !(((short*)a)[1] == ((short*)b)[1]) | \
6260 + !(((short*)a)[2] == ((short*)b)[2]))
6261 +
6262 +/* copy an ethernet address - assumes the pointers can be referenced as shorts */
6263 +#define ether_copy(s, d) { \
6264 + ((short*)d)[0] = ((short*)s)[0]; \
6265 + ((short*)d)[1] = ((short*)s)[1]; \
6266 + ((short*)d)[2] = ((short*)s)[2]; }
6267 +
6268 +/*
6269 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
6270 + */
6271 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
6272 + ((uint8 *)(ea))[1] & \
6273 + ((uint8 *)(ea))[2] & \
6274 + ((uint8 *)(ea))[3] & \
6275 + ((uint8 *)(ea))[4] & \
6276 + ((uint8 *)(ea))[5]) == 0xff)
6277 +
6278 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
6279 +
6280 +/*
6281 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
6282 + */
6283 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
6284 + ((uint8 *)(ea))[1] | \
6285 + ((uint8 *)(ea))[2] | \
6286 + ((uint8 *)(ea))[3] | \
6287 + ((uint8 *)(ea))[4] | \
6288 + ((uint8 *)(ea))[5]) == 0)
6289 +
6290 +/* Differentiated Services Codepoint - upper 6 bits of tos in iphdr */
6291 +#define DSCP_MASK 0xFC /* upper 6 bits */
6292 +#define DSCP_SHIFT 2
6293 +#define DSCP_WME_PRI_MASK 0xE0 /* upper 3 bits */
6294 +#define DSCP_WME_PRI_SHIFT 5
6295 +
6296 +#undef PACKED
6297 +#if !defined(__GNUC__)
6298 +#pragma pack()
6299 +#endif
6300 +
6301 +#endif /* _NET_ETHERNET_H_ */
6302 diff -urN linux.old/arch/mips/bcm947xx/include/proto/vlan.h linux.dev/arch/mips/bcm947xx/include/proto/vlan.h
6303 --- linux.old/arch/mips/bcm947xx/include/proto/vlan.h 1970-01-01 01:00:00.000000000 +0100
6304 +++ linux.dev/arch/mips/bcm947xx/include/proto/vlan.h 2005-11-07 21:57:07.873587500 +0100
6305 @@ -0,0 +1,50 @@
6306 +/*
6307 + * 802.1Q VLAN protocol definitions
6308 + *
6309 + * Copyright 2005, Broadcom Corporation
6310 + * All Rights Reserved.
6311 + *
6312 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6313 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6314 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6315 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6316 + *
6317 + * $Id$
6318 + */
6319 +
6320 +#ifndef _vlan_h_
6321 +#define _vlan_h_
6322 +
6323 +/* enable structure packing */
6324 +#if defined(__GNUC__)
6325 +#define PACKED __attribute__((packed))
6326 +#else
6327 +#pragma pack(1)
6328 +#define PACKED
6329 +#endif
6330 +
6331 +#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
6332 +#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
6333 +#define VLAN_PRI_SHIFT 13 /* user priority */
6334 +
6335 +#define VLAN_PRI_MASK 7 /* 3 bits of priority */
6336 +
6337 +#define VLAN_TAG_LEN 4
6338 +#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN)
6339 +
6340 +struct ethervlan_header {
6341 + uint8 ether_dhost[ETHER_ADDR_LEN];
6342 + uint8 ether_shost[ETHER_ADDR_LEN];
6343 + uint16 vlan_type; /* 0x8100 */
6344 + uint16 vlan_tag; /* priority, cfi and vid */
6345 + uint16 ether_type;
6346 +};
6347 +
6348 +#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
6349 +
6350 +#undef PACKED
6351 +#if !defined(__GNUC__)
6352 +#pragma pack()
6353 +#endif
6354 +
6355 +#endif /* _vlan_h_ */
6356 diff -urN linux.old/arch/mips/bcm947xx/include/proto/wpa.h linux.dev/arch/mips/bcm947xx/include/proto/wpa.h
6357 --- linux.old/arch/mips/bcm947xx/include/proto/wpa.h 1970-01-01 01:00:00.000000000 +0100
6358 +++ linux.dev/arch/mips/bcm947xx/include/proto/wpa.h 2005-11-07 21:57:07.873587500 +0100
6359 @@ -0,0 +1,140 @@
6360 +/*
6361 + * Fundamental types and constants relating to WPA
6362 + *
6363 + * Copyright 2005, Broadcom Corporation
6364 + * All Rights Reserved.
6365 + *
6366 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6367 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6368 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6369 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6370 + *
6371 + * $Id$
6372 + */
6373 +
6374 +#ifndef _proto_wpa_h_
6375 +#define _proto_wpa_h_
6376 +
6377 +#include <typedefs.h>
6378 +#include <proto/ethernet.h>
6379 +
6380 +/* enable structure packing */
6381 +#if defined(__GNUC__)
6382 +#define PACKED __attribute__((packed))
6383 +#else
6384 +#pragma pack(1)
6385 +#define PACKED
6386 +#endif
6387 +
6388 +/* Reason Codes */
6389 +
6390 +/* 10 and 11 are from TGh. */
6391 +#define DOT11_RC_BAD_PC 10 /* Unacceptable power capability element */
6392 +#define DOT11_RC_BAD_CHANNELS 11 /* Unacceptable supported channels element */
6393 +/* 12 is unused */
6394 +/* 13 through 23 taken from P802.11i/D3.0, November 2002 */
6395 +#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
6396 +#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
6397 +#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
6398 +#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
6399 +#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from (re-)assoc. request/probe response */
6400 +#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
6401 +#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
6402 +#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
6403 +#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
6404 +#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
6405 +#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
6406 +
6407 +#define WPA2_PMKID_LEN 16
6408 +
6409 +/* WPA IE fixed portion */
6410 +typedef struct
6411 +{
6412 + uint8 tag; /* TAG */
6413 + uint8 length; /* TAG length */
6414 + uint8 oui[3]; /* IE OUI */
6415 + uint8 oui_type; /* OUI type */
6416 + struct {
6417 + uint8 low;
6418 + uint8 high;
6419 + } PACKED version; /* IE version */
6420 +} PACKED wpa_ie_fixed_t;
6421 +#define WPA_IE_OUITYPE_LEN 4
6422 +#define WPA_IE_FIXED_LEN 8
6423 +#define WPA_IE_TAG_FIXED_LEN 6
6424 +
6425 +typedef struct {
6426 + uint8 tag; /* TAG */
6427 + uint8 length; /* TAG length */
6428 + struct {
6429 + uint8 low;
6430 + uint8 high;
6431 + } PACKED version; /* IE version */
6432 +} PACKED wpa_rsn_ie_fixed_t;
6433 +#define WPA_RSN_IE_FIXED_LEN 4
6434 +#define WPA_RSN_IE_TAG_FIXED_LEN 2
6435 +typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
6436 +
6437 +/* WPA suite/multicast suite */
6438 +typedef struct
6439 +{
6440 + uint8 oui[3];
6441 + uint8 type;
6442 +} PACKED wpa_suite_t, wpa_suite_mcast_t;
6443 +#define WPA_SUITE_LEN 4
6444 +
6445 +/* WPA unicast suite list/key management suite list */
6446 +typedef struct
6447 +{
6448 + struct {
6449 + uint8 low;
6450 + uint8 high;
6451 + } PACKED count;
6452 + wpa_suite_t list[1];
6453 +} PACKED wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
6454 +#define WPA_IE_SUITE_COUNT_LEN 2
6455 +typedef struct
6456 +{
6457 + struct {
6458 + uint8 low;
6459 + uint8 high;
6460 + } PACKED count;
6461 + wpa_pmkid_t list[1];
6462 +} PACKED wpa_pmkid_list_t;
6463 +
6464 +/* WPA cipher suites */
6465 +#define WPA_CIPHER_NONE 0 /* None */
6466 +#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
6467 +#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
6468 +#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
6469 +#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
6470 +#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
6471 +
6472 +#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
6473 + (cipher) == WPA_CIPHER_WEP_40 || \
6474 + (cipher) == WPA_CIPHER_WEP_104 || \
6475 + (cipher) == WPA_CIPHER_TKIP || \
6476 + (cipher) == WPA_CIPHER_AES_OCB || \
6477 + (cipher) == WPA_CIPHER_AES_CCM)
6478 +
6479 +/* WPA TKIP countermeasures parameters */
6480 +#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
6481 +#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
6482 +
6483 +/* WPA capabilities defined in 802.11i */
6484 +#define WPA_CAP_4_REPLAY_CNTRS 2
6485 +#define WPA_CAP_16_REPLAY_CNTRS 3
6486 +#define WPA_CAP_REPLAY_CNTR_SHIFT 2
6487 +#define WPA_CAP_REPLAY_CNTR_MASK 0x000c
6488 +
6489 +/* WPA Specific defines */
6490 +#define WPA_CAP_LEN 2
6491 +
6492 +#define WPA_CAP_WPA2_PREAUTH 1
6493 +
6494 +#undef PACKED
6495 +#if !defined(__GNUC__)
6496 +#pragma pack()
6497 +#endif
6498 +
6499 +#endif /* _proto_wpa_h_ */
6500 diff -urN linux.old/arch/mips/bcm947xx/include/rts/crc.h linux.dev/arch/mips/bcm947xx/include/rts/crc.h
6501 --- linux.old/arch/mips/bcm947xx/include/rts/crc.h 1970-01-01 01:00:00.000000000 +0100
6502 +++ linux.dev/arch/mips/bcm947xx/include/rts/crc.h 2005-11-07 21:57:07.873587500 +0100
6503 @@ -0,0 +1,69 @@
6504 +/*******************************************************************************
6505 + * $Id$
6506 + * Copyright 2005, Broadcom Corporation
6507 + * All Rights Reserved.
6508 + *
6509 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6510 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6511 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6512 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6513 + * crc.h - a function to compute crc for iLine10 headers
6514 + ******************************************************************************/
6515 +
6516 +#ifndef _RTS_CRC_H_
6517 +#define _RTS_CRC_H_ 1
6518 +
6519 +#include "typedefs.h"
6520 +
6521 +#ifdef __cplusplus
6522 +extern "C" {
6523 +#endif
6524 +
6525 +
6526 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6527 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6528 +#define HCS_GOOD_VALUE 0x39 /* Good final header checksum value */
6529 +
6530 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6531 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6532 +
6533 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6534 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6535 +
6536 +void hcs(uint8 *, uint);
6537 +uint8 crc8(uint8 *, uint, uint8);
6538 +uint16 crc16(uint8 *, uint, uint16);
6539 +uint32 crc32(uint8 *, uint, uint32);
6540 +
6541 +/* macros for common usage */
6542 +
6543 +#define APPEND_CRC8(pbytes, nbytes) \
6544 +do { \
6545 + uint8 tmp = crc8(pbytes, nbytes, CRC8_INIT_VALUE) ^ 0xff; \
6546 + (pbytes)[(nbytes)] = tmp; \
6547 + (nbytes) += 1; \
6548 +} while (0)
6549 +
6550 +#define APPEND_CRC16(pbytes, nbytes) \
6551 +do { \
6552 + uint16 tmp = crc16(pbytes, nbytes, CRC16_INIT_VALUE) ^ 0xffff; \
6553 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6554 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6555 + (nbytes) += 2; \
6556 +} while (0)
6557 +
6558 +#define APPEND_CRC32(pbytes, nbytes) \
6559 +do { \
6560 + uint32 tmp = crc32(pbytes, nbytes, CRC32_INIT_VALUE) ^ 0xffffffff; \
6561 + (pbytes)[(nbytes) + 0] = (tmp >> 0) & 0xff; \
6562 + (pbytes)[(nbytes) + 1] = (tmp >> 8) & 0xff; \
6563 + (pbytes)[(nbytes) + 2] = (tmp >> 16) & 0xff; \
6564 + (pbytes)[(nbytes) + 3] = (tmp >> 24) & 0xff; \
6565 + (nbytes) += 4; \
6566 +} while (0)
6567 +
6568 +#ifdef __cplusplus
6569 +}
6570 +#endif
6571 +
6572 +#endif /* _RTS_CRC_H_ */
6573 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
6574 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
6575 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-11-07 22:51:38.784726500 +0100
6576 @@ -0,0 +1,440 @@
6577 +/*
6578 + * SiliconBackplane Chipcommon core hardware definitions.
6579 + *
6580 + * The chipcommon core provides chip identification, SB control,
6581 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
6582 + * gpio interface, extbus, and support for serial and parallel flashes.
6583 + *
6584 + * $Id$
6585 + * Copyright 2005, Broadcom Corporation
6586 + * All Rights Reserved.
6587 + *
6588 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6589 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6590 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6591 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6592 + *
6593 + */
6594 +
6595 +#ifndef _SBCHIPC_H
6596 +#define _SBCHIPC_H
6597 +
6598 +
6599 +#ifndef _LANGUAGE_ASSEMBLY
6600 +
6601 +/* cpp contortions to concatenate w/arg prescan */
6602 +#ifndef PAD
6603 +#define _PADLINE(line) pad ## line
6604 +#define _XSTR(line) _PADLINE(line)
6605 +#define PAD _XSTR(__LINE__)
6606 +#endif /* PAD */
6607 +
6608 +typedef volatile struct {
6609 + uint32 chipid; /* 0x0 */
6610 + uint32 capabilities;
6611 + uint32 corecontrol; /* corerev >= 1 */
6612 + uint32 bist;
6613 +
6614 + /* OTP */
6615 + uint32 otpstatus; /* 0x10, corerev >= 10 */
6616 + uint32 otpcontrol;
6617 + uint32 otpprog;
6618 + uint32 PAD;
6619 +
6620 + /* Interrupt control */
6621 + uint32 intstatus; /* 0x20 */
6622 + uint32 intmask;
6623 + uint32 chipcontrol; /* 0x28, rev >= 11 */
6624 + uint32 chipstatus; /* 0x2c, rev >= 11 */
6625 +
6626 + /* Jtag Master */
6627 + uint32 jtagcmd; /* 0x30, rev >= 10 */
6628 + uint32 jtagir;
6629 + uint32 jtagdr;
6630 + uint32 jtagctrl;
6631 +
6632 + /* serial flash interface registers */
6633 + uint32 flashcontrol; /* 0x40 */
6634 + uint32 flashaddress;
6635 + uint32 flashdata;
6636 + uint32 PAD[1];
6637 +
6638 + /* Silicon backplane configuration broadcast control */
6639 + uint32 broadcastaddress; /* 0x50 */
6640 + uint32 broadcastdata;
6641 + uint32 PAD[2];
6642 +
6643 + /* gpio - cleared only by power-on-reset */
6644 + uint32 gpioin; /* 0x60 */
6645 + uint32 gpioout;
6646 + uint32 gpioouten;
6647 + uint32 gpiocontrol;
6648 + uint32 gpiointpolarity;
6649 + uint32 gpiointmask;
6650 + uint32 PAD[2];
6651 +
6652 + /* Watchdog timer */
6653 + uint32 watchdog; /* 0x80 */
6654 + uint32 PAD[1];
6655 +
6656 + /*GPIO based LED powersave registers corerev >= 16*/
6657 + uint32 gpiotimerval; /*0x88 */
6658 + uint32 gpiotimeroutmask;
6659 +
6660 + /* clock control */
6661 + uint32 clockcontrol_n; /* 0x90 */
6662 + uint32 clockcontrol_sb; /* aka m0 */
6663 + uint32 clockcontrol_pci; /* aka m1 */
6664 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
6665 + uint32 clockcontrol_mips; /* aka m3 */
6666 + uint32 clkdiv; /* corerev >= 3 */
6667 + uint32 PAD[2];
6668 +
6669 + /* pll delay registers (corerev >= 4) */
6670 + uint32 pll_on_delay; /* 0xb0 */
6671 + uint32 fref_sel_delay;
6672 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
6673 + uint32 PAD[1];
6674 +
6675 + /* Instaclock registers (corerev >= 10) */
6676 + uint32 system_clk_ctl; /* 0xc0 */
6677 + uint32 clkstatestretch;
6678 + uint32 PAD[14];
6679 +
6680 + /* ExtBus control registers (corerev >= 3) */
6681 + uint32 pcmcia_config; /* 0x100 */
6682 + uint32 pcmcia_memwait;
6683 + uint32 pcmcia_attrwait;
6684 + uint32 pcmcia_iowait;
6685 + uint32 ide_config;
6686 + uint32 ide_memwait;
6687 + uint32 ide_attrwait;
6688 + uint32 ide_iowait;
6689 + uint32 prog_config;
6690 + uint32 prog_waitcount;
6691 + uint32 flash_config;
6692 + uint32 flash_waitcount;
6693 + uint32 PAD[116];
6694 +
6695 + /* uarts */
6696 + uint8 uart0data; /* 0x300 */
6697 + uint8 uart0imr;
6698 + uint8 uart0fcr;
6699 + uint8 uart0lcr;
6700 + uint8 uart0mcr;
6701 + uint8 uart0lsr;
6702 + uint8 uart0msr;
6703 + uint8 uart0scratch;
6704 + uint8 PAD[248]; /* corerev >= 1 */
6705 +
6706 + uint8 uart1data; /* 0x400 */
6707 + uint8 uart1imr;
6708 + uint8 uart1fcr;
6709 + uint8 uart1lcr;
6710 + uint8 uart1mcr;
6711 + uint8 uart1lsr;
6712 + uint8 uart1msr;
6713 + uint8 uart1scratch;
6714 +} chipcregs_t;
6715 +
6716 +#endif /* _LANGUAGE_ASSEMBLY */
6717 +
6718 +#define CC_CHIPID 0
6719 +#define CC_CAPABILITIES 4
6720 +#define CC_JTAGCMD 0x30
6721 +#define CC_JTAGIR 0x34
6722 +#define CC_JTAGDR 0x38
6723 +#define CC_JTAGCTRL 0x3c
6724 +#define CC_WATCHDOG 0x80
6725 +#define CC_CLKC_N 0x90
6726 +#define CC_CLKC_M0 0x94
6727 +#define CC_CLKC_M1 0x98
6728 +#define CC_CLKC_M2 0x9c
6729 +#define CC_CLKC_M3 0xa0
6730 +#define CC_CLKDIV 0xa4
6731 +#define CC_SYS_CLK_CTL 0xc0
6732 +#define CC_OTP 0x800
6733 +
6734 +/* chipid */
6735 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
6736 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
6737 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
6738 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
6739 +#define CID_PKG_SHIFT 20 /* Package Option shift */
6740 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
6741 +#define CID_CC_SHIFT 24
6742 +
6743 +/* capabilities */
6744 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
6745 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
6746 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
6747 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
6748 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
6749 +#define CAP_EXTBUS 0x00000040 /* External bus present */
6750 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
6751 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
6752 +#define CAP_PWR_CTL 0x00040000 /* Power control */
6753 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
6754 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
6755 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
6756 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
6757 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
6758 +
6759 +/* PLL type */
6760 +#define PLL_NONE 0x00000000
6761 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
6762 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
6763 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
6764 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
6765 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
6766 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
6767 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
6768 +
6769 +/* corecontrol */
6770 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
6771 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
6772 +
6773 +/* Fields in the otpstatus register */
6774 +#define OTPS_PROGFAIL 0x80000000
6775 +#define OTPS_PROTECT 0x00000007
6776 +#define OTPS_HW_PROTECT 0x00000001
6777 +#define OTPS_SW_PROTECT 0x00000002
6778 +#define OTPS_CID_PROTECT 0x00000004
6779 +
6780 +/* Fields in the otpcontrol register */
6781 +#define OTPC_RECWAIT 0xff000000
6782 +#define OTPC_PROGWAIT 0x00ffff00
6783 +#define OTPC_PRW_SHIFT 8
6784 +#define OTPC_MAXFAIL 0x00000038
6785 +#define OTPC_VSEL 0x00000006
6786 +#define OTPC_SELVL 0x00000001
6787 +
6788 +/* Fields in otpprog */
6789 +#define OTPP_COL_MASK 0x000000ff
6790 +#define OTPP_ROW_MASK 0x0000ff00
6791 +#define OTPP_ROW_SHIFT 8
6792 +#define OTPP_READERR 0x10000000
6793 +#define OTPP_VALUE 0x20000000
6794 +#define OTPP_VALUE_SHIFT 29
6795 +#define OTPP_READ 0x40000000
6796 +#define OTPP_START 0x80000000
6797 +#define OTPP_BUSY 0x80000000
6798 +
6799 +/* jtagcmd */
6800 +#define JCMD_START 0x80000000
6801 +#define JCMD_BUSY 0x80000000
6802 +#define JCMD_PAUSE 0x40000000
6803 +#define JCMD0_ACC_MASK 0x0000f000
6804 +#define JCMD0_ACC_IRDR 0x00000000
6805 +#define JCMD0_ACC_DR 0x00001000
6806 +#define JCMD0_ACC_IR 0x00002000
6807 +#define JCMD0_ACC_RESET 0x00003000
6808 +#define JCMD0_ACC_IRPDR 0x00004000
6809 +#define JCMD0_ACC_PDR 0x00005000
6810 +#define JCMD0_IRW_MASK 0x00000f00
6811 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
6812 +#define JCMD_ACC_IRDR 0x00000000
6813 +#define JCMD_ACC_DR 0x00010000
6814 +#define JCMD_ACC_IR 0x00020000
6815 +#define JCMD_ACC_RESET 0x00030000
6816 +#define JCMD_ACC_IRPDR 0x00040000
6817 +#define JCMD_ACC_PDR 0x00050000
6818 +#define JCMD_IRW_MASK 0x00001f00
6819 +#define JCMD_IRW_SHIFT 8
6820 +#define JCMD_DRW_MASK 0x0000003f
6821 +
6822 +/* jtagctrl */
6823 +#define JCTRL_FORCE_CLK 4 /* Force clock */
6824 +#define JCTRL_EXT_EN 2 /* Enable external targets */
6825 +#define JCTRL_EN 1 /* Enable Jtag master */
6826 +
6827 +/* Fields in clkdiv */
6828 +#define CLKD_SFLASH 0x0f000000
6829 +#define CLKD_SFLASH_SHIFT 24
6830 +#define CLKD_OTP 0x000f0000
6831 +#define CLKD_OTP_SHIFT 16
6832 +#define CLKD_JTAG 0x00000f00
6833 +#define CLKD_JTAG_SHIFT 8
6834 +#define CLKD_UART 0x000000ff
6835 +
6836 +/* intstatus/intmask */
6837 +#define CI_GPIO 0x00000001 /* gpio intr */
6838 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
6839 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
6840 +
6841 +/* slow_clk_ctl */
6842 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
6843 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
6844 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
6845 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
6846 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
6847 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
6848 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
6849 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
6850 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
6851 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
6852 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
6853 +#define SCC_CD_SHIFT 16
6854 +
6855 +/* system_clk_ctl */
6856 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
6857 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
6858 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
6859 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
6860 +#define SYCC_HR 0x00000010 /* Force HT */
6861 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
6862 +#define SYCC_CD_SHIFT 16
6863 +
6864 +/* gpiotimerval*/
6865 +#define GPIO_ONTIME_SHIFT 16
6866 +
6867 +/* clockcontrol_n */
6868 +#define CN_N1_MASK 0x3f /* n1 control */
6869 +#define CN_N2_MASK 0x3f00 /* n2 control */
6870 +#define CN_N2_SHIFT 8
6871 +#define CN_PLLC_MASK 0xf0000 /* pll control */
6872 +#define CN_PLLC_SHIFT 16
6873 +
6874 +/* clockcontrol_sb/pci/uart */
6875 +#define CC_M1_MASK 0x3f /* m1 control */
6876 +#define CC_M2_MASK 0x3f00 /* m2 control */
6877 +#define CC_M2_SHIFT 8
6878 +#define CC_M3_MASK 0x3f0000 /* m3 control */
6879 +#define CC_M3_SHIFT 16
6880 +#define CC_MC_MASK 0x1f000000 /* mux control */
6881 +#define CC_MC_SHIFT 24
6882 +
6883 +/* N3M Clock control magic field values */
6884 +#define CC_F6_2 0x02 /* A factor of 2 in */
6885 +#define CC_F6_3 0x03 /* 6-bit fields like */
6886 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
6887 +#define CC_F6_5 0x09
6888 +#define CC_F6_6 0x11
6889 +#define CC_F6_7 0x21
6890 +
6891 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
6892 +
6893 +#define CC_MC_BYPASS 0x08
6894 +#define CC_MC_M1 0x04
6895 +#define CC_MC_M1M2 0x02
6896 +#define CC_MC_M1M2M3 0x01
6897 +#define CC_MC_M1M3 0x11
6898 +
6899 +/* Type 2 Clock control magic field values */
6900 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
6901 +#define CC_T2M2_BIAS 3 /* m2 bias */
6902 +
6903 +#define CC_T2MC_M1BYP 1
6904 +#define CC_T2MC_M2BYP 2
6905 +#define CC_T2MC_M3BYP 4
6906 +
6907 +/* Type 6 Clock control magic field values */
6908 +#define CC_T6_MMASK 1 /* bits of interest in m */
6909 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
6910 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
6911 +#define SB2MIPS_T6(sb) (2 * (sb))
6912 +
6913 +/* Common clock base */
6914 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
6915 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
6916 +
6917 +/* Clock control values for 200Mhz in 5350 */
6918 +#define CLKC_5350_N 0x0311
6919 +#define CLKC_5350_M 0x04020009
6920 +
6921 +/* Flash types in the chipcommon capabilities register */
6922 +#define FLASH_NONE 0x000 /* No flash */
6923 +#define SFLASH_ST 0x100 /* ST serial flash */
6924 +#define SFLASH_AT 0x200 /* Atmel serial flash */
6925 +#define PFLASH 0x700 /* Parallel flash */
6926 +
6927 +/* Bits in the config registers */
6928 +#define CC_CFG_EN 0x0001 /* Enable */
6929 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
6930 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
6931 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
6932 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
6933 +#define CC_CFG_EM_IDE 0x000a /* IDE */
6934 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
6935 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
6936 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
6937 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
6938 +
6939 +/* Start/busy bit in flashcontrol */
6940 +#define SFLASH_START 0x80000000
6941 +#define SFLASH_BUSY SFLASH_START
6942 +
6943 +/* flashcontrol opcodes for ST flashes */
6944 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
6945 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
6946 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
6947 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
6948 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
6949 +#define SFLASH_ST_PP 0x0302 /* Page Program */
6950 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
6951 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
6952 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
6953 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
6954 +
6955 +/* Status register bits for ST flashes */
6956 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
6957 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
6958 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
6959 +#define SFLASH_ST_BP_SHIFT 2
6960 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
6961 +
6962 +/* flashcontrol opcodes for Atmel flashes */
6963 +#define SFLASH_AT_READ 0x07e8
6964 +#define SFLASH_AT_PAGE_READ 0x07d2
6965 +#define SFLASH_AT_BUF1_READ
6966 +#define SFLASH_AT_BUF2_READ
6967 +#define SFLASH_AT_STATUS 0x01d7
6968 +#define SFLASH_AT_BUF1_WRITE 0x0384
6969 +#define SFLASH_AT_BUF2_WRITE 0x0387
6970 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
6971 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
6972 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
6973 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
6974 +#define SFLASH_AT_PAGE_ERASE 0x0281
6975 +#define SFLASH_AT_BLOCK_ERASE 0x0250
6976 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
6977 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
6978 +#define SFLASH_AT_BUF1_LOAD 0x0253
6979 +#define SFLASH_AT_BUF2_LOAD 0x0255
6980 +#define SFLASH_AT_BUF1_COMPARE 0x0260
6981 +#define SFLASH_AT_BUF2_COMPARE 0x0261
6982 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
6983 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
6984 +
6985 +/* Status register bits for Atmel flashes */
6986 +#define SFLASH_AT_READY 0x80
6987 +#define SFLASH_AT_MISMATCH 0x40
6988 +#define SFLASH_AT_ID_MASK 0x38
6989 +#define SFLASH_AT_ID_SHIFT 3
6990 +
6991 +/* OTP regions */
6992 +#define OTP_HW_REGION OTPS_HW_PROTECT
6993 +#define OTP_SW_REGION OTPS_SW_PROTECT
6994 +#define OTP_CID_REGION OTPS_CID_PROTECT
6995 +
6996 +/* OTP regions (Byte offsets from otp size) */
6997 +#define OTP_SWLIM_OFF (-8)
6998 +#define OTP_CIDBASE_OFF 0
6999 +#define OTP_CIDLIM_OFF 8
7000 +
7001 +/* Predefined OTP words (Word offset from otp size) */
7002 +#define OTP_BOUNDARY_OFF (-4)
7003 +#define OTP_HWSIGN_OFF (-3)
7004 +#define OTP_SWSIGN_OFF (-2)
7005 +#define OTP_CIDSIGN_OFF (-1)
7006 +
7007 +#define OTP_CID_OFF 0
7008 +#define OTP_PKG_OFF 1
7009 +#define OTP_FID_OFF 2
7010 +#define OTP_RSV_OFF 3
7011 +#define OTP_LIM_OFF 4
7012 +
7013 +#define OTP_SIGNATURE 0x578a
7014 +#define OTP_MAGIC 0x4e56
7015 +
7016 +#endif /* _SBCHIPC_H */
7017 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
7018 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
7019 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-11-07 22:51:38.784726500 +0100
7020 @@ -0,0 +1,342 @@
7021 +/*
7022 + * Broadcom SiliconBackplane hardware register definitions.
7023 + *
7024 + * Copyright 2005, Broadcom Corporation
7025 + * All Rights Reserved.
7026 + *
7027 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7028 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7029 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7030 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7031 + * $Id$
7032 + */
7033 +
7034 +#ifndef _SBCONFIG_H
7035 +#define _SBCONFIG_H
7036 +
7037 +/* cpp contortions to concatenate w/arg prescan */
7038 +#ifndef PAD
7039 +#define _PADLINE(line) pad ## line
7040 +#define _XSTR(line) _PADLINE(line)
7041 +#define PAD _XSTR(__LINE__)
7042 +#endif
7043 +
7044 +/*
7045 + * SiliconBackplane Address Map.
7046 + * All regions may not exist on all chips.
7047 + */
7048 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
7049 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
7050 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
7051 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
7052 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
7053 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
7054 +
7055 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
7056 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
7057 +
7058 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
7059 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
7060 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
7061 +
7062 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
7063 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
7064 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
7065 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
7066 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
7067 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
7068 +
7069 +
7070 +/* enumeration space related defs */
7071 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
7072 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
7073 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
7074 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
7075 +
7076 +/* mips address */
7077 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
7078 +
7079 +/*
7080 + * Sonics Configuration Space Registers.
7081 + */
7082 +#define SBIPSFLAG 0x08
7083 +#define SBTPSFLAG 0x18
7084 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
7085 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
7086 +#define SBADMATCH3 0x60
7087 +#define SBADMATCH2 0x68
7088 +#define SBADMATCH1 0x70
7089 +#define SBIMSTATE 0x90
7090 +#define SBINTVEC 0x94
7091 +#define SBTMSTATELOW 0x98
7092 +#define SBTMSTATEHIGH 0x9c
7093 +#define SBBWA0 0xa0
7094 +#define SBIMCONFIGLOW 0xa8
7095 +#define SBIMCONFIGHIGH 0xac
7096 +#define SBADMATCH0 0xb0
7097 +#define SBTMCONFIGLOW 0xb8
7098 +#define SBTMCONFIGHIGH 0xbc
7099 +#define SBBCONFIG 0xc0
7100 +#define SBBSTATE 0xc8
7101 +#define SBACTCNFG 0xd8
7102 +#define SBFLAGST 0xe8
7103 +#define SBIDLOW 0xf8
7104 +#define SBIDHIGH 0xfc
7105 +
7106 +#ifndef _LANGUAGE_ASSEMBLY
7107 +
7108 +typedef volatile struct _sbconfig {
7109 + uint32 PAD[2];
7110 + uint32 sbipsflag; /* initiator port ocp slave flag */
7111 + uint32 PAD[3];
7112 + uint32 sbtpsflag; /* target port ocp slave flag */
7113 + uint32 PAD[11];
7114 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
7115 + uint32 PAD;
7116 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
7117 + uint32 PAD[3];
7118 + uint32 sbadmatch3; /* address match3 */
7119 + uint32 PAD;
7120 + uint32 sbadmatch2; /* address match2 */
7121 + uint32 PAD;
7122 + uint32 sbadmatch1; /* address match1 */
7123 + uint32 PAD[7];
7124 + uint32 sbimstate; /* initiator agent state */
7125 + uint32 sbintvec; /* interrupt mask */
7126 + uint32 sbtmstatelow; /* target state */
7127 + uint32 sbtmstatehigh; /* target state */
7128 + uint32 sbbwa0; /* bandwidth allocation table0 */
7129 + uint32 PAD;
7130 + uint32 sbimconfiglow; /* initiator configuration */
7131 + uint32 sbimconfighigh; /* initiator configuration */
7132 + uint32 sbadmatch0; /* address match0 */
7133 + uint32 PAD;
7134 + uint32 sbtmconfiglow; /* target configuration */
7135 + uint32 sbtmconfighigh; /* target configuration */
7136 + uint32 sbbconfig; /* broadcast configuration */
7137 + uint32 PAD;
7138 + uint32 sbbstate; /* broadcast state */
7139 + uint32 PAD[3];
7140 + uint32 sbactcnfg; /* activate configuration */
7141 + uint32 PAD[3];
7142 + uint32 sbflagst; /* current sbflags */
7143 + uint32 PAD[3];
7144 + uint32 sbidlow; /* identification */
7145 + uint32 sbidhigh; /* identification */
7146 +} sbconfig_t;
7147 +
7148 +#endif /* _LANGUAGE_ASSEMBLY */
7149 +
7150 +/* sbipsflag */
7151 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
7152 +#define SBIPS_INT1_SHIFT 0
7153 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
7154 +#define SBIPS_INT2_SHIFT 8
7155 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
7156 +#define SBIPS_INT3_SHIFT 16
7157 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
7158 +#define SBIPS_INT4_SHIFT 24
7159 +
7160 +/* sbtpsflag */
7161 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
7162 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
7163 +
7164 +/* sbtmerrlog */
7165 +#define SBTMEL_CM 0x00000007 /* command */
7166 +#define SBTMEL_CI 0x0000ff00 /* connection id */
7167 +#define SBTMEL_EC 0x0f000000 /* error code */
7168 +#define SBTMEL_ME 0x80000000 /* multiple error */
7169 +
7170 +/* sbimstate */
7171 +#define SBIM_PC 0xf /* pipecount */
7172 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
7173 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
7174 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
7175 +#define SBIM_AP_TK 0x20 /* use token only */
7176 +#define SBIM_AP_RSV 0x30 /* reserved */
7177 +#define SBIM_IBE 0x20000 /* inbanderror */
7178 +#define SBIM_TO 0x40000 /* timeout */
7179 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
7180 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
7181 +
7182 +/* sbtmstatelow */
7183 +#define SBTML_RESET 0x1 /* reset */
7184 +#define SBTML_REJ_MASK 0x6 /* reject */
7185 +#define SBTML_REJ_SHIFT 1
7186 +#define SBTML_CLK 0x10000 /* clock enable */
7187 +#define SBTML_FGC 0x20000 /* force gated clocks on */
7188 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
7189 +#define SBTML_PE 0x40000000 /* pme enable */
7190 +#define SBTML_BE 0x80000000 /* bist enable */
7191 +
7192 +/* sbtmstatehigh */
7193 +#define SBTMH_SERR 0x1 /* serror */
7194 +#define SBTMH_INT 0x2 /* interrupt */
7195 +#define SBTMH_BUSY 0x4 /* busy */
7196 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
7197 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
7198 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
7199 +#define SBTMH_GCR 0x20000000 /* gated clock request */
7200 +#define SBTMH_BISTF 0x40000000 /* bist failed */
7201 +#define SBTMH_BISTD 0x80000000 /* bist done */
7202 +
7203 +
7204 +/* sbbwa0 */
7205 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
7206 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
7207 +#define SBBWA_TAB1_SHIFT 16
7208 +
7209 +/* sbimconfiglow */
7210 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
7211 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
7212 +#define SBIMCL_RTO_SHIFT 4
7213 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
7214 +#define SBIMCL_CID_SHIFT 16
7215 +
7216 +/* sbimconfighigh */
7217 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
7218 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
7219 +#define SBIMCH_TEM_SHIFT 4
7220 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
7221 +#define SBIMCH_BEM_SHIFT 6
7222 +
7223 +/* sbadmatch0 */
7224 +#define SBAM_TYPE_MASK 0x3 /* address type */
7225 +#define SBAM_AD64 0x4 /* reserved */
7226 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
7227 +#define SBAM_ADINT0_SHIFT 3
7228 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
7229 +#define SBAM_ADINT1_SHIFT 3
7230 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
7231 +#define SBAM_ADINT2_SHIFT 3
7232 +#define SBAM_ADEN 0x400 /* enable */
7233 +#define SBAM_ADNEG 0x800 /* negative decode */
7234 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
7235 +#define SBAM_BASE0_SHIFT 8
7236 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
7237 +#define SBAM_BASE1_SHIFT 12
7238 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
7239 +#define SBAM_BASE2_SHIFT 16
7240 +
7241 +/* sbtmconfiglow */
7242 +#define SBTMCL_CD_MASK 0xff /* clock divide */
7243 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
7244 +#define SBTMCL_CO_SHIFT 11
7245 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
7246 +#define SBTMCL_IF_SHIFT 18
7247 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
7248 +#define SBTMCL_IM_SHIFT 24
7249 +
7250 +/* sbtmconfighigh */
7251 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
7252 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
7253 +#define SBTMCH_RM_SHIFT 2
7254 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
7255 +#define SBTMCH_SM_SHIFT 4
7256 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
7257 +#define SBTMCH_EM_SHIFT 8
7258 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
7259 +#define SBTMCH_IM_SHIFT 10
7260 +
7261 +/* sbbconfig */
7262 +#define SBBC_LAT_MASK 0x3 /* sb latency */
7263 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
7264 +#define SBBC_MAX0_SHIFT 16
7265 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
7266 +#define SBBC_MAX1_SHIFT 20
7267 +
7268 +/* sbbstate */
7269 +#define SBBS_SRD 0x1 /* st reg disable */
7270 +#define SBBS_HRD 0x2 /* hold reg disable */
7271 +
7272 +/* sbidlow */
7273 +#define SBIDL_CS_MASK 0x3 /* config space */
7274 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
7275 +#define SBIDL_AR_SHIFT 3
7276 +#define SBIDL_SYNCH 0x40 /* sync */
7277 +#define SBIDL_INIT 0x80 /* initiator */
7278 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
7279 +#define SBIDL_MINLAT_SHIFT 8
7280 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
7281 +#define SBIDL_MAXLAT_SHIFT 12
7282 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
7283 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
7284 +#define SBIDL_CW_SHIFT 18
7285 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
7286 +#define SBIDL_TP_SHIFT 20
7287 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
7288 +#define SBIDL_IP_SHIFT 24
7289 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
7290 +#define SBIDL_RV_SHIFT 28
7291 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
7292 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
7293 +
7294 +/* sbidhigh */
7295 +#define SBIDH_RC_MASK 0x000f /* revision code */
7296 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
7297 +#define SBIDH_RCE_SHIFT 8
7298 +#define SBCOREREV(sbidh) \
7299 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
7300 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
7301 +#define SBIDH_CC_SHIFT 4
7302 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
7303 +#define SBIDH_VC_SHIFT 16
7304 +
7305 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
7306 +
7307 +/* vendor codes */
7308 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
7309 +
7310 +/* core codes */
7311 +#define SB_CC 0x800 /* chipcommon core */
7312 +#define SB_ILINE20 0x801 /* iline20 core */
7313 +#define SB_SDRAM 0x803 /* sdram core */
7314 +#define SB_PCI 0x804 /* pci core */
7315 +#define SB_MIPS 0x805 /* mips core */
7316 +#define SB_ENET 0x806 /* enet mac core */
7317 +#define SB_CODEC 0x807 /* v90 codec core */
7318 +#define SB_USB 0x808 /* usb 1.1 host/device core */
7319 +#define SB_ADSL 0x809 /* ADSL core */
7320 +#define SB_ILINE100 0x80a /* iline100 core */
7321 +#define SB_IPSEC 0x80b /* ipsec core */
7322 +#define SB_PCMCIA 0x80d /* pcmcia core */
7323 +#define SB_SOCRAM 0x80e /* internal memory core */
7324 +#define SB_MEMC 0x80f /* memc sdram core */
7325 +#define SB_EXTIF 0x811 /* external interface core */
7326 +#define SB_D11 0x812 /* 802.11 MAC core */
7327 +#define SB_MIPS33 0x816 /* mips3302 core */
7328 +#define SB_USB11H 0x817 /* usb 1.1 host core */
7329 +#define SB_USB11D 0x818 /* usb 1.1 device core */
7330 +#define SB_USB20H 0x819 /* usb 2.0 host core */
7331 +#define SB_USB20D 0x81a /* usb 2.0 device core */
7332 +#define SB_SDIOH 0x81b /* sdio host core */
7333 +#define SB_ROBO 0x81c /* roboswitch core */
7334 +#define SB_ATA100 0x81d /* parallel ATA core */
7335 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
7336 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
7337 +#define SB_PCIE 0x820 /* pci express core */
7338 +#define SB_SRAMC 0x822 /* SRAM controller core */
7339 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
7340 +
7341 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
7342 +
7343 +/* Not really related to Silicon Backplane, but a couple of software
7344 + * conventions for the use the flash space:
7345 + */
7346 +
7347 +/* Minumum amount of flash we support */
7348 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
7349 +
7350 +/* A boot/binary may have an embedded block that describes its size */
7351 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
7352 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
7353 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
7354 +#define BISZ_TXTST_IDX 1 /* 1: text start */
7355 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
7356 +#define BISZ_DATAST_IDX 3 /* 3: text start */
7357 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
7358 +#define BISZ_BSSST_IDX 5 /* 5: text start */
7359 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
7360 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
7361 +
7362 +#endif /* _SBCONFIG_H */
7363 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
7364 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
7365 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-11-07 21:57:07.877587750 +0100
7366 @@ -0,0 +1,242 @@
7367 +/*
7368 + * Hardware-specific External Interface I/O core definitions
7369 + * for the BCM47xx family of SiliconBackplane-based chips.
7370 + *
7371 + * The External Interface core supports a total of three external chip selects
7372 + * supporting external interfaces. One of the external chip selects is
7373 + * used for Flash, one is used for PCMCIA, and the other may be
7374 + * programmed to support either a synchronous interface or an
7375 + * asynchronous interface. The asynchronous interface can be used to
7376 + * support external devices such as UARTs and the BCM2019 Bluetooth
7377 + * baseband processor.
7378 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
7379 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
7380 + *
7381 + * Copyright 2005, Broadcom Corporation
7382 + * All Rights Reserved.
7383 + *
7384 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7385 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7386 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7387 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7388 + * $Id$
7389 + */
7390 +
7391 +#ifndef _SBEXTIF_H
7392 +#define _SBEXTIF_H
7393 +
7394 +/* external interface address space */
7395 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
7396 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
7397 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
7398 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
7399 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
7400 +
7401 +/* cpp contortions to concatenate w/arg prescan */
7402 +#ifndef PAD
7403 +#define _PADLINE(line) pad ## line
7404 +#define _XSTR(line) _PADLINE(line)
7405 +#define PAD _XSTR(__LINE__)
7406 +#endif /* PAD */
7407 +
7408 +/*
7409 + * The multiple instances of output and output enable registers
7410 + * are present to allow driver software for multiple cores to control
7411 + * gpio outputs without needing to share a single register pair.
7412 + */
7413 +struct gpiouser {
7414 + uint32 out;
7415 + uint32 outen;
7416 +};
7417 +#define NGPIOUSER 5
7418 +
7419 +typedef volatile struct {
7420 + uint32 corecontrol;
7421 + uint32 extstatus;
7422 + uint32 PAD[2];
7423 +
7424 + /* pcmcia control registers */
7425 + uint32 pcmcia_config;
7426 + uint32 pcmcia_memwait;
7427 + uint32 pcmcia_attrwait;
7428 + uint32 pcmcia_iowait;
7429 +
7430 + /* programmable interface control registers */
7431 + uint32 prog_config;
7432 + uint32 prog_waitcount;
7433 +
7434 + /* flash control registers */
7435 + uint32 flash_config;
7436 + uint32 flash_waitcount;
7437 + uint32 PAD[4];
7438 +
7439 + uint32 watchdog;
7440 +
7441 + /* clock control */
7442 + uint32 clockcontrol_n;
7443 + uint32 clockcontrol_sb;
7444 + uint32 clockcontrol_pci;
7445 + uint32 clockcontrol_mii;
7446 + uint32 PAD[3];
7447 +
7448 + /* gpio */
7449 + uint32 gpioin;
7450 + struct gpiouser gpio[NGPIOUSER];
7451 + uint32 PAD;
7452 + uint32 ejtagouten;
7453 + uint32 gpiointpolarity;
7454 + uint32 gpiointmask;
7455 + uint32 PAD[153];
7456 +
7457 + uint8 uartdata;
7458 + uint8 PAD[3];
7459 + uint8 uartimer;
7460 + uint8 PAD[3];
7461 + uint8 uartfcr;
7462 + uint8 PAD[3];
7463 + uint8 uartlcr;
7464 + uint8 PAD[3];
7465 + uint8 uartmcr;
7466 + uint8 PAD[3];
7467 + uint8 uartlsr;
7468 + uint8 PAD[3];
7469 + uint8 uartmsr;
7470 + uint8 PAD[3];
7471 + uint8 uartscratch;
7472 + uint8 PAD[3];
7473 +} extifregs_t;
7474 +
7475 +/* corecontrol */
7476 +#define CC_UE (1 << 0) /* uart enable */
7477 +
7478 +/* extstatus */
7479 +#define ES_EM (1 << 0) /* endian mode (ro) */
7480 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
7481 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
7482 +
7483 +/* gpio bit mask */
7484 +#define GPIO_BIT0 (1 << 0)
7485 +#define GPIO_BIT1 (1 << 1)
7486 +#define GPIO_BIT2 (1 << 2)
7487 +#define GPIO_BIT3 (1 << 3)
7488 +#define GPIO_BIT4 (1 << 4)
7489 +#define GPIO_BIT5 (1 << 5)
7490 +#define GPIO_BIT6 (1 << 6)
7491 +#define GPIO_BIT7 (1 << 7)
7492 +
7493 +
7494 +/* pcmcia/prog/flash_config */
7495 +#define CF_EN (1 << 0) /* enable */
7496 +#define CF_EM_MASK 0xe /* mode */
7497 +#define CF_EM_SHIFT 1
7498 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
7499 +#define CF_EM_SYNC 0x2 /* synchronous mode */
7500 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
7501 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
7502 +#define CF_BS (1 << 5) /* byteswap */
7503 +#define CF_CD_MASK 0xc0 /* clock divider */
7504 +#define CF_CD_SHIFT 6
7505 +#define CF_CD_DIV2 0x0 /* backplane/2 */
7506 +#define CF_CD_DIV3 0x40 /* backplane/3 */
7507 +#define CF_CD_DIV4 0x80 /* backplane/4 */
7508 +#define CF_CE (1 << 8) /* clock enable */
7509 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
7510 +
7511 +/* pcmcia_memwait */
7512 +#define PM_W0_MASK 0x3f /* waitcount0 */
7513 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
7514 +#define PM_W1_SHIFT 8
7515 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
7516 +#define PM_W2_SHIFT 16
7517 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
7518 +#define PM_W3_SHIFT 24
7519 +
7520 +/* pcmcia_attrwait */
7521 +#define PA_W0_MASK 0x3f /* waitcount0 */
7522 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
7523 +#define PA_W1_SHIFT 8
7524 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
7525 +#define PA_W2_SHIFT 16
7526 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
7527 +#define PA_W3_SHIFT 24
7528 +
7529 +/* pcmcia_iowait */
7530 +#define PI_W0_MASK 0x3f /* waitcount0 */
7531 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
7532 +#define PI_W1_SHIFT 8
7533 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
7534 +#define PI_W2_SHIFT 16
7535 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
7536 +#define PI_W3_SHIFT 24
7537 +
7538 +/* prog_waitcount */
7539 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
7540 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
7541 +#define PW_W1_SHIFT 8
7542 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
7543 +#define PW_W2_SHIFT 16
7544 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
7545 +#define PW_W3_SHIFT 24
7546 +
7547 +#define PW_W0 0x0000000c
7548 +#define PW_W1 0x00000a00
7549 +#define PW_W2 0x00020000
7550 +#define PW_W3 0x01000000
7551 +
7552 +/* flash_waitcount */
7553 +#define FW_W0_MASK 0x1f /* waitcount0 */
7554 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
7555 +#define FW_W1_SHIFT 8
7556 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
7557 +#define FW_W2_SHIFT 16
7558 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
7559 +#define FW_W3_SHIFT 24
7560 +
7561 +/* watchdog */
7562 +#define WATCHDOG_CLOCK 48000000 /* Hz */
7563 +
7564 +/* clockcontrol_n */
7565 +#define CN_N1_MASK 0x3f /* n1 control */
7566 +#define CN_N2_MASK 0x3f00 /* n2 control */
7567 +#define CN_N2_SHIFT 8
7568 +
7569 +/* clockcontrol_sb/pci/mii */
7570 +#define CC_M1_MASK 0x3f /* m1 control */
7571 +#define CC_M2_MASK 0x3f00 /* m2 control */
7572 +#define CC_M2_SHIFT 8
7573 +#define CC_M3_MASK 0x3f0000 /* m3 control */
7574 +#define CC_M3_SHIFT 16
7575 +#define CC_MC_MASK 0x1f000000 /* mux control */
7576 +#define CC_MC_SHIFT 24
7577 +
7578 +/* Clock control default values */
7579 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
7580 +#define CC_DEF_100 0x04020011
7581 +#define CC_DEF_33 0x11030011
7582 +#define CC_DEF_25 0x11050011
7583 +
7584 +/* Clock control values for 125Mhz */
7585 +#define CC_125_N 0x0802
7586 +#define CC_125_M 0x04020009
7587 +#define CC_125_M25 0x11090009
7588 +#define CC_125_M33 0x11090005
7589 +
7590 +/* Clock control magic field values */
7591 +#define CC_F6_2 0x02 /* A factor of 2 in */
7592 +#define CC_F6_3 0x03 /* 6-bit fields like */
7593 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
7594 +#define CC_F6_5 0x09
7595 +#define CC_F6_6 0x11
7596 +#define CC_F6_7 0x21
7597 +
7598 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
7599 +
7600 +#define CC_MC_BYPASS 0x08
7601 +#define CC_MC_M1 0x04
7602 +#define CC_MC_M1M2 0x02
7603 +#define CC_MC_M1M2M3 0x01
7604 +#define CC_MC_M1M3 0x11
7605 +
7606 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
7607 +
7608 +#endif /* _SBEXTIF_H */
7609 diff -urN linux.old/arch/mips/bcm947xx/include/sbhnddma.h linux.dev/arch/mips/bcm947xx/include/sbhnddma.h
7610 --- linux.old/arch/mips/bcm947xx/include/sbhnddma.h 1970-01-01 01:00:00.000000000 +0100
7611 +++ linux.dev/arch/mips/bcm947xx/include/sbhnddma.h 2005-11-07 23:37:03.453685750 +0100
7612 @@ -0,0 +1,312 @@
7613 +/*
7614 + * Generic Broadcom Home Networking Division (HND) DMA engine HW interface
7615 + * This supports the following chips: BCM42xx, 44xx, 47xx .
7616 + *
7617 + * Copyright 2005, Broadcom Corporation
7618 + * All Rights Reserved.
7619 + *
7620 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7621 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7622 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7623 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7624 + * $Id$
7625 + */
7626 +
7627 +#ifndef _sbhnddma_h_
7628 +#define _sbhnddma_h_
7629 +
7630 +
7631 +/* 2byte-wide pio register set per channel(xmt or rcv) */
7632 +typedef volatile struct {
7633 + uint16 fifocontrol;
7634 + uint16 fifodata;
7635 + uint16 fifofree; /* only valid in xmt channel, not in rcv channel */
7636 + uint16 PAD;
7637 +} pio2regs_t;
7638 +
7639 +/* a pair of pio channels(tx and rx) */
7640 +typedef volatile struct {
7641 + pio2regs_t tx;
7642 + pio2regs_t rx;
7643 +} pio2regp_t;
7644 +
7645 +/* 4byte-wide pio register set per channel(xmt or rcv) */
7646 +typedef volatile struct {
7647 + uint32 fifocontrol;
7648 + uint32 fifodata;
7649 +} pio4regs_t;
7650 +
7651 +/* a pair of pio channels(tx and rx) */
7652 +typedef volatile struct {
7653 + pio4regs_t tx;
7654 + pio4regs_t rx;
7655 +} pio4regp_t;
7656 +
7657 +
7658 +
7659 +/* DMA structure:
7660 + * support two DMA engines: 32 bits address or 64 bit addressing
7661 + * basic DMA register set is per channel(transmit or receive)
7662 + * a pair of channels is defined for convenience
7663 + */
7664 +
7665 +
7666 +/*** 32 bits addressing ***/
7667 +
7668 +/* dma registers per channel(xmt or rcv) */
7669 +typedef volatile struct {
7670 + uint32 control; /* enable, et al */
7671 + uint32 addr; /* descriptor ring base address (4K aligned) */
7672 + uint32 ptr; /* last descriptor posted to chip */
7673 + uint32 status; /* current active descriptor, et al */
7674 +} dma32regs_t;
7675 +
7676 +typedef volatile struct {
7677 + dma32regs_t xmt; /* dma tx channel */
7678 + dma32regs_t rcv; /* dma rx channel */
7679 +} dma32regp_t;
7680 +
7681 +typedef volatile struct { /* diag access */
7682 + uint32 fifoaddr; /* diag address */
7683 + uint32 fifodatalow; /* low 32bits of data */
7684 + uint32 fifodatahigh; /* high 32bits of data */
7685 + uint32 pad; /* reserved */
7686 +} dma32diag_t;
7687 +
7688 +/*
7689 + * DMA Descriptor
7690 + * Descriptors are only read by the hardware, never written back.
7691 + */
7692 +typedef volatile struct {
7693 + uint32 ctrl; /* misc control bits & bufcount */
7694 + uint32 addr; /* data buffer address */
7695 +} dma32dd_t;
7696 +
7697 +/*
7698 + * Each descriptor ring must be 4096byte aligned, and fit within a single 4096byte page.
7699 + */
7700 +#define D32MAXRINGSZ 4096
7701 +#define D32RINGALIGN 4096
7702 +#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
7703 +
7704 +/* transmit channel control */
7705 +#define XC_XE ((uint32)1 << 0) /* transmit enable */
7706 +#define XC_SE ((uint32)1 << 1) /* transmit suspend request */
7707 +#define XC_LE ((uint32)1 << 2) /* loopback enable */
7708 +#define XC_FL ((uint32)1 << 4) /* flush request */
7709 +#define XC_AE ((uint32)3 << 16) /* address extension bits */
7710 +#define XC_AE_SHIFT 16
7711 +
7712 +/* transmit descriptor table pointer */
7713 +#define XP_LD_MASK 0xfff /* last valid descriptor */
7714 +
7715 +/* transmit channel status */
7716 +#define XS_CD_MASK 0x0fff /* current descriptor pointer */
7717 +#define XS_XS_MASK 0xf000 /* transmit state */
7718 +#define XS_XS_SHIFT 12
7719 +#define XS_XS_DISABLED 0x0000 /* disabled */
7720 +#define XS_XS_ACTIVE 0x1000 /* active */
7721 +#define XS_XS_IDLE 0x2000 /* idle wait */
7722 +#define XS_XS_STOPPED 0x3000 /* stopped */
7723 +#define XS_XS_SUSP 0x4000 /* suspend pending */
7724 +#define XS_XE_MASK 0xf0000 /* transmit errors */
7725 +#define XS_XE_SHIFT 16
7726 +#define XS_XE_NOERR 0x00000 /* no error */
7727 +#define XS_XE_DPE 0x10000 /* descriptor protocol error */
7728 +#define XS_XE_DFU 0x20000 /* data fifo underrun */
7729 +#define XS_XE_BEBR 0x30000 /* bus error on buffer read */
7730 +#define XS_XE_BEDA 0x40000 /* bus error on descriptor access */
7731 +#define XS_AD_MASK 0xfff00000 /* active descriptor */
7732 +#define XS_AD_SHIFT 20
7733 +
7734 +/* receive channel control */
7735 +#define RC_RE ((uint32)1 << 0) /* receive enable */
7736 +#define RC_RO_MASK 0xfe /* receive frame offset */
7737 +#define RC_RO_SHIFT 1
7738 +#define RC_FM ((uint32)1 << 8) /* direct fifo receive (pio) mode */
7739 +#define RC_AE ((uint32)3 << 16) /* address extension bits */
7740 +#define RC_AE_SHIFT 16
7741 +
7742 +/* receive descriptor table pointer */
7743 +#define RP_LD_MASK 0xfff /* last valid descriptor */
7744 +
7745 +/* receive channel status */
7746 +#define RS_CD_MASK 0x0fff /* current descriptor pointer */
7747 +#define RS_RS_MASK 0xf000 /* receive state */
7748 +#define RS_RS_SHIFT 12
7749 +#define RS_RS_DISABLED 0x0000 /* disabled */
7750 +#define RS_RS_ACTIVE 0x1000 /* active */
7751 +#define RS_RS_IDLE 0x2000 /* idle wait */
7752 +#define RS_RS_STOPPED 0x3000 /* reserved */
7753 +#define RS_RE_MASK 0xf0000 /* receive errors */
7754 +#define RS_RE_SHIFT 16
7755 +#define RS_RE_NOERR 0x00000 /* no error */
7756 +#define RS_RE_DPE 0x10000 /* descriptor protocol error */
7757 +#define RS_RE_DFO 0x20000 /* data fifo overflow */
7758 +#define RS_RE_BEBW 0x30000 /* bus error on buffer write */
7759 +#define RS_RE_BEDA 0x40000 /* bus error on descriptor access */
7760 +#define RS_AD_MASK 0xfff00000 /* active descriptor */
7761 +#define RS_AD_SHIFT 20
7762 +
7763 +/* fifoaddr */
7764 +#define FA_OFF_MASK 0xffff /* offset */
7765 +#define FA_SEL_MASK 0xf0000 /* select */
7766 +#define FA_SEL_SHIFT 16
7767 +#define FA_SEL_XDD 0x00000 /* transmit dma data */
7768 +#define FA_SEL_XDP 0x10000 /* transmit dma pointers */
7769 +#define FA_SEL_RDD 0x40000 /* receive dma data */
7770 +#define FA_SEL_RDP 0x50000 /* receive dma pointers */
7771 +#define FA_SEL_XFD 0x80000 /* transmit fifo data */
7772 +#define FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7773 +#define FA_SEL_RFD 0xc0000 /* receive fifo data */
7774 +#define FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7775 +#define FA_SEL_RSD 0xe0000 /* receive frame status data */
7776 +#define FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7777 +
7778 +/* descriptor control flags */
7779 +#define CTRL_BC_MASK 0x1fff /* buffer byte count */
7780 +#define CTRL_AE ((uint32)3 << 16) /* address extension bits */
7781 +#define CTRL_AE_SHIFT 16
7782 +#define CTRL_EOT ((uint32)1 << 28) /* end of descriptor table */
7783 +#define CTRL_IOC ((uint32)1 << 29) /* interrupt on completion */
7784 +#define CTRL_EOF ((uint32)1 << 30) /* end of frame */
7785 +#define CTRL_SOF ((uint32)1 << 31) /* start of frame */
7786 +
7787 +/* control flags in the range [27:20] are core-specific and not defined here */
7788 +#define CTRL_CORE_MASK 0x0ff00000
7789 +
7790 +/*** 64 bits addressing ***/
7791 +
7792 +/* dma registers per channel(xmt or rcv) */
7793 +typedef volatile struct {
7794 + uint32 control; /* enable, et al */
7795 + uint32 ptr; /* last descriptor posted to chip */
7796 + uint32 addrlow; /* descriptor ring base address low 32-bits (8K aligned) */
7797 + uint32 addrhigh; /* descriptor ring base address bits 63:32 (8K aligned) */
7798 + uint32 status0; /* current descriptor, xmt state */
7799 + uint32 status1; /* active descriptor, xmt error */
7800 +} dma64regs_t;
7801 +
7802 +typedef volatile struct {
7803 + dma64regs_t tx; /* dma64 tx channel */
7804 + dma64regs_t rx; /* dma64 rx channel */
7805 +} dma64regp_t;
7806 +
7807 +typedef volatile struct { /* diag access */
7808 + uint32 fifoaddr; /* diag address */
7809 + uint32 fifodatalow; /* low 32bits of data */
7810 + uint32 fifodatahigh; /* high 32bits of data */
7811 + uint32 pad; /* reserved */
7812 +} dma64diag_t;
7813 +
7814 +/*
7815 + * DMA Descriptor
7816 + * Descriptors are only read by the hardware, never written back.
7817 + */
7818 +typedef volatile struct {
7819 + uint32 ctrl1; /* misc control bits & bufcount */
7820 + uint32 ctrl2; /* buffer count and address extension */
7821 + uint32 addrlow; /* memory address of the first byte of the date buffer, bits 31:0 */
7822 + uint32 addrhigh; /* memory address of the first byte of the date buffer, bits 63:32 */
7823 +} dma64dd_t;
7824 +
7825 +/*
7826 + * Each descriptor ring must be 8kB aligned, and fit within a contiguous 8kB physical addresss.
7827 + */
7828 +#define D64MAXRINGSZ 8192
7829 +#define D64RINGALIGN 8192
7830 +#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
7831 +
7832 +/* transmit channel control */
7833 +#define D64_XC_XE 0x00000001 /* transmit enable */
7834 +#define D64_XC_SE 0x00000002 /* transmit suspend request */
7835 +#define D64_XC_LE 0x00000004 /* loopback enable */
7836 +#define D64_XC_FL 0x00000010 /* flush request */
7837 +#define D64_XC_AE 0x00110000 /* address extension bits */
7838 +#define D64_XC_AE_SHIFT 16
7839 +
7840 +/* transmit descriptor table pointer */
7841 +#define D64_XP_LD_MASK 0x00000fff /* last valid descriptor */
7842 +
7843 +/* transmit channel status */
7844 +#define D64_XS0_CD_MASK 0x00001fff /* current descriptor pointer */
7845 +#define D64_XS0_XS_MASK 0xf0000000 /* transmit state */
7846 +#define D64_XS0_XS_SHIFT 28
7847 +#define D64_XS0_XS_DISABLED 0x00000000 /* disabled */
7848 +#define D64_XS0_XS_ACTIVE 0x10000000 /* active */
7849 +#define D64_XS0_XS_IDLE 0x20000000 /* idle wait */
7850 +#define D64_XS0_XS_STOPPED 0x30000000 /* stopped */
7851 +#define D64_XS0_XS_SUSP 0x40000000 /* suspend pending */
7852 +
7853 +#define D64_XS1_AD_MASK 0x0001ffff /* active descriptor */
7854 +#define D64_XS1_XE_MASK 0xf0000000 /* transmit errors */
7855 +#define D64_XS1_XE_SHIFT 28
7856 +#define D64_XS1_XE_NOERR 0x00000000 /* no error */
7857 +#define D64_XS1_XE_DPE 0x10000000 /* descriptor protocol error */
7858 +#define D64_XS1_XE_DFU 0x20000000 /* data fifo underrun */
7859 +#define D64_XS1_XE_DTE 0x30000000 /* data transfer error */
7860 +#define D64_XS1_XE_DESRE 0x40000000 /* descriptor read error */
7861 +#define D64_XS1_XE_COREE 0x50000000 /* core error */
7862 +
7863 +/* receive channel control */
7864 +#define D64_RC_RE 0x00000001 /* receive enable */
7865 +#define D64_RC_RO_MASK 0x000000fe /* receive frame offset */
7866 +#define D64_RC_RO_SHIFT 1
7867 +#define D64_RC_FM 0x00000100 /* direct fifo receive (pio) mode */
7868 +#define D64_RC_AE 0x00110000 /* address extension bits */
7869 +#define D64_RC_AE_SHIFT 16
7870 +
7871 +/* receive descriptor table pointer */
7872 +#define D64_RP_LD_MASK 0x00000fff /* last valid descriptor */
7873 +
7874 +/* receive channel status */
7875 +#define D64_RS0_CD_MASK 0x00001fff /* current descriptor pointer */
7876 +#define D64_RS0_RS_MASK 0xf0000000 /* receive state */
7877 +#define D64_RS0_RS_SHIFT 28
7878 +#define D64_RS0_RS_DISABLED 0x00000000 /* disabled */
7879 +#define D64_RS0_RS_ACTIVE 0x10000000 /* active */
7880 +#define D64_RS0_RS_IDLE 0x20000000 /* idle wait */
7881 +#define D64_RS0_RS_STOPPED 0x30000000 /* stopped */
7882 +#define D64_RS0_RS_SUSP 0x40000000 /* suspend pending */
7883 +
7884 +#define D64_RS1_AD_MASK 0x0001ffff /* active descriptor */
7885 +#define D64_RS1_RE_MASK 0xf0000000 /* receive errors */
7886 +#define D64_RS1_RE_SHIFT 28
7887 +#define D64_RS1_RE_NOERR 0x00000000 /* no error */
7888 +#define D64_RS1_RE_DPO 0x10000000 /* descriptor protocol error */
7889 +#define D64_RS1_RE_DFU 0x20000000 /* data fifo overflow */
7890 +#define D64_RS1_RE_DTE 0x30000000 /* data transfer error */
7891 +#define D64_RS1_RE_DESRE 0x40000000 /* descriptor read error */
7892 +#define D64_RS1_RE_COREE 0x50000000 /* core error */
7893 +
7894 +/* fifoaddr */
7895 +#define D64_FA_OFF_MASK 0xffff /* offset */
7896 +#define D64_FA_SEL_MASK 0xf0000 /* select */
7897 +#define D64_FA_SEL_SHIFT 16
7898 +#define D64_FA_SEL_XDD 0x00000 /* transmit dma data */
7899 +#define D64_FA_SEL_XDP 0x10000 /* transmit dma pointers */
7900 +#define D64_FA_SEL_RDD 0x40000 /* receive dma data */
7901 +#define D64_FA_SEL_RDP 0x50000 /* receive dma pointers */
7902 +#define D64_FA_SEL_XFD 0x80000 /* transmit fifo data */
7903 +#define D64_FA_SEL_XFP 0x90000 /* transmit fifo pointers */
7904 +#define D64_FA_SEL_RFD 0xc0000 /* receive fifo data */
7905 +#define D64_FA_SEL_RFP 0xd0000 /* receive fifo pointers */
7906 +#define D64_FA_SEL_RSD 0xe0000 /* receive frame status data */
7907 +#define D64_FA_SEL_RSP 0xf0000 /* receive frame status pointers */
7908 +
7909 +/* descriptor control flags 1 */
7910 +#define D64_CTRL1_EOT ((uint32)1 << 28) /* end of descriptor table */
7911 +#define D64_CTRL1_IOC ((uint32)1 << 29) /* interrupt on completion */
7912 +#define D64_CTRL1_EOF ((uint32)1 << 30) /* end of frame */
7913 +#define D64_CTRL1_SOF ((uint32)1 << 31) /* start of frame */
7914 +
7915 +/* descriptor control flags 2 */
7916 +#define D64_CTRL2_BC_MASK 0x00007fff /* buffer byte count mask */
7917 +#define D64_CTRL2_AE 0x00110000 /* address extension bits */
7918 +#define D64_CTRL2_AE_SHIFT 16
7919 +
7920 +/* control flags in the range [27:20] are core-specific and not defined here */
7921 +#define D64_CTRL_CORE_MASK 0x0ff00000
7922 +
7923 +
7924 +#endif /* _sbhnddma_h_ */
7925 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
7926 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
7927 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-11-07 22:51:38.784726500 +0100
7928 @@ -0,0 +1,148 @@
7929 +/*
7930 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
7931 + *
7932 + * Copyright 2005, Broadcom Corporation
7933 + * All Rights Reserved.
7934 + *
7935 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7936 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7937 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7938 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7939 + *
7940 + * $Id$
7941 + */
7942 +
7943 +#ifndef _SBMEMC_H
7944 +#define _SBMEMC_H
7945 +
7946 +#ifdef _LANGUAGE_ASSEMBLY
7947 +
7948 +#define MEMC_CONTROL 0x00
7949 +#define MEMC_CONFIG 0x04
7950 +#define MEMC_REFRESH 0x08
7951 +#define MEMC_BISTSTAT 0x0c
7952 +#define MEMC_MODEBUF 0x10
7953 +#define MEMC_BKCLS 0x14
7954 +#define MEMC_PRIORINV 0x18
7955 +#define MEMC_DRAMTIM 0x1c
7956 +#define MEMC_INTSTAT 0x20
7957 +#define MEMC_INTMASK 0x24
7958 +#define MEMC_INTINFO 0x28
7959 +#define MEMC_NCDLCTL 0x30
7960 +#define MEMC_RDNCDLCOR 0x34
7961 +#define MEMC_WRNCDLCOR 0x38
7962 +#define MEMC_MISCDLYCTL 0x3c
7963 +#define MEMC_DQSGATENCDL 0x40
7964 +#define MEMC_SPARE 0x44
7965 +#define MEMC_TPADDR 0x48
7966 +#define MEMC_TPDATA 0x4c
7967 +#define MEMC_BARRIER 0x50
7968 +#define MEMC_CORE 0x54
7969 +
7970 +
7971 +#else
7972 +
7973 +/* Sonics side: MEMC core registers */
7974 +typedef volatile struct sbmemcregs {
7975 + uint32 control;
7976 + uint32 config;
7977 + uint32 refresh;
7978 + uint32 biststat;
7979 + uint32 modebuf;
7980 + uint32 bkcls;
7981 + uint32 priorinv;
7982 + uint32 dramtim;
7983 + uint32 intstat;
7984 + uint32 intmask;
7985 + uint32 intinfo;
7986 + uint32 reserved1;
7987 + uint32 ncdlctl;
7988 + uint32 rdncdlcor;
7989 + uint32 wrncdlcor;
7990 + uint32 miscdlyctl;
7991 + uint32 dqsgatencdl;
7992 + uint32 spare;
7993 + uint32 tpaddr;
7994 + uint32 tpdata;
7995 + uint32 barrier;
7996 + uint32 core;
7997 +} sbmemcregs_t;
7998 +
7999 +#endif
8000 +
8001 +/* MEMC Core Init values (OCP ID 0x80f) */
8002 +
8003 +/* For sdr: */
8004 +#define MEMC_SD_CONFIG_INIT 0x00048000
8005 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
8006 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
8007 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
8008 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
8009 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
8010 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
8011 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
8012 +#define MEMC_SD_CONTROL_INIT0 0x00000002
8013 +#define MEMC_SD_CONTROL_INIT1 0x00000008
8014 +#define MEMC_SD_CONTROL_INIT2 0x00000004
8015 +#define MEMC_SD_CONTROL_INIT3 0x00000010
8016 +#define MEMC_SD_CONTROL_INIT4 0x00000001
8017 +#define MEMC_SD_MODEBUF_INIT 0x00000000
8018 +#define MEMC_SD_REFRESH_INIT 0x0000840f
8019 +
8020 +
8021 +/* This is for SDRM8X8X4 */
8022 +#define MEMC_SDR_INIT 0x0008
8023 +#define MEMC_SDR_MODE 0x32
8024 +#define MEMC_SDR_NCDL 0x00020032
8025 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
8026 +
8027 +/* For ddr: */
8028 +#define MEMC_CONFIG_INIT 0x00048000
8029 +#define MEMC_DRAMTIM2_INIT 0x000754d8
8030 +#define MEMC_DRAMTIM25_INIT 0x000754d9
8031 +#define MEMC_RDNCDLCOR_INIT 0x00000000
8032 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
8033 +#define MEMC_WRNCDLCOR_INIT 0x49351200
8034 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
8035 +#define MEMC_DQSGATENCDL_INIT 0x00030000
8036 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
8037 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
8038 +#define MEMC_NCDLCTL_INIT 0x00002001
8039 +#define MEMC_CONTROL_INIT0 0x00000002
8040 +#define MEMC_CONTROL_INIT1 0x00000008
8041 +#define MEMC_MODEBUF_INIT0 0x00004000
8042 +#define MEMC_CONTROL_INIT2 0x00000010
8043 +#define MEMC_MODEBUF_INIT1 0x00000100
8044 +#define MEMC_CONTROL_INIT3 0x00000010
8045 +#define MEMC_CONTROL_INIT4 0x00000008
8046 +#define MEMC_REFRESH_INIT 0x0000840f
8047 +#define MEMC_CONTROL_INIT5 0x00000004
8048 +#define MEMC_MODEBUF_INIT2 0x00000000
8049 +#define MEMC_CONTROL_INIT6 0x00000010
8050 +#define MEMC_CONTROL_INIT7 0x00000001
8051 +
8052 +
8053 +/* This is for DDRM16X16X2 */
8054 +#define MEMC_DDR_INIT 0x0009
8055 +#define MEMC_DDR_MODE 0x62
8056 +#define MEMC_DDR_NCDL 0x0005050a
8057 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
8058 +
8059 +/* mask for sdr/ddr calibration registers */
8060 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
8061 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
8062 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
8063 +
8064 +/* masks for miscdlyctl registers */
8065 +#define MEMC_MISC_SM_MASK 0x30000000
8066 +#define MEMC_MISC_SM_SHIFT 28
8067 +#define MEMC_MISC_SD_MASK 0x0f000000
8068 +#define MEMC_MISC_SD_SHIFT 24
8069 +
8070 +/* hw threshhold for calculating wr/rd for sdr memc */
8071 +#define MEMC_CD_THRESHOLD 128
8072 +
8073 +/* Low bit of init register says if memc is ddr or sdr */
8074 +#define MEMC_CONFIG_DDR 0x00000001
8075 +
8076 +#endif /* _SBMEMC_H */
8077 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
8078 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
8079 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-11-07 22:51:38.784726500 +0100
8080 @@ -0,0 +1,62 @@
8081 +/*
8082 + * Broadcom SiliconBackplane MIPS definitions
8083 + *
8084 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
8085 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
8086 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
8087 + * interface. The core revision is stored in the SB ID register in SB
8088 + * configuration space.
8089 + *
8090 + * Copyright 2005, Broadcom Corporation
8091 + * All Rights Reserved.
8092 + *
8093 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8094 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8095 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8096 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8097 + *
8098 + * $Id$
8099 + */
8100 +
8101 +#ifndef _SBMIPS_H
8102 +#define _SBMIPS_H
8103 +
8104 +#include <mipsinc.h>
8105 +
8106 +#ifndef _LANGUAGE_ASSEMBLY
8107 +
8108 +/* cpp contortions to concatenate w/arg prescan */
8109 +#ifndef PAD
8110 +#define _PADLINE(line) pad ## line
8111 +#define _XSTR(line) _PADLINE(line)
8112 +#define PAD _XSTR(__LINE__)
8113 +#endif /* PAD */
8114 +
8115 +typedef volatile struct {
8116 + uint32 corecontrol;
8117 + uint32 PAD[2];
8118 + uint32 biststatus;
8119 + uint32 PAD[4];
8120 + uint32 intstatus;
8121 + uint32 intmask;
8122 + uint32 timer;
8123 +} mipsregs_t;
8124 +
8125 +extern uint32 sb_flag(sb_t *sbh);
8126 +extern uint sb_irq(sb_t *sbh);
8127 +
8128 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
8129 +
8130 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
8131 +extern void sb_jtagm_disable(void *h);
8132 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
8133 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
8134 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
8135 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
8136 +extern void BCMINIT(enable_pfc)(uint32 mode);
8137 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
8138 +
8139 +
8140 +#endif /* _LANGUAGE_ASSEMBLY */
8141 +
8142 +#endif /* _SBMIPS_H */
8143 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
8144 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
8145 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-11-07 22:51:38.788726750 +0100
8146 @@ -0,0 +1,122 @@
8147 +/*
8148 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
8149 + *
8150 + * $Id$
8151 + * Copyright 2005, Broadcom Corporation
8152 + * All Rights Reserved.
8153 + *
8154 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8155 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8156 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8157 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8158 + */
8159 +
8160 +#ifndef _SBPCI_H
8161 +#define _SBPCI_H
8162 +
8163 +/* cpp contortions to concatenate w/arg prescan */
8164 +#ifndef PAD
8165 +#define _PADLINE(line) pad ## line
8166 +#define _XSTR(line) _PADLINE(line)
8167 +#define PAD _XSTR(__LINE__)
8168 +#endif
8169 +
8170 +/* Sonics side: PCI core and host control registers */
8171 +typedef struct sbpciregs {
8172 + uint32 control; /* PCI control */
8173 + uint32 PAD[3];
8174 + uint32 arbcontrol; /* PCI arbiter control */
8175 + uint32 PAD[3];
8176 + uint32 intstatus; /* Interrupt status */
8177 + uint32 intmask; /* Interrupt mask */
8178 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
8179 + uint32 PAD[9];
8180 + uint32 bcastaddr; /* Sonics broadcast address */
8181 + uint32 bcastdata; /* Sonics broadcast data */
8182 + uint32 PAD[2];
8183 + uint32 gpioin; /* ro: gpio input (>=rev2) */
8184 + uint32 gpioout; /* rw: gpio output (>=rev2) */
8185 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
8186 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
8187 + uint32 PAD[36];
8188 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
8189 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
8190 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
8191 + uint32 PAD[445];
8192 + uint16 sprom[36]; /* SPROM shadow Area */
8193 + uint32 PAD[46];
8194 +} sbpciregs_t;
8195 +
8196 +/* PCI control */
8197 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
8198 +#define PCI_RST 0x02 /* Value driven out to pin */
8199 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
8200 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
8201 +
8202 +/* PCI arbiter control */
8203 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
8204 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
8205 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
8206 +#define PCI_PARKID_SHIFT 1
8207 +#define PCI_PARKID_LAST 0 /* Last requestor */
8208 +#define PCI_PARKID_4710 1 /* 4710 */
8209 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
8210 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
8211 +
8212 +/* Interrupt status/mask */
8213 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
8214 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
8215 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
8216 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
8217 +#define PCI_PME 0x10 /* PCI PME# is asserted */
8218 +
8219 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
8220 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
8221 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
8222 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
8223 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
8224 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
8225 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
8226 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
8227 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
8228 +
8229 +/* Sonics broadcast address */
8230 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
8231 +
8232 +/* Sonics to PCI translation types */
8233 +#define SBTOPCI0_MASK 0xfc000000
8234 +#define SBTOPCI1_MASK 0xfc000000
8235 +#define SBTOPCI2_MASK 0xc0000000
8236 +#define SBTOPCI_MEM 0
8237 +#define SBTOPCI_IO 1
8238 +#define SBTOPCI_CFG0 2
8239 +#define SBTOPCI_CFG1 3
8240 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
8241 +#define SBTOPCI_BURST 0x8 /* burst enable */
8242 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
8243 +#define SBTOPCI_RC_READ 0x00 /* memory read */
8244 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
8245 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
8246 +
8247 +/* PCI core index in SROM shadow area */
8248 +#define SRSH_PI_OFFSET 0 /* first word */
8249 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
8250 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
8251 +
8252 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
8253 +#define cap_list rsvd_a[0]
8254 +#define bar0_window dev_dep[0x80 - 0x40]
8255 +#define bar1_window dev_dep[0x84 - 0x40]
8256 +#define sprom_control dev_dep[0x88 - 0x40]
8257 +
8258 +#ifndef _LANGUAGE_ASSEMBLY
8259 +
8260 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8261 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
8262 +extern void sbpci_ban(uint16 core);
8263 +extern int sbpci_init(sb_t *sbh);
8264 +extern void sbpci_check(sb_t *sbh);
8265 +
8266 +#endif /* !_LANGUAGE_ASSEMBLY */
8267 +
8268 +#endif /* _SBPCI_H */
8269 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcie.h linux.dev/arch/mips/bcm947xx/include/sbpcie.h
8270 --- linux.old/arch/mips/bcm947xx/include/sbpcie.h 1970-01-01 01:00:00.000000000 +0100
8271 +++ linux.dev/arch/mips/bcm947xx/include/sbpcie.h 2005-11-07 23:39:41.403557000 +0100
8272 @@ -0,0 +1,199 @@
8273 +/*
8274 + * BCM43XX SiliconBackplane PCIE core hardware definitions.
8275 + *
8276 + * $Id:
8277 + * Copyright 2005, Broadcom Corporation
8278 + * All Rights Reserved.
8279 + *
8280 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8281 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8282 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8283 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8284 + */
8285 +
8286 +#ifndef _SBPCIE_H
8287 +#define _SBPCIE_H
8288 +
8289 +/* cpp contortions to concatenate w/arg prescan */
8290 +#ifndef PAD
8291 +#define _PADLINE(line) pad ## line
8292 +#define _XSTR(line) _PADLINE(line)
8293 +#define PAD _XSTR(__LINE__)
8294 +#endif
8295 +
8296 +/* PCIE Enumeration space offsets*/
8297 +#define PCIE_CORE_CONFIG_OFFSET 0x0
8298 +#define PCIE_FUNC0_CONFIG_OFFSET 0x400
8299 +#define PCIE_FUNC1_CONFIG_OFFSET 0x500
8300 +#define PCIE_FUNC2_CONFIG_OFFSET 0x600
8301 +#define PCIE_FUNC3_CONFIG_OFFSET 0x700
8302 +#define PCIE_SPROM_SHADOW_OFFSET 0x800
8303 +#define PCIE_SBCONFIG_OFFSET 0xE00
8304 +
8305 +/* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
8306 +#define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
8307 +#define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
8308 +#define PCIE_BAR0_PCIECORE_OFFSET 0x2000
8309 +#define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
8310 +
8311 +/* SB side: PCIE core and host control registers */
8312 +typedef struct sbpcieregs {
8313 +
8314 + uint32 PAD[3];
8315 + uint32 biststatus; /* bist Status: 0x00C*/
8316 + uint32 PAD[6];
8317 + uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028*/
8318 + uint32 PAD[54];
8319 + uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
8320 + uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
8321 + uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
8322 + uint32 PAD[4];
8323 +
8324 + /* pcie core supports in direct access to config space */
8325 + uint32 configaddr; /* pcie config space access: Address field: 0x120*/
8326 + uint32 configdata; /* pcie config space access: Data field: 0x124*/
8327 +
8328 + /* mdio access to serdes */
8329 + uint32 mdiocontrol; /* controls the mdio access: 0x128 */
8330 + uint32 mdiodata; /* Data to the mdio access: 0x12c */
8331 +
8332 + /* pcie protocol phy/dllp/tlp register access mechanism*/
8333 + uint32 pcieaddr; /* address of the internal registeru: 0x130 */
8334 + uint32 pciedata; /* Data to/from the internal regsiter: 0x134 */
8335 +
8336 + uint32 PAD[434];
8337 + uint16 sprom[36]; /* SPROM shadow Area */
8338 +} sbpcieregs_t;
8339 +
8340 +/* SB to PCIE translation masks */
8341 +#define SBTOPCIE0_MASK 0xfc000000
8342 +#define SBTOPCIE1_MASK 0xfc000000
8343 +#define SBTOPCIE2_MASK 0xc0000000
8344 +
8345 +/* Access type bits (0:1)*/
8346 +#define SBTOPCIE_MEM 0
8347 +#define SBTOPCIE_IO 1
8348 +#define SBTOPCIE_CFG0 2
8349 +#define SBTOPCIE_CFG1 3
8350 +
8351 +/*Prefetch enable bit 2*/
8352 +#define SBTOPCIE_PF 4
8353 +
8354 +/*Write Burst enable for memory write bit 3*/
8355 +#define SBTOPCIE_WR_BURST 8
8356 +
8357 +/* config access */
8358 +#define CONFIGADDR_FUNC_MASK 0x7000
8359 +#define CONFIGADDR_FUNC_SHF 12
8360 +#define CONFIGADDR_REG_MASK 0x0FFF
8361 +#define CONFIGADDR_REG_SHF 0
8362 +
8363 +/* PCIE protocol regs Indirect Address */
8364 +#define PCIEADDR_PROT_MASK 0x300
8365 +#define PCIEADDR_PROT_SHF 8
8366 +#define PCIEADDR_PL_TLP 0
8367 +#define PCIEADDR_PL_DLLP 1
8368 +#define PCIEADDR_PL_PLP 2
8369 +
8370 +/* PCIE protocol PHY diagnostic registers */
8371 +#define PCIE_PLP_MODEREG 0x200 /* Mode*/
8372 +#define PCIE_PLP_STATUSREG 0x204 /* Status*/
8373 +#define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
8374 +#define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number*/
8375 +#define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number*/
8376 +#define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
8377 +#define PCIE_PLP_ATTNREG 0x218 /* Attention */
8378 +#define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
8379 +#define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
8380 +#define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error*/
8381 +#define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
8382 +#define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg*/
8383 +#define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
8384 +#define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
8385 +#define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag*/
8386 +#define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag*/
8387 +
8388 +/* PCIE protocol DLLP diagnostic registers */
8389 +#define PCIE_DLLP_LCREG 0x100 /* Link Control*/
8390 +#define PCIE_DLLP_LSREG 0x104 /* Link Status */
8391 +#define PCIE_DLLP_LAREG 0x108 /* Link Attention*/
8392 +#define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
8393 +#define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num*/
8394 +#define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num*/
8395 +#define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num*/
8396 +#define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
8397 +#define PCIE_DLLP_LRREG 0x120 /* Link Replay*/
8398 +#define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout*/
8399 +#define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold*/
8400 +#define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr*/
8401 +#define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr*/
8402 +#define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr*/
8403 +#define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write*/
8404 +#define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
8405 +#define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
8406 +#define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter*/
8407 +#define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter*/
8408 +#define PCIE_DLLP_TESTREG 0x14C /* Test */
8409 +#define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST*/
8410 +
8411 +/* PCIE protocol TLP diagnostic registers */
8412 +#define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
8413 +#define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
8414 +#define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address*/
8415 +#define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address*/
8416 +#define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req*/
8417 +#define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address*/
8418 +#define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address*/
8419 +#define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req*/
8420 +#define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address*/
8421 +#define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address*/
8422 +#define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req*/
8423 +#define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len*/
8424 +#define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs*/
8425 +#define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req*/
8426 +#define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len*/
8427 +#define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0*/
8428 +#define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1*/
8429 +#define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2*/
8430 +#define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
8431 +#define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
8432 +#define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
8433 +#define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len*/
8434 +#define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0*/
8435 +#define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1*/
8436 +#define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func*/
8437 +#define PCIE_TLP_RESETCTR 0x06C /* Reset Counter*/
8438 +#define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value*/
8439 +#define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1*/
8440 +#define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2*/
8441 +#define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3*/
8442 +#define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4*/
8443 +
8444 +/* MDIO control */
8445 +#define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
8446 +#define MDIOCTL_DIVISOR_VAL 0x2
8447 +#define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
8448 +#define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
8449 +
8450 +/* MDIO Data */
8451 +#define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
8452 +#define MDIODATA_TA 0x00020000 /* Turnaround */
8453 +#define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
8454 +#define MDIODATA_REGADDR_MASK 0x003c0000 /* Regaddr Mask */
8455 +#define MDIODATA_DEVADDR_SHF 22 /* Physmedia devaddr shift */
8456 +#define MDIODATA_DEVADDR_MASK 0x0fc00000 /* Physmedia devaddr Mask */
8457 +#define MDIODATA_WRITE 0x10000000 /* write Transaction */
8458 +#define MDIODATA_READ 0x20000000 /* Read Transaction */
8459 +#define MDIODATA_START 0x40000000 /* start of Transaction */
8460 +
8461 +/* MDIO devices (SERDES modules) */
8462 +#define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
8463 +#define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
8464 +#define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
8465 +
8466 +/* SERDES registers */
8467 +#define SERDES_RX_TIMER1 2 /* Rx Timer1 */
8468 +#define SERDES_RX_CDR 6 /* CDR */
8469 +#define SERDES_RX_CDRBW 7 /* CDR BW */
8470 +
8471 +#endif /* _SBPCIE_H */
8472 diff -urN linux.old/arch/mips/bcm947xx/include/sbpcmcia.h linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h
8473 --- linux.old/arch/mips/bcm947xx/include/sbpcmcia.h 1970-01-01 01:00:00.000000000 +0100
8474 +++ linux.dev/arch/mips/bcm947xx/include/sbpcmcia.h 2005-11-07 22:51:38.788726750 +0100
8475 @@ -0,0 +1,146 @@
8476 +/*
8477 + * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
8478 + *
8479 + * $Id$
8480 + * Copyright 2005, Broadcom Corporation
8481 + * All Rights Reserved.
8482 + *
8483 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8484 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8485 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8486 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8487 + */
8488 +
8489 +#ifndef _SBPCMCIA_H
8490 +#define _SBPCMCIA_H
8491 +
8492 +
8493 +/* All the addresses that are offsets in attribute space are divided
8494 + * by two to account for the fact that odd bytes are invalid in
8495 + * attribute space and our read/write routines make the space appear
8496 + * as if they didn't exist. Still we want to show the original numbers
8497 + * as documented in the hnd_pcmcia core manual.
8498 + */
8499 +
8500 +/* PCMCIA Function Configuration Registers */
8501 +#define PCMCIA_FCR (0x700 / 2)
8502 +
8503 +#define FCR0_OFF 0
8504 +#define FCR1_OFF (0x40 / 2)
8505 +#define FCR2_OFF (0x80 / 2)
8506 +#define FCR3_OFF (0xc0 / 2)
8507 +
8508 +#define PCMCIA_FCR0 (0x700 / 2)
8509 +#define PCMCIA_FCR1 (0x740 / 2)
8510 +#define PCMCIA_FCR2 (0x780 / 2)
8511 +#define PCMCIA_FCR3 (0x7c0 / 2)
8512 +
8513 +/* Standard PCMCIA FCR registers */
8514 +
8515 +#define PCMCIA_COR 0
8516 +
8517 +#define COR_RST 0x80
8518 +#define COR_LEV 0x40
8519 +#define COR_IRQEN 0x04
8520 +#define COR_BLREN 0x01
8521 +#define COR_FUNEN 0x01
8522 +
8523 +
8524 +#define PCICIA_FCSR (2 / 2)
8525 +#define PCICIA_PRR (4 / 2)
8526 +#define PCICIA_SCR (6 / 2)
8527 +#define PCICIA_ESR (8 / 2)
8528 +
8529 +
8530 +#define PCM_MEMOFF 0x0000
8531 +#define F0_MEMOFF 0x1000
8532 +#define F1_MEMOFF 0x2000
8533 +#define F2_MEMOFF 0x3000
8534 +#define F3_MEMOFF 0x4000
8535 +
8536 +/* Memory base in the function fcr's */
8537 +#define MEM_ADDR0 (0x728 / 2)
8538 +#define MEM_ADDR1 (0x72a / 2)
8539 +#define MEM_ADDR2 (0x72c / 2)
8540 +
8541 +/* PCMCIA base plus Srom access in fcr0: */
8542 +#define PCMCIA_ADDR0 (0x072e / 2)
8543 +#define PCMCIA_ADDR1 (0x0730 / 2)
8544 +#define PCMCIA_ADDR2 (0x0732 / 2)
8545 +
8546 +#define MEM_SEG (0x0734 / 2)
8547 +#define SROM_CS (0x0736 / 2)
8548 +#define SROM_DATAL (0x0738 / 2)
8549 +#define SROM_DATAH (0x073a / 2)
8550 +#define SROM_ADDRL (0x073c / 2)
8551 +#define SROM_ADDRH (0x073e / 2)
8552 +
8553 +/* Values for srom_cs: */
8554 +#define SROM_IDLE 0
8555 +#define SROM_WRITE 1
8556 +#define SROM_READ 2
8557 +#define SROM_WEN 4
8558 +#define SROM_WDS 7
8559 +#define SROM_DONE 8
8560 +
8561 +/* CIS stuff */
8562 +
8563 +/* The CIS stops where the FCRs start */
8564 +#define CIS_SIZE PCMCIA_FCR
8565 +
8566 +/* Standard tuples we know about */
8567 +
8568 +#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
8569 +#define CISTPL_FUNCE 0x22 /* Function extensions */
8570 +#define CISTPL_CFTABLE 0x1b /* Config table entry */
8571 +
8572 +/* Function extensions for LANs */
8573 +
8574 +#define LAN_TECH 1 /* Technology type */
8575 +#define LAN_SPEED 2 /* Raw bit rate */
8576 +#define LAN_MEDIA 3 /* Transmission media */
8577 +#define LAN_NID 4 /* Node identification (aka MAC addr) */
8578 +#define LAN_CONN 5 /* Connector standard */
8579 +
8580 +
8581 +/* CFTable */
8582 +#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
8583 +#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
8584 +#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
8585 +
8586 +/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
8587 + * take one for HNBU, and use "extensions" (a la FUNCE) within it.
8588 + */
8589 +
8590 +#define CISTPL_BRCM_HNBU 0x80
8591 +
8592 +/* Subtypes of BRCM_HNBU: */
8593 +
8594 +#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
8595 +#define HNBU_CHIPID 0x01 /* Six bytes with PCI vendor &
8596 + * device id and chiprev
8597 + */
8598 +#define HNBU_BOARDREV 0x02 /* Two bytes board revision */
8599 +#define HNBU_PAPARMS 0x03 /* PA parameters: 1 (old), 8 (sreomrev == 1)
8600 + * or 9 (sromrev > 1) bytes */
8601 +#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
8602 +#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
8603 +#define HNBU_AA 0x06 /* Antennas available */
8604 +#define HNBU_AG 0x07 /* Antenna gain */
8605 +#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
8606 +#define HNBU_LEDS 0x09 /* LED set */
8607 +#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
8608 + * in rev 2
8609 + */
8610 +#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
8611 +#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
8612 +
8613 +
8614 +/* sbtmstatelow */
8615 +#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
8616 +#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
8617 +
8618 +/* sbtmstatehigh */
8619 +#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
8620 +
8621 +#endif /* _SBPCMCIA_H */
8622 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
8623 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
8624 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-11-07 21:57:07.877587750 +0100
8625 @@ -0,0 +1,75 @@
8626 +/*
8627 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
8628 + *
8629 + * Copyright 2005, Broadcom Corporation
8630 + * All Rights Reserved.
8631 + *
8632 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8633 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8634 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8635 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8636 + * $Id$
8637 + */
8638 +
8639 +#ifndef _SBSDRAM_H
8640 +#define _SBSDRAM_H
8641 +
8642 +#ifndef _LANGUAGE_ASSEMBLY
8643 +
8644 +/* Sonics side: SDRAM core registers */
8645 +typedef volatile struct sbsdramregs {
8646 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
8647 + uint32 config; /* Initializes external SDRAM mode register */
8648 + uint32 refresh; /* Controls external SDRAM refresh rate */
8649 + uint32 pad1;
8650 + uint32 pad2;
8651 +} sbsdramregs_t;
8652 +
8653 +#endif
8654 +
8655 +/* SDRAM initialization control (initcontrol) register bits */
8656 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
8657 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
8658 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
8659 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
8660 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
8661 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
8662 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
8663 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
8664 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
8665 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
8666 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
8667 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
8668 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
8669 +
8670 +/* SDRAM configuration (config) register bits */
8671 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
8672 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
8673 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
8674 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
8675 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
8676 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
8677 +
8678 +/* SDRAM refresh control (refresh) register bits */
8679 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
8680 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
8681 +
8682 +/* SDRAM Core default Init values (OCP ID 0x803) */
8683 +#define SDRAM_INIT MEM4MX16X2
8684 +#define SDRAM_CONFIG SDRAM_BURSTFULL
8685 +#define SDRAM_REFRESH SDRAM_REF(0x40)
8686 +
8687 +#define MEM1MX16 0x009 /* 2 MB */
8688 +#define MEM1MX16X2 0x409 /* 4 MB */
8689 +#define MEM2MX8X2 0x809 /* 4 MB */
8690 +#define MEM2MX8X4 0xc09 /* 8 MB */
8691 +#define MEM2MX32 0x439 /* 8 MB */
8692 +#define MEM4MX16 0x019 /* 8 MB */
8693 +#define MEM4MX16X2 0x419 /* 16 MB */
8694 +#define MEM8MX8X2 0x819 /* 16 MB */
8695 +#define MEM8MX16 0x829 /* 16 MB */
8696 +#define MEM4MX32 0x429 /* 16 MB */
8697 +#define MEM8MX8X4 0xc19 /* 32 MB */
8698 +#define MEM8MX16X2 0xc29 /* 32 MB */
8699 +
8700 +#endif /* _SBSDRAM_H */
8701 diff -urN linux.old/arch/mips/bcm947xx/include/sbsocram.h linux.dev/arch/mips/bcm947xx/include/sbsocram.h
8702 --- linux.old/arch/mips/bcm947xx/include/sbsocram.h 1970-01-01 01:00:00.000000000 +0100
8703 +++ linux.dev/arch/mips/bcm947xx/include/sbsocram.h 2005-11-07 21:57:07.877587750 +0100
8704 @@ -0,0 +1,37 @@
8705 +/*
8706 + * BCM47XX Sonics SiliconBackplane embedded ram core
8707 + *
8708 + * Copyright 2005, Broadcom Corporation
8709 + * All Rights Reserved.
8710 + *
8711 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8712 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8713 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8714 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8715 + *
8716 + * $Id$
8717 + */
8718 +
8719 +#ifndef _SBSOCRAM_H
8720 +#define _SBSOCRAM_H
8721 +
8722 +#define SOCRAM_MEMSIZE 0x00
8723 +#define SOCRAM_BISTSTAT 0x0c
8724 +
8725 +
8726 +#ifndef _LANGUAGE_ASSEMBLY
8727 +
8728 +/* Memcsocram core registers */
8729 +typedef volatile struct sbsocramregs {
8730 + uint32 memsize;
8731 + uint32 biststat;
8732 +} sbsocramregs_t;
8733 +
8734 +#endif
8735 +
8736 +/* Them memory size is 2 to the power of the following
8737 + * base added to the contents of the memsize register.
8738 + */
8739 +#define SOCRAM_MEMSIZE_BASESHIFT 16
8740 +
8741 +#endif /* _SBSOCRAM_H */
8742 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
8743 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
8744 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-11-07 22:51:38.788726750 +0100
8745 @@ -0,0 +1,140 @@
8746 +/*
8747 + * Misc utility routines for accessing chip-specific features
8748 + * of Broadcom HNBU SiliconBackplane-based chips.
8749 + *
8750 + * Copyright 2005, Broadcom Corporation
8751 + * All Rights Reserved.
8752 + *
8753 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8754 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8755 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8756 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8757 + *
8758 + * $Id$
8759 + */
8760 +
8761 +#ifndef _sbutils_h_
8762 +#define _sbutils_h_
8763 +
8764 +/*
8765 + * Datastructure to export all chip specific common variables
8766 + * public (read-only) portion of sbutils handle returned by
8767 + * sb_attach()/sb_kattach()
8768 +*/
8769 +
8770 +struct sb_pub {
8771 +
8772 + uint bustype; /* SB_BUS, PCI_BUS */
8773 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
8774 + uint buscorerev; /* buscore rev */
8775 + uint buscoreidx; /* buscore index */
8776 + int ccrev; /* chip common core rev */
8777 + uint boardtype; /* board type */
8778 + uint boardvendor; /* board vendor */
8779 + uint chip; /* chip number */
8780 + uint chiprev; /* chip revision */
8781 + uint chippkg; /* chip package option */
8782 + uint sonicsrev; /* sonics backplane rev */
8783 +};
8784 +
8785 +typedef const struct sb_pub sb_t;
8786 +
8787 +/*
8788 + * Many of the routines below take an 'sbh' handle as their first arg.
8789 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
8790 + * At any one time, the sbh is logically focused on one particular sb core
8791 + * (the "current core").
8792 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
8793 + */
8794 +
8795 +/* exported externs */
8796 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
8797 +extern sb_t * BCMINIT(sb_kattach)(void);
8798 +extern void sb_detach(sb_t *sbh);
8799 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
8800 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
8801 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
8802 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
8803 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
8804 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
8805 +extern uint BCMINIT(sb_pcmciarev)(sb_t *sbh);
8806 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
8807 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
8808 +extern uint sb_bus(sb_t *sbh);
8809 +extern uint sb_buscoretype(sb_t *sbh);
8810 +extern uint sb_buscorerev(sb_t *sbh);
8811 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
8812 +extern uint sb_coreid(sb_t *sbh);
8813 +extern uint sb_coreidx(sb_t *sbh);
8814 +extern uint sb_coreunit(sb_t *sbh);
8815 +extern uint sb_corevendor(sb_t *sbh);
8816 +extern uint sb_corerev(sb_t *sbh);
8817 +extern void *sb_osh(sb_t *sbh);
8818 +extern void *sb_coreregs(sb_t *sbh);
8819 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
8820 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
8821 +extern bool sb_iscoreup(sb_t *sbh);
8822 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
8823 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
8824 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
8825 +extern void sb_commit(sb_t *sbh);
8826 +extern uint32 sb_base(uint32 admatch);
8827 +extern uint32 sb_size(uint32 admatch);
8828 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
8829 +extern void sb_core_tofixup(sb_t *sbh);
8830 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
8831 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
8832 +extern uint32 sb_clock(sb_t *sbh);
8833 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
8834 +extern void sb_pcmcia_init(sb_t *sbh);
8835 +extern void sb_watchdog(sb_t *sbh, uint ticks);
8836 +extern void *sb_gpiosetcore(sb_t *sbh);
8837 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8838 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8839 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8840 +extern uint32 sb_gpioin(sb_t *sbh);
8841 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8842 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
8843 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
8844 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
8845 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
8846 +
8847 +extern void sb_clkctl_init(sb_t *sbh);
8848 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
8849 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
8850 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
8851 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
8852 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
8853 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
8854 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
8855 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
8856 +extern uint sb_pcie_readreg(void *sbh, void* arg1, uint offset);
8857 +extern uint sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val);
8858 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
8859 +
8860 +
8861 +
8862 +/*
8863 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
8864 +* The returned path is NULL terminated and has trailing '/'.
8865 +* Return 0 on success, nonzero otherwise.
8866 +*/
8867 +extern int sb_devpath(sb_t *sbh, char *path, int size);
8868 +
8869 +/* clkctl xtal what flags */
8870 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
8871 +#define PLL 0x2 /* main chip pll */
8872 +
8873 +/* clkctl clk mode */
8874 +#define CLK_FAST 0 /* force fast (pll) clock */
8875 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
8876 +
8877 +
8878 +/* GPIO usage priorities */
8879 +#define GPIO_DRV_PRIORITY 0
8880 +#define GPIO_APP_PRIORITY 1
8881 +
8882 +/* device path */
8883 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
8884 +
8885 +#endif /* _sbutils_h_ */
8886 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
8887 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
8888 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-11-07 21:57:07.881588000 +0100
8889 @@ -0,0 +1,36 @@
8890 +/*
8891 + * Broadcom SiliconBackplane chipcommon serial flash interface
8892 + *
8893 + * Copyright 2005, Broadcom Corporation
8894 + * All Rights Reserved.
8895 + *
8896 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8897 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8898 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8899 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8900 + *
8901 + * $Id$
8902 + */
8903 +
8904 +#ifndef _sflash_h_
8905 +#define _sflash_h_
8906 +
8907 +#include <typedefs.h>
8908 +#include <sbchipc.h>
8909 +
8910 +struct sflash {
8911 + uint blocksize; /* Block size */
8912 + uint numblocks; /* Number of blocks */
8913 + uint32 type; /* Type */
8914 + uint size; /* Total size in bytes */
8915 +};
8916 +
8917 +/* Utility functions */
8918 +extern int sflash_poll(chipcregs_t *cc, uint offset);
8919 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
8920 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8921 +extern int sflash_erase(chipcregs_t *cc, uint offset);
8922 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
8923 +extern struct sflash * sflash_init(chipcregs_t *cc);
8924 +
8925 +#endif /* _sflash_h_ */
8926 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
8927 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
8928 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-11-07 21:57:07.881588000 +0100
8929 @@ -0,0 +1,33 @@
8930 +/*
8931 + * TRX image file header format.
8932 + *
8933 + * Copyright 2005, Broadcom Corporation
8934 + * All Rights Reserved.
8935 + *
8936 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8937 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8938 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8939 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8940 + *
8941 + * $Id$
8942 + */
8943 +
8944 +#include <typedefs.h>
8945 +
8946 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
8947 +#define TRX_VERSION 1
8948 +#define TRX_MAX_LEN 0x3A0000
8949 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
8950 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
8951 +#define TRX_MAX_OFFSET 3
8952 +
8953 +struct trx_header {
8954 + uint32 magic; /* "HDR0" */
8955 + uint32 len; /* Length of file including header */
8956 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
8957 + uint32 flag_version; /* 0:15 flags, 16:31 version */
8958 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
8959 +};
8960 +
8961 +/* Compatibility */
8962 +typedef struct trx_header TRXHDR, *PTRXHDR;
8963 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
8964 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
8965 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-11-07 22:51:38.788726750 +0100
8966 @@ -0,0 +1,326 @@
8967 +/*
8968 + * Copyright 2005, Broadcom Corporation
8969 + * All Rights Reserved.
8970 + *
8971 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8972 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8973 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8974 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8975 + * $Id$
8976 + */
8977 +
8978 +#ifndef _TYPEDEFS_H_
8979 +#define _TYPEDEFS_H_
8980 +
8981 +
8982 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
8983 + * typedef file "site_typedefs.h".
8984 + *
8985 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
8986 + * section of this file makes inferences about the compile environment
8987 + * based on defined symbols and possibly compiler pragmas.
8988 + *
8989 + * Following these two sections is the "Default Typedefs"
8990 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
8991 + * defined. This section has a default set of typedefs and a few
8992 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
8993 + */
8994 +
8995 +#ifdef SITE_TYPEDEFS
8996 +
8997 +/*******************************************************************************
8998 + * Site Specific Typedefs
8999 + *******************************************************************************/
9000 +
9001 +#include "site_typedefs.h"
9002 +
9003 +#else
9004 +
9005 +/*******************************************************************************
9006 + * Inferred Typedefs
9007 + *******************************************************************************/
9008 +
9009 +/* Infer the compile environment based on preprocessor symbols and pramas.
9010 + * Override type definitions as needed, and include configuration dependent
9011 + * header files to define types.
9012 + */
9013 +
9014 +#ifdef __cplusplus
9015 +
9016 +#define TYPEDEF_BOOL
9017 +#ifndef FALSE
9018 +#define FALSE false
9019 +#endif
9020 +#ifndef TRUE
9021 +#define TRUE true
9022 +#endif
9023 +
9024 +#else /* ! __cplusplus */
9025 +
9026 +#if defined(_WIN32)
9027 +
9028 +#define TYPEDEF_BOOL
9029 +typedef unsigned char bool; /* consistent w/BOOL */
9030 +
9031 +#endif /* _WIN32 */
9032 +
9033 +#endif /* ! __cplusplus */
9034 +
9035 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
9036 +#if defined(_WIN64)
9037 +#include <basetsd.h>
9038 +#define TYPEDEF_UINTPTR
9039 +typedef ULONG_PTR uintptr;
9040 +#endif
9041 +
9042 +#ifdef _HNDRTE_
9043 +typedef long unsigned int size_t;
9044 +#endif
9045 +
9046 +#ifdef _MSC_VER /* Microsoft C */
9047 +#define TYPEDEF_INT64
9048 +#define TYPEDEF_UINT64
9049 +typedef signed __int64 int64;
9050 +typedef unsigned __int64 uint64;
9051 +#endif
9052 +
9053 +#if defined(MACOSX) && defined(KERNEL)
9054 +#define TYPEDEF_BOOL
9055 +#endif
9056 +
9057 +
9058 +#if defined(linux)
9059 +#define TYPEDEF_UINT
9060 +#define TYPEDEF_USHORT
9061 +#define TYPEDEF_ULONG
9062 +#endif
9063 +
9064 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
9065 +#define TYPEDEF_UINT
9066 +#define TYPEDEF_USHORT
9067 +#endif
9068 +
9069 +
9070 +/* Do not support the (u)int64 types with strict ansi for GNU C */
9071 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
9072 +#define TYPEDEF_INT64
9073 +#define TYPEDEF_UINT64
9074 +#endif
9075 +
9076 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
9077 + * for singned or unsigned */
9078 +#if defined(__ICL)
9079 +
9080 +#define TYPEDEF_INT64
9081 +
9082 +#if defined(__STDC__)
9083 +#define TYPEDEF_UINT64
9084 +#endif
9085 +
9086 +#endif /* __ICL */
9087 +
9088 +
9089 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
9090 +
9091 +/* pick up ushort & uint from standard types.h */
9092 +#if defined(linux) && defined(__KERNEL__)
9093 +
9094 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
9095 +
9096 +#else
9097 +
9098 +#include <sys/types.h>
9099 +
9100 +#endif
9101 +
9102 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
9103 +
9104 +#if defined(MACOSX) && defined(KERNEL)
9105 +#include <IOKit/IOTypes.h>
9106 +#endif
9107 +
9108 +
9109 +/* use the default typedefs in the next section of this file */
9110 +#define USE_TYPEDEF_DEFAULTS
9111 +
9112 +#endif /* SITE_TYPEDEFS */
9113 +
9114 +
9115 +/*******************************************************************************
9116 + * Default Typedefs
9117 + *******************************************************************************/
9118 +
9119 +#ifdef USE_TYPEDEF_DEFAULTS
9120 +#undef USE_TYPEDEF_DEFAULTS
9121 +
9122 +#ifndef TYPEDEF_BOOL
9123 +typedef /*@abstract@*/ unsigned char bool;
9124 +#endif
9125 +
9126 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
9127 +
9128 +#ifndef TYPEDEF_UCHAR
9129 +typedef unsigned char uchar;
9130 +#endif
9131 +
9132 +#ifndef TYPEDEF_USHORT
9133 +typedef unsigned short ushort;
9134 +#endif
9135 +
9136 +#ifndef TYPEDEF_UINT
9137 +typedef unsigned int uint;
9138 +#endif
9139 +
9140 +#ifndef TYPEDEF_ULONG
9141 +typedef unsigned long ulong;
9142 +#endif
9143 +
9144 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
9145 +
9146 +#ifndef TYPEDEF_UINT8
9147 +typedef unsigned char uint8;
9148 +#endif
9149 +
9150 +#ifndef TYPEDEF_UINT16
9151 +typedef unsigned short uint16;
9152 +#endif
9153 +
9154 +#ifndef TYPEDEF_UINT32
9155 +typedef unsigned int uint32;
9156 +#endif
9157 +
9158 +#ifndef TYPEDEF_UINT64
9159 +typedef unsigned long long uint64;
9160 +#endif
9161 +
9162 +#ifndef TYPEDEF_UINTPTR
9163 +typedef unsigned int uintptr;
9164 +#endif
9165 +
9166 +#ifndef TYPEDEF_INT8
9167 +typedef signed char int8;
9168 +#endif
9169 +
9170 +#ifndef TYPEDEF_INT16
9171 +typedef signed short int16;
9172 +#endif
9173 +
9174 +#ifndef TYPEDEF_INT32
9175 +typedef signed int int32;
9176 +#endif
9177 +
9178 +#ifndef TYPEDEF_INT64
9179 +typedef signed long long int64;
9180 +#endif
9181 +
9182 +/*----------------------- define float32/64, float_t -----------------------*/
9183 +
9184 +#ifndef TYPEDEF_FLOAT32
9185 +typedef float float32;
9186 +#endif
9187 +
9188 +#ifndef TYPEDEF_FLOAT64
9189 +typedef double float64;
9190 +#endif
9191 +
9192 +/*
9193 + * abstracted floating point type allows for compile time selection of
9194 + * single or double precision arithmetic. Compiling with -DFLOAT32
9195 + * selects single precision; the default is double precision.
9196 + */
9197 +
9198 +#ifndef TYPEDEF_FLOAT_T
9199 +
9200 +#if defined(FLOAT32)
9201 +typedef float32 float_t;
9202 +#else /* default to double precision floating point */
9203 +typedef float64 float_t;
9204 +#endif
9205 +
9206 +#endif /* TYPEDEF_FLOAT_T */
9207 +
9208 +/*----------------------- define macro values -----------------------------*/
9209 +
9210 +#ifndef FALSE
9211 +#define FALSE 0
9212 +#endif
9213 +
9214 +#ifndef TRUE
9215 +#define TRUE 1
9216 +#endif
9217 +
9218 +#ifndef NULL
9219 +#define NULL 0
9220 +#endif
9221 +
9222 +#ifndef OFF
9223 +#define OFF 0
9224 +#endif
9225 +
9226 +#ifndef ON
9227 +#define ON 1
9228 +#endif
9229 +
9230 +#define AUTO (-1)
9231 +
9232 +/* Reclaiming text and data :
9233 + The following macros specify special linker sections that can be reclaimed
9234 + after a system is considered 'up'.
9235 + */
9236 +#if defined(__GNUC__) && defined(BCMRECLAIM)
9237 +extern bool bcmreclaimed;
9238 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
9239 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
9240 +#define BCMINIT(_id) _id##_ini
9241 +#else
9242 +#define BCMINITDATA(_data) _data
9243 +#define BCMINITFN(_fn) _fn
9244 +#define BCMINIT(_id) _id
9245 +#define bcmreclaimed 0
9246 +#endif
9247 +
9248 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
9249 +
9250 +#ifndef PTRSZ
9251 +#define PTRSZ sizeof (char*)
9252 +#endif
9253 +
9254 +#ifndef INLINE
9255 +
9256 +#ifdef _MSC_VER
9257 +
9258 +#define INLINE __inline
9259 +
9260 +#elif __GNUC__
9261 +
9262 +#define INLINE __inline__
9263 +
9264 +#else
9265 +
9266 +#define INLINE
9267 +
9268 +#endif /* _MSC_VER */
9269 +
9270 +#endif /* INLINE */
9271 +
9272 +#undef TYPEDEF_BOOL
9273 +#undef TYPEDEF_UCHAR
9274 +#undef TYPEDEF_USHORT
9275 +#undef TYPEDEF_UINT
9276 +#undef TYPEDEF_ULONG
9277 +#undef TYPEDEF_UINT8
9278 +#undef TYPEDEF_UINT16
9279 +#undef TYPEDEF_UINT32
9280 +#undef TYPEDEF_UINT64
9281 +#undef TYPEDEF_UINTPTR
9282 +#undef TYPEDEF_INT8
9283 +#undef TYPEDEF_INT16
9284 +#undef TYPEDEF_INT32
9285 +#undef TYPEDEF_INT64
9286 +#undef TYPEDEF_FLOAT32
9287 +#undef TYPEDEF_FLOAT64
9288 +#undef TYPEDEF_FLOAT_T
9289 +
9290 +#endif /* USE_TYPEDEF_DEFAULTS */
9291 +
9292 +#endif /* _TYPEDEFS_H_ */
9293 diff -urN linux.old/arch/mips/bcm947xx/include/wlioctl.h linux.dev/arch/mips/bcm947xx/include/wlioctl.h
9294 --- linux.old/arch/mips/bcm947xx/include/wlioctl.h 1970-01-01 01:00:00.000000000 +0100
9295 +++ linux.dev/arch/mips/bcm947xx/include/wlioctl.h 2005-11-07 22:51:38.792727000 +0100
9296 @@ -0,0 +1,1030 @@
9297 +/*
9298 + * Custom OID/ioctl definitions for
9299 + * Broadcom 802.11abg Networking Device Driver
9300 + *
9301 + * Definitions subject to change without notice.
9302 + *
9303 + * Copyright 2005, Broadcom Corporation
9304 + * All Rights Reserved.
9305 + *
9306 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9307 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9308 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9309 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9310 + *
9311 + * $Id$
9312 + */
9313 +
9314 +#ifndef _wlioctl_h_
9315 +#define _wlioctl_h_
9316 +
9317 +#include <typedefs.h>
9318 +#include <proto/ethernet.h>
9319 +#include <proto/bcmeth.h>
9320 +#include <proto/bcmevent.h>
9321 +#include <proto/802.11.h>
9322 +
9323 +/* require default structure packing */
9324 +#if !defined(__GNUC__)
9325 +#pragma pack(push,8)
9326 +#endif
9327 +
9328 +#define WL_NUMRATES 255 /* max # of rates in a rateset */
9329 +
9330 +typedef struct wl_rateset {
9331 + uint32 count; /* # rates in this set */
9332 + uint8 rates[WL_NUMRATES]; /* rates in 500kbps units w/hi bit set if basic */
9333 +} wl_rateset_t;
9334 +
9335 +#define WL_CHANSPEC_CHAN_MASK 0x0fff
9336 +#define WL_CHANSPEC_BAND_MASK 0xf000
9337 +#define WL_CHANSPEC_BAND_SHIFT 12
9338 +#define WL_CHANSPEC_BAND_A 0x1000
9339 +#define WL_CHANSPEC_BAND_B 0x2000
9340 +
9341 +/*
9342 + * Per-bss information structure.
9343 + */
9344 +
9345 +#define WL_BSS_INFO_VERSION 107 /* current version of wl_bss_info struct */
9346 +
9347 +typedef struct wl_bss_info {
9348 + uint32 version; /* version field */
9349 + uint32 length; /* byte length of data in this record, starting at version and including IEs */
9350 + struct ether_addr BSSID;
9351 + uint16 beacon_period; /* units are Kusec */
9352 + uint16 capability; /* Capability information */
9353 + uint8 SSID_len;
9354 + uint8 SSID[32];
9355 + struct {
9356 + uint count; /* # rates in this set */
9357 + uint8 rates[16]; /* rates in 500kbps units w/hi bit set if basic */
9358 + } rateset; /* supported rates */
9359 + uint8 channel; /* Channel no. */
9360 + uint16 atim_window; /* units are Kusec */
9361 + uint8 dtim_period; /* DTIM period */
9362 + int16 RSSI; /* receive signal strength (in dBm) */
9363 + int8 phy_noise; /* noise (in dBm) */
9364 + uint32 ie_length; /* byte length of Information Elements */
9365 + /* variable length Information Elements */
9366 +} wl_bss_info_t;
9367 +
9368 +typedef struct wlc_ssid {
9369 + uint32 SSID_len;
9370 + uchar SSID[32];
9371 +} wlc_ssid_t;
9372 +
9373 +typedef struct wl_scan_params {
9374 + wlc_ssid_t ssid; /* default is {0, ""} */
9375 + struct ether_addr bssid;/* default is bcast */
9376 + int8 bss_type; /* default is any, DOT11_BSSTYPE_ANY/INFRASTRUCTURE/INDEPENDENT */
9377 + int8 scan_type; /* -1 use default, DOT11_SCANTYPE_ACTIVE/PASSIVE */
9378 + int32 nprobes; /* -1 use default, number of probes per channel */
9379 + int32 active_time; /* -1 use default, dwell time per channel for active scanning */
9380 + int32 passive_time; /* -1 use default, dwell time per channel for passive scanning */
9381 + int32 home_time; /* -1 use default, dwell time for the home channel between channel scans */
9382 + int32 channel_num; /* 0 use default (all available channels), count of channels in channel_list */
9383 + uint16 channel_list[1]; /* list of chanspecs */
9384 +} wl_scan_params_t;
9385 +/* size of wl_scan_params not including variable length array */
9386 +#define WL_SCAN_PARAMS_FIXED_SIZE 64
9387 +
9388 +typedef struct wl_scan_results {
9389 + uint32 buflen;
9390 + uint32 version;
9391 + uint32 count;
9392 + wl_bss_info_t bss_info[1];
9393 +} wl_scan_results_t;
9394 +/* size of wl_scan_results not including variable length array */
9395 +#define WL_SCAN_RESULTS_FIXED_SIZE 12
9396 +
9397 +/* uint32 list */
9398 +typedef struct wl_uint32_list {
9399 + /* in - # of elements, out - # of entries */
9400 + uint32 count;
9401 + /* variable length uint32 list */
9402 + uint32 element[1];
9403 +} wl_uint32_list_t;
9404 +
9405 +#define WLC_CNTRY_BUF_SZ 4 /* Country string is 3 bytes + NULL */
9406 +
9407 +typedef struct wl_channels_in_country {
9408 + uint32 buflen;
9409 + uint32 band;
9410 + char country_abbrev[WLC_CNTRY_BUF_SZ];
9411 + uint32 count;
9412 + uint32 channel[1];
9413 +} wl_channels_in_country_t;
9414 +
9415 +typedef struct wl_country_list {
9416 + uint32 buflen;
9417 + uint32 band_set;
9418 + uint32 band;
9419 + uint32 count;
9420 + char country_abbrev[1];
9421 +} wl_country_list_t;
9422 +
9423 +#define WL_RM_TYPE_BASIC 1
9424 +#define WL_RM_TYPE_CCA 2
9425 +#define WL_RM_TYPE_RPI 3
9426 +
9427 +#define WL_RM_FLAG_PARALLEL (1<<0)
9428 +
9429 +#define WL_RM_FLAG_LATE (1<<1)
9430 +#define WL_RM_FLAG_INCAPABLE (1<<2)
9431 +#define WL_RM_FLAG_REFUSED (1<<3)
9432 +
9433 +typedef struct wl_rm_req_elt {
9434 + int8 type;
9435 + int8 flags;
9436 + uint16 chanspec;
9437 + uint32 token; /* token for this measurement */
9438 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9439 + uint32 tsf_l; /* TSF low 32-bits */
9440 + uint32 dur; /* TUs */
9441 +} wl_rm_req_elt_t;
9442 +
9443 +typedef struct wl_rm_req {
9444 + uint32 token; /* overall measurement set token */
9445 + uint32 count; /* number of measurement reqests */
9446 + wl_rm_req_elt_t req[1]; /* variable length block of requests */
9447 +} wl_rm_req_t;
9448 +#define WL_RM_REQ_FIXED_LEN 8
9449 +
9450 +typedef struct wl_rm_rep_elt {
9451 + int8 type;
9452 + int8 flags;
9453 + uint16 chanspec;
9454 + uint32 token; /* token for this measurement */
9455 + uint32 tsf_h; /* TSF high 32-bits of Measurement start time */
9456 + uint32 tsf_l; /* TSF low 32-bits */
9457 + uint32 dur; /* TUs */
9458 + uint32 len; /* byte length of data block */
9459 + uint8 data[1]; /* variable length data block */
9460 +} wl_rm_rep_elt_t;
9461 +#define WL_RM_REP_ELT_FIXED_LEN 24 /* length excluding data block */
9462 +
9463 +#define WL_RPI_REP_BIN_NUM 8
9464 +typedef struct wl_rm_rpi_rep {
9465 + uint8 rpi[WL_RPI_REP_BIN_NUM];
9466 + int8 rpi_max[WL_RPI_REP_BIN_NUM];
9467 +} wl_rm_rpi_rep_t;
9468 +
9469 +typedef struct wl_rm_rep {
9470 + uint32 token; /* overall measurement set token */
9471 + uint32 len; /* length of measurement report block */
9472 + wl_rm_rep_elt_t rep[1]; /* variable length block of reports */
9473 +} wl_rm_rep_t;
9474 +#define WL_RM_REP_FIXED_LEN 8
9475 +
9476 +
9477 +#if defined(BCMSUP_PSK)
9478 +typedef enum sup_auth_status {
9479 + WLC_SUP_DISCONNECTED = 0,
9480 + WLC_SUP_CONNECTING,
9481 + WLC_SUP_IDREQUIRED,
9482 + WLC_SUP_AUTHENTICATING,
9483 + WLC_SUP_AUTHENTICATED,
9484 + WLC_SUP_KEYXCHANGE,
9485 + WLC_SUP_KEYED,
9486 + WLC_SUP_TIMEOUT
9487 +} sup_auth_status_t;
9488 +#endif /* BCMCCX | BCMSUP_PSK */
9489 +
9490 +/* Enumerate crypto algorithms */
9491 +#define CRYPTO_ALGO_OFF 0
9492 +#define CRYPTO_ALGO_WEP1 1
9493 +#define CRYPTO_ALGO_TKIP 2
9494 +#define CRYPTO_ALGO_WEP128 3
9495 +#define CRYPTO_ALGO_AES_CCM 4
9496 +#define CRYPTO_ALGO_AES_OCB_MSDU 5
9497 +#define CRYPTO_ALGO_AES_OCB_MPDU 6
9498 +#define CRYPTO_ALGO_NALG 7
9499 +
9500 +#define WSEC_GEN_MIC_ERROR 0x0001
9501 +#define WSEC_GEN_REPLAY 0x0002
9502 +
9503 +#define WL_SOFT_KEY (1 << 0) /* Indicates this key is using soft encrypt */
9504 +#define WL_PRIMARY_KEY (1 << 1) /* Indicates this key is the primary (ie tx) key */
9505 +#define WL_KF_RES_4 (1 << 4) /* Reserved for backward compat */
9506 +#define WL_KF_RES_5 (1 << 5) /* Reserved for backward compat */
9507 +
9508 +typedef struct wl_wsec_key {
9509 + uint32 index; /* key index */
9510 + uint32 len; /* key length */
9511 + uint8 data[DOT11_MAX_KEY_SIZE]; /* key data */
9512 + uint32 pad_1[18];
9513 + uint32 algo; /* CRYPTO_ALGO_AES_CCM, CRYPTO_ALGO_WEP128, etc */
9514 + uint32 flags; /* misc flags */
9515 + uint32 pad_2[2];
9516 + int pad_3;
9517 + int iv_initialized; /* has IV been initialized already? */
9518 + int pad_4;
9519 + /* Rx IV */
9520 + struct {
9521 + uint32 hi; /* upper 32 bits of IV */
9522 + uint16 lo; /* lower 16 bits of IV */
9523 + } rxiv;
9524 + uint32 pad_5[2];
9525 + struct ether_addr ea; /* per station */
9526 +} wl_wsec_key_t;
9527 +
9528 +
9529 +#define WSEC_MIN_PSK_LEN 8
9530 +#define WSEC_MAX_PSK_LEN 64
9531 +
9532 +/* Flag for key material needing passhash'ing */
9533 +#define WSEC_PASSPHRASE (1<<0)
9534 +
9535 +/* recepticle for WLC_SET_WSEC_PMK parameter */
9536 +typedef struct {
9537 + ushort key_len; /* octets in key material */
9538 + ushort flags; /* key handling qualification */
9539 + uint8 key[WSEC_MAX_PSK_LEN]; /* PMK material */
9540 +} wsec_pmk_t;
9541 +
9542 +/* wireless security bitvec */
9543 +#define WEP_ENABLED 0x0001
9544 +#define TKIP_ENABLED 0x0002
9545 +#define AES_ENABLED 0x0004
9546 +#define WSEC_SWFLAG 0x0008
9547 +#define SES_OW_ENABLED 0x0040 /* to go into transition mode without setting wep */
9548 +
9549 +/* WPA authentication mode bitvec */
9550 +#define WPA_AUTH_DISABLED 0x0000 /* Legacy (i.e., non-WPA) */
9551 +#define WPA_AUTH_NONE 0x0001 /* none (IBSS) */
9552 +#define WPA_AUTH_UNSPECIFIED 0x0002 /* over 802.1x */
9553 +#define WPA_AUTH_PSK 0x0004 /* Pre-shared key */
9554 +/*#define WPA_AUTH_8021X 0x0020*/ /* 802.1x, reserved */
9555 +
9556 +#define WPA2_AUTH_UNSPECIFIED 0x0040 /* over 802.1x */
9557 +#define WPA2_AUTH_PSK 0x0080 /* Pre-shared key */
9558 +
9559 +
9560 +
9561 +/* pmkid */
9562 +#define MAXPMKID 16
9563 +
9564 +typedef struct _pmkid
9565 +{
9566 + struct ether_addr BSSID;
9567 + uint8 PMKID[WPA2_PMKID_LEN];
9568 +} pmkid_t;
9569 +
9570 +typedef struct _pmkid_list
9571 +{
9572 + uint32 npmkid;
9573 + pmkid_t pmkid[1];
9574 +} pmkid_list_t;
9575 +
9576 +typedef struct _pmkid_cand {
9577 + struct ether_addr BSSID;
9578 + uint8 preauth;
9579 +} pmkid_cand_t;
9580 +
9581 +typedef struct _pmkid_cand_list {
9582 + uint32 npmkid_cand;
9583 + pmkid_cand_t pmkid_cand[1];
9584 +} pmkid_cand_list_t;
9585 +
9586 +
9587 +typedef struct wl_led_info {
9588 + uint32 index; /* led index */
9589 + uint32 behavior;
9590 + bool activehi;
9591 +} wl_led_info_t;
9592 +
9593 +typedef struct wlc_assoc_info {
9594 + uint32 req_len;
9595 + uint32 resp_len;
9596 + uint32 flags;
9597 + struct dot11_assoc_req req;
9598 + struct ether_addr reassoc_bssid; /* used in reassoc's */
9599 + struct dot11_assoc_resp resp;
9600 +} wl_assoc_info_t;
9601 +/* flags */
9602 +#define WLC_ASSOC_REQ_IS_REASSOC 0x01 /* assoc req was actually a reassoc */
9603 +/* srom read/write struct passed through ioctl */
9604 +typedef struct {
9605 + uint byteoff; /* byte offset */
9606 + uint nbytes; /* number of bytes */
9607 + uint16 buf[1];
9608 +} srom_rw_t;
9609 +
9610 +/* R_REG and W_REG struct passed through ioctl */
9611 +typedef struct {
9612 + uint32 byteoff; /* byte offset of the field in d11regs_t */
9613 + uint32 val; /* read/write value of the field */
9614 + uint32 size; /* sizeof the field */
9615 + uint band; /* band (optional) */
9616 +} rw_reg_t;
9617 +
9618 +/* Structure used by GET/SET_ATTEN ioctls */
9619 +typedef struct {
9620 + uint16 auto_ctrl; /* 1: Automatic control, 0: overriden */
9621 + uint16 bb; /* Baseband attenuation */
9622 + uint16 radio; /* Radio attenuation */
9623 + uint16 txctl1; /* Radio TX_CTL1 value */
9624 +} atten_t;
9625 +
9626 +/* Used to get specific STA parameters */
9627 +typedef struct {
9628 + uint32 val;
9629 + struct ether_addr ea;
9630 +} scb_val_t;
9631 +
9632 +
9633 +/* Event data type */
9634 +typedef struct wlc_event {
9635 + wl_event_msg_t event; /* encapsulated event */
9636 + struct ether_addr *addr; /* used to keep a trace of the potential present of
9637 + an address in wlc_event_msg_t */
9638 + void *data; /* used to hang additional data on an event */
9639 + struct wlc_event *next; /* enables ordered list of pending events */
9640 +} wlc_event_t;
9641 +
9642 +#define BCM_MAC_STATUS_INDICATION (0x40010200L)
9643 +
9644 +typedef struct {
9645 + uint16 ver; /* version of this struct */
9646 + uint16 len; /* length in bytes of this structure */
9647 + uint16 cap; /* sta's advertized capabilities */
9648 + uint32 flags; /* flags defined below */
9649 + uint32 idle; /* time since data pkt rx'd from sta */
9650 + struct ether_addr ea; /* Station address */
9651 + wl_rateset_t rateset; /* rateset in use */
9652 + uint32 in; /* seconds elapsed since associated */
9653 + uint32 listen_interval_inms; /* Min Listen interval in ms for this STA*/
9654 +} sta_info_t;
9655 +
9656 +#define WL_STA_VER 2
9657 +
9658 +/* flags fields */
9659 +#define WL_STA_BRCM 0x01
9660 +#define WL_STA_WME 0x02
9661 +#define WL_STA_ABCAP 0x04
9662 +#define WL_STA_AUTHE 0x08
9663 +#define WL_STA_ASSOC 0x10
9664 +#define WL_STA_AUTHO 0x20
9665 +#define WL_STA_WDS 0x40
9666 +#define WL_WDS_LINKUP 0x80
9667 +
9668 +
9669 +/*
9670 + * Country locale determines which channels are available to us.
9671 + */
9672 +typedef enum _wlc_locale {
9673 + WLC_WW = 0, /* Worldwide */
9674 + WLC_THA, /* Thailand */
9675 + WLC_ISR, /* Israel */
9676 + WLC_JDN, /* Jordan */
9677 + WLC_PRC, /* China */
9678 + WLC_JPN, /* Japan */
9679 + WLC_FCC, /* USA */
9680 + WLC_EUR, /* Europe */
9681 + WLC_USL, /* US Low Band only */
9682 + WLC_JPH, /* Japan High Band only */
9683 + WLC_ALL, /* All the channels in this band */
9684 + WLC_11D, /* Represents locale recieved by 11d beacons */
9685 + WLC_LAST_LOCALE,
9686 + WLC_UNDEFINED_LOCALE = 0xf
9687 +} wlc_locale_t;
9688 +
9689 +/* channel encoding */
9690 +typedef struct channel_info {
9691 + int hw_channel;
9692 + int target_channel;
9693 + int scan_channel;
9694 +} channel_info_t;
9695 +
9696 +/* For ioctls that take a list of MAC addresses */
9697 +struct maclist {
9698 + uint count; /* number of MAC addresses */
9699 + struct ether_addr ea[1]; /* variable length array of MAC addresses */
9700 +};
9701 +
9702 +/* get pkt count struct passed through ioctl */
9703 +typedef struct get_pktcnt {
9704 + uint rx_good_pkt;
9705 + uint rx_bad_pkt;
9706 + uint tx_good_pkt;
9707 + uint tx_bad_pkt;
9708 +} get_pktcnt_t;
9709 +
9710 +/* Linux network driver ioctl encoding */
9711 +typedef struct wl_ioctl {
9712 + uint cmd; /* common ioctl definition */
9713 + void *buf; /* pointer to user buffer */
9714 + uint len; /* length of user buffer */
9715 + bool set; /* get or set request (optional) */
9716 + uint used; /* bytes read or written (optional) */
9717 + uint needed; /* bytes needed (optional) */
9718 +} wl_ioctl_t;
9719 +
9720 +/*
9721 + * Structure for passing hardware and software
9722 + * revision info up from the driver.
9723 + */
9724 +typedef struct wlc_rev_info {
9725 + uint vendorid; /* PCI vendor id */
9726 + uint deviceid; /* device id of chip */
9727 + uint radiorev; /* radio revision */
9728 + uint chiprev; /* chip revision */
9729 + uint corerev; /* core revision */
9730 + uint boardid; /* board identifier (usu. PCI sub-device id) */
9731 + uint boardvendor; /* board vendor (usu. PCI sub-vendor id) */
9732 + uint boardrev; /* board revision */
9733 + uint driverrev; /* driver version */
9734 + uint ucoderev; /* microcode version */
9735 + uint bus; /* bus type */
9736 + uint chipnum; /* chip number */
9737 +} wlc_rev_info_t;
9738 +
9739 +#define WL_BRAND_MAX 10
9740 +typedef struct wl_instance_info {
9741 + uint instance;
9742 + char brand[WL_BRAND_MAX];
9743 +} wl_instance_info_t;
9744 +
9745 +/* check this magic number */
9746 +#define WLC_IOCTL_MAGIC 0x14e46c77
9747 +
9748 +/* bump this number if you change the ioctl interface */
9749 +#define WLC_IOCTL_VERSION 1
9750 +
9751 +#define WLC_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
9752 +#define WLC_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
9753 +
9754 +/* common ioctl definitions */
9755 +#define WLC_GET_MAGIC 0
9756 +#define WLC_GET_VERSION 1
9757 +#define WLC_UP 2
9758 +#define WLC_DOWN 3
9759 +#define WLC_DUMP 6
9760 +#define WLC_GET_MSGLEVEL 7
9761 +#define WLC_SET_MSGLEVEL 8
9762 +#define WLC_GET_PROMISC 9
9763 +#define WLC_SET_PROMISC 10
9764 +#define WLC_GET_RATE 12
9765 +/* #define WLC_SET_RATE 13 */ /* no longer supported */
9766 +#define WLC_GET_INSTANCE 14
9767 +/* #define WLC_GET_FRAG 15 */ /* no longer supported */
9768 +/* #define WLC_SET_FRAG 16 */ /* no longer supported */
9769 +/* #define WLC_GET_RTS 17 */ /* no longer supported */
9770 +/* #define WLC_SET_RTS 18 */ /* no longer supported */
9771 +#define WLC_GET_INFRA 19
9772 +#define WLC_SET_INFRA 20
9773 +#define WLC_GET_AUTH 21
9774 +#define WLC_SET_AUTH 22
9775 +#define WLC_GET_BSSID 23
9776 +#define WLC_SET_BSSID 24
9777 +#define WLC_GET_SSID 25
9778 +#define WLC_SET_SSID 26
9779 +#define WLC_RESTART 27
9780 +#define WLC_GET_CHANNEL 29
9781 +#define WLC_SET_CHANNEL 30
9782 +#define WLC_GET_SRL 31
9783 +#define WLC_SET_SRL 32
9784 +#define WLC_GET_LRL 33
9785 +#define WLC_SET_LRL 34
9786 +#define WLC_GET_PLCPHDR 35
9787 +#define WLC_SET_PLCPHDR 36
9788 +#define WLC_GET_RADIO 37
9789 +#define WLC_SET_RADIO 38
9790 +#define WLC_GET_PHYTYPE 39
9791 +/* #define WLC_GET_WEP 42 */ /* no longer supported */
9792 +/* #define WLC_SET_WEP 43 */ /* no longer supported */
9793 +#define WLC_GET_KEY 44
9794 +#define WLC_SET_KEY 45
9795 +#define WLC_GET_REGULATORY 46
9796 +#define WLC_SET_REGULATORY 47
9797 +#define WLC_SCAN 50
9798 +#define WLC_SCAN_RESULTS 51
9799 +#define WLC_DISASSOC 52
9800 +#define WLC_REASSOC 53
9801 +#define WLC_GET_ROAM_TRIGGER 54
9802 +#define WLC_SET_ROAM_TRIGGER 55
9803 +#define WLC_GET_TXANT 61
9804 +#define WLC_SET_TXANT 62
9805 +#define WLC_GET_ANTDIV 63
9806 +#define WLC_SET_ANTDIV 64
9807 +/* #define WLC_GET_TXPWR 65 */ /* no longer supported */
9808 +/* #define WLC_SET_TXPWR 66 */ /* no longer supported */
9809 +#define WLC_GET_CLOSED 67
9810 +#define WLC_SET_CLOSED 68
9811 +#define WLC_GET_MACLIST 69
9812 +#define WLC_SET_MACLIST 70
9813 +#define WLC_GET_RATESET 71
9814 +#define WLC_SET_RATESET 72
9815 +#define WLC_GET_LOCALE 73
9816 +#define WLC_LONGTRAIN 74
9817 +#define WLC_GET_BCNPRD 75
9818 +#define WLC_SET_BCNPRD 76
9819 +#define WLC_GET_DTIMPRD 77
9820 +#define WLC_SET_DTIMPRD 78
9821 +#define WLC_GET_SROM 79
9822 +#define WLC_SET_SROM 80
9823 +#define WLC_GET_WEP_RESTRICT 81
9824 +#define WLC_SET_WEP_RESTRICT 82
9825 +#define WLC_GET_COUNTRY 83
9826 +#define WLC_SET_COUNTRY 84
9827 +#define WLC_GET_REVINFO 98
9828 +#define WLC_GET_MACMODE 105
9829 +#define WLC_SET_MACMODE 106
9830 +#define WLC_GET_GMODE 109
9831 +#define WLC_SET_GMODE 110
9832 +#define WLC_GET_CURR_RATESET 114 /* current rateset */
9833 +#define WLC_GET_SCANSUPPRESS 115
9834 +#define WLC_SET_SCANSUPPRESS 116
9835 +#define WLC_GET_AP 117
9836 +#define WLC_SET_AP 118
9837 +#define WLC_GET_EAP_RESTRICT 119
9838 +#define WLC_SET_EAP_RESTRICT 120
9839 +#define WLC_GET_WDSLIST 123
9840 +#define WLC_SET_WDSLIST 124
9841 +#define WLC_GET_RSSI 127
9842 +#define WLC_GET_WSEC 133
9843 +#define WLC_SET_WSEC 134
9844 +#define WLC_GET_BSS_INFO 136
9845 +#define WLC_GET_LAZYWDS 138
9846 +#define WLC_SET_LAZYWDS 139
9847 +#define WLC_GET_BANDLIST 140
9848 +#define WLC_GET_BAND 141
9849 +#define WLC_SET_BAND 142
9850 +#define WLC_GET_SHORTSLOT 144
9851 +#define WLC_GET_SHORTSLOT_OVERRIDE 145
9852 +#define WLC_SET_SHORTSLOT_OVERRIDE 146
9853 +#define WLC_GET_SHORTSLOT_RESTRICT 147
9854 +#define WLC_SET_SHORTSLOT_RESTRICT 148
9855 +#define WLC_GET_GMODE_PROTECTION 149
9856 +#define WLC_GET_GMODE_PROTECTION_OVERRIDE 150
9857 +#define WLC_SET_GMODE_PROTECTION_OVERRIDE 151
9858 +#define WLC_UPGRADE 152
9859 +/* #define WLC_GET_MRATE 153 */ /* no longer supported */
9860 +/* #define WLC_SET_MRATE 154 */ /* no longer supported */
9861 +#define WLC_GET_ASSOCLIST 159
9862 +#define WLC_GET_CLK 160
9863 +#define WLC_SET_CLK 161
9864 +#define WLC_GET_UP 162
9865 +#define WLC_OUT 163
9866 +#define WLC_GET_WPA_AUTH 164
9867 +#define WLC_SET_WPA_AUTH 165
9868 +#define WLC_GET_GMODE_PROTECTION_CONTROL 178
9869 +#define WLC_SET_GMODE_PROTECTION_CONTROL 179
9870 +#define WLC_GET_PHYLIST 180
9871 +#define WLC_GET_KEY_SEQ 183
9872 +#define WLC_GET_GMODE_PROTECTION_CTS 198
9873 +#define WLC_SET_GMODE_PROTECTION_CTS 199
9874 +#define WLC_GET_PIOMODE 203
9875 +#define WLC_SET_PIOMODE 204
9876 +#define WLC_SET_LED 209
9877 +#define WLC_GET_LED 210
9878 +#define WLC_GET_CHANNEL_SEL 215
9879 +#define WLC_START_CHANNEL_SEL 216
9880 +#define WLC_GET_VALID_CHANNELS 217
9881 +#define WLC_GET_FAKEFRAG 218
9882 +#define WLC_SET_FAKEFRAG 219
9883 +#define WLC_GET_WET 230
9884 +#define WLC_SET_WET 231
9885 +#define WLC_GET_KEY_PRIMARY 235
9886 +#define WLC_SET_KEY_PRIMARY 236
9887 +#define WLC_GET_RADAR 242
9888 +#define WLC_SET_RADAR 243
9889 +#define WLC_SET_SPECT_MANAGMENT 244
9890 +#define WLC_GET_SPECT_MANAGMENT 245
9891 +#define WLC_WDS_GET_REMOTE_HWADDR 246 /* currently handled in wl_linux.c/wl_vx.c */
9892 +#define WLC_SET_CS_SCAN_TIMER 248
9893 +#define WLC_GET_CS_SCAN_TIMER 249
9894 +#define WLC_SEND_PWR_CONSTRAINT 254
9895 +#define WLC_CURRENT_PWR 256
9896 +#define WLC_GET_CHANNELS_IN_COUNTRY 260
9897 +#define WLC_GET_COUNTRY_LIST 261
9898 +#define WLC_GET_VAR 262 /* get value of named variable */
9899 +#define WLC_SET_VAR 263 /* set named variable to value */
9900 +#define WLC_NVRAM_GET 264
9901 +#define WLC_NVRAM_SET 265
9902 +#define WLC_SET_WSEC_PMK 268
9903 +#define WLC_GET_AUTH_MODE 269
9904 +#define WLC_SET_AUTH_MODE 270
9905 +#define WLC_NDCONFIG_ITEM 273 /* currently handled in wl_oid.c */
9906 +#define WLC_NVOTPW 274
9907 +/* #define WLC_OTPW 275 */ /* no longer supported */
9908 +#define WLC_SET_LOCALE 278
9909 +#define WLC_LAST 279 /* do not change - use get_var/set_var */
9910 +
9911 +/*
9912 + * Minor kludge alert:
9913 + * Duplicate a few definitions that irelay requires from epiioctl.h here
9914 + * so caller doesn't have to include this file and epiioctl.h .
9915 + * If this grows any more, it would be time to move these irelay-specific
9916 + * definitions out of the epiioctl.h and into a separate driver common file.
9917 + */
9918 +#ifndef EPICTRL_COOKIE
9919 +#define EPICTRL_COOKIE 0xABADCEDE
9920 +#endif
9921 +
9922 +/* vx wlc ioctl's offset */
9923 +#define CMN_IOCTL_OFF 0x180
9924 +
9925 +/*
9926 + * custom OID support
9927 + *
9928 + * 0xFF - implementation specific OID
9929 + * 0xE4 - first byte of Broadcom PCI vendor ID
9930 + * 0x14 - second byte of Broadcom PCI vendor ID
9931 + * 0xXX - the custom OID number
9932 + */
9933 +
9934 +/* begin 0x1f values beyond the start of the ET driver range. */
9935 +#define WL_OID_BASE 0xFFE41420
9936 +
9937 +/* NDIS overrides */
9938 +#define OID_WL_GETINSTANCE (WL_OID_BASE + WLC_GET_INSTANCE)
9939 +#define OID_WL_NDCONFIG_ITEM (WL_OID_BASE + WLC_NDCONFIG_ITEM)
9940 +
9941 +#define WL_DECRYPT_STATUS_SUCCESS 1
9942 +#define WL_DECRYPT_STATUS_FAILURE 2
9943 +#define WL_DECRYPT_STATUS_UNKNOWN 3
9944 +
9945 +/* allows user-mode app to poll the status of USB image upgrade */
9946 +#define WLC_UPGRADE_SUCCESS 0
9947 +#define WLC_UPGRADE_PENDING 1
9948 +
9949 +#ifdef CONFIG_USBRNDIS_RETAIL
9950 +/* struct passed in for WLC_NDCONFIG_ITEM */
9951 +typedef struct {
9952 + char *name;
9953 + void *param;
9954 +} ndconfig_item_t;
9955 +#endif
9956 +
9957 +/* Bit masks for radio disabled status - returned by WL_GET_RADIO */
9958 +#define WL_RADIO_SW_DISABLE (1<<0)
9959 +#define WL_RADIO_HW_DISABLE (1<<1)
9960 +#define WL_RADIO_MPC_DISABLE (1<<2)
9961 +#define WL_RADIO_COUNTRY_DISABLE (1<<3) /* some countries don't support any 802.11 channel */
9962 +
9963 +/* Override bit for WLC_SET_TXPWR. if set, ignore other level limits */
9964 +#define WL_TXPWR_OVERRIDE (1<<31)
9965 +
9966 +/* "diag" iovar argument and error code */
9967 +#define WL_DIAG_INTERRUPT 1 /* d11 loopback interrupt test */
9968 +#define WL_DIAG_MEMORY 3 /* d11 memory test */
9969 +#define WL_DIAG_LED 4 /* LED test */
9970 +#define WL_DIAG_REG 5 /* d11/phy register test */
9971 +#define WL_DIAG_SROM 6 /* srom read/crc test */
9972 +#define WL_DIAG_DMA 7 /* DMA test */
9973 +
9974 +#define WL_DIAGERR_SUCCESS 0
9975 +#define WL_DIAGERR_FAIL_TO_RUN 1 /* unable to run requested diag */
9976 +#define WL_DIAGERR_NOT_SUPPORTED 2 /* diag requested is not supported */
9977 +#define WL_DIAGERR_INTERRUPT_FAIL 3 /* loopback interrupt test failed */
9978 +#define WL_DIAGERR_LOOPBACK_FAIL 4 /* loopback data test failed */
9979 +#define WL_DIAGERR_SROM_FAIL 5 /* srom read failed */
9980 +#define WL_DIAGERR_SROM_BADCRC 6 /* srom crc failed */
9981 +#define WL_DIAGERR_REG_FAIL 7 /* d11/phy register test failed */
9982 +#define WL_DIAGERR_MEMORY_FAIL 8 /* d11 memory test failed */
9983 +#define WL_DIAGERR_NOMEM 9 /* diag test failed due to no memory */
9984 +#define WL_DIAGERR_DMA_FAIL 10 /* DMA test failed */
9985 +
9986 +/* Bus types */
9987 +#define WL_SB_BUS 0 /* Silicon Backplane */
9988 +#define WL_PCI_BUS 1 /* PCI target */
9989 +#define WL_PCMCIA_BUS 2 /* PCMCIA target */
9990 +
9991 +/* band types */
9992 +#define WLC_BAND_AUTO 0 /* auto-select */
9993 +#define WLC_BAND_A 1 /* "a" band (5 Ghz) */
9994 +#define WLC_BAND_B 2 /* "b" band (2.4 Ghz) */
9995 +#define WLC_BAND_ALL 3 /* all bands */
9996 +
9997 +/* phy types (returned by WLC_GET_PHYTPE) */
9998 +#define WLC_PHY_TYPE_A 0
9999 +#define WLC_PHY_TYPE_B 1
10000 +#define WLC_PHY_TYPE_G 2
10001 +#define WLC_PHY_TYPE_NULL 0xf
10002 +
10003 +/* MAC list modes */
10004 +#define WLC_MACMODE_DISABLED 0 /* MAC list disabled */
10005 +#define WLC_MACMODE_DENY 1 /* Deny specified (i.e. allow unspecified) */
10006 +#define WLC_MACMODE_ALLOW 2 /* Allow specified (i.e. deny unspecified) */
10007 +
10008 +/*
10009 + *
10010 + */
10011 +#define GMODE_LEGACY_B 0
10012 +#define GMODE_AUTO 1
10013 +#define GMODE_ONLY 2
10014 +#define GMODE_B_DEFERRED 3
10015 +#define GMODE_PERFORMANCE 4
10016 +#define GMODE_LRS 5
10017 +#define GMODE_MAX 6
10018 +
10019 +/* values for PLCPHdr_override */
10020 +#define WLC_PLCP_AUTO -1
10021 +#define WLC_PLCP_SHORT 0
10022 +#define WLC_PLCP_LONG 1
10023 +
10024 +/* values for g_protection_override */
10025 +#define WLC_G_PROTECTION_AUTO -1
10026 +#define WLC_G_PROTECTION_OFF 0
10027 +#define WLC_G_PROTECTION_ON 1
10028 +
10029 +/* values for g_protection_control */
10030 +#define WLC_G_PROTECTION_CTL_OFF 0
10031 +#define WLC_G_PROTECTION_CTL_LOCAL 1
10032 +#define WLC_G_PROTECTION_CTL_OVERLAP 2
10033 +
10034 +/* Values for PM */
10035 +#define PM_OFF 0
10036 +#define PM_MAX 1
10037 +#define PM_FAST 2
10038 +
10039 +
10040 +
10041 +typedef struct {
10042 + int npulses; /* required number of pulses at n * t_int */
10043 + int ncontig; /* required number of pulses at t_int */
10044 + int min_pw; /* minimum pulse width (20 MHz clocks) */
10045 + int max_pw; /* maximum pulse width (20 MHz clocks) */
10046 + uint16 thresh0; /* Radar detection, thresh 0 */
10047 + uint16 thresh1; /* Radar detection, thresh 1 */
10048 +} wl_radar_args_t;
10049 +
10050 +/* radar iovar SET defines */
10051 +#define WL_RADRA_DETECTOR_OFF 0 /* radar dector off */
10052 +#define WL_RADAR_DETECTOR_ON 1 /* radar detector on */
10053 +#define WL_RADAR_SIMULATED 2 /* force radar detector to declare detection once */
10054 +
10055 +/* dfs_status iovar-related defines */
10056 +
10057 +/* cac - channel availability check,
10058 + * ism - in-service monitoring
10059 + * csa - channel switching anouncement
10060 + */
10061 +
10062 +/* cac state values */
10063 +#define WL_DFS_CACSTATE_IDLE 0 /* state for operating in non-radar channel */
10064 +#define WL_DFS_CACSTATE_PREISM_CAC 1 /* CAC in progress */
10065 +#define WL_DFS_CACSTATE_ISM 2 /* ISM in progress */
10066 +#define WL_DFS_CACSTATE_CSA 3 /* csa */
10067 +#define WL_DFS_CACSTATE_POSTISM_CAC 4 /* ISM CAC */
10068 +#define WL_DFS_CACSTATE_PREISM_OOC 5 /* PREISM OOC */
10069 +#define WL_DFS_CACSTATE_POSTISM_OOC 6 /* POSTISM OOC */
10070 +#define WL_DFS_CACSTATES 7 /* this many states exist */
10071 +
10072 +/* data structure used in 'dfs_status' wl interface, which is used to query dfs status */
10073 +typedef struct {
10074 + uint state; /* noted by WL_DFS_CACSTATE_XX. */
10075 + uint duration; /* time spent in ms in state. */
10076 + /* as dfs enters ISM state, it removes the operational channel from quiet channel list
10077 + * and notes the channel in channel_cleared. set to 0 if no channel is cleared
10078 + */
10079 + uint channel_cleared;
10080 +} wl_dfs_status_t;
10081 +
10082 +#define NUM_PWRCTRL_RATES 12
10083 +
10084 +
10085 +/* 802.11h enforcement levels */
10086 +#define SPECT_MNGMT_OFF 0 /* 11h disabled */
10087 +#define SPECT_MNGMT_LOOSE 1 /* allow scan lists to contain non-11h AP */
10088 +#define SPECT_MNGMT_STRICT 2 /* prune out non-11h APs from scan list */
10089 +#define SPECT_MNGMT_11D 3 /* switch to 802.11D mode */
10090 +
10091 +#define WL_CHAN_VALID_HW (1 << 0) /* valid with current HW */
10092 +#define WL_CHAN_VALID_SW (1 << 1) /* valid with current country setting */
10093 +#define WL_CHAN_BAND_A (1 << 2) /* A-band channel */
10094 +#define WL_CHAN_RADAR (1 << 3) /* radar sensitive channel */
10095 +#define WL_CHAN_INACTIVE (1 << 4) /* temporarily out of service due to radar */
10096 +#define WL_CHAN_RADAR_PASSIVE (1 << 5) /* radar channel is in passive mode */
10097 +
10098 +#define WL_MPC_VAL 0x00400000
10099 +#define WL_APSTA_VAL 0x00800000
10100 +#define WL_DFS_VAL 0x01000000
10101 +
10102 +/* max # of leds supported by GPIO (gpio pin# == led index#) */
10103 +#define WL_LED_NUMGPIO 16 /* gpio 0-15 */
10104 +
10105 +/* led per-pin behaviors */
10106 +#define WL_LED_OFF 0 /* always off */
10107 +#define WL_LED_ON 1 /* always on */
10108 +#define WL_LED_ACTIVITY 2 /* activity */
10109 +#define WL_LED_RADIO 3 /* radio enabled */
10110 +#define WL_LED_ARADIO 4 /* 5 Ghz radio enabled */
10111 +#define WL_LED_BRADIO 5 /* 2.4Ghz radio enabled */
10112 +#define WL_LED_BGMODE 6 /* on if gmode, off if bmode */
10113 +#define WL_LED_WI1 7
10114 +#define WL_LED_WI2 8
10115 +#define WL_LED_WI3 9
10116 +#define WL_LED_ASSOC 10 /* associated state indicator */
10117 +#define WL_LED_INACTIVE 11 /* null behavior (clears default behavior) */
10118 +#define WL_LED_NUMBEHAVIOR 12
10119 +
10120 +/* led behavior numeric value format */
10121 +#define WL_LED_BEH_MASK 0x7f /* behavior mask */
10122 +#define WL_LED_AL_MASK 0x80 /* activelow (polarity) bit */
10123 +
10124 +
10125 +/* WDS link local endpoint WPA role */
10126 +#define WL_WDS_WPA_ROLE_AUTH 0 /* authenticator */
10127 +#define WL_WDS_WPA_ROLE_SUP 1 /* supplicant */
10128 +#define WL_WDS_WPA_ROLE_AUTO 255 /* auto, based on mac addr value */
10129 +
10130 +/* number of bytes needed to define a 128-bit mask for MAC event reporting */
10131 +#define WL_EVENTING_MASK_LEN 16
10132 +
10133 +/* Structures and constants used for "vndr_ie" IOVar interface */
10134 +#define VNDR_IE_CMD_LEN 4 /* length of the set command string: "add", "del" (+ NULL) */
10135 +
10136 +/* 802.11 Mgmt Packet flags */
10137 +#define VNDR_IE_BEACON_FLAG 0x1
10138 +#define VNDR_IE_PRBRSP_FLAG 0x2
10139 +#define VNDR_IE_ASSOCRSP_FLAG 0x4
10140 +#define VNDR_IE_AUTHRSP_FLAG 0x8
10141 +
10142 +typedef struct {
10143 + uint32 pktflag; /* bitmask indicating which packet(s) contain this IE */
10144 + vndr_ie_t vndr_ie_data; /* vendor IE data */
10145 +} vndr_ie_info_t;
10146 +
10147 +typedef struct {
10148 + int iecount; /* number of entries in the vndr_ie_list[] array */
10149 + vndr_ie_info_t vndr_ie_list[1]; /* variable size list of vndr_ie_info_t structs */
10150 +} vndr_ie_buf_t;
10151 +
10152 +typedef struct {
10153 + char cmd[VNDR_IE_CMD_LEN]; /* vndr_ie IOVar set command : "add", "del" + NULL */
10154 + vndr_ie_buf_t vndr_ie_buffer; /* buffer containing Vendor IE list information */
10155 +} vndr_ie_setbuf_t;
10156 +
10157 +/* join target preference types */
10158 +#define WL_JOIN_PREF_RSSI 1 /* by RSSI, mandatory */
10159 +#define WL_JOIN_PREF_WPA 2 /* by akm and ciphers, optional, RSN and WPA as values */
10160 +#define WL_JOIN_PREF_BAND 3 /* by 802.11 band, optional, WLC_BAND_XXXX as values */
10161 +
10162 +/* band preference */
10163 +#define WLJP_BAND_ASSOC_PREF 255 /* use assoc preference settings */
10164 + /* others use WLC_BAND_XXXX as values */
10165 +
10166 +/* any multicast cipher suite */
10167 +#define WL_WPA_ACP_MCS_ANY "\x00\x00\x00\x00"
10168 +
10169 +#if !defined(__GNUC__)
10170 +#pragma pack(pop)
10171 +#endif
10172 +
10173 +#define NFIFO 6 /* # tx/rx fifopairs */
10174 +
10175 +#define WL_CNT_T_VERSION 1 /* current version of wl_cnt_t struct */
10176 +
10177 +typedef struct {
10178 + uint16 version; /* see definition of WL_CNT_T_VERSION */
10179 + uint16 length; /* length of entire structure */
10180 +
10181 + /* transmit stat counters */
10182 + uint32 txframe; /* tx data frames */
10183 + uint32 txbyte; /* tx data bytes */
10184 + uint32 txretrans; /* tx mac retransmits */
10185 + uint32 txerror; /* tx data errors */
10186 + uint32 txctl; /* tx management frames */
10187 + uint32 txprshort; /* tx short preamble frames */
10188 + uint32 txserr; /* tx status errors */
10189 + uint32 txnobuf; /* tx out of buffers errors */
10190 + uint32 txnoassoc; /* tx discard because we're not associated */
10191 + uint32 txrunt; /* tx runt frames */
10192 + uint32 txchit; /* tx header cache hit (fastpath) */
10193 + uint32 txcmiss; /* tx header cache miss (slowpath) */
10194 +
10195 + /* transmit chip error counters */
10196 + uint32 txuflo; /* tx fifo underflows */
10197 + uint32 txphyerr; /* tx phy errors (indicated in tx status) */
10198 + uint32 txphycrs;
10199 +
10200 + /* receive stat counters */
10201 + uint32 rxframe; /* rx data frames */
10202 + uint32 rxbyte; /* rx data bytes */
10203 + uint32 rxerror; /* rx data errors */
10204 + uint32 rxctl; /* rx management frames */
10205 + uint32 rxnobuf; /* rx out of buffers errors */
10206 + uint32 rxnondata; /* rx non data frames in the data channel errors */
10207 + uint32 rxbadds; /* rx bad DS errors */
10208 + uint32 rxbadcm; /* rx bad control or management frames */
10209 + uint32 rxfragerr; /* rx fragmentation errors */
10210 + uint32 rxrunt; /* rx runt frames */
10211 + uint32 rxgiant; /* rx giant frames */
10212 + uint32 rxnoscb; /* rx no scb error */
10213 + uint32 rxbadproto; /* rx invalid frames */
10214 + uint32 rxbadsrcmac; /* rx frames with Invalid Src Mac*/
10215 + uint32 rxbadda; /* rx frames tossed for invalid da */
10216 + uint32 rxfilter; /* rx frames filtered out */
10217 +
10218 + /* receive chip error counters */
10219 + uint32 rxoflo; /* rx fifo overflow errors */
10220 + uint32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
10221 +
10222 + uint32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
10223 + uint32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
10224 + uint32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
10225 +
10226 + /* misc counters */
10227 + uint32 dmade; /* tx/rx dma descriptor errors */
10228 + uint32 dmada; /* tx/rx dma data errors */
10229 + uint32 dmape; /* tx/rx dma descriptor protocol errors */
10230 + uint32 reset; /* reset count */
10231 + uint32 tbtt; /* cnts the TBTT int's */
10232 + uint32 txdmawar;
10233 +
10234 + /* MAC counters: 32-bit version of d11.h's macstat_t */
10235 + uint32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
10236 + Control Management (includes retransmissions) */
10237 + uint32 txrtsfrm; /* number of RTS sent out by the MAC */
10238 + uint32 txctsfrm; /* number of CTS sent out by the MAC */
10239 + uint32 txackfrm; /* number of ACK frames sent out */
10240 + uint32 txdnlfrm; /* Not used */
10241 + uint32 txbcnfrm; /* beacons transmitted */
10242 + uint32 txfunfl[8]; /* per-fifo tx underflows */
10243 + uint32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS or BCN) */
10244 + uint32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
10245 + driver enqueued frames*/
10246 + uint32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
10247 + uint32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
10248 + uint32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
10249 + data/control/management*/
10250 + uint32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
10251 + uint32 rxbadplcp; /* parity check of the PLCP header failed */
10252 + uint32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
10253 + uint32 rxstrt; /* Number of received frames with a good PLCP (i.e. passing parity check) */
10254 + uint32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
10255 + uint32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
10256 + uint32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
10257 + uint32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
10258 + uint32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS)*/
10259 + uint32 rxackucast; /* number of ucast ACKS received (good FCS)*/
10260 + uint32 rxdfrmocast; /* number of received DATA frames with good FCS and not matching RA */
10261 + uint32 rxmfrmocast; /* number of received MGMT frames with good FCS and not matching RA */
10262 + uint32 rxcfrmocast; /* number of received CNTRL frame with good FCS and not matching RA */
10263 + uint32 rxrtsocast; /* number of received RTS not addressed to the MAC */
10264 + uint32 rxctsocast; /* number of received CTS not addressed to the MAC */
10265 + uint32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
10266 + uint32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
10267 + uint32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC (unlikely
10268 + to see these) */
10269 + uint32 rxbeaconmbss; /* beacons received from member of BSS */
10270 + uint32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from other BSS (WDS FRAME) */
10271 + uint32 rxbeaconobss; /* beacons received from other BSS */
10272 + uint32 rxrsptmout; /* Number of response timeouts for transmitted frames expecting a
10273 + response */
10274 + uint32 bcntxcancl; /* transmit beacons cancelled due to receipt of beacon (IBSS) */
10275 + uint32 rxf0ovfl; /* Number of receive fifo 0 overflows */
10276 + uint32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
10277 + uint32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
10278 + uint32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
10279 + uint32 pmqovfl; /* Number of PMQ overflows */
10280 + uint32 rxcgprqfrm; /* Number of received Probe requests that made it into the PRQ fifo */
10281 + uint32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
10282 + uint32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did not get ACK */
10283 + uint32 txcgprssuc; /* Tx Probe Rresponse Success (ACK was received) */
10284 + uint32 prs_timeout; /* Number of probe requests that were dropped from the PRQ fifo because
10285 + a probe response could not be sent out within the time limit defined
10286 + in M_PRS_MAXTIME */
10287 + uint32 rxnack; /* Number of NACKS received (Afterburner) */
10288 + uint32 frmscons; /* Number of frames completed without transmission because of an
10289 + Afterburner re-queue */
10290 + uint32 txnack; /* Number of NACKs transmtitted (Afterburner) */
10291 + uint32 txglitch_nack; /* obsolete */
10292 + uint32 txburst; /* obsolete */
10293 + uint32 rxburst; /* obsolete */
10294 +
10295 + /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
10296 + uint32 txfrag; /* dot11TransmittedFragmentCount */
10297 + uint32 txmulti; /* dot11MulticastTransmittedFrameCount */
10298 + uint32 txfail; /* dot11FailedCount */
10299 + uint32 txretry; /* dot11RetryCount */
10300 + uint32 txretrie; /* dot11MultipleRetryCount */
10301 + uint32 rxdup; /* dot11FrameduplicateCount */
10302 + uint32 txrts; /* dot11RTSSuccessCount */
10303 + uint32 txnocts; /* dot11RTSFailureCount */
10304 + uint32 txnoack; /* dot11ACKFailureCount */
10305 + uint32 rxfrag; /* dot11ReceivedFragmentCount */
10306 + uint32 rxmulti; /* dot11MulticastReceivedFrameCount */
10307 + uint32 rxcrc; /* dot11FCSErrorCount */
10308 + uint32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
10309 + uint32 rxundec; /* dot11WEPUndecryptableCount */
10310 +
10311 + /* WPA2 counters (see rxundec for DecryptFailureCount) */
10312 + uint32 tkipmicfaill; /* TKIPLocalMICFailures */
10313 + uint32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
10314 + uint32 tkipreplay; /* TKIPReplays */
10315 + uint32 ccmpfmterr; /* CCMPFormatErrors */
10316 + uint32 ccmpreplay; /* CCMPReplays */
10317 + uint32 ccmpundec; /* CCMPDecryptErrors */
10318 + uint32 fourwayfail; /* FourWayHandshakeFailures */
10319 + uint32 wepundec; /* dot11WEPUndecryptableCount */
10320 + uint32 wepicverr; /* dot11WEPICVErrorCount */
10321 + uint32 decsuccess; /* DecryptSuccessCount */
10322 + uint32 tkipicverr; /* TKIPICVErrorCount */
10323 + uint32 wepexcluded; /* dot11WEPExcludedCount */
10324 +} wl_cnt_t;
10325 +
10326 +#endif /* _wlioctl_h_ */
10327 diff -urN linux.old/arch/mips/bcm947xx/nvram.c linux.dev/arch/mips/bcm947xx/nvram.c
10328 --- linux.old/arch/mips/bcm947xx/nvram.c 1970-01-01 01:00:00.000000000 +0100
10329 +++ linux.dev/arch/mips/bcm947xx/nvram.c 2005-11-07 21:57:07.881588000 +0100
10330 @@ -0,0 +1,321 @@
10331 +/*
10332 + * NVRAM variable manipulation (common)
10333 + *
10334 + * Copyright 2004, Broadcom Corporation
10335 + * All Rights Reserved.
10336 + *
10337 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10338 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10339 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10340 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10341 + *
10342 + * $Id$
10343 + */
10344 +
10345 +#include <typedefs.h>
10346 +#include <osl.h>
10347 +#include <bcmendian.h>
10348 +#include <bcmnvram.h>
10349 +#include <bcmutils.h>
10350 +#include <sbsdram.h>
10351 +
10352 +extern struct nvram_tuple * BCMINIT(_nvram_realloc)(struct nvram_tuple *t, const char *name, const char *value);
10353 +extern void BCMINIT(_nvram_free)(struct nvram_tuple *t);
10354 +extern int BCMINIT(_nvram_read)(void *buf);
10355 +
10356 +char * BCMINIT(_nvram_get)(const char *name);
10357 +int BCMINIT(_nvram_set)(const char *name, const char *value);
10358 +int BCMINIT(_nvram_unset)(const char *name);
10359 +int BCMINIT(_nvram_getall)(char *buf, int count);
10360 +int BCMINIT(_nvram_commit)(struct nvram_header *header);
10361 +int BCMINIT(_nvram_init)(void);
10362 +void BCMINIT(_nvram_exit)(void);
10363 +
10364 +static struct nvram_tuple * BCMINITDATA(nvram_hash)[257];
10365 +static struct nvram_tuple * nvram_dead;
10366 +
10367 +/* Free all tuples. Should be locked. */
10368 +static void
10369 +BCMINITFN(nvram_free)(void)
10370 +{
10371 + uint i;
10372 + struct nvram_tuple *t, *next;
10373 +
10374 + /* Free hash table */
10375 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10376 + for (t = BCMINIT(nvram_hash)[i]; t; t = next) {
10377 + next = t->next;
10378 + BCMINIT(_nvram_free)(t);
10379 + }
10380 + BCMINIT(nvram_hash)[i] = NULL;
10381 + }
10382 +
10383 + /* Free dead table */
10384 + for (t = nvram_dead; t; t = next) {
10385 + next = t->next;
10386 + BCMINIT(_nvram_free)(t);
10387 + }
10388 + nvram_dead = NULL;
10389 +
10390 + /* Indicate to per-port code that all tuples have been freed */
10391 + BCMINIT(_nvram_free)(NULL);
10392 +}
10393 +
10394 +/* String hash */
10395 +static INLINE uint
10396 +hash(const char *s)
10397 +{
10398 + uint hash = 0;
10399 +
10400 + while (*s)
10401 + hash = 31 * hash + *s++;
10402 +
10403 + return hash;
10404 +}
10405 +
10406 +/* (Re)initialize the hash table. Should be locked. */
10407 +static int
10408 +BCMINITFN(nvram_rehash)(struct nvram_header *header)
10409 +{
10410 + char buf[] = "0xXXXXXXXX", *name, *value, *end, *eq;
10411 +
10412 + /* (Re)initialize hash table */
10413 + BCMINIT(nvram_free)();
10414 +
10415 + /* Parse and set "name=value\0 ... \0\0" */
10416 + name = (char *) &header[1];
10417 + end = (char *) header + NVRAM_SPACE - 2;
10418 + end[0] = end[1] = '\0';
10419 + for (; *name; name = value + strlen(value) + 1) {
10420 + if (!(eq = strchr(name, '=')))
10421 + break;
10422 + *eq = '\0';
10423 + value = eq + 1;
10424 + BCMINIT(_nvram_set)(name, value);
10425 + *eq = '=';
10426 + }
10427 +
10428 + /* Set special SDRAM parameters */
10429 + if (!BCMINIT(_nvram_get)("sdram_init")) {
10430 + sprintf(buf, "0x%04X", (uint16)(header->crc_ver_init >> 16));
10431 + BCMINIT(_nvram_set)("sdram_init", buf);
10432 + }
10433 + if (!BCMINIT(_nvram_get)("sdram_config")) {
10434 + sprintf(buf, "0x%04X", (uint16)(header->config_refresh & 0xffff));
10435 + BCMINIT(_nvram_set)("sdram_config", buf);
10436 + }
10437 + if (!BCMINIT(_nvram_get)("sdram_refresh")) {
10438 + sprintf(buf, "0x%04X", (uint16)((header->config_refresh >> 16) & 0xffff));
10439 + BCMINIT(_nvram_set)("sdram_refresh", buf);
10440 + }
10441 + if (!BCMINIT(_nvram_get)("sdram_ncdl")) {
10442 + sprintf(buf, "0x%08X", header->config_ncdl);
10443 + BCMINIT(_nvram_set)("sdram_ncdl", buf);
10444 + }
10445 +
10446 + return 0;
10447 +}
10448 +
10449 +/* Get the value of an NVRAM variable. Should be locked. */
10450 +char *
10451 +BCMINITFN(_nvram_get)(const char *name)
10452 +{
10453 + uint i;
10454 + struct nvram_tuple *t;
10455 + char *value;
10456 +
10457 + if (!name)
10458 + return NULL;
10459 +
10460 + /* Hash the name */
10461 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10462 +
10463 + /* Find the associated tuple in the hash table */
10464 + for (t = BCMINIT(nvram_hash)[i]; t && strcmp(t->name, name); t = t->next);
10465 +
10466 + value = t ? t->value : NULL;
10467 +
10468 + return value;
10469 +}
10470 +
10471 +/* Get the value of an NVRAM variable. Should be locked. */
10472 +int
10473 +BCMINITFN(_nvram_set)(const char *name, const char *value)
10474 +{
10475 + uint i;
10476 + struct nvram_tuple *t, *u, **prev;
10477 +
10478 + /* Hash the name */
10479 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10480 +
10481 + /* Find the associated tuple in the hash table */
10482 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10483 +
10484 + /* (Re)allocate tuple */
10485 + if (!(u = BCMINIT(_nvram_realloc)(t, name, value)))
10486 + return -12; /* -ENOMEM */
10487 +
10488 + /* Value reallocated */
10489 + if (t && t == u)
10490 + return 0;
10491 +
10492 + /* Move old tuple to the dead table */
10493 + if (t) {
10494 + *prev = t->next;
10495 + t->next = nvram_dead;
10496 + nvram_dead = t;
10497 + }
10498 +
10499 + /* Add new tuple to the hash table */
10500 + u->next = BCMINIT(nvram_hash)[i];
10501 + BCMINIT(nvram_hash)[i] = u;
10502 +
10503 + return 0;
10504 +}
10505 +
10506 +/* Unset the value of an NVRAM variable. Should be locked. */
10507 +int
10508 +BCMINITFN(_nvram_unset)(const char *name)
10509 +{
10510 + uint i;
10511 + struct nvram_tuple *t, **prev;
10512 +
10513 + if (!name)
10514 + return 0;
10515 +
10516 + /* Hash the name */
10517 + i = hash(name) % ARRAYSIZE(BCMINIT(nvram_hash));
10518 +
10519 + /* Find the associated tuple in the hash table */
10520 + for (prev = &BCMINIT(nvram_hash)[i], t = *prev; t && strcmp(t->name, name); prev = &t->next, t = *prev);
10521 +
10522 + /* Move it to the dead table */
10523 + if (t) {
10524 + *prev = t->next;
10525 + t->next = nvram_dead;
10526 + nvram_dead = t;
10527 + }
10528 +
10529 + return 0;
10530 +}
10531 +
10532 +/* Get all NVRAM variables. Should be locked. */
10533 +int
10534 +BCMINITFN(_nvram_getall)(char *buf, int count)
10535 +{
10536 + uint i;
10537 + struct nvram_tuple *t;
10538 + int len = 0;
10539 +
10540 + bzero(buf, count);
10541 +
10542 + /* Write name=value\0 ... \0\0 */
10543 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10544 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10545 + if ((count - len) > (strlen(t->name) + 1 + strlen(t->value) + 1))
10546 + len += sprintf(buf + len, "%s=%s", t->name, t->value) + 1;
10547 + else
10548 + break;
10549 + }
10550 + }
10551 +
10552 + return 0;
10553 +}
10554 +
10555 +/* Regenerate NVRAM. Should be locked. */
10556 +int
10557 +BCMINITFN(_nvram_commit)(struct nvram_header *header)
10558 +{
10559 + char *init, *config, *refresh, *ncdl;
10560 + char *ptr, *end;
10561 + int i;
10562 + struct nvram_tuple *t;
10563 + struct nvram_header tmp;
10564 + uint8 crc;
10565 +
10566 + /* Regenerate header */
10567 + header->magic = NVRAM_MAGIC;
10568 + header->crc_ver_init = (NVRAM_VERSION << 8);
10569 + if (!(init = BCMINIT(_nvram_get)("sdram_init")) ||
10570 + !(config = BCMINIT(_nvram_get)("sdram_config")) ||
10571 + !(refresh = BCMINIT(_nvram_get)("sdram_refresh")) ||
10572 + !(ncdl = BCMINIT(_nvram_get)("sdram_ncdl"))) {
10573 + header->crc_ver_init |= SDRAM_INIT << 16;
10574 + header->config_refresh = SDRAM_CONFIG;
10575 + header->config_refresh |= SDRAM_REFRESH << 16;
10576 + header->config_ncdl = 0;
10577 + } else {
10578 + header->crc_ver_init |= (bcm_strtoul(init, NULL, 0) & 0xffff) << 16;
10579 + header->config_refresh = bcm_strtoul(config, NULL, 0) & 0xffff;
10580 + header->config_refresh |= (bcm_strtoul(refresh, NULL, 0) & 0xffff) << 16;
10581 + header->config_ncdl = bcm_strtoul(ncdl, NULL, 0);
10582 + }
10583 +
10584 + /* Clear data area */
10585 + ptr = (char *) header + sizeof(struct nvram_header);
10586 + bzero(ptr, NVRAM_SPACE - sizeof(struct nvram_header));
10587 +
10588 + /* Leave space for a double NUL at the end */
10589 + end = (char *) header + NVRAM_SPACE - 2;
10590 +
10591 + /* Write out all tuples */
10592 + for (i = 0; i < ARRAYSIZE(BCMINIT(nvram_hash)); i++) {
10593 + for (t = BCMINIT(nvram_hash)[i]; t; t = t->next) {
10594 + if ((ptr + strlen(t->name) + 1 + strlen(t->value) + 1) > end)
10595 + break;
10596 + ptr += sprintf(ptr, "%s=%s", t->name, t->value) + 1;
10597 + }
10598 + }
10599 +
10600 + /* End with a double NUL */
10601 + ptr += 2;
10602 +
10603 + /* Set new length */
10604 + header->len = ROUNDUP(ptr - (char *) header, 4);
10605 +
10606 + /* Little-endian CRC8 over the last 11 bytes of the header */
10607 + tmp.crc_ver_init = htol32(header->crc_ver_init);
10608 + tmp.config_refresh = htol32(header->config_refresh);
10609 + tmp.config_ncdl = htol32(header->config_ncdl);
10610 + crc = hndcrc8((char *) &tmp + 9, sizeof(struct nvram_header) - 9, CRC8_INIT_VALUE);
10611 +
10612 + /* Continue CRC8 over data bytes */
10613 + crc = hndcrc8((char *) &header[1], header->len - sizeof(struct nvram_header), crc);
10614 +
10615 + /* Set new CRC8 */
10616 + header->crc_ver_init |= crc;
10617 +
10618 + /* Reinitialize hash table */
10619 + return BCMINIT(nvram_rehash)(header);
10620 +}
10621 +
10622 +/* Initialize hash table. Should be locked. */
10623 +int
10624 +BCMINITFN(_nvram_init)(void)
10625 +{
10626 + struct nvram_header *header;
10627 + int ret;
10628 + void *osh;
10629 +
10630 + /* get kernel osl handler */
10631 + osh = osl_attach(NULL);
10632 +
10633 + if (!(header = (struct nvram_header *) MALLOC(osh, NVRAM_SPACE))) {
10634 + printf("nvram_init: out of memory, malloced %d bytes\n", MALLOCED(osh));
10635 + return -12; /* -ENOMEM */
10636 + }
10637 +
10638 + if ((ret = BCMINIT(_nvram_read)(header)) == 0 &&
10639 + header->magic == NVRAM_MAGIC)
10640 + BCMINIT(nvram_rehash)(header);
10641 +
10642 + MFREE(osh, header, NVRAM_SPACE);
10643 + return ret;
10644 +}
10645 +
10646 +/* Free hash table. Should be locked. */
10647 +void
10648 +BCMINITFN(_nvram_exit)(void)
10649 +{
10650 + BCMINIT(nvram_free)();
10651 +}
10652 diff -urN linux.old/arch/mips/bcm947xx/nvram_linux.c linux.dev/arch/mips/bcm947xx/nvram_linux.c
10653 --- linux.old/arch/mips/bcm947xx/nvram_linux.c 1970-01-01 01:00:00.000000000 +0100
10654 +++ linux.dev/arch/mips/bcm947xx/nvram_linux.c 2005-11-08 00:54:56.755597250 +0100
10655 @@ -0,0 +1,633 @@
10656 +/*
10657 + * NVRAM variable manipulation (Linux kernel half)
10658 + *
10659 + * Copyright 2005, Broadcom Corporation
10660 + * All Rights Reserved.
10661 + *
10662 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10663 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10664 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10665 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10666 + *
10667 + * $Id$
10668 + */
10669 +
10670 +#include <linux/config.h>
10671 +#include <linux/init.h>
10672 +#include <linux/module.h>
10673 +#include <linux/kernel.h>
10674 +#include <linux/string.h>
10675 +#include <linux/interrupt.h>
10676 +#include <linux/spinlock.h>
10677 +#include <linux/slab.h>
10678 +#include <linux/bootmem.h>
10679 +#include <linux/wrapper.h>
10680 +#include <linux/fs.h>
10681 +#include <linux/miscdevice.h>
10682 +#include <linux/mtd/mtd.h>
10683 +#include <asm/addrspace.h>
10684 +#include <asm/io.h>
10685 +#include <asm/uaccess.h>
10686 +
10687 +#include <typedefs.h>
10688 +#include <bcmendian.h>
10689 +#include <bcmnvram.h>
10690 +#include <bcmutils.h>
10691 +#include <sbconfig.h>
10692 +#include <sbchipc.h>
10693 +#include <sbutils.h>
10694 +#include <sbmips.h>
10695 +#include <sflash.h>
10696 +
10697 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
10698 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
10699 +
10700 +#ifdef MODULE
10701 +
10702 +#define early_nvram_get(name) nvram_get(name)
10703 +
10704 +#else /* !MODULE */
10705 +
10706 +/* Global SB handle */
10707 +extern void *bcm947xx_sbh;
10708 +extern spinlock_t bcm947xx_sbh_lock;
10709 +
10710 +/* Convenience */
10711 +#define sbh bcm947xx_sbh
10712 +#define sbh_lock bcm947xx_sbh_lock
10713 +#define KB * 1024
10714 +#define MB * 1024 * 1024
10715 +
10716 +/* Probe for NVRAM header */
10717 +static void __init
10718 +early_nvram_init(void)
10719 +{
10720 + struct nvram_header *header;
10721 + chipcregs_t *cc;
10722 + struct sflash *info = NULL;
10723 + int i;
10724 + uint32 base, off, lim;
10725 + u32 *src, *dst;
10726 +
10727 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
10728 + base = KSEG1ADDR(SB_FLASH2);
10729 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
10730 + case PFLASH:
10731 + lim = SB_FLASH2_SZ;
10732 + break;
10733 +
10734 + case SFLASH_ST:
10735 + case SFLASH_AT:
10736 + if ((info = sflash_init(cc)) == NULL)
10737 + return;
10738 + lim = info->size;
10739 + break;
10740 +
10741 + case FLASH_NONE:
10742 + default:
10743 + return;
10744 + }
10745 + } else {
10746 + /* extif assumed, Stop at 4 MB */
10747 + base = KSEG1ADDR(SB_FLASH1);
10748 + lim = SB_FLASH1_SZ;
10749 + }
10750 +
10751 + off = FLASH_MIN;
10752 + while (off <= lim) {
10753 + /* Windowed flash access */
10754 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
10755 + if (header->magic == NVRAM_MAGIC)
10756 + goto found;
10757 + off <<= 1;
10758 + }
10759 +
10760 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
10761 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
10762 + if (header->magic == NVRAM_MAGIC)
10763 + goto found;
10764 +
10765 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
10766 + if (header->magic == NVRAM_MAGIC)
10767 + goto found;
10768 +
10769 + printk("early_nvram_init: NVRAM not found\n");
10770 + return;
10771 +
10772 +found:
10773 + src = (u32 *) header;
10774 + dst = (u32 *) nvram_buf;
10775 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
10776 + *dst++ = *src++;
10777 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
10778 + *dst++ = ltoh32(*src++);
10779 +}
10780 +
10781 +/* Early (before mm or mtd) read-only access to NVRAM */
10782 +static char * __init
10783 +early_nvram_get(const char *name)
10784 +{
10785 + char *var, *value, *end, *eq;
10786 +
10787 + if (!name)
10788 + return NULL;
10789 +
10790 + /* Too early? */
10791 + if (sbh == NULL)
10792 + return NULL;
10793 +
10794 + if (!nvram_buf[0])
10795 + early_nvram_init();
10796 +
10797 + /* Look for name=value and return value */
10798 + var = &nvram_buf[sizeof(struct nvram_header)];
10799 + end = nvram_buf + sizeof(nvram_buf) - 2;
10800 + end[0] = end[1] = '\0';
10801 + for (; *var; var = value + strlen(value) + 1) {
10802 + if (!(eq = strchr(var, '=')))
10803 + break;
10804 + value = eq + 1;
10805 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
10806 + return value;
10807 + }
10808 +
10809 + return NULL;
10810 +}
10811 +
10812 +#endif /* !MODULE */
10813 +
10814 +extern char * _nvram_get(const char *name);
10815 +extern int _nvram_set(const char *name, const char *value);
10816 +extern int _nvram_unset(const char *name);
10817 +extern int _nvram_getall(char *buf, int count);
10818 +extern int _nvram_commit(struct nvram_header *header);
10819 +extern int _nvram_init(void);
10820 +extern void _nvram_exit(void);
10821 +
10822 +/* Globals */
10823 +static spinlock_t nvram_lock = SPIN_LOCK_UNLOCKED;
10824 +static struct semaphore nvram_sem;
10825 +static unsigned long nvram_offset = 0;
10826 +static int nvram_major = -1;
10827 +static devfs_handle_t nvram_handle = NULL;
10828 +static struct mtd_info *nvram_mtd = NULL;
10829 +
10830 +int
10831 +_nvram_read(char *buf)
10832 +{
10833 + struct nvram_header *header = (struct nvram_header *) buf;
10834 + size_t len;
10835 +
10836 + if (!nvram_mtd ||
10837 + MTD_READ(nvram_mtd, nvram_mtd->size - NVRAM_SPACE, NVRAM_SPACE, &len, buf) ||
10838 + len != NVRAM_SPACE ||
10839 + header->magic != NVRAM_MAGIC) {
10840 + /* Maybe we can recover some data from early initialization */
10841 + memcpy(buf, nvram_buf, NVRAM_SPACE);
10842 + }
10843 +
10844 + return 0;
10845 +}
10846 +
10847 +struct nvram_tuple *
10848 +_nvram_realloc(struct nvram_tuple *t, const char *name, const char *value)
10849 +{
10850 + if ((nvram_offset + strlen(value) + 1) > NVRAM_SPACE)
10851 + return NULL;
10852 +
10853 + if (!t) {
10854 + if (!(t = kmalloc(sizeof(struct nvram_tuple) + strlen(name) + 1, GFP_ATOMIC)))
10855 + return NULL;
10856 +
10857 + /* Copy name */
10858 + t->name = (char *) &t[1];
10859 + strcpy(t->name, name);
10860 +
10861 + t->value = NULL;
10862 + }
10863 +
10864 + /* Copy value */
10865 + if (!t->value || strcmp(t->value, value)) {
10866 + t->value = &nvram_buf[nvram_offset];
10867 + strcpy(t->value, value);
10868 + nvram_offset += strlen(value) + 1;
10869 + }
10870 +
10871 + return t;
10872 +}
10873 +
10874 +void
10875 +_nvram_free(struct nvram_tuple *t)
10876 +{
10877 + if (!t)
10878 + nvram_offset = 0;
10879 + else
10880 + kfree(t);
10881 +}
10882 +
10883 +int
10884 +nvram_set(const char *name, const char *value)
10885 +{
10886 + unsigned long flags;
10887 + int ret;
10888 + struct nvram_header *header;
10889 +
10890 + spin_lock_irqsave(&nvram_lock, flags);
10891 + if ((ret = _nvram_set(name, value))) {
10892 + /* Consolidate space and try again */
10893 + if ((header = kmalloc(NVRAM_SPACE, GFP_ATOMIC))) {
10894 + if (_nvram_commit(header) == 0)
10895 + ret = _nvram_set(name, value);
10896 + kfree(header);
10897 + }
10898 + }
10899 + spin_unlock_irqrestore(&nvram_lock, flags);
10900 +
10901 + return ret;
10902 +}
10903 +
10904 +char *
10905 +real_nvram_get(const char *name)
10906 +{
10907 + unsigned long flags;
10908 + char *value;
10909 +
10910 + spin_lock_irqsave(&nvram_lock, flags);
10911 + value = _nvram_get(name);
10912 + spin_unlock_irqrestore(&nvram_lock, flags);
10913 +
10914 + return value;
10915 +}
10916 +
10917 +char *
10918 +nvram_get(const char *name)
10919 +{
10920 + if (nvram_major >= 0)
10921 + return real_nvram_get(name);
10922 + else
10923 + return early_nvram_get(name);
10924 +}
10925 +
10926 +int
10927 +nvram_unset(const char *name)
10928 +{
10929 + unsigned long flags;
10930 + int ret;
10931 +
10932 + spin_lock_irqsave(&nvram_lock, flags);
10933 + ret = _nvram_unset(name);
10934 + spin_unlock_irqrestore(&nvram_lock, flags);
10935 +
10936 + return ret;
10937 +}
10938 +
10939 +static void
10940 +erase_callback(struct erase_info *done)
10941 +{
10942 + wait_queue_head_t *wait_q = (wait_queue_head_t *) done->priv;
10943 + wake_up(wait_q);
10944 +}
10945 +
10946 +int
10947 +nvram_commit(void)
10948 +{
10949 + char *buf;
10950 + size_t erasesize, len;
10951 + unsigned int i;
10952 + int ret;
10953 + struct nvram_header *header;
10954 + unsigned long flags;
10955 + u_int32_t offset;
10956 + DECLARE_WAITQUEUE(wait, current);
10957 + wait_queue_head_t wait_q;
10958 + struct erase_info erase;
10959 +
10960 + if (!nvram_mtd) {
10961 + printk("nvram_commit: NVRAM not found\n");
10962 + return -ENODEV;
10963 + }
10964 +
10965 + if (in_interrupt()) {
10966 + printk("nvram_commit: not committing in interrupt\n");
10967 + return -EINVAL;
10968 + }
10969 +
10970 + /* Backup sector blocks to be erased */
10971 + erasesize = ROUNDUP(NVRAM_SPACE, nvram_mtd->erasesize);
10972 + if (!(buf = kmalloc(erasesize, GFP_KERNEL))) {
10973 + printk("nvram_commit: out of memory\n");
10974 + return -ENOMEM;
10975 + }
10976 +
10977 + down(&nvram_sem);
10978 +
10979 + if ((i = erasesize - NVRAM_SPACE) > 0) {
10980 + offset = nvram_mtd->size - erasesize;
10981 + len = 0;
10982 + ret = MTD_READ(nvram_mtd, offset, i, &len, buf);
10983 + if (ret || len != i) {
10984 + printk("nvram_commit: read error ret = %d, len = %d/%d\n", ret, len, i);
10985 + ret = -EIO;
10986 + goto done;
10987 + }
10988 + header = (struct nvram_header *)(buf + i);
10989 + } else {
10990 + offset = nvram_mtd->size - NVRAM_SPACE;
10991 + header = (struct nvram_header *)buf;
10992 + }
10993 +
10994 + /* Regenerate NVRAM */
10995 + spin_lock_irqsave(&nvram_lock, flags);
10996 + ret = _nvram_commit(header);
10997 + spin_unlock_irqrestore(&nvram_lock, flags);
10998 + if (ret)
10999 + goto done;
11000 +
11001 + /* Erase sector blocks */
11002 + init_waitqueue_head(&wait_q);
11003 + for (; offset < nvram_mtd->size - NVRAM_SPACE + header->len; offset += nvram_mtd->erasesize) {
11004 + erase.mtd = nvram_mtd;
11005 + erase.addr = offset;
11006 + erase.len = nvram_mtd->erasesize;
11007 + erase.callback = erase_callback;
11008 + erase.priv = (u_long) &wait_q;
11009 +
11010 + set_current_state(TASK_INTERRUPTIBLE);
11011 + add_wait_queue(&wait_q, &wait);
11012 +
11013 + /* Unlock sector blocks */
11014 + if (nvram_mtd->unlock)
11015 + nvram_mtd->unlock(nvram_mtd, offset, nvram_mtd->erasesize);
11016 +
11017 + if ((ret = MTD_ERASE(nvram_mtd, &erase))) {
11018 + set_current_state(TASK_RUNNING);
11019 + remove_wait_queue(&wait_q, &wait);
11020 + printk("nvram_commit: erase error\n");
11021 + goto done;
11022 + }
11023 +
11024 + /* Wait for erase to finish */
11025 + schedule();
11026 + remove_wait_queue(&wait_q, &wait);
11027 + }
11028 +
11029 + /* Write partition up to end of data area */
11030 + offset = nvram_mtd->size - erasesize;
11031 + i = erasesize - NVRAM_SPACE + header->len;
11032 + ret = MTD_WRITE(nvram_mtd, offset, i, &len, buf);
11033 + if (ret || len != i) {
11034 + printk("nvram_commit: write error\n");
11035 + ret = -EIO;
11036 + goto done;
11037 + }
11038 +
11039 + offset = nvram_mtd->size - erasesize;
11040 + ret = MTD_READ(nvram_mtd, offset, 4, &len, buf);
11041 +
11042 + done:
11043 + up(&nvram_sem);
11044 + kfree(buf);
11045 + return ret;
11046 +}
11047 +
11048 +int
11049 +nvram_getall(char *buf, int count)
11050 +{
11051 + unsigned long flags;
11052 + int ret;
11053 +
11054 + spin_lock_irqsave(&nvram_lock, flags);
11055 + ret = _nvram_getall(buf, count);
11056 + spin_unlock_irqrestore(&nvram_lock, flags);
11057 +
11058 + return ret;
11059 +}
11060 +
11061 +EXPORT_SYMBOL(nvram_get);
11062 +EXPORT_SYMBOL(nvram_getall);
11063 +EXPORT_SYMBOL(nvram_set);
11064 +EXPORT_SYMBOL(nvram_unset);
11065 +EXPORT_SYMBOL(nvram_commit);
11066 +
11067 +/* User mode interface below */
11068 +
11069 +static ssize_t
11070 +dev_nvram_read(struct file *file, char *buf, size_t count, loff_t *ppos)
11071 +{
11072 + char tmp[100], *name = tmp, *value;
11073 + ssize_t ret;
11074 + unsigned long off;
11075 +
11076 + if (count > sizeof(tmp)) {
11077 + if (!(name = kmalloc(count, GFP_KERNEL)))
11078 + return -ENOMEM;
11079 + }
11080 +
11081 + if (copy_from_user(name, buf, count)) {
11082 + ret = -EFAULT;
11083 + goto done;
11084 + }
11085 +
11086 + if (*name == '\0') {
11087 + /* Get all variables */
11088 + ret = nvram_getall(name, count);
11089 + if (ret == 0) {
11090 + if (copy_to_user(buf, name, count)) {
11091 + ret = -EFAULT;
11092 + goto done;
11093 + }
11094 + ret = count;
11095 + }
11096 + } else {
11097 + if (!(value = nvram_get(name))) {
11098 + ret = 0;
11099 + goto done;
11100 + }
11101 +
11102 + /* Provide the offset into mmap() space */
11103 + off = (unsigned long) value - (unsigned long) nvram_buf;
11104 +
11105 + if (put_user(off, (unsigned long *) buf)) {
11106 + ret = -EFAULT;
11107 + goto done;
11108 + }
11109 +
11110 + ret = sizeof(unsigned long);
11111 + }
11112 +
11113 + flush_cache_all();
11114 +
11115 +done:
11116 + if (name != tmp)
11117 + kfree(name);
11118 +
11119 + return ret;
11120 +}
11121 +
11122 +static ssize_t
11123 +dev_nvram_write(struct file *file, const char *buf, size_t count, loff_t *ppos)
11124 +{
11125 + char tmp[100], *name = tmp, *value;
11126 + ssize_t ret;
11127 +
11128 + if (count > sizeof(tmp)) {
11129 + if (!(name = kmalloc(count, GFP_KERNEL)))
11130 + return -ENOMEM;
11131 + }
11132 +
11133 + if (copy_from_user(name, buf, count)) {
11134 + ret = -EFAULT;
11135 + goto done;
11136 + }
11137 +
11138 + value = name;
11139 + name = strsep(&value, "=");
11140 + if (value)
11141 + ret = nvram_set(name, value) ? : count;
11142 + else
11143 + ret = nvram_unset(name) ? : count;
11144 +
11145 + done:
11146 + if (name != tmp)
11147 + kfree(name);
11148 +
11149 + return ret;
11150 +}
11151 +
11152 +static int
11153 +dev_nvram_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
11154 +{
11155 + if (cmd != NVRAM_MAGIC)
11156 + return -EINVAL;
11157 + return nvram_commit();
11158 +}
11159 +
11160 +static int
11161 +dev_nvram_mmap(struct file *file, struct vm_area_struct *vma)
11162 +{
11163 + unsigned long offset = virt_to_phys(nvram_buf);
11164 +
11165 + if (remap_page_range(vma->vm_start, offset, vma->vm_end-vma->vm_start,
11166 + vma->vm_page_prot))
11167 + return -EAGAIN;
11168 +
11169 + return 0;
11170 +}
11171 +
11172 +static int
11173 +dev_nvram_open(struct inode *inode, struct file * file)
11174 +{
11175 + MOD_INC_USE_COUNT;
11176 + return 0;
11177 +}
11178 +
11179 +static int
11180 +dev_nvram_release(struct inode *inode, struct file * file)
11181 +{
11182 + MOD_DEC_USE_COUNT;
11183 + return 0;
11184 +}
11185 +
11186 +static struct file_operations dev_nvram_fops = {
11187 + owner: THIS_MODULE,
11188 + open: dev_nvram_open,
11189 + release: dev_nvram_release,
11190 + read: dev_nvram_read,
11191 + write: dev_nvram_write,
11192 + ioctl: dev_nvram_ioctl,
11193 + mmap: dev_nvram_mmap,
11194 +};
11195 +
11196 +static void
11197 +dev_nvram_exit(void)
11198 +{
11199 + int order = 0;
11200 + struct page *page, *end;
11201 +
11202 + if (nvram_handle)
11203 + devfs_unregister(nvram_handle);
11204 +
11205 + if (nvram_major >= 0)
11206 + devfs_unregister_chrdev(nvram_major, "nvram");
11207 +
11208 + if (nvram_mtd)
11209 + put_mtd_device(nvram_mtd);
11210 +
11211 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11212 + order++;
11213 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11214 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11215 + mem_map_unreserve(page);
11216 +
11217 + _nvram_exit();
11218 +}
11219 +
11220 +static int __init
11221 +dev_nvram_init(void)
11222 +{
11223 + int order = 0, ret = 0;
11224 + struct page *page, *end;
11225 + unsigned int i;
11226 +
11227 + /* Allocate and reserve memory to mmap() */
11228 + while ((PAGE_SIZE << order) < NVRAM_SPACE)
11229 + order++;
11230 + end = virt_to_page(nvram_buf + (PAGE_SIZE << order) - 1);
11231 + for (page = virt_to_page(nvram_buf); page <= end; page++)
11232 + mem_map_reserve(page);
11233 +
11234 +#ifdef CONFIG_MTD
11235 + /* Find associated MTD device */
11236 + for (i = 0; i < MAX_MTD_DEVICES; i++) {
11237 + nvram_mtd = get_mtd_device(NULL, i);
11238 + if (nvram_mtd) {
11239 + if (!strcmp(nvram_mtd->name, "nvram") &&
11240 + nvram_mtd->size >= NVRAM_SPACE)
11241 + break;
11242 + put_mtd_device(nvram_mtd);
11243 + }
11244 + }
11245 + if (i >= MAX_MTD_DEVICES)
11246 + nvram_mtd = NULL;
11247 +#endif
11248 +
11249 + /* Initialize hash table lock */
11250 + spin_lock_init(&nvram_lock);
11251 +
11252 + /* Initialize commit semaphore */
11253 + init_MUTEX(&nvram_sem);
11254 +
11255 + /* Register char device */
11256 + if ((nvram_major = devfs_register_chrdev(0, "nvram", &dev_nvram_fops)) < 0) {
11257 + ret = nvram_major;
11258 + goto err;
11259 + }
11260 +
11261 + /* Initialize hash table */
11262 + _nvram_init();
11263 +
11264 + /* Create /dev/nvram handle */
11265 + nvram_handle = devfs_register(NULL, "nvram", DEVFS_FL_NONE, nvram_major, 0,
11266 + S_IFCHR | S_IRUSR | S_IWUSR | S_IRGRP, &dev_nvram_fops, NULL);
11267 +
11268 + /* Set the SDRAM NCDL value into NVRAM if not already done */
11269 + if (getintvar(NULL, "sdram_ncdl") == 0) {
11270 + unsigned int ncdl;
11271 + char buf[] = "0x00000000";
11272 +
11273 + if ((ncdl = sb_memc_get_ncdl(sbh))) {
11274 + sprintf(buf, "0x%08x", ncdl);
11275 + nvram_set("sdram_ncdl", buf);
11276 + nvram_commit();
11277 + }
11278 + }
11279 +
11280 + return 0;
11281 +
11282 + err:
11283 + dev_nvram_exit();
11284 + return ret;
11285 +}
11286 +
11287 +module_init(dev_nvram_init);
11288 +module_exit(dev_nvram_exit);
11289 diff -urN linux.old/arch/mips/bcm947xx/pcibios.c linux.dev/arch/mips/bcm947xx/pcibios.c
11290 --- linux.old/arch/mips/bcm947xx/pcibios.c 1970-01-01 01:00:00.000000000 +0100
11291 +++ linux.dev/arch/mips/bcm947xx/pcibios.c 2005-11-07 23:59:38.908750500 +0100
11292 @@ -0,0 +1,355 @@
11293 +/*
11294 + * Low-Level PCI and SB support for BCM47xx (Linux support code)
11295 + *
11296 + * Copyright 2005, Broadcom Corporation
11297 + * All Rights Reserved.
11298 + *
11299 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11300 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11301 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11302 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11303 + *
11304 + * $Id$
11305 + */
11306 +
11307 +#include <linux/config.h>
11308 +#include <linux/types.h>
11309 +#include <linux/kernel.h>
11310 +#include <linux/sched.h>
11311 +#include <linux/pci.h>
11312 +#include <linux/init.h>
11313 +#include <linux/delay.h>
11314 +#include <asm/io.h>
11315 +#include <asm/irq.h>
11316 +#include <asm/paccess.h>
11317 +
11318 +#include <typedefs.h>
11319 +#include <bcmutils.h>
11320 +#include <sbconfig.h>
11321 +#include <sbutils.h>
11322 +#include <sbpci.h>
11323 +#include <pcicfg.h>
11324 +#include <bcmdevs.h>
11325 +#include <bcmnvram.h>
11326 +
11327 +/* Global SB handle */
11328 +extern sb_t *bcm947xx_sbh;
11329 +extern spinlock_t bcm947xx_sbh_lock;
11330 +
11331 +/* Convenience */
11332 +#define sbh bcm947xx_sbh
11333 +#define sbh_lock bcm947xx_sbh_lock
11334 +
11335 +static int
11336 +sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
11337 +{
11338 + unsigned long flags;
11339 + int ret;
11340 +
11341 + spin_lock_irqsave(&sbh_lock, flags);
11342 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11343 + spin_unlock_irqrestore(&sbh_lock, flags);
11344 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11345 +}
11346 +
11347 +static int
11348 +sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
11349 +{
11350 + unsigned long flags;
11351 + int ret;
11352 +
11353 + spin_lock_irqsave(&sbh_lock, flags);
11354 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11355 + spin_unlock_irqrestore(&sbh_lock, flags);
11356 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11357 +}
11358 +
11359 +static int
11360 +sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
11361 +{
11362 + unsigned long flags;
11363 + int ret;
11364 +
11365 + spin_lock_irqsave(&sbh_lock, flags);
11366 + ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, value, sizeof(*value));
11367 + spin_unlock_irqrestore(&sbh_lock, flags);
11368 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11369 +}
11370 +
11371 +static int
11372 +sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
11373 +{
11374 + unsigned long flags;
11375 + int ret;
11376 +
11377 + spin_lock_irqsave(&sbh_lock, flags);
11378 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11379 + spin_unlock_irqrestore(&sbh_lock, flags);
11380 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11381 +}
11382 +
11383 +static int
11384 +sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
11385 +{
11386 + unsigned long flags;
11387 + int ret;
11388 +
11389 + spin_lock_irqsave(&sbh_lock, flags);
11390 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11391 + spin_unlock_irqrestore(&sbh_lock, flags);
11392 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11393 +}
11394 +
11395 +static int
11396 +sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
11397 +{
11398 + unsigned long flags;
11399 + int ret;
11400 +
11401 + spin_lock_irqsave(&sbh_lock, flags);
11402 + ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn), where, &value, sizeof(value));
11403 + spin_unlock_irqrestore(&sbh_lock, flags);
11404 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11405 +}
11406 +
11407 +static struct pci_ops pcibios_ops = {
11408 + sbpci_read_config_byte,
11409 + sbpci_read_config_word,
11410 + sbpci_read_config_dword,
11411 + sbpci_write_config_byte,
11412 + sbpci_write_config_word,
11413 + sbpci_write_config_dword
11414 +};
11415 +
11416 +
11417 +void __init
11418 +pcibios_init(void)
11419 +{
11420 + ulong flags;
11421 +
11422 + if (!(sbh = sb_kattach()))
11423 + panic("sb_kattach failed");
11424 + spin_lock_init(&sbh_lock);
11425 +
11426 + spin_lock_irqsave(&sbh_lock, flags);
11427 + sbpci_init(sbh);
11428 + spin_unlock_irqrestore(&sbh_lock, flags);
11429 +
11430 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11431 +
11432 + mdelay(300); //By Joey for Atheros Card
11433 +
11434 + /* Scan the SB bus */
11435 + pci_scan_bus(0, &pcibios_ops, NULL);
11436 +
11437 +}
11438 +
11439 +char * __init
11440 +pcibios_setup(char *str)
11441 +{
11442 + if (!strncmp(str, "ban=", 4)) {
11443 + sbpci_ban(simple_strtoul(str + 4, NULL, 0));
11444 + return NULL;
11445 + }
11446 +
11447 + return (str);
11448 +}
11449 +
11450 +static u32 pci_iobase = 0x100;
11451 +static u32 pci_membase = SB_PCI_DMA;
11452 +
11453 +void __init
11454 +pcibios_fixup_bus(struct pci_bus *b)
11455 +{
11456 + struct list_head *ln;
11457 + struct pci_dev *d;
11458 + struct resource *res;
11459 + int pos, size;
11460 + u32 *base;
11461 + u8 irq;
11462 +
11463 + printk("PCI: Fixing up bus %d\n", b->number);
11464 +
11465 + /* Fix up SB */
11466 + if (b->number == 0) {
11467 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11468 + d = pci_dev_b(ln);
11469 + /* Fix up interrupt lines */
11470 + pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
11471 + d->irq = irq + 2;
11472 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11473 + }
11474 + }
11475 +
11476 + /* Fix up external PCI */
11477 + else {
11478 + for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
11479 + d = pci_dev_b(ln);
11480 + /* Fix up resource bases */
11481 + for (pos = 0; pos < 6; pos++) {
11482 + res = &d->resource[pos];
11483 + base = (res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase;
11484 + if (res->end) {
11485 + size = res->end - res->start + 1;
11486 + if (*base & (size - 1))
11487 + *base = (*base + size) & ~(size - 1);
11488 + res->start = *base;
11489 + res->end = res->start + size - 1;
11490 + *base += size;
11491 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11492 + }
11493 + /* Fix up PCI bridge BAR0 only */
11494 + if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
11495 + break;
11496 + }
11497 + /* Fix up interrupt lines */
11498 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11499 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11500 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11501 + }
11502 + }
11503 +}
11504 +
11505 +unsigned int
11506 +pcibios_assign_all_busses(void)
11507 +{
11508 + return 1;
11509 +}
11510 +
11511 +void
11512 +pcibios_align_resource(void *data, struct resource *res,
11513 + unsigned long size, unsigned long align)
11514 +{
11515 +}
11516 +
11517 +int
11518 +pcibios_enable_resources(struct pci_dev *dev)
11519 +{
11520 + u16 cmd, old_cmd;
11521 + int idx;
11522 + struct resource *r;
11523 +
11524 + /* External PCI only */
11525 + if (dev->bus->number == 0)
11526 + return 0;
11527 +
11528 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
11529 + old_cmd = cmd;
11530 + for(idx=0; idx<6; idx++) {
11531 + r = &dev->resource[idx];
11532 + if (r->flags & IORESOURCE_IO)
11533 + cmd |= PCI_COMMAND_IO;
11534 + if (r->flags & IORESOURCE_MEM)
11535 + cmd |= PCI_COMMAND_MEMORY;
11536 + }
11537 + if (dev->resource[PCI_ROM_RESOURCE].start)
11538 + cmd |= PCI_COMMAND_MEMORY;
11539 + if (cmd != old_cmd) {
11540 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
11541 + pci_write_config_word(dev, PCI_COMMAND, cmd);
11542 + }
11543 + return 0;
11544 +}
11545 +
11546 +int
11547 +pcibios_enable_device(struct pci_dev *dev, int mask)
11548 +{
11549 + ulong flags;
11550 + uint coreidx;
11551 +
11552 + /* External PCI device enable */
11553 + if (dev->bus->number != 0)
11554 + return pcibios_enable_resources(dev);
11555 +
11556 + /* These cores come out of reset enabled */
11557 + if (dev->device == SB_MIPS ||
11558 + dev->device == SB_MIPS33 ||
11559 + dev->device == SB_EXTIF ||
11560 + dev->device == SB_CC)
11561 + return 0;
11562 +
11563 + spin_lock_irqsave(&sbh_lock, flags);
11564 + coreidx = sb_coreidx(sbh);
11565 + if (!sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)))
11566 + return PCIBIOS_DEVICE_NOT_FOUND;
11567 +
11568 + /*
11569 + * The USB core requires a special bit to be set during core
11570 + * reset to enable host (OHCI) mode. Resetting the SB core in
11571 + * pcibios_enable_device() is a hack for compatibility with
11572 + * vanilla usb-ohci so that it does not have to know about
11573 + * SB. A driver that wants to use the USB core in device mode
11574 + * should know about SB and should reset the bit back to 0
11575 + * after calling pcibios_enable_device().
11576 + */
11577 + if (sb_coreid(sbh) == SB_USB) {
11578 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11579 + sb_core_reset(sbh, 1 << 29);
11580 + } else
11581 + sb_core_reset(sbh, 0);
11582 +
11583 + sb_setcoreidx(sbh, coreidx);
11584 + spin_unlock_irqrestore(&sbh_lock, flags);
11585 +
11586 + return 0;
11587 +}
11588 +
11589 +void
11590 +pcibios_update_resource(struct pci_dev *dev, struct resource *root,
11591 + struct resource *res, int resource)
11592 +{
11593 + unsigned long where, size;
11594 + u32 reg;
11595 +
11596 + /* External PCI only */
11597 + if (dev->bus->number == 0)
11598 + return;
11599 +
11600 + where = PCI_BASE_ADDRESS_0 + (resource * 4);
11601 + size = res->end - res->start;
11602 + pci_read_config_dword(dev, where, &reg);
11603 + reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
11604 + pci_write_config_dword(dev, where, reg);
11605 +}
11606 +
11607 +static void __init
11608 +quirk_sbpci_bridge(struct pci_dev *dev)
11609 +{
11610 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11611 + return;
11612 +
11613 + printk("PCI: Fixing up bridge\n");
11614 +
11615 + /* Enable PCI bridge bus mastering and memory space */
11616 + pci_set_master(dev);
11617 + pcibios_enable_resources(dev);
11618 +
11619 + /* Enable PCI bridge BAR1 prefetch and burst */
11620 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11621 +}
11622 +
11623 +struct pci_fixup pcibios_fixups[] = {
11624 + { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
11625 + { 0 }
11626 +};
11627 +
11628 +/*
11629 + * If we set up a device for bus mastering, we need to check the latency
11630 + * timer as certain crappy BIOSes forget to set it properly.
11631 + */
11632 +unsigned int pcibios_max_latency = 255;
11633 +
11634 +void pcibios_set_master(struct pci_dev *dev)
11635 +{
11636 + u8 lat;
11637 + pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
11638 + if (lat < 16)
11639 + lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
11640 + else if (lat > pcibios_max_latency)
11641 + lat = pcibios_max_latency;
11642 + else
11643 + return;
11644 + printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
11645 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
11646 +}
11647 +
11648 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11649 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11650 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-11-07 21:57:07.885588250 +0100
11651 @@ -0,0 +1,41 @@
11652 +/*
11653 + * Early initialization code for BCM94710 boards
11654 + *
11655 + * Copyright 2004, Broadcom Corporation
11656 + * All Rights Reserved.
11657 + *
11658 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11659 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11660 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11661 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11662 + *
11663 + * $Id: prom.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
11664 + */
11665 +
11666 +#include <linux/config.h>
11667 +#include <linux/init.h>
11668 +#include <linux/kernel.h>
11669 +#include <linux/types.h>
11670 +#include <asm/bootinfo.h>
11671 +
11672 +void __init
11673 +prom_init(int argc, const char **argv)
11674 +{
11675 + unsigned long mem;
11676 +
11677 + mips_machgroup = MACH_GROUP_BRCM;
11678 + mips_machtype = MACH_BCM947XX;
11679 +
11680 + /* Figure out memory size by finding aliases */
11681 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11682 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11683 + *(unsigned long *)(prom_init))
11684 + break;
11685 + }
11686 + add_memory_region(0, mem, BOOT_MEM_RAM);
11687 +}
11688 +
11689 +void __init
11690 +prom_free_prom_memory(void)
11691 +{
11692 +}
11693 diff -urN linux.old/arch/mips/bcm947xx/sbmips.c linux.dev/arch/mips/bcm947xx/sbmips.c
11694 --- linux.old/arch/mips/bcm947xx/sbmips.c 1970-01-01 01:00:00.000000000 +0100
11695 +++ linux.dev/arch/mips/bcm947xx/sbmips.c 2005-11-07 23:55:45.682174750 +0100
11696 @@ -0,0 +1,1038 @@
11697 +/*
11698 + * BCM47XX Sonics SiliconBackplane MIPS core routines
11699 + *
11700 + * Copyright 2005, Broadcom Corporation
11701 + * All Rights Reserved.
11702 + *
11703 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
11704 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
11705 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11706 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11707 + *
11708 + * $Id$
11709 + */
11710 +
11711 +#include <typedefs.h>
11712 +#include <osl.h>
11713 +#include <sbutils.h>
11714 +#include <bcmdevs.h>
11715 +#include <bcmnvram.h>
11716 +#include <bcmutils.h>
11717 +#include <hndmips.h>
11718 +#include <sbconfig.h>
11719 +#include <sbextif.h>
11720 +#include <sbchipc.h>
11721 +#include <sbmemc.h>
11722 +#include <mipsinc.h>
11723 +#include <sbutils.h>
11724 +
11725 +/*
11726 + * Returns TRUE if an external UART exists at the given base
11727 + * register.
11728 + */
11729 +static bool
11730 +BCMINITFN(serial_exists)(uint8 *regs)
11731 +{
11732 + uint8 save_mcr, status1;
11733 +
11734 + save_mcr = R_REG(&regs[UART_MCR]);
11735 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
11736 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
11737 + W_REG(&regs[UART_MCR], save_mcr);
11738 +
11739 + return (status1 == 0x90);
11740 +}
11741 +
11742 +/*
11743 + * Initializes UART access. The callback function will be called once
11744 + * per found UART.
11745 + */
11746 +void
11747 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
11748 +{
11749 + void *regs;
11750 + ulong base;
11751 + uint irq;
11752 + int i, n;
11753 +
11754 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
11755 + extifregs_t *eir = (extifregs_t *) regs;
11756 + sbconfig_t *sb;
11757 +
11758 + /* Determine external UART register base */
11759 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
11760 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
11761 +
11762 + /* Determine IRQ */
11763 + irq = sb_irq(sbh);
11764 +
11765 + /* Disable GPIO interrupt initially */
11766 + W_REG(&eir->gpiointpolarity, 0);
11767 + W_REG(&eir->gpiointmask, 0);
11768 +
11769 + /* Search for external UARTs */
11770 + n = 2;
11771 + for (i = 0; i < 2; i++) {
11772 + regs = (void *) REG_MAP(base + (i * 8), 8);
11773 + if (BCMINIT(serial_exists)(regs)) {
11774 + /* Set GPIO 1 to be the external UART IRQ */
11775 + W_REG(&eir->gpiointmask, 2);
11776 + if (add)
11777 + add(regs, irq, 13500000, 0);
11778 + }
11779 + }
11780 +
11781 + /* Add internal UART if enabled */
11782 + if (R_REG(&eir->corecontrol) & CC_UE)
11783 + if (add)
11784 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
11785 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
11786 + chipcregs_t *cc = (chipcregs_t *) regs;
11787 + uint32 rev, cap, pll, baud_base, div;
11788 +
11789 + /* Determine core revision and capabilities */
11790 + rev = sb_corerev(sbh);
11791 + cap = R_REG(&cc->capabilities);
11792 + pll = cap & CAP_PLL_MASK;
11793 +
11794 + /* Determine IRQ */
11795 + irq = sb_irq(sbh);
11796 +
11797 + if (pll == PLL_TYPE1) {
11798 + /* PLL clock */
11799 + baud_base = sb_clock_rate(pll,
11800 + R_REG(&cc->clockcontrol_n),
11801 + R_REG(&cc->clockcontrol_m2));
11802 + div = 1;
11803 + } else {
11804 + if (rev >= 11) {
11805 + /* Fixed ALP clock */
11806 + baud_base = 20000000;
11807 + div = 1;
11808 + /* Set the override bit so we don't divide it */
11809 + W_REG(&cc->corecontrol, CC_UARTCLKO);
11810 + } else if (rev >= 3) {
11811 + /* Internal backplane clock */
11812 + baud_base = sb_clock(sbh);
11813 + div = 2; /* Minimum divisor */
11814 + W_REG(&cc->clkdiv,
11815 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
11816 + } else {
11817 + /* Fixed internal backplane clock */
11818 + baud_base = 88000000;
11819 + div = 48;
11820 + }
11821 +
11822 + /* Clock source depends on strapping if UartClkOverride is unset */
11823 + if ((rev > 0) &&
11824 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
11825 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
11826 + /* Internal divided backplane clock */
11827 + baud_base /= div;
11828 + } else {
11829 + /* Assume external clock of 1.8432 MHz */
11830 + baud_base = 1843200;
11831 + }
11832 + }
11833 + }
11834 +
11835 + /* Add internal UARTs */
11836 + n = cap & CAP_UARTS_MASK;
11837 + for (i = 0; i < n; i++) {
11838 + /* Register offset changed after revision 0 */
11839 + if (rev)
11840 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
11841 + else
11842 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
11843 +
11844 + if (add)
11845 + add(regs, irq, baud_base, 0);
11846 + }
11847 + }
11848 +}
11849 +
11850 +/*
11851 + * Initialize jtag master and return handle for
11852 + * jtag_rwreg. Returns NULL on failure.
11853 + */
11854 +void *
11855 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
11856 +{
11857 + void *regs;
11858 +
11859 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
11860 + chipcregs_t *cc = (chipcregs_t *) regs;
11861 + uint32 tmp;
11862 +
11863 + /*
11864 + * Determine jtagm availability from
11865 + * core revision and capabilities.
11866 + */
11867 + tmp = sb_corerev(sbh);
11868 + /*
11869 + * Corerev 10 has jtagm, but the only chip
11870 + * with it does not have a mips, and
11871 + * the layout of the jtagcmd register is
11872 + * different. We'll only accept >= 11.
11873 + */
11874 + if (tmp < 11)
11875 + return (NULL);
11876 +
11877 + tmp = R_REG(&cc->capabilities);
11878 + if ((tmp & CAP_JTAGP) == 0)
11879 + return (NULL);
11880 +
11881 + /* Set clock divider if requested */
11882 + if (clkd != 0) {
11883 + tmp = R_REG(&cc->clkdiv);
11884 + tmp = (tmp & ~CLKD_JTAG) |
11885 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
11886 + W_REG(&cc->clkdiv, tmp);
11887 + }
11888 +
11889 + /* Enable jtagm */
11890 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
11891 + W_REG(&cc->jtagctrl, tmp);
11892 + }
11893 +
11894 + return (regs);
11895 +}
11896 +
11897 +void
11898 +sb_jtagm_disable(void *h)
11899 +{
11900 + chipcregs_t *cc = (chipcregs_t *)h;
11901 +
11902 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
11903 +}
11904 +
11905 +/*
11906 + * Read/write a jtag register. Assumes a target with
11907 + * 8 bit IR and 32 bit DR.
11908 + */
11909 +#define IRWIDTH 8
11910 +#define DRWIDTH 32
11911 +uint32
11912 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
11913 +{
11914 + chipcregs_t *cc = (chipcregs_t *) h;
11915 + uint32 tmp;
11916 +
11917 + W_REG(&cc->jtagir, ir);
11918 + W_REG(&cc->jtagdr, dr);
11919 + tmp = JCMD_START | JCMD_ACC_IRDR |
11920 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
11921 + (DRWIDTH - 1);
11922 + W_REG(&cc->jtagcmd, tmp);
11923 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
11924 + /* OSL_DELAY(1); */
11925 + }
11926 +
11927 + tmp = R_REG(&cc->jtagdr);
11928 + return (tmp);
11929 +}
11930 +
11931 +/* Returns the SB interrupt flag of the current core. */
11932 +uint32
11933 +sb_flag(sb_t *sbh)
11934 +{
11935 + void *regs;
11936 + sbconfig_t *sb;
11937 +
11938 + regs = sb_coreregs(sbh);
11939 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11940 +
11941 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
11942 +}
11943 +
11944 +static const uint32 sbips_int_mask[] = {
11945 + 0,
11946 + SBIPS_INT1_MASK,
11947 + SBIPS_INT2_MASK,
11948 + SBIPS_INT3_MASK,
11949 + SBIPS_INT4_MASK
11950 +};
11951 +
11952 +static const uint32 sbips_int_shift[] = {
11953 + 0,
11954 + 0,
11955 + SBIPS_INT2_SHIFT,
11956 + SBIPS_INT3_SHIFT,
11957 + SBIPS_INT4_SHIFT
11958 +};
11959 +
11960 +/*
11961 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
11962 + * 0 is returned.
11963 + */
11964 +uint
11965 +sb_irq(sb_t *sbh)
11966 +{
11967 + uint idx;
11968 + void *regs;
11969 + sbconfig_t *sb;
11970 + uint32 flag, sbipsflag;
11971 + uint irq = 0;
11972 +
11973 + flag = sb_flag(sbh);
11974 +
11975 + idx = sb_coreidx(sbh);
11976 +
11977 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
11978 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
11979 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
11980 +
11981 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
11982 + sbipsflag = R_REG(&sb->sbipsflag);
11983 + for (irq = 1; irq <= 4; irq++) {
11984 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
11985 + break;
11986 + }
11987 + if (irq == 5)
11988 + irq = 0;
11989 + }
11990 +
11991 + sb_setcoreidx(sbh, idx);
11992 +
11993 + return irq;
11994 +}
11995 +
11996 +/* Clears the specified MIPS IRQ. */
11997 +static void
11998 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
11999 +{
12000 + void *regs;
12001 + sbconfig_t *sb;
12002 +
12003 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
12004 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
12005 + ASSERT(regs);
12006 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12007 +
12008 + if (irq == 0)
12009 + W_REG(&sb->sbintvec, 0);
12010 + else
12011 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
12012 +}
12013 +
12014 +/*
12015 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
12016 + * IRQ 0 may be assigned more than once.
12017 + */
12018 +static void
12019 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
12020 +{
12021 + void *regs;
12022 + sbconfig_t *sb;
12023 + uint32 flag;
12024 +
12025 + regs = sb_setcore(sbh, coreid, coreunit);
12026 + ASSERT(regs);
12027 + flag = sb_flag(sbh);
12028 +
12029 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
12030 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
12031 + ASSERT(regs);
12032 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12033 +
12034 + if (irq == 0)
12035 + OR_REG(&sb->sbintvec, 1 << flag);
12036 + else {
12037 + flag <<= sbips_int_shift[irq];
12038 + ASSERT(!(flag & ~sbips_int_mask[irq]));
12039 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
12040 + W_REG(&sb->sbipsflag, flag);
12041 + }
12042 +}
12043 +
12044 +/*
12045 + * Initializes clocks and interrupts. SB and NVRAM access must be
12046 + * initialized prior to calling.
12047 + */
12048 +void
12049 +BCMINITFN(sb_mips_init)(sb_t *sbh)
12050 +{
12051 + ulong hz, ns, tmp;
12052 + extifregs_t *eir;
12053 + chipcregs_t *cc;
12054 + char *value;
12055 + uint irq;
12056 +
12057 + /* Figure out current SB clock speed */
12058 + if ((hz = sb_clock(sbh)) == 0)
12059 + hz = 100000000;
12060 + ns = 1000000000 / hz;
12061 +
12062 + /* Setup external interface timing */
12063 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
12064 + /* Initialize extif so we can get to the LEDs and external UART */
12065 + W_REG(&eir->prog_config, CF_EN);
12066 +
12067 + /* Set timing for the flash */
12068 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12069 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
12070 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
12071 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
12072 +
12073 + /* Set programmable interface timing for external uart */
12074 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12075 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
12076 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
12077 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
12078 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
12079 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
12080 + /* Set timing for the flash */
12081 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
12082 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
12083 + tmp |= CEIL(120, ns); /* W0 = 120nS */
12084 +
12085 + // Added by Chen-I for 5365
12086 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12087 + {
12088 + W_REG(&cc->flash_waitcount, tmp);
12089 + W_REG(&cc->pcmcia_memwait, tmp);
12090 + }
12091 + else
12092 + {
12093 + if (sb_corerev(sbh) < 9)
12094 + W_REG(&cc->flash_waitcount, tmp);
12095 +
12096 + if ((sb_corerev(sbh) < 9) ||
12097 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
12098 + W_REG(&cc->pcmcia_memwait, tmp);
12099 + }
12100 + }
12101 + }
12102 +
12103 + /* Chip specific initialization */
12104 + switch (BCMINIT(sb_chip)(sbh)) {
12105 + case BCM4710_DEVICE_ID:
12106 + /* Clear interrupt map */
12107 + for (irq = 0; irq <= 4; irq++)
12108 + BCMINIT(sb_clearirq)(sbh, irq);
12109 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
12110 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
12111 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
12112 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
12113 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
12114 + ASSERT(eir);
12115 + value = BCMINIT(nvram_get)("et0phyaddr");
12116 + if (value && !strcmp(value, "31")) {
12117 + /* Enable internal UART */
12118 + W_REG(&eir->corecontrol, CC_UE);
12119 + /* Give USB its own interrupt */
12120 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
12121 + } else {
12122 + /* Disable internal UART */
12123 + W_REG(&eir->corecontrol, 0);
12124 + /* Give Ethernet its own interrupt */
12125 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
12126 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
12127 + }
12128 + break;
12129 + case BCM5350_DEVICE_ID:
12130 + /* Clear interrupt map */
12131 + for (irq = 0; irq <= 4; irq++)
12132 + BCMINIT(sb_clearirq)(sbh, irq);
12133 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
12134 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
12135 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
12136 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
12137 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
12138 + break;
12139 + }
12140 +}
12141 +
12142 +uint32
12143 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
12144 +{
12145 + extifregs_t *eir;
12146 + chipcregs_t *cc;
12147 + uint32 n, m;
12148 + uint idx;
12149 + uint32 pll_type, rate = 0;
12150 +
12151 + /* get index of the current core */
12152 + idx = sb_coreidx(sbh);
12153 + pll_type = PLL_TYPE1;
12154 +
12155 + /* switch to extif or chipc core */
12156 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12157 + n = R_REG(&eir->clockcontrol_n);
12158 + m = R_REG(&eir->clockcontrol_sb);
12159 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12160 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12161 + n = R_REG(&cc->clockcontrol_n);
12162 + if ((pll_type == PLL_TYPE2) ||
12163 + (pll_type == PLL_TYPE4) ||
12164 + (pll_type == PLL_TYPE6) ||
12165 + (pll_type == PLL_TYPE7))
12166 + m = R_REG(&cc->clockcontrol_mips);
12167 + else if (pll_type == PLL_TYPE5) {
12168 + rate = 200000000;
12169 + goto out;
12170 + }
12171 + else if (pll_type == PLL_TYPE3) {
12172 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
12173 + rate = 200000000;
12174 + goto out;
12175 + } else
12176 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
12177 + } else
12178 + m = R_REG(&cc->clockcontrol_sb);
12179 + } else
12180 + goto out;
12181 +
12182 + // Added by Chen-I for 5365
12183 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
12184 + rate = 100000000;
12185 + else
12186 + /* calculate rate */
12187 + rate = sb_clock_rate(pll_type, n, m);
12188 +
12189 + if (pll_type == PLL_TYPE6)
12190 + rate = SB2MIPS_T6(rate);
12191 +
12192 +out:
12193 + /* switch back to previous core */
12194 + sb_setcoreidx(sbh, idx);
12195 +
12196 + return rate;
12197 +}
12198 +
12199 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
12200 +
12201 +static void
12202 +BCMINITFN(handler)(void)
12203 +{
12204 + /* Step 11 */
12205 + __asm__ (
12206 + ".set\tmips32\n\t"
12207 + "ssnop\n\t"
12208 + "ssnop\n\t"
12209 + /* Disable interrupts */
12210 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
12211 + "mfc0 $15, $12\n\t"
12212 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
12213 + "li $14, -31746\n\t"
12214 + "and $15, $15, $14\n\t"
12215 + "mtc0 $15, $12\n\t"
12216 + "eret\n\t"
12217 + "nop\n\t"
12218 + "nop\n\t"
12219 + ".set\tmips0"
12220 + );
12221 +}
12222 +
12223 +/* The following MUST come right after handler() */
12224 +static void
12225 +BCMINITFN(afterhandler)(void)
12226 +{
12227 +}
12228 +
12229 +/*
12230 + * Set the MIPS, backplane and PCI clocks as closely as possible.
12231 + */
12232 +bool
12233 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
12234 +{
12235 + extifregs_t *eir = NULL;
12236 + chipcregs_t *cc = NULL;
12237 + mipsregs_t *mipsr = NULL;
12238 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
12239 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
12240 + uint32 pll_type, sync_mode;
12241 + uint ic_size, ic_lsize;
12242 + uint idx, i;
12243 + typedef struct {
12244 + uint32 mipsclock;
12245 + uint16 n;
12246 + uint32 sb;
12247 + uint32 pci33;
12248 + uint32 pci25;
12249 + } n3m_table_t;
12250 + static n3m_table_t BCMINITDATA(type1_table)[] = {
12251 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
12252 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
12253 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
12254 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
12255 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
12256 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
12257 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
12258 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
12259 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
12260 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
12261 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
12262 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
12263 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
12264 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
12265 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
12266 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
12267 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
12268 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
12269 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
12270 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
12271 + };
12272 + typedef struct {
12273 + uint32 mipsclock;
12274 + uint16 n;
12275 + uint32 m2; /* that is the clockcontrol_m2 */
12276 + } type3_table_t;
12277 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
12278 + { 150000000, 0x311, 0x4020005 },
12279 + { 200000000, 0x311, 0x4020003 },
12280 + };
12281 + typedef struct {
12282 + uint32 mipsclock;
12283 + uint32 sbclock;
12284 + uint16 n;
12285 + uint32 sb;
12286 + uint32 pci33;
12287 + uint32 m2;
12288 + uint32 m3;
12289 + uint32 ratio_cfg;
12290 + uint32 ratio_parm;
12291 + } n4m_table_t;
12292 +
12293 + static n4m_table_t BCMINITDATA(type2_table)[] = {
12294 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12295 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12296 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
12297 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12298 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12299 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12300 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12301 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12302 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
12303 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
12304 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12305 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12306 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12307 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12308 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
12309 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
12310 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
12311 + };
12312 +
12313 + static n4m_table_t BCMINITDATA(type4_table)[] = {
12314 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12315 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12316 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12317 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12318 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12319 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12320 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12321 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12322 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
12323 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12324 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
12325 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
12326 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
12327 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12328 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
12329 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12330 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12331 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
12332 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
12333 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
12334 + };
12335 +
12336 + static n4m_table_t BCMINITDATA(type7_table)[] = {
12337 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12338 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
12339 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12340 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
12341 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
12342 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12343 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12344 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12345 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12346 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12347 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
12348 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
12349 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
12350 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
12351 + };
12352 +
12353 + ulong start, end, dst;
12354 + bool ret = FALSE;
12355 +
12356 + /* get index of the current core */
12357 + idx = sb_coreidx(sbh);
12358 + clockcontrol_m2 = NULL;
12359 +
12360 + /* switch to extif or chipc core */
12361 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
12362 + pll_type = PLL_TYPE1;
12363 + clockcontrol_n = &eir->clockcontrol_n;
12364 + clockcontrol_sb = &eir->clockcontrol_sb;
12365 + clockcontrol_pci = &eir->clockcontrol_pci;
12366 + clockcontrol_m2 = &cc->clockcontrol_m2;
12367 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
12368 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
12369 + if (pll_type == PLL_TYPE6) {
12370 + clockcontrol_n = NULL;
12371 + clockcontrol_sb = NULL;
12372 + clockcontrol_pci = NULL;
12373 + } else {
12374 + clockcontrol_n = &cc->clockcontrol_n;
12375 + clockcontrol_sb = &cc->clockcontrol_sb;
12376 + clockcontrol_pci = &cc->clockcontrol_pci;
12377 + clockcontrol_m2 = &cc->clockcontrol_m2;
12378 + }
12379 + } else
12380 + goto done;
12381 +
12382 + if (pll_type == PLL_TYPE6) {
12383 + /* Silence compilers */
12384 + orig_n = orig_sb = orig_pci = 0;
12385 + } else {
12386 + /* Store the current clock register values */
12387 + orig_n = R_REG(clockcontrol_n);
12388 + orig_sb = R_REG(clockcontrol_sb);
12389 + orig_pci = R_REG(clockcontrol_pci);
12390 + }
12391 +
12392 + if (pll_type == PLL_TYPE1) {
12393 + /* Keep the current PCI clock if not specified */
12394 + if (pciclock == 0) {
12395 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
12396 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
12397 + }
12398 +
12399 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12400 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
12401 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
12402 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
12403 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
12404 + break;
12405 + }
12406 + if (i == 0) {
12407 + ret = FALSE;
12408 + goto done;
12409 + } else {
12410 + ret = TRUE;
12411 + i--;
12412 + }
12413 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
12414 +
12415 + /* No PLL change */
12416 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
12417 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
12418 + (orig_pci == BCMINIT(type1_table)[i].pci33))
12419 + goto done;
12420 +
12421 + /* Set the PLL controls */
12422 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
12423 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
12424 + if (pciclock == 25000000)
12425 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
12426 + else
12427 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
12428 +
12429 + /* Reset */
12430 + sb_watchdog(sbh, 1);
12431 +
12432 + while (1);
12433 + } else if ((pll_type == PLL_TYPE3) &&
12434 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
12435 + /* 5350 */
12436 + /* Search for the closest MIPS clock less than or equal to a preferred value */
12437 +
12438 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
12439 + if (type3_table[i].mipsclock > mipsclock)
12440 + break;
12441 + }
12442 + if (i == 0) {
12443 + ret = FALSE;
12444 + goto done;
12445 + } else {
12446 + ret = TRUE;
12447 + i--;
12448 + }
12449 + ASSERT(type3_table[i].mipsclock <= mipsclock);
12450 +
12451 + /* No PLL change */
12452 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12453 + if ((orig_n == type3_table[i].n) &&
12454 + (orig_m2 == type3_table[i].m2)) {
12455 + goto done;
12456 + }
12457 +
12458 + /* Set the PLL controls */
12459 + W_REG(clockcontrol_n, type3_table[i].n);
12460 + W_REG(clockcontrol_m2, type3_table[i].m2);
12461 +
12462 + /* Reset */
12463 + sb_watchdog(sbh, 1);
12464 + while (1);
12465 + } else if ((pll_type == PLL_TYPE2) ||
12466 + (pll_type == PLL_TYPE4) ||
12467 + (pll_type == PLL_TYPE6) ||
12468 + (pll_type == PLL_TYPE7)) {
12469 + n4m_table_t *table = NULL, *te;
12470 + uint tabsz = 0;
12471 +
12472 + ASSERT(cc);
12473 +
12474 + orig_mips = R_REG(&cc->clockcontrol_mips);
12475 +
12476 + if (pll_type == PLL_TYPE6) {
12477 + uint32 new_mips = 0;
12478 +
12479 + ret = TRUE;
12480 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
12481 + new_mips = CC_T6_MMASK;
12482 +
12483 + if (orig_mips == new_mips)
12484 + goto done;
12485 +
12486 + W_REG(&cc->clockcontrol_mips, new_mips);
12487 + goto end_fill;
12488 + }
12489 +
12490 + if (pll_type == PLL_TYPE2) {
12491 + table = BCMINIT(type2_table);
12492 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
12493 + } else if (pll_type == PLL_TYPE4) {
12494 + table = BCMINIT(type4_table);
12495 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
12496 + } else if (pll_type == PLL_TYPE7) {
12497 + table = BCMINIT(type7_table);
12498 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
12499 + } else
12500 + ASSERT("No table for plltype" == NULL);
12501 +
12502 + /* Store the current clock register values */
12503 + orig_m2 = R_REG(&cc->clockcontrol_m2);
12504 + orig_ratio_parm = 0;
12505 + orig_ratio_cfg = 0;
12506 +
12507 + /* Look up current ratio */
12508 + for (i = 0; i < tabsz; i++) {
12509 + if ((orig_n == table[i].n) &&
12510 + (orig_sb == table[i].sb) &&
12511 + (orig_pci == table[i].pci33) &&
12512 + (orig_m2 == table[i].m2) &&
12513 + (orig_mips == table[i].m3)) {
12514 + orig_ratio_parm = table[i].ratio_parm;
12515 + orig_ratio_cfg = table[i].ratio_cfg;
12516 + break;
12517 + }
12518 + }
12519 +
12520 + /* Search for the closest MIPS clock greater or equal to a preferred value */
12521 + for (i = 0; i < tabsz; i++) {
12522 + ASSERT(table[i].mipsclock ==
12523 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
12524 + if ((mipsclock <= table[i].mipsclock) &&
12525 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
12526 + break;
12527 + }
12528 + if (i == tabsz) {
12529 + ret = FALSE;
12530 + goto done;
12531 + } else {
12532 + te = &table[i];
12533 + ret = TRUE;
12534 + }
12535 +
12536 + /* No PLL change */
12537 + if ((orig_n == te->n) &&
12538 + (orig_sb == te->sb) &&
12539 + (orig_pci == te->pci33) &&
12540 + (orig_m2 == te->m2) &&
12541 + (orig_mips == te->m3))
12542 + goto done;
12543 +
12544 + /* Set the PLL controls */
12545 + W_REG(clockcontrol_n, te->n);
12546 + W_REG(clockcontrol_sb, te->sb);
12547 + W_REG(clockcontrol_pci, te->pci33);
12548 + W_REG(&cc->clockcontrol_m2, te->m2);
12549 + W_REG(&cc->clockcontrol_mips, te->m3);
12550 +
12551 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
12552 + if ((pll_type == PLL_TYPE7) &&
12553 + (te->sb != te->m2) &&
12554 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
12555 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
12556 +
12557 + /* No ratio change */
12558 + if (orig_ratio_parm == te->ratio_parm)
12559 + goto end_fill;
12560 +
12561 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
12562 +
12563 + /* Preload the code into the cache */
12564 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
12565 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
12566 + while (start < end) {
12567 + cache_op(start, Fill_I);
12568 + start += ic_lsize;
12569 + }
12570 +
12571 + /* Copy the handler */
12572 + start = (ulong) &BCMINIT(handler);
12573 + end = (ulong) &BCMINIT(afterhandler);
12574 + dst = KSEG1ADDR(0x180);
12575 + for (i = 0; i < (end - start); i += 4)
12576 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
12577 +
12578 + /* Preload handler into the cache one line at a time */
12579 + for (i = 0; i < (end - start); i += 4)
12580 + cache_op(dst + i, Fill_I);
12581 +
12582 + /* Clear BEV bit */
12583 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
12584 +
12585 + /* Enable interrupts */
12586 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
12587 +
12588 + /* Enable MIPS timer interrupt */
12589 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
12590 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
12591 + ASSERT(mipsr);
12592 + W_REG(&mipsr->intmask, 1);
12593 +
12594 + start_fill:
12595 + /* step 1, set clock ratios */
12596 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
12597 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
12598 +
12599 + /* step 2: program timer intr */
12600 + W_REG(&mipsr->timer, 100);
12601 + (void) R_REG(&mipsr->timer);
12602 +
12603 + /* step 3, switch to async */
12604 + sync_mode = MFC0(C0_BROADCOM, 4);
12605 + MTC0(C0_BROADCOM, 4, 1 << 22);
12606 +
12607 + /* step 4, set cfg active */
12608 + MTC0(C0_BROADCOM, 2, 0x9);
12609 +
12610 +
12611 + /* steps 5 & 6 */
12612 + __asm__ __volatile__ (
12613 + ".set\tmips3\n\t"
12614 + "wait\n\t"
12615 + ".set\tmips0"
12616 + );
12617 +
12618 + /* step 7, clear cfg_active */
12619 + MTC0(C0_BROADCOM, 2, 0);
12620 +
12621 + /* Additional Step: set back to orig sync mode */
12622 + MTC0(C0_BROADCOM, 4, sync_mode);
12623 +
12624 + /* step 8, fake soft reset */
12625 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
12626 +
12627 + end_fill:
12628 + /* step 9 set watchdog timer */
12629 + sb_watchdog(sbh, 20);
12630 + (void) R_REG(&cc->chipid);
12631 +
12632 + /* step 11 */
12633 + __asm__ __volatile__ (
12634 + ".set\tmips3\n\t"
12635 + "sync\n\t"
12636 + "wait\n\t"
12637 + ".set\tmips0"
12638 + );
12639 + while (1);
12640 + }
12641 +
12642 +done:
12643 + /* switch back to previous core */
12644 + sb_setcoreidx(sbh, idx);
12645 +
12646 + return ret;
12647 +}
12648 +
12649 +/*
12650 + * This also must be run from the cache on 47xx
12651 + * so there are no mips core BIU ops in progress
12652 + * when the PFC is enabled.
12653 + */
12654 +
12655 +static void
12656 +BCMINITFN(_enable_pfc)(uint32 mode)
12657 +{
12658 + /* write range */
12659 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
12660 +
12661 + /* enable */
12662 + *(volatile uint32 *)PFC_CR0 = mode;
12663 +}
12664 +
12665 +void
12666 +BCMINITFN(enable_pfc)(uint32 mode)
12667 +{
12668 + ulong start, end;
12669 + int i;
12670 +
12671 + /* If auto then choose the correct mode for this
12672 + platform, currently we only ever select one mode */
12673 + if (mode == PFC_AUTO)
12674 + mode = PFC_INST;
12675 +
12676 + /* enable prefetch cache if available */
12677 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
12678 + start = (ulong) &BCMINIT(_enable_pfc);
12679 + end = (ulong) &BCMINIT(enable_pfc);
12680 +
12681 + /* Preload handler into the cache one line at a time */
12682 + for (i = 0; i < (end - start); i += 4)
12683 + cache_op(start + i, Fill_I);
12684 +
12685 + BCMINIT(_enable_pfc)(mode);
12686 + }
12687 +}
12688 +
12689 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
12690 +uint32
12691 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
12692 +{
12693 + sbmemcregs_t *memc;
12694 + uint32 ret = 0;
12695 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
12696 + uint idx, rev;
12697 +
12698 + idx = sb_coreidx(sbh);
12699 +
12700 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
12701 + if (memc == 0)
12702 + goto out;
12703 +
12704 + rev = sb_corerev(sbh);
12705 +
12706 + config = R_REG(&memc->config);
12707 + wr = R_REG(&memc->wrncdlcor);
12708 + rd = R_REG(&memc->rdncdlcor);
12709 + misc = R_REG(&memc->miscdlyctl);
12710 + dqsg = R_REG(&memc->dqsgatencdl);
12711 +
12712 + rd &= MEMC_RDNCDLCOR_RD_MASK;
12713 + wr &= MEMC_WRNCDLCOR_WR_MASK;
12714 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
12715 +
12716 + if (config & MEMC_CONFIG_DDR) {
12717 + ret = (wr << 16) | (rd << 8) | dqsg;
12718 + } else {
12719 + if (rev > 0)
12720 + cd = rd;
12721 + else
12722 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
12723 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
12724 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
12725 + ret = (sm << 16) | (sd << 8) | cd;
12726 + }
12727 +
12728 +out:
12729 + /* switch back to previous core */
12730 + sb_setcoreidx(sbh, idx);
12731 +
12732 + return ret;
12733 +}
12734 +
12735 diff -urN linux.old/arch/mips/bcm947xx/sbpci.c linux.dev/arch/mips/bcm947xx/sbpci.c
12736 --- linux.old/arch/mips/bcm947xx/sbpci.c 1970-01-01 01:00:00.000000000 +0100
12737 +++ linux.dev/arch/mips/bcm947xx/sbpci.c 2005-11-07 23:53:20.981131500 +0100
12738 @@ -0,0 +1,588 @@
12739 +/*
12740 + * Low-Level PCI and SB support for BCM47xx
12741 + *
12742 + * Copyright 2005, Broadcom Corporation
12743 + * All Rights Reserved.
12744 + *
12745 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
12746 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
12747 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
12748 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12749 + *
12750 + * $Id$
12751 + */
12752 +
12753 +#include <typedefs.h>
12754 +#include <pcicfg.h>
12755 +#include <bcmdevs.h>
12756 +#include <sbconfig.h>
12757 +#include <osl.h>
12758 +#include <sbutils.h>
12759 +#include <sbpci.h>
12760 +#include <bcmendian.h>
12761 +#include <bcmutils.h>
12762 +#include <bcmnvram.h>
12763 +#include <hndmips.h>
12764 +
12765 +/* Can free sbpci_init() memory after boot */
12766 +#ifndef linux
12767 +#define __init
12768 +#endif
12769 +
12770 +/* Emulated configuration space */
12771 +static pci_config_regs sb_config_regs[SB_MAXCORES];
12772 +
12773 +/* Banned cores */
12774 +static uint16 pci_ban[32] = { 0 };
12775 +static uint pci_banned = 0;
12776 +
12777 +/* CardBus mode */
12778 +static bool cardbus = FALSE;
12779 +
12780 +/* Disable PCI host core */
12781 +static bool pci_disabled = FALSE;
12782 +
12783 +/*
12784 + * Functions for accessing external PCI configuration space
12785 + */
12786 +
12787 +/* Assume one-hot slot wiring */
12788 +#define PCI_SLOT_MAX 16
12789 +
12790 +static uint32
12791 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
12792 +{
12793 + uint coreidx;
12794 + sbpciregs_t *regs;
12795 + uint32 addr = 0;
12796 +
12797 + /* CardBusMode supports only one device */
12798 + if (cardbus && dev > 1)
12799 + return 0;
12800 +
12801 + coreidx = sb_coreidx(sbh);
12802 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
12803 +
12804 + /* Type 0 transaction */
12805 + if (bus == 1) {
12806 + /* Skip unwired slots */
12807 + if (dev < PCI_SLOT_MAX) {
12808 + /* Slide the PCI window to the appropriate slot */
12809 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
12810 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
12811 + (func << 8) | (off & ~3);
12812 + }
12813 + }
12814 +
12815 + /* Type 1 transaction */
12816 + else {
12817 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
12818 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
12819 + }
12820 +
12821 + sb_setcoreidx(sbh, coreidx);
12822 +
12823 + return addr;
12824 +}
12825 +
12826 +static int
12827 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12828 +{
12829 + uint32 addr, *reg = NULL, val;
12830 + int ret = 0;
12831 +
12832 + if (pci_disabled ||
12833 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12834 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12835 + BUSPROBE(val, reg))
12836 + val = 0xffffffff;
12837 +
12838 + val >>= 8 * (off & 3);
12839 + if (len == 4)
12840 + *((uint32 *) buf) = val;
12841 + else if (len == 2)
12842 + *((uint16 *) buf) = (uint16) val;
12843 + else if (len == 1)
12844 + *((uint8 *) buf) = (uint8) val;
12845 + else
12846 + ret = -1;
12847 +
12848 + if (reg)
12849 + REG_UNMAP(reg);
12850 +
12851 + return ret;
12852 +}
12853 +
12854 +static int
12855 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12856 +{
12857 + uint32 addr, *reg = NULL, val;
12858 + int ret = 0;
12859 +
12860 + if (pci_disabled ||
12861 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
12862 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
12863 + BUSPROBE(val, reg))
12864 + goto done;
12865 +
12866 + if (len == 4)
12867 + val = *((uint32 *) buf);
12868 + else if (len == 2) {
12869 + val &= ~(0xffff << (8 * (off & 3)));
12870 + val |= *((uint16 *) buf) << (8 * (off & 3));
12871 + } else if (len == 1) {
12872 + val &= ~(0xff << (8 * (off & 3)));
12873 + val |= *((uint8 *) buf) << (8 * (off & 3));
12874 + } else
12875 + ret = -1;
12876 +
12877 + W_REG(reg, val);
12878 +
12879 + done:
12880 + if (reg)
12881 + REG_UNMAP(reg);
12882 +
12883 + return ret;
12884 +}
12885 +
12886 +/*
12887 + * Functions for accessing translated SB configuration space
12888 + */
12889 +
12890 +static int
12891 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12892 +{
12893 + pci_config_regs *cfg;
12894 +
12895 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
12896 + return -1;
12897 + cfg = &sb_config_regs[dev];
12898 +
12899 + ASSERT(ISALIGNED(off, len));
12900 + ASSERT(ISALIGNED((uintptr)buf, len));
12901 +
12902 + if (len == 4)
12903 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
12904 + else if (len == 2)
12905 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
12906 + else if (len == 1)
12907 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
12908 + else
12909 + return -1;
12910 +
12911 + return 0;
12912 +}
12913 +
12914 +static int
12915 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12916 +{
12917 + uint coreidx, n;
12918 + void *regs;
12919 + sbconfig_t *sb;
12920 + pci_config_regs *cfg;
12921 +
12922 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
12923 + return -1;
12924 + cfg = &sb_config_regs[dev];
12925 +
12926 + ASSERT(ISALIGNED(off, len));
12927 + ASSERT(ISALIGNED((uintptr)buf, len));
12928 +
12929 + /* Emulate BAR sizing */
12930 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
12931 + len == 4 && *((uint32 *) buf) == ~0) {
12932 + coreidx = sb_coreidx(sbh);
12933 + if ((regs = sb_setcoreidx(sbh, dev))) {
12934 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
12935 + /* Highest numbered address match register */
12936 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
12937 + if (off == OFFSETOF(pci_config_regs, base[0]))
12938 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
12939 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
12940 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
12941 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
12942 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
12943 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
12944 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
12945 + }
12946 + sb_setcoreidx(sbh, coreidx);
12947 + return 0;
12948 + }
12949 +
12950 + if (len == 4)
12951 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
12952 + else if (len == 2)
12953 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
12954 + else if (len == 1)
12955 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
12956 + else
12957 + return -1;
12958 +
12959 + return 0;
12960 +}
12961 +
12962 +int
12963 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12964 +{
12965 + if (bus == 0)
12966 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
12967 + else
12968 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
12969 +}
12970 +
12971 +int
12972 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
12973 +{
12974 + if (bus == 0)
12975 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
12976 + else
12977 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
12978 +}
12979 +
12980 +void
12981 +sbpci_ban(uint16 core)
12982 +{
12983 + if (pci_banned < ARRAYSIZE(pci_ban))
12984 + pci_ban[pci_banned++] = core;
12985 +}
12986 +
12987 +static int
12988 +sbpci_init_pci(sb_t *sbh)
12989 +{
12990 + uint chip, chiprev, chippkg, host;
12991 + uint32 boardflags;
12992 + sbpciregs_t *pci;
12993 + sbconfig_t *sb;
12994 + uint32 val;
12995 +
12996 + chip = sb_chip(sbh);
12997 + chiprev = sb_chiprev(sbh);
12998 + chippkg = sb_chippkg(sbh);
12999 +
13000 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
13001 + printf("PCI: no core\n");
13002 + pci_disabled = TRUE;
13003 + return -1;
13004 + }
13005 + sb_core_reset(sbh, 0);
13006 +
13007 + boardflags = (uint32) getintvar(NULL, "boardflags");
13008 +
13009 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
13010 + pci_disabled = TRUE;
13011 +
13012 + /*
13013 + * The 200-pin BCM4712 package does not bond out PCI. Even when
13014 + * PCI is bonded out, some boards may leave the pins
13015 + * floating.
13016 + */
13017 + if (((chip == BCM4712_DEVICE_ID) &&
13018 + ((chippkg == BCM4712SMALL_PKG_ID) ||
13019 + (chippkg == BCM4712MID_PKG_ID))) ||
13020 + (boardflags & BFL_NOPCI))
13021 + pci_disabled = TRUE;
13022 +
13023 + /*
13024 + * If the PCI core should not be touched (disabled, not bonded
13025 + * out, or pins floating), do not even attempt to access core
13026 + * registers. Otherwise, try to determine if it is in host
13027 + * mode.
13028 + */
13029 + if (pci_disabled)
13030 + host = 0;
13031 + else
13032 + host = !BUSPROBE(val, &pci->control);
13033 +
13034 + if (!host) {
13035 + /* Disable PCI interrupts in client mode */
13036 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
13037 + W_REG(&sb->sbintvec, 0);
13038 +
13039 + /* Disable the PCI bridge in client mode */
13040 + sbpci_ban(SB_PCI);
13041 + printf("PCI: Disabled\n");
13042 + } else {
13043 + /* Reset the external PCI bus and enable the clock */
13044 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
13045 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
13046 + OSL_DELAY(150); /* delay > 100 us */
13047 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
13048 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
13049 + OSL_DELAY(1); /* delay 1 us */
13050 +
13051 + /* Enable CardBusMode */
13052 + cardbus = nvram_match("cardbus", "1");
13053 + if (cardbus) {
13054 + printf("PCI: Enabling CardBus\n");
13055 + /* GPIO 1 resets the CardBus device on bcm94710ap */
13056 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
13057 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
13058 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
13059 + }
13060 +
13061 + /* 64 MB I/O access window */
13062 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
13063 + /* 64 MB configuration access window */
13064 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
13065 + /* 1 GB memory access window */
13066 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
13067 +
13068 + /* Enable PCI bridge BAR0 prefetch and burst */
13069 + val = 6;
13070 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
13071 +
13072 + /* Enable PCI interrupts */
13073 + W_REG(&pci->intmask, PCI_INTA);
13074 + }
13075 +
13076 + return 0;
13077 +}
13078 +
13079 +static int
13080 +sbpci_init_cores(sb_t *sbh)
13081 +{
13082 + uint chip, chiprev, chippkg, coreidx, i;
13083 + sbconfig_t *sb;
13084 + pci_config_regs *cfg;
13085 + void *regs;
13086 + char varname[8];
13087 + uint wlidx = 0;
13088 + uint16 vendor, core;
13089 + uint8 class, subclass, progif;
13090 + uint32 val;
13091 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
13092 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
13093 +
13094 + chip = sb_chip(sbh);
13095 + chiprev = sb_chiprev(sbh);
13096 + chippkg = sb_chippkg(sbh);
13097 + coreidx = sb_coreidx(sbh);
13098 +
13099 + /* Scan the SB bus */
13100 + bzero(sb_config_regs, sizeof(sb_config_regs));
13101 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
13102 + cfg->vendor = 0xffff;
13103 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
13104 + continue;
13105 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13106 +
13107 + /* Read ID register and parse vendor and core */
13108 + val = R_REG(&sb->sbidhigh);
13109 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
13110 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
13111 + progif = 0;
13112 +
13113 + /* Check if this core is banned */
13114 + for (i = 0; i < pci_banned; i++)
13115 + if (core == pci_ban[i])
13116 + break;
13117 + if (i < pci_banned)
13118 + continue;
13119 +
13120 + /* Known vendor translations */
13121 + switch (vendor) {
13122 + case SB_VEND_BCM:
13123 + vendor = VENDOR_BROADCOM;
13124 + break;
13125 + }
13126 +
13127 + /* Determine class based on known core codes */
13128 + switch (core) {
13129 + case SB_ILINE20:
13130 + class = PCI_CLASS_NET;
13131 + subclass = PCI_NET_ETHER;
13132 + core = BCM47XX_ILINE_ID;
13133 + break;
13134 + case SB_ILINE100:
13135 + class = PCI_CLASS_NET;
13136 + subclass = PCI_NET_ETHER;
13137 + core = BCM4610_ILINE_ID;
13138 + break;
13139 + case SB_ENET:
13140 + class = PCI_CLASS_NET;
13141 + subclass = PCI_NET_ETHER;
13142 + core = BCM47XX_ENET_ID;
13143 + break;
13144 + case SB_SDRAM:
13145 + case SB_MEMC:
13146 + class = PCI_CLASS_MEMORY;
13147 + subclass = PCI_MEMORY_RAM;
13148 + break;
13149 + case SB_PCI:
13150 + class = PCI_CLASS_BRIDGE;
13151 + subclass = PCI_BRIDGE_PCI;
13152 + break;
13153 + case SB_MIPS:
13154 + case SB_MIPS33:
13155 + class = PCI_CLASS_CPU;
13156 + subclass = PCI_CPU_MIPS;
13157 + break;
13158 + case SB_CODEC:
13159 + class = PCI_CLASS_COMM;
13160 + subclass = PCI_COMM_MODEM;
13161 + core = BCM47XX_V90_ID;
13162 + break;
13163 + case SB_USB:
13164 + class = PCI_CLASS_SERIAL;
13165 + subclass = PCI_SERIAL_USB;
13166 + progif = 0x10; /* OHCI */
13167 + core = BCM47XX_USB_ID;
13168 + break;
13169 + case SB_USB11H:
13170 + class = PCI_CLASS_SERIAL;
13171 + subclass = PCI_SERIAL_USB;
13172 + progif = 0x10; /* OHCI */
13173 + core = BCM47XX_USBH_ID;
13174 + break;
13175 + case SB_USB11D:
13176 + class = PCI_CLASS_SERIAL;
13177 + subclass = PCI_SERIAL_USB;
13178 + core = BCM47XX_USBD_ID;
13179 + break;
13180 + case SB_IPSEC:
13181 + class = PCI_CLASS_CRYPT;
13182 + subclass = PCI_CRYPT_NETWORK;
13183 + core = BCM47XX_IPSEC_ID;
13184 + break;
13185 + case SB_ROBO:
13186 + class = PCI_CLASS_NET;
13187 + subclass = PCI_NET_OTHER;
13188 + core = BCM47XX_ROBO_ID;
13189 + break;
13190 + case SB_EXTIF:
13191 + case SB_CC:
13192 + class = PCI_CLASS_MEMORY;
13193 + subclass = PCI_MEMORY_FLASH;
13194 + break;
13195 + case SB_D11:
13196 + class = PCI_CLASS_NET;
13197 + subclass = PCI_NET_OTHER;
13198 + /* Let an nvram variable override this */
13199 + sprintf(varname, "wl%did", wlidx);
13200 + wlidx++;
13201 + if ((core = getintvar(NULL, varname)) == 0) {
13202 + if (chip == BCM4712_DEVICE_ID) {
13203 + if (chippkg == BCM4712SMALL_PKG_ID)
13204 + core = BCM4306_D11G_ID;
13205 + else
13206 + core = BCM4306_D11DUAL_ID;
13207 + } else {
13208 + /* 4310 */
13209 + core = BCM4310_D11B_ID;
13210 + }
13211 + }
13212 + break;
13213 +
13214 + default:
13215 + class = subclass = progif = 0xff;
13216 + break;
13217 + }
13218 +
13219 + /* Supported translations */
13220 + cfg->vendor = htol16(vendor);
13221 + cfg->device = htol16(core);
13222 + cfg->rev_id = chiprev;
13223 + cfg->prog_if = progif;
13224 + cfg->sub_class = subclass;
13225 + cfg->base_class = class;
13226 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
13227 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
13228 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
13229 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
13230 + cfg->base[4] = 0;
13231 + cfg->base[5] = 0;
13232 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
13233 + cfg->header_type = PCI_HEADER_BRIDGE;
13234 + else
13235 + cfg->header_type = PCI_HEADER_NORMAL;
13236 + /* Save core interrupt flag */
13237 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
13238 + /* Default to MIPS shared interrupt 0 */
13239 + cfg->int_line = 0;
13240 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
13241 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
13242 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
13243 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
13244 + val = R_REG(&sb->sbipsflag);
13245 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
13246 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
13247 + break;
13248 + }
13249 + if (cfg->int_line > 4)
13250 + cfg->int_line = 0;
13251 + }
13252 + /* Emulated core */
13253 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
13254 + }
13255 +
13256 + sb_setcoreidx(sbh, coreidx);
13257 + return 0;
13258 +}
13259 +
13260 +int __init
13261 +sbpci_init(sb_t *sbh)
13262 +{
13263 + sbpci_init_pci(sbh);
13264 + sbpci_init_cores(sbh);
13265 + return 0;
13266 +}
13267 +
13268 +void
13269 +sbpci_check(sb_t *sbh)
13270 +{
13271 + uint coreidx;
13272 + sbpciregs_t *pci;
13273 + uint32 sbtopci1;
13274 + uint32 buf[64], *ptr, i;
13275 + ulong pa;
13276 + volatile uint j;
13277 +
13278 + coreidx = sb_coreidx(sbh);
13279 + pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
13280 +
13281 + /* Clear the test array */
13282 + pa = (ulong) DMA_MAP(NULL, buf, sizeof(buf), DMA_RX, NULL);
13283 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13284 + memset(ptr, 0, sizeof(buf));
13285 +
13286 + /* Point PCI window 1 to memory */
13287 + sbtopci1 = R_REG(&pci->sbtopci1);
13288 + W_REG(&pci->sbtopci1, SBTOPCI_MEM | (pa & SBTOPCI1_MASK));
13289 +
13290 + /* Fill the test array via PCI window 1 */
13291 + ptr = (uint32 *) REG_MAP(SB_PCI_CFG + (pa & ~SBTOPCI1_MASK), sizeof(buf));
13292 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13293 + for (j = 0; j < 2; j++);
13294 + W_REG(&ptr[i], i);
13295 + }
13296 + REG_UNMAP(ptr);
13297 +
13298 + /* Restore PCI window 1 */
13299 + W_REG(&pci->sbtopci1, sbtopci1);
13300 +
13301 + /* Check the test array */
13302 + DMA_UNMAP(NULL, pa, sizeof(buf), DMA_RX, NULL);
13303 + ptr = (uint32 *) OSL_UNCACHED(&buf[0]);
13304 + for (i = 0; i < ARRAYSIZE(buf); i++) {
13305 + if (ptr[i] != i)
13306 + break;
13307 + }
13308 +
13309 + /* Change the clock if the test fails */
13310 + if (i < ARRAYSIZE(buf)) {
13311 + uint32 req, cur;
13312 +
13313 + cur = sb_clock(sbh);
13314 + printf("PCI: Test failed at %d MHz\n", (cur + 500000) / 1000000);
13315 + for (req = 104000000; req < 176000000; req += 4000000) {
13316 + printf("PCI: Resetting to %d MHz\n", (req + 500000) / 1000000);
13317 + /* This will only reset if the clocks are valid and have changed */
13318 + sb_mips_setclock(sbh, req, 0, 0);
13319 + }
13320 + /* Should not reach here */
13321 + ASSERT(0);
13322 + }
13323 +
13324 + sb_setcoreidx(sbh, coreidx);
13325 +}
13326 +
13327 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
13328 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
13329 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-11-08 00:11:55.346775000 +0100
13330 @@ -0,0 +1,272 @@
13331 +/*
13332 + * Generic setup routines for Broadcom MIPS boards
13333 + *
13334 + * Copyright 2005, Broadcom Corporation
13335 + * All Rights Reserved.
13336 + *
13337 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13338 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13339 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13340 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13341 + *
13342 + * $Id$
13343 + */
13344 +
13345 +#include <linux/config.h>
13346 +#include <linux/init.h>
13347 +#include <linux/kernel.h>
13348 +#include <linux/serialP.h>
13349 +#include <linux/ide.h>
13350 +#include <asm/bootinfo.h>
13351 +#include <asm/cpu.h>
13352 +#include <asm/time.h>
13353 +#include <asm/reboot.h>
13354 +
13355 +#ifdef CONFIG_MTD_PARTITIONS
13356 +#include <linux/mtd/mtd.h>
13357 +#include <linux/mtd/partitions.h>
13358 +#endif
13359 +
13360 +#include <typedefs.h>
13361 +#include <osl.h>
13362 +#include <sbutils.h>
13363 +#include <bcmutils.h>
13364 +#include <bcmnvram.h>
13365 +#include <sbmips.h>
13366 +#include <trxhdr.h>
13367 +
13368 +extern void bcm947xx_time_init(void);
13369 +extern void bcm947xx_timer_setup(struct irqaction *irq);
13370 +
13371 +#ifdef CONFIG_REMOTE_DEBUG
13372 +extern void set_debug_traps(void);
13373 +extern void rs_kgdb_hook(struct serial_state *);
13374 +extern void breakpoint(void);
13375 +#endif
13376 +
13377 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13378 +extern struct ide_ops std_ide_ops;
13379 +#endif
13380 +
13381 +/* Global SB handle */
13382 +sb_t *bcm947xx_sbh = NULL;
13383 +spinlock_t bcm947xx_sbh_lock = SPIN_LOCK_UNLOCKED;
13384 +EXPORT_SYMBOL(bcm947xx_sbh);
13385 +EXPORT_SYMBOL(bcm947xx_sbh_lock);
13386 +
13387 +/* Convenience */
13388 +#define sbh bcm947xx_sbh
13389 +#define sbh_lock bcm947xx_sbh_lock
13390 +
13391 +/* Kernel command line */
13392 +char arcs_cmdline[CL_SIZE] __initdata = CONFIG_CMDLINE;
13393 +
13394 +void
13395 +bcm947xx_machine_restart(char *command)
13396 +{
13397 + printk("Please stand by while rebooting the system...\n");
13398 +
13399 + /* Set the watchdog timer to reset immediately */
13400 + __cli();
13401 + sb_watchdog(sbh, 1);
13402 + while (1);
13403 +}
13404 +
13405 +void
13406 +bcm947xx_machine_halt(void)
13407 +{
13408 + printk("System halted\n");
13409 +
13410 + /* Disable interrupts and watchdog and spin forever */
13411 + __cli();
13412 + sb_watchdog(sbh, 0);
13413 + while (1);
13414 +}
13415 +
13416 +#ifdef CONFIG_SERIAL
13417 +
13418 +static struct serial_struct rs = {
13419 + line: 0,
13420 + flags: ASYNC_BOOT_AUTOCONF,
13421 + io_type: SERIAL_IO_MEM,
13422 +};
13423 +
13424 +static void __init
13425 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
13426 +{
13427 + rs.iomem_base = regs;
13428 + rs.irq = irq + 2;
13429 + rs.baud_base = baud_base / 16;
13430 + rs.iomem_reg_shift = reg_shift;
13431 +
13432 + early_serial_setup(&rs);
13433 +
13434 + rs.line++;
13435 +}
13436 +
13437 +static void __init
13438 +serial_setup(sb_t *sbh)
13439 +{
13440 + sb_serial_init(sbh, serial_add);
13441 +
13442 +#ifdef CONFIG_REMOTE_DEBUG
13443 + /* Use the last port for kernel debugging */
13444 + if (rs.iomem_base)
13445 + rs_kgdb_hook(&rs);
13446 +#endif
13447 +}
13448 +
13449 +#endif /* CONFIG_SERIAL */
13450 +
13451 +void __init
13452 +brcm_setup(void)
13453 +{
13454 + char *value;
13455 +
13456 + /* Get global SB handle */
13457 + sbh = sb_kattach();
13458 +
13459 + /* Initialize clocks and interrupts */
13460 + sb_mips_init(sbh);
13461 +
13462 + if (BCM330X(current_cpu_data.processor_id) &&
13463 + (read_c0_diag() & BRCM_PFC_AVAIL)) {
13464 + /*
13465 + * Now that the sbh is inited set the proper PFC value
13466 + */
13467 + printk("Setting the PFC to its default value\n");
13468 + enable_pfc(PFC_AUTO);
13469 + }
13470 +
13471 +
13472 +#ifdef CONFIG_SERIAL
13473 + /* Initialize UARTs */
13474 + serial_setup(sbh);
13475 +#endif
13476 +
13477 +#if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
13478 + ide_ops = &std_ide_ops;
13479 +#endif
13480 +
13481 + /* Override default command line arguments */
13482 + value = nvram_get("kernel_cmdline");
13483 + if (value && strlen(value) && strncmp(value, "empty", 5))
13484 + strncpy(arcs_cmdline, value, sizeof(arcs_cmdline));
13485 +
13486 +
13487 + /* Generic setup */
13488 + _machine_restart = bcm947xx_machine_restart;
13489 + _machine_halt = bcm947xx_machine_halt;
13490 + _machine_power_off = bcm947xx_machine_halt;
13491 +
13492 + board_time_init = bcm947xx_time_init;
13493 + board_timer_setup = bcm947xx_timer_setup;
13494 +}
13495 +
13496 +const char *
13497 +get_system_type(void)
13498 +{
13499 + static char s[32];
13500 +
13501 + if (bcm947xx_sbh) {
13502 + sprintf(s, "Broadcom BCM%X chip rev %d", sb_chip(bcm947xx_sbh),
13503 + sb_chiprev(bcm947xx_sbh));
13504 + return s;
13505 + }
13506 + else
13507 + return "Broadcom BCM947XX";
13508 +}
13509 +
13510 +void __init
13511 +bus_error_init(void)
13512 +{
13513 +}
13514 +
13515 +#ifdef CONFIG_MTD_PARTITIONS
13516 +
13517 +static struct mtd_partition bcm947xx_parts[] = {
13518 + { name: "pmon", offset: 0, size: 0, mask_flags: MTD_WRITEABLE, },
13519 + { name: "linux", offset: 0, size: 0, },
13520 + { name: "rootfs", offset: 0, size: 0, },
13521 + { name: "nvram", offset: 0, size: 0, },
13522 + { name: "OpenWrt", offset: 0, size: 0, },
13523 + { name: NULL, },
13524 +};
13525 +
13526 +static int __init
13527 +find_root(struct mtd_info *mtd, size_t size, struct mtd_partition *part)
13528 +{
13529 + struct trx_header *trx;
13530 + unsigned char buf[512];
13531 + int off;
13532 + size_t len;
13533 +
13534 + trx = (struct trx_header *) buf;
13535 +
13536 + for (off = (256*1024); off < size; off += mtd->erasesize) {
13537 + memset(buf, 0xe5, sizeof(buf));
13538 +
13539 + /*
13540 + * Read into buffer
13541 + */
13542 + if (MTD_READ(mtd, off, sizeof(buf), &len, buf) ||
13543 + len != sizeof(buf))
13544 + continue;
13545 +
13546 + /* found a TRX header */
13547 + if (le32_to_cpu(trx->magic) == TRX_MAGIC) {
13548 + part->offset = le32_to_cpu(trx->offsets[2]) ? :
13549 + le32_to_cpu(trx->offsets[1]);
13550 + part->size = le32_to_cpu(trx->len);
13551 +
13552 + part->size -= part->offset;
13553 + part->offset += off;
13554 +
13555 + goto done;
13556 + }
13557 + }
13558 +
13559 + printk(KERN_NOTICE
13560 + "%s: Couldn't find root filesystem\n",
13561 + mtd->name);
13562 + return -1;
13563 +
13564 + done:
13565 + return part->size;
13566 +}
13567 +
13568 +struct mtd_partition * __init
13569 +init_mtd_partitions(struct mtd_info *mtd, size_t size)
13570 +{
13571 +
13572 + /* boot loader */
13573 + bcm947xx_parts[0].offset=0;
13574 + bcm947xx_parts[0].size=256*1024;
13575 +
13576 + /* nvram */
13577 + bcm947xx_parts[3].offset = size - ROUNDUP(NVRAM_SPACE, mtd->erasesize);
13578 + bcm947xx_parts[3].size = size - bcm947xx_parts[3].offset;
13579 +
13580 + /* Size linux (kernel and rootfs) */
13581 + bcm947xx_parts[1].offset = bcm947xx_parts[0].size;
13582 + bcm947xx_parts[1].size = bcm947xx_parts[3].offset - bcm947xx_parts[1].offset;
13583 +
13584 + /* Find and size rootfs */
13585 + if (find_root(mtd,size,&bcm947xx_parts[2])==0) {
13586 + /* entirely jffs2 */
13587 + bcm947xx_parts[2].size = bcm947xx_parts[3].offset - bcm947xx_parts[2].offset;
13588 + bcm947xx_parts[4].name = NULL;
13589 + } else {
13590 + /* legacy setup */
13591 + /* calculate leftover flash, and assign it to the jffs2 partition */
13592 + bcm947xx_parts[4].offset = bcm947xx_parts[2].offset + bcm947xx_parts[2].size;
13593 + bcm947xx_parts[4].offset = ROUNDUP(bcm947xx_parts[4].offset, mtd->erasesize);
13594 + bcm947xx_parts[4].size = bcm947xx_parts[3].offset - bcm947xx_parts[4].offset;
13595 + }
13596 +
13597 + return bcm947xx_parts;
13598 +}
13599 +
13600 +EXPORT_SYMBOL(init_mtd_partitions);
13601 +
13602 +#endif
13603 diff -urN linux.old/arch/mips/bcm947xx/sflash.c linux.dev/arch/mips/bcm947xx/sflash.c
13604 --- linux.old/arch/mips/bcm947xx/sflash.c 1970-01-01 01:00:00.000000000 +0100
13605 +++ linux.dev/arch/mips/bcm947xx/sflash.c 2005-11-08 00:54:43.022739000 +0100
13606 @@ -0,0 +1,418 @@
13607 +/*
13608 + * Broadcom SiliconBackplane chipcommon serial flash interface
13609 + *
13610 + * Copyright 2005, Broadcom Corporation
13611 + * All Rights Reserved.
13612 + *
13613 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
13614 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
13615 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
13616 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
13617 + *
13618 + * $Id$
13619 + */
13620 +
13621 +#include <osl.h>
13622 +#include <typedefs.h>
13623 +#include <sbconfig.h>
13624 +#include <sbchipc.h>
13625 +#include <mipsinc.h>
13626 +#include <bcmutils.h>
13627 +#include <bcmdevs.h>
13628 +#include <sflash.h>
13629 +
13630 +/* Private global state */
13631 +static struct sflash sflash;
13632 +
13633 +/* Issue a serial flash command */
13634 +static INLINE void
13635 +sflash_cmd(chipcregs_t *cc, uint opcode)
13636 +{
13637 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
13638 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
13639 +}
13640 +
13641 +/* Initialize serial flash access */
13642 +struct sflash *
13643 +sflash_init(chipcregs_t *cc)
13644 +{
13645 + uint32 id, id2;
13646 +
13647 + bzero(&sflash, sizeof(sflash));
13648 +
13649 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
13650 +
13651 + switch (sflash.type) {
13652 + case SFLASH_ST:
13653 + /* Probe for ST chips */
13654 + sflash_cmd(cc, SFLASH_ST_DP);
13655 + sflash_cmd(cc, SFLASH_ST_RES);
13656 + id = R_REG(&cc->flashdata);
13657 + switch (id) {
13658 + case 0x11:
13659 + /* ST M25P20 2 Mbit Serial Flash */
13660 + sflash.blocksize = 64 * 1024;
13661 + sflash.numblocks = 4;
13662 + break;
13663 + case 0x12:
13664 + /* ST M25P40 4 Mbit Serial Flash */
13665 + sflash.blocksize = 64 * 1024;
13666 + sflash.numblocks = 8;
13667 + break;
13668 + case 0x13:
13669 + /* ST M25P80 8 Mbit Serial Flash */
13670 + sflash.blocksize = 64 * 1024;
13671 + sflash.numblocks = 16;
13672 + break;
13673 + case 0x14:
13674 + /* ST M25P16 16 Mbit Serial Flash */
13675 + sflash.blocksize = 64 * 1024;
13676 + sflash.numblocks = 32;
13677 + break;
13678 + case 0x15:
13679 + /* ST M25P32 32 Mbit Serial Flash */
13680 + sflash.blocksize = 64 * 1024;
13681 + sflash.numblocks = 64;
13682 + break;
13683 + case 0xbf:
13684 + W_REG(&cc->flashaddress, 1);
13685 + sflash_cmd(cc, SFLASH_ST_RES);
13686 + id2 = R_REG(&cc->flashdata);
13687 + if (id2 == 0x44) {
13688 + /* SST M25VF80 4 Mbit Serial Flash */
13689 + sflash.blocksize = 64 * 1024;
13690 + sflash.numblocks = 8;
13691 + }
13692 + break;
13693 + }
13694 + break;
13695 +
13696 + case SFLASH_AT:
13697 + /* Probe for Atmel chips */
13698 + sflash_cmd(cc, SFLASH_AT_STATUS);
13699 + id = R_REG(&cc->flashdata) & 0x3c;
13700 + switch (id) {
13701 + case 0xc:
13702 + /* Atmel AT45DB011 1Mbit Serial Flash */
13703 + sflash.blocksize = 256;
13704 + sflash.numblocks = 512;
13705 + break;
13706 + case 0x14:
13707 + /* Atmel AT45DB021 2Mbit Serial Flash */
13708 + sflash.blocksize = 256;
13709 + sflash.numblocks = 1024;
13710 + break;
13711 + case 0x1c:
13712 + /* Atmel AT45DB041 4Mbit Serial Flash */
13713 + sflash.blocksize = 256;
13714 + sflash.numblocks = 2048;
13715 + break;
13716 + case 0x24:
13717 + /* Atmel AT45DB081 8Mbit Serial Flash */
13718 + sflash.blocksize = 256;
13719 + sflash.numblocks = 4096;
13720 + break;
13721 + case 0x2c:
13722 + /* Atmel AT45DB161 16Mbit Serial Flash */
13723 + sflash.blocksize = 512;
13724 + sflash.numblocks = 4096;
13725 + break;
13726 + case 0x34:
13727 + /* Atmel AT45DB321 32Mbit Serial Flash */
13728 + sflash.blocksize = 512;
13729 + sflash.numblocks = 8192;
13730 + break;
13731 + case 0x3c:
13732 + /* Atmel AT45DB642 64Mbit Serial Flash */
13733 + sflash.blocksize = 1024;
13734 + sflash.numblocks = 8192;
13735 + break;
13736 + }
13737 + break;
13738 + }
13739 +
13740 + sflash.size = sflash.blocksize * sflash.numblocks;
13741 + return sflash.size ? &sflash : NULL;
13742 +}
13743 +
13744 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
13745 +int
13746 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
13747 +{
13748 + int cnt;
13749 + uint32 *from, *to;
13750 +
13751 + if (!len)
13752 + return 0;
13753 +
13754 + if ((offset + len) > sflash.size)
13755 + return -22;
13756 +
13757 + if ((len >= 4) && (offset & 3))
13758 + cnt = 4 - (offset & 3);
13759 + else if ((len >= 4) && ((uint32)buf & 3))
13760 + cnt = 4 - ((uint32)buf & 3);
13761 + else
13762 + cnt = len;
13763 +
13764 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
13765 + to = (uint32 *)buf;
13766 +
13767 + if (cnt < 4) {
13768 + bcopy(from, to, cnt);
13769 + return cnt;
13770 + }
13771 +
13772 + while (cnt >= 4) {
13773 + *to++ = *from++;
13774 + cnt -= 4;
13775 + }
13776 +
13777 + return (len - cnt);
13778 +}
13779 +
13780 +/* Poll for command completion. Returns zero when complete. */
13781 +int
13782 +sflash_poll(chipcregs_t *cc, uint offset)
13783 +{
13784 + if (offset >= sflash.size)
13785 + return -22;
13786 +
13787 + switch (sflash.type) {
13788 + case SFLASH_ST:
13789 + /* Check for ST Write In Progress bit */
13790 + sflash_cmd(cc, SFLASH_ST_RDSR);
13791 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
13792 + case SFLASH_AT:
13793 + /* Check for Atmel Ready bit */
13794 + sflash_cmd(cc, SFLASH_AT_STATUS);
13795 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
13796 + }
13797 +
13798 + return 0;
13799 +}
13800 +
13801 +/* Write len bytes starting at offset into buf. Returns number of bytes
13802 + * written. Caller should poll for completion.
13803 + */
13804 +int
13805 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13806 +{
13807 + struct sflash *sfl;
13808 + int ret = 0;
13809 + bool is4712b0;
13810 + uint32 page, byte, mask;
13811 +
13812 + if (!len)
13813 + return 0;
13814 +
13815 + if ((offset + len) > sflash.size)
13816 + return -22;
13817 +
13818 + sfl = &sflash;
13819 + switch (sfl->type) {
13820 + case SFLASH_ST:
13821 + mask = R_REG(&cc->chipid);
13822 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
13823 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
13824 + /* Enable writes */
13825 + sflash_cmd(cc, SFLASH_ST_WREN);
13826 + if (is4712b0) {
13827 + mask = 1 << 14;
13828 + W_REG(&cc->flashaddress, offset);
13829 + W_REG(&cc->flashdata, *buf++);
13830 + /* Set chip select */
13831 + OR_REG(&cc->gpioout, mask);
13832 + /* Issue a page program with the first byte */
13833 + sflash_cmd(cc, SFLASH_ST_PP);
13834 + ret = 1;
13835 + offset++;
13836 + len--;
13837 + while (len > 0) {
13838 + if ((offset & 255) == 0) {
13839 + /* Page boundary, drop cs and return */
13840 + AND_REG(&cc->gpioout, ~mask);
13841 + if (!sflash_poll(cc, offset)) {
13842 + /* Flash rejected command */
13843 + return -11;
13844 + }
13845 + return ret;
13846 + } else {
13847 + /* Write single byte */
13848 + sflash_cmd(cc, *buf++);
13849 + }
13850 + ret++;
13851 + offset++;
13852 + len--;
13853 + }
13854 + /* All done, drop cs if needed */
13855 + if ((offset & 255) != 1) {
13856 + /* Drop cs */
13857 + AND_REG(&cc->gpioout, ~mask);
13858 + if (!sflash_poll(cc, offset)) {
13859 + /* Flash rejected command */
13860 + return -12;
13861 + }
13862 + }
13863 + } else {
13864 + ret = 1;
13865 + W_REG(&cc->flashaddress, offset);
13866 + W_REG(&cc->flashdata, *buf);
13867 + /* Page program */
13868 + sflash_cmd(cc, SFLASH_ST_PP);
13869 + }
13870 + break;
13871 + case SFLASH_AT:
13872 + mask = sfl->blocksize - 1;
13873 + page = (offset & ~mask) << 1;
13874 + byte = offset & mask;
13875 + /* Read main memory page into buffer 1 */
13876 + if (byte || len < sfl->blocksize) {
13877 + W_REG(&cc->flashaddress, page);
13878 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
13879 + /* 250 us for AT45DB321B */
13880 + SPINWAIT(sflash_poll(cc, offset), 1000);
13881 + ASSERT(!sflash_poll(cc, offset));
13882 + }
13883 + /* Write into buffer 1 */
13884 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
13885 + W_REG(&cc->flashaddress, byte++);
13886 + W_REG(&cc->flashdata, *buf++);
13887 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
13888 + }
13889 + /* Write buffer 1 into main memory page */
13890 + W_REG(&cc->flashaddress, page);
13891 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
13892 + break;
13893 + }
13894 +
13895 + return ret;
13896 +}
13897 +
13898 +/* Erase a region. Returns number of bytes scheduled for erasure.
13899 + * Caller should poll for completion.
13900 + */
13901 +int
13902 +sflash_erase(chipcregs_t *cc, uint offset)
13903 +{
13904 + struct sflash *sfl;
13905 +
13906 + if (offset >= sflash.size)
13907 + return -22;
13908 +
13909 + sfl = &sflash;
13910 + switch (sfl->type) {
13911 + case SFLASH_ST:
13912 + sflash_cmd(cc, SFLASH_ST_WREN);
13913 + W_REG(&cc->flashaddress, offset);
13914 + sflash_cmd(cc, SFLASH_ST_SE);
13915 + return sfl->blocksize;
13916 + case SFLASH_AT:
13917 + W_REG(&cc->flashaddress, offset << 1);
13918 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
13919 + return sfl->blocksize;
13920 + }
13921 +
13922 + return 0;
13923 +}
13924 +
13925 +/*
13926 + * writes the appropriate range of flash, a NULL buf simply erases
13927 + * the region of flash
13928 + */
13929 +int
13930 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
13931 +{
13932 + struct sflash *sfl;
13933 + uchar *block = NULL, *cur_ptr, *blk_ptr;
13934 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
13935 + uint blk_offset, blk_len, copied;
13936 + int bytes, ret = 0;
13937 +
13938 + /* Check address range */
13939 + if (len <= 0)
13940 + return 0;
13941 +
13942 + sfl = &sflash;
13943 + if ((offset + len) > sfl->size)
13944 + return -1;
13945 +
13946 + blocksize = sfl->blocksize;
13947 + mask = blocksize - 1;
13948 +
13949 + /* Allocate a block of mem */
13950 + if (!(block = MALLOC(NULL, blocksize)))
13951 + return -1;
13952 +
13953 + while (len) {
13954 + /* Align offset */
13955 + cur_offset = offset & ~mask;
13956 + cur_length = blocksize;
13957 + cur_ptr = block;
13958 +
13959 + remainder = blocksize - (offset & mask);
13960 + if (len < remainder)
13961 + cur_retlen = len;
13962 + else
13963 + cur_retlen = remainder;
13964 +
13965 + /* buf == NULL means erase only */
13966 + if (buf) {
13967 + /* Copy existing data into holding block if necessary */
13968 + if ((offset & mask) || (len < blocksize)) {
13969 + blk_offset = cur_offset;
13970 + blk_len = cur_length;
13971 + blk_ptr = cur_ptr;
13972 +
13973 + /* Copy entire block */
13974 + while(blk_len) {
13975 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
13976 + blk_offset += copied;
13977 + blk_len -= copied;
13978 + blk_ptr += copied;
13979 + }
13980 + }
13981 +
13982 + /* Copy input data into holding block */
13983 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
13984 + }
13985 +
13986 + /* Erase block */
13987 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
13988 + goto done;
13989 + while (sflash_poll(cc, (uint) cur_offset));
13990 +
13991 + /* buf == NULL means erase only */
13992 + if (!buf) {
13993 + offset += cur_retlen;
13994 + len -= cur_retlen;
13995 + continue;
13996 + }
13997 +
13998 + /* Write holding block */
13999 + while (cur_length > 0) {
14000 + if ((bytes = sflash_write(cc,
14001 + (uint) cur_offset,
14002 + (uint) cur_length,
14003 + (uchar *) cur_ptr)) < 0) {
14004 + ret = bytes;
14005 + goto done;
14006 + }
14007 + while (sflash_poll(cc, (uint) cur_offset));
14008 + cur_offset += bytes;
14009 + cur_length -= bytes;
14010 + cur_ptr += bytes;
14011 + }
14012 +
14013 + offset += cur_retlen;
14014 + len -= cur_retlen;
14015 + buf += cur_retlen;
14016 + }
14017 +
14018 + ret = len;
14019 +done:
14020 + if (block)
14021 + MFREE(NULL, block, blocksize);
14022 + return ret;
14023 +}
14024 +
14025 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
14026 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
14027 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-11-07 23:47:27.528101500 +0100
14028 @@ -0,0 +1,118 @@
14029 +/*
14030 + * Copyright 2004, Broadcom Corporation
14031 + * All Rights Reserved.
14032 + *
14033 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14034 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14035 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14036 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14037 + *
14038 + * $Id: time.c,v 1.1 2005/03/16 13:49:59 wbx Exp $
14039 + */
14040 +#include <linux/config.h>
14041 +#include <linux/init.h>
14042 +#include <linux/kernel.h>
14043 +#include <linux/sched.h>
14044 +#include <linux/serial_reg.h>
14045 +#include <linux/interrupt.h>
14046 +#include <asm/addrspace.h>
14047 +#include <asm/io.h>
14048 +#include <asm/time.h>
14049 +
14050 +#include <typedefs.h>
14051 +#include <osl.h>
14052 +#include <sbutils.h>
14053 +#include <bcmnvram.h>
14054 +#include <sbconfig.h>
14055 +#include <sbextif.h>
14056 +#include <sbmips.h>
14057 +
14058 +/* Global SB handle */
14059 +extern void *bcm947xx_sbh;
14060 +extern spinlock_t bcm947xx_sbh_lock;
14061 +
14062 +/* Convenience */
14063 +#define sbh bcm947xx_sbh
14064 +#define sbh_lock bcm947xx_sbh_lock
14065 +
14066 +extern int panic_timeout;
14067 +static int watchdog = 0;
14068 +static u8 *mcr = NULL;
14069 +
14070 +void __init
14071 +bcm947xx_time_init(void)
14072 +{
14073 + unsigned int hz;
14074 + extifregs_t *eir;
14075 +
14076 + /*
14077 + * Use deterministic values for initial counter interrupt
14078 + * so that calibrate delay avoids encountering a counter wrap.
14079 + */
14080 + write_c0_count(0);
14081 + write_c0_compare(0xffff);
14082 +
14083 + if (!(hz = sb_mips_clock(sbh)))
14084 + hz = 100000000;
14085 +
14086 + printk("CPU: BCM%04x rev %d at %d MHz\n", sb_chip(sbh), sb_chiprev(sbh),
14087 + (hz + 500000) / 1000000);
14088 +
14089 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
14090 + mips_hpt_frequency = hz / 2;
14091 +
14092 + /* Set watchdog interval in ms */
14093 + watchdog = simple_strtoul(nvram_safe_get("watchdog"), NULL, 0);
14094 +
14095 + /* Please set the watchdog to 3 sec if it is less than 3 but not equal to 0 */
14096 + if (watchdog > 0) {
14097 + if (watchdog < 3000)
14098 + watchdog = 3000;
14099 + }
14100 +
14101 +
14102 + /* Set panic timeout in seconds */
14103 + panic_timeout = watchdog / 1000;
14104 +
14105 + /* Setup blink */
14106 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
14107 + sbconfig_t *sb = (sbconfig_t *)((unsigned int) eir + SBCONFIGOFF);
14108 + unsigned long base = EXTIF_CFGIF_BASE(sb_base(readl(&sb->sbadmatch1)));
14109 + mcr = (u8 *) ioremap_nocache(base + UART_MCR, 1);
14110 + }
14111 +}
14112 +
14113 +static void
14114 +bcm947xx_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
14115 +{
14116 + /* Generic MIPS timer code */
14117 + timer_interrupt(irq, dev_id, regs);
14118 +
14119 + /* Set the watchdog timer to reset after the specified number of ms */
14120 + if (watchdog > 0)
14121 + sb_watchdog(sbh, WATCHDOG_CLOCK / 1000 * watchdog);
14122 +
14123 +#ifdef CONFIG_HWSIM
14124 + (*((int *)0xa0000f1c))++;
14125 +#else
14126 + /* Blink one of the LEDs in the external UART */
14127 + if (mcr && !(jiffies % (HZ/2)))
14128 + writeb(readb(mcr) ^ UART_MCR_OUT2, mcr);
14129 +#endif
14130 +}
14131 +
14132 +static struct irqaction bcm947xx_timer_irqaction = {
14133 + bcm947xx_timer_interrupt,
14134 + SA_INTERRUPT,
14135 + 0,
14136 + "timer",
14137 + NULL,
14138 + NULL
14139 +};
14140 +
14141 +void __init
14142 +bcm947xx_timer_setup(struct irqaction *irq)
14143 +{
14144 + /* Enable the timer interrupt */
14145 + setup_irq(7, &bcm947xx_timer_irqaction);
14146 +}
14147 diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in
14148 --- linux.old/arch/mips/config-shared.in 2005-11-07 23:12:50.850903750 +0100
14149 +++ linux.dev/arch/mips/config-shared.in 2005-11-07 21:57:07.889588500 +0100
14150 @@ -208,6 +208,14 @@
14151 fi
14152 define_bool CONFIG_MIPS_RTC y
14153 fi
14154 +dep_bool 'Support for Broadcom MIPS-based boards' CONFIG_MIPS_BRCM $CONFIG_EXPERIMENTAL
14155 +dep_bool 'Support for Broadcom BCM947XX' CONFIG_BCM947XX $CONFIG_MIPS_BRCM
14156 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14157 + bool ' Support for Broadcom BCM4710' CONFIG_BCM4710
14158 + bool ' Support for Broadcom BCM4310' CONFIG_BCM4310
14159 + bool ' Support for Broadcom BCM4704' CONFIG_BCM4704
14160 + bool ' Support for Broadcom BCM5365' CONFIG_BCM5365
14161 +fi
14162 bool 'Support for SNI RM200 PCI' CONFIG_SNI_RM200_PCI
14163 bool 'Support for TANBAC TB0226 (Mbase)' CONFIG_TANBAC_TB0226
14164 bool 'Support for TANBAC TB0229 (VR4131DIMM)' CONFIG_TANBAC_TB0229
14165 @@ -229,6 +237,11 @@
14166 define_bool CONFIG_RWSEM_XCHGADD_ALGORITHM n
14167
14168 #
14169 +# Provide an option for a default kernel command line
14170 +#
14171 +string 'Default kernel command string' CONFIG_CMDLINE ""
14172 +
14173 +#
14174 # Select some configuration options automatically based on user selections.
14175 #
14176 if [ "$CONFIG_ACER_PICA_61" = "y" ]; then
14177 @@ -554,6 +567,13 @@
14178 define_bool CONFIG_SWAP_IO_SPACE_L y
14179 define_bool CONFIG_BOOT_ELF32 y
14180 fi
14181 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14182 + define_bool CONFIG_PCI y
14183 + define_bool CONFIG_NONCOHERENT_IO y
14184 + define_bool CONFIG_NEW_TIME_C y
14185 + define_bool CONFIG_NEW_IRQ y
14186 + define_bool CONFIG_HND y
14187 +fi
14188 if [ "$CONFIG_SNI_RM200_PCI" = "y" ]; then
14189 define_bool CONFIG_ARC32 y
14190 define_bool CONFIG_ARC_MEMORY y
14191 @@ -1042,7 +1062,11 @@
14192
14193 bool 'Are you using a crosscompiler' CONFIG_CROSSCOMPILE
14194 bool 'Enable run-time debugging' CONFIG_RUNTIME_DEBUG
14195 -bool 'Remote GDB kernel debugging' CONFIG_KGDB
14196 +if [ "$CONFIG_BCM947XX" = "y" ] ; then
14197 + bool 'Remote GDB kernel debugging' CONFIG_REMOTE_DEBUG
14198 +else
14199 + bool 'Remote GDB kernel debugging' CONFIG_KGDB
14200 +fi
14201 dep_bool ' Console output to GDB' CONFIG_GDB_CONSOLE $CONFIG_KGDB
14202 if [ "$CONFIG_KGDB" = "y" ]; then
14203 define_bool CONFIG_DEBUG_INFO y
14204 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
14205 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-11-07 23:12:50.890906250 +0100
14206 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-11-07 21:57:07.893588750 +0100
14207 @@ -163,7 +163,7 @@
14208
14209 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
14210 {
14211 - switch (c->processor_id & 0xff00) {
14212 + switch (c->processor_id & PRID_IMP_MASK) {
14213 case PRID_IMP_R2000:
14214 c->cputype = CPU_R2000;
14215 c->isa_level = MIPS_CPU_ISA_I;
14216 @@ -173,7 +173,7 @@
14217 c->tlbsize = 64;
14218 break;
14219 case PRID_IMP_R3000:
14220 - if ((c->processor_id & 0xff) == PRID_REV_R3000A)
14221 + if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A)
14222 if (cpu_has_confreg())
14223 c->cputype = CPU_R3081E;
14224 else
14225 @@ -188,12 +188,12 @@
14226 break;
14227 case PRID_IMP_R4000:
14228 if (read_c0_config() & CONF_SC) {
14229 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14230 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14231 c->cputype = CPU_R4400PC;
14232 else
14233 c->cputype = CPU_R4000PC;
14234 } else {
14235 - if ((c->processor_id & 0xff) >= PRID_REV_R4400)
14236 + if ((c->processor_id & PRID_REV_MASK) >= PRID_REV_R4400)
14237 c->cputype = CPU_R4400SC;
14238 else
14239 c->cputype = CPU_R4000SC;
14240 @@ -439,7 +439,7 @@
14241 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
14242 {
14243 decode_config1(c);
14244 - switch (c->processor_id & 0xff00) {
14245 + switch (c->processor_id & PRID_IMP_MASK) {
14246 case PRID_IMP_4KC:
14247 c->cputype = CPU_4KC;
14248 c->isa_level = MIPS_CPU_ISA_M32;
14249 @@ -480,10 +480,10 @@
14250 {
14251 decode_config1(c);
14252 c->options |= MIPS_CPU_PREFETCH;
14253 - switch (c->processor_id & 0xff00) {
14254 + switch (c->processor_id & PRID_IMP_MASK) {
14255 case PRID_IMP_AU1_REV1:
14256 case PRID_IMP_AU1_REV2:
14257 - switch ((c->processor_id >> 24) & 0xff) {
14258 + switch ((c->processor_id >> 24) & PRID_REV_MASK) {
14259 case 0:
14260 c->cputype = CPU_AU1000;
14261 break;
14262 @@ -511,10 +511,34 @@
14263 }
14264 }
14265
14266 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
14267 +{
14268 + decode_config1(c);
14269 + c->options |= MIPS_CPU_PREFETCH;
14270 + switch (c->processor_id & PRID_IMP_MASK) {
14271 + case PRID_IMP_BCM4710:
14272 + c->cputype = CPU_BCM4710;
14273 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14274 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14275 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14276 + break;
14277 + case PRID_IMP_4KC:
14278 + case PRID_IMP_BCM3302:
14279 + c->cputype = CPU_BCM3302;
14280 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
14281 + MIPS_CPU_4KTLB | MIPS_CPU_COUNTER;
14282 + c->scache.flags = MIPS_CACHE_NOT_PRESENT;
14283 + break;
14284 + default:
14285 + c->cputype = CPU_UNKNOWN;
14286 + break;
14287 + }
14288 +}
14289 +
14290 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
14291 {
14292 decode_config1(c);
14293 - switch (c->processor_id & 0xff00) {
14294 + switch (c->processor_id & PRID_IMP_MASK) {
14295 case PRID_IMP_SB1:
14296 c->cputype = CPU_SB1;
14297 c->isa_level = MIPS_CPU_ISA_M64;
14298 @@ -536,7 +560,7 @@
14299 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
14300 {
14301 decode_config1(c);
14302 - switch (c->processor_id & 0xff00) {
14303 + switch (c->processor_id & PRID_IMP_MASK) {
14304 case PRID_IMP_SR71000:
14305 c->cputype = CPU_SR71000;
14306 c->isa_level = MIPS_CPU_ISA_M64;
14307 @@ -561,7 +585,7 @@
14308 c->cputype = CPU_UNKNOWN;
14309
14310 c->processor_id = read_c0_prid();
14311 - switch (c->processor_id & 0xff0000) {
14312 + switch (c->processor_id & PRID_COMP_MASK) {
14313
14314 case PRID_COMP_LEGACY:
14315 cpu_probe_legacy(c);
14316 @@ -572,6 +596,9 @@
14317 case PRID_COMP_ALCHEMY:
14318 cpu_probe_alchemy(c);
14319 break;
14320 + case PRID_COMP_BROADCOM:
14321 + cpu_probe_broadcom(c);
14322 + break;
14323 case PRID_COMP_SIBYTE:
14324 cpu_probe_sibyte(c);
14325 break;
14326 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
14327 --- linux.old/arch/mips/kernel/head.S 2005-11-07 23:12:50.898906750 +0100
14328 +++ linux.dev/arch/mips/kernel/head.S 2005-11-07 21:57:07.893588750 +0100
14329 @@ -28,12 +28,20 @@
14330 #include <asm/mipsregs.h>
14331 #include <asm/stackframe.h>
14332
14333 +#ifdef CONFIG_BCM4710
14334 +#undef eret
14335 +#define eret nop; nop; eret
14336 +#endif
14337 +
14338 .text
14339 + j kernel_entry
14340 + nop
14341 +
14342 /*
14343 * Reserved space for exception handlers.
14344 * Necessary for machines which link their kernels at KSEG0.
14345 */
14346 - .fill 0x400
14347 + .fill 0x3f4
14348
14349 /* The following two symbols are used for kernel profiling. */
14350 EXPORT(stext)
14351 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
14352 --- linux.old/arch/mips/kernel/proc.c 2005-11-07 23:12:50.906907250 +0100
14353 +++ linux.dev/arch/mips/kernel/proc.c 2005-11-07 21:57:07.893588750 +0100
14354 @@ -78,9 +78,10 @@
14355 [CPU_AU1550] "Au1550",
14356 [CPU_24K] "MIPS 24K",
14357 [CPU_AU1200] "Au1200",
14358 + [CPU_BCM4710] "BCM4710",
14359 + [CPU_BCM3302] "BCM3302",
14360 };
14361
14362 -
14363 static int show_cpuinfo(struct seq_file *m, void *v)
14364 {
14365 unsigned int version = current_cpu_data.processor_id;
14366 diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c
14367 --- linux.old/arch/mips/kernel/setup.c 2005-11-07 23:12:50.906907250 +0100
14368 +++ linux.dev/arch/mips/kernel/setup.c 2005-11-07 21:57:07.893588750 +0100
14369 @@ -493,6 +493,7 @@
14370 void swarm_setup(void);
14371 void hp_setup(void);
14372 void au1x00_setup(void);
14373 + void brcm_setup(void);
14374 void frame_info_init(void);
14375
14376 frame_info_init();
14377 @@ -691,6 +692,11 @@
14378 pmc_yosemite_setup();
14379 break;
14380 #endif
14381 +#if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4310)
14382 + case MACH_GROUP_BRCM:
14383 + brcm_setup();
14384 + break;
14385 +#endif
14386 default:
14387 panic("Unsupported architecture");
14388 }
14389 diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c
14390 --- linux.old/arch/mips/kernel/traps.c 2005-11-07 23:12:50.922908250 +0100
14391 +++ linux.dev/arch/mips/kernel/traps.c 2005-11-07 21:57:07.893588750 +0100
14392 @@ -920,6 +920,7 @@
14393 void __init trap_init(void)
14394 {
14395 extern char except_vec1_generic;
14396 + extern char except_vec2_generic;
14397 extern char except_vec3_generic, except_vec3_r4000;
14398 extern char except_vec_ejtag_debug;
14399 extern char except_vec4;
14400 @@ -927,6 +928,7 @@
14401
14402 /* Copy the generic exception handler code to it's final destination. */
14403 memcpy((void *)(KSEG0 + 0x80), &except_vec1_generic, 0x80);
14404 + memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
14405
14406 /*
14407 * Setup default vectors
14408 @@ -985,6 +987,12 @@
14409 set_except_vector(13, handle_tr);
14410 set_except_vector(22, handle_mdmx);
14411
14412 + if (current_cpu_data.cputype == CPU_SB1) {
14413 + /* Enable timer interrupt and scd mapped interrupt */
14414 + clear_c0_status(0xf000);
14415 + set_c0_status(0xc00);
14416 + }
14417 +
14418 if (cpu_has_fpu && !cpu_has_nofpuex)
14419 set_except_vector(15, handle_fpe);
14420
14421 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
14422 --- linux.old/arch/mips/mm/c-r4k.c 2005-11-07 23:12:50.954910250 +0100
14423 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-11-07 21:57:08.157605250 +0100
14424 @@ -1166,3 +1166,47 @@
14425 build_clear_page();
14426 build_copy_page();
14427 }
14428 +
14429 +#ifdef CONFIG_BCM4704
14430 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
14431 +{
14432 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
14433 + int i;
14434 + for (i = 0; i < nbytes; i += ic_lsize)
14435 + fill_icache_line((addr + i));
14436 +}
14437 +
14438 +/*
14439 + * This must be run from the cache on 4704A0
14440 + * so there are no mips core BIU ops in progress
14441 + * when the PFC is enabled.
14442 + */
14443 +#define PFC_CR0 0xff400000 /* control reg 0 */
14444 +#define PFC_CR1 0xff400004 /* control reg 1 */
14445 +static void __init enable_pfc(u32 mode)
14446 +{
14447 + /* write range */
14448 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
14449 +
14450 + /* enable */
14451 + *(volatile u32 *)PFC_CR0 = mode;
14452 +}
14453 +#endif
14454 +
14455 +
14456 +void check_enable_mips_pfc(int val)
14457 +{
14458 +
14459 +#ifdef CONFIG_BCM4704
14460 + struct cpuinfo_mips *c = &current_cpu_data;
14461 +
14462 + /* enable prefetch cache */
14463 + if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
14464 + && (read_c0_diag() & (1 << 29))) {
14465 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
14466 + enable_pfc(val);
14467 + }
14468 +#endif
14469 +}
14470 +
14471 +
14472 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
14473 --- linux.old/arch/mips/pci/Makefile 2005-11-07 23:12:50.978911750 +0100
14474 +++ linux.dev/arch/mips/pci/Makefile 2005-11-07 21:57:07.897589000 +0100
14475 @@ -13,7 +13,9 @@
14476 obj-$(CONFIG_MIPS_MSC) += ops-msc.o
14477 obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o
14478 obj-$(CONFIG_SNI_RM200_PCI) += ops-sni.o
14479 +ifndef CONFIG_BCM947XX
14480 obj-y += pci.o
14481 +endif
14482 obj-$(CONFIG_PCI_AUTO) += pci_auto.o
14483
14484 include $(TOPDIR)/Rules.make
14485 diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c
14486 --- linux.old/drivers/char/serial.c 2005-11-07 23:12:51.038915500 +0100
14487 +++ linux.dev/drivers/char/serial.c 2005-11-07 21:57:07.901589250 +0100
14488 @@ -444,6 +444,10 @@
14489 return inb(info->port+1);
14490 #endif
14491 case SERIAL_IO_MEM:
14492 +#ifdef CONFIG_BCM4310
14493 + readb((unsigned long) info->iomem_base +
14494 + (UART_SCR<<info->iomem_reg_shift));
14495 +#endif
14496 return readb((unsigned long) info->iomem_base +
14497 (offset<<info->iomem_reg_shift));
14498 default:
14499 @@ -464,6 +468,9 @@
14500 case SERIAL_IO_MEM:
14501 writeb(value, (unsigned long) info->iomem_base +
14502 (offset<<info->iomem_reg_shift));
14503 +#ifdef CONFIG_BCM4704
14504 + *((volatile unsigned int *) KSEG1ADDR(0x18000000));
14505 +#endif
14506 break;
14507 default:
14508 outb(value, info->port+offset);
14509 @@ -1728,7 +1735,7 @@
14510 /* Special case since 134 is really 134.5 */
14511 quot = (2*baud_base / 269);
14512 else if (baud)
14513 - quot = baud_base / baud;
14514 + quot = (baud_base + (baud / 2)) / baud;
14515 }
14516 /* If the quotient is zero refuse the change */
14517 if (!quot && old_termios) {
14518 @@ -1745,12 +1752,12 @@
14519 /* Special case since 134 is really 134.5 */
14520 quot = (2*baud_base / 269);
14521 else if (baud)
14522 - quot = baud_base / baud;
14523 + quot = (baud_base + (baud / 2)) / baud;
14524 }
14525 }
14526 /* As a last resort, if the quotient is zero, default to 9600 bps */
14527 if (!quot)
14528 - quot = baud_base / 9600;
14529 + quot = (baud_base + 4800) / 9600;
14530 /*
14531 * Work around a bug in the Oxford Semiconductor 952 rev B
14532 * chip which causes it to seriously miscalculate baud rates
14533 @@ -5984,6 +5991,13 @@
14534 * Divisor, bytesize and parity
14535 */
14536 state = rs_table + co->index;
14537 + /*
14538 + * Safe guard: state structure must have been initialized
14539 + */
14540 + if (state->iomem_base == NULL) {
14541 + printk("!unable to setup serial console!\n");
14542 + return -1;
14543 + }
14544 if (doflow)
14545 state->flags |= ASYNC_CONS_FLOW;
14546 info = &async_sercons;
14547 @@ -5997,7 +6011,7 @@
14548 info->io_type = state->io_type;
14549 info->iomem_base = state->iomem_base;
14550 info->iomem_reg_shift = state->iomem_reg_shift;
14551 - quot = state->baud_base / baud;
14552 + quot = (state->baud_base + (baud / 2)) / baud;
14553 cval = cflag & (CSIZE | CSTOPB);
14554 #if defined(__powerpc__) || defined(__alpha__)
14555 cval >>= 8;
14556 diff -urN linux.old/drivers/mtd/maps/Config.in linux.dev/drivers/mtd/maps/Config.in
14557 --- linux.old/drivers/mtd/maps/Config.in 2005-11-07 23:12:51.086918500 +0100
14558 +++ linux.dev/drivers/mtd/maps/Config.in 2005-11-07 21:57:07.901589250 +0100
14559 @@ -48,6 +48,7 @@
14560 fi
14561
14562 if [ "$CONFIG_MIPS" = "y" ]; then
14563 + dep_tristate ' CFI Flash device mapped on Broadcom BCM947XX boards' CONFIG_MTD_BCM947XX $CONFIG_MTD_CFI
14564 dep_tristate ' Pb1000 MTD support' CONFIG_MTD_PB1000 $CONFIG_MIPS_PB1000
14565 dep_tristate ' Pb1500 MTD support' CONFIG_MTD_PB1500 $CONFIG_MIPS_PB1500
14566 dep_tristate ' Pb1100 MTD support' CONFIG_MTD_PB1100 $CONFIG_MIPS_PB1100
14567 diff -urN linux.old/drivers/mtd/maps/Makefile linux.dev/drivers/mtd/maps/Makefile
14568 --- linux.old/drivers/mtd/maps/Makefile 2005-11-07 23:12:51.086918500 +0100
14569 +++ linux.dev/drivers/mtd/maps/Makefile 2005-11-07 21:57:07.905589500 +0100
14570 @@ -3,6 +3,8 @@
14571 #
14572 # $Id: Makefile,v 1.37 2003/01/24 14:26:38 dwmw2 Exp $
14573
14574 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
14575 +
14576 BELOW25 := $(shell echo $(PATCHLEVEL) | sed s/[1234]/y/)
14577
14578 ifeq ($(BELOW25),y)
14579 @@ -10,6 +12,7 @@
14580 endif
14581
14582 # Chip mappings
14583 +obj-$(CONFIG_MTD_BCM947XX) += bcm947xx-flash.o
14584 obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
14585 obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
14586 obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
14587 diff -urN linux.old/drivers/mtd/maps/bcm947xx-flash.c linux.dev/drivers/mtd/maps/bcm947xx-flash.c
14588 --- linux.old/drivers/mtd/maps/bcm947xx-flash.c 1970-01-01 01:00:00.000000000 +0100
14589 +++ linux.dev/drivers/mtd/maps/bcm947xx-flash.c 2005-11-07 23:33:20.715765500 +0100
14590 @@ -0,0 +1,237 @@
14591 +/*
14592 + * Flash mapping for BCM947XX boards
14593 + *
14594 + * Copyright 2004, Broadcom Corporation
14595 + * All Rights Reserved.
14596 + *
14597 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14598 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14599 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14600 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14601 + *
14602 + * $Id: bcm947xx-flash.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
14603 + */
14604 +
14605 +#include <linux/module.h>
14606 +#include <linux/types.h>
14607 +#include <linux/kernel.h>
14608 +#include <asm/io.h>
14609 +#include <linux/mtd/mtd.h>
14610 +#include <linux/mtd/map.h>
14611 +#include <linux/mtd/partitions.h>
14612 +#include <linux/config.h>
14613 +
14614 +#include <osl.h>
14615 +#include <typedefs.h>
14616 +#include <bcmnvram.h>
14617 +#include <bcmutils.h>
14618 +#include <sbconfig.h>
14619 +#include <sbchipc.h>
14620 +#include <sbutils.h>
14621 +#include <trxhdr.h>
14622 +
14623 +/* Global SB handle */
14624 +extern void *bcm947xx_sbh;
14625 +extern spinlock_t bcm947xx_sbh_lock;
14626 +
14627 +/* Convenience */
14628 +#define sbh bcm947xx_sbh
14629 +#define sbh_lock bcm947xx_sbh_lock
14630 +
14631 +#ifdef CONFIG_MTD_PARTITIONS
14632 +extern struct mtd_partition * init_mtd_partitions(struct mtd_info *mtd, size_t size);
14633 +#endif
14634 +
14635 +#define WINDOW_ADDR 0x1fc00000
14636 +#define WINDOW_SIZE 0x400000
14637 +#define BUSWIDTH 2
14638 +
14639 +/* e.g., flash=2M or flash=4M */
14640 +static int flash = 0;
14641 +MODULE_PARM(flash, "i");
14642 +static int __init
14643 +bcm947xx_setup(char *str)
14644 +{
14645 + flash = memparse(str, &str);
14646 + return 1;
14647 +}
14648 +__setup("flash=", bcm947xx_setup);
14649 +
14650 +static struct mtd_info *bcm947xx_mtd;
14651 +
14652 +__u8 bcm947xx_map_read8(struct map_info *map, unsigned long ofs)
14653 +{
14654 + if (map->map_priv_2 == 1)
14655 + return __raw_readb(map->map_priv_1 + ofs);
14656 +
14657 + u16 val = __raw_readw(map->map_priv_1 + (ofs & ~1));
14658 + if (ofs & 1)
14659 + return ((val >> 8) & 0xff);
14660 + else
14661 + return (val & 0xff);
14662 +}
14663 +
14664 +__u16 bcm947xx_map_read16(struct map_info *map, unsigned long ofs)
14665 +{
14666 + return __raw_readw(map->map_priv_1 + ofs);
14667 +}
14668 +
14669 +__u32 bcm947xx_map_read32(struct map_info *map, unsigned long ofs)
14670 +{
14671 + return __raw_readl(map->map_priv_1 + ofs);
14672 +}
14673 +
14674 +void bcm947xx_map_copy_from(struct map_info *map, void *to, unsigned long from, ssize_t len)
14675 +{
14676 + if (len==1) {
14677 + memcpy_fromio(to, map->map_priv_1 + from, len);
14678 + } else {
14679 + int i;
14680 + u16 *dest = (u16 *) to;
14681 + u16 *src = (u16 *) (map->map_priv_1 + from);
14682 + for (i = 0; i < (len / 2); i++) {
14683 + dest[i] = src[i];
14684 + }
14685 + if (len & 1)
14686 + *((u8 *)dest+len-1) = src[i] & 0xff;
14687 + }
14688 +}
14689 +
14690 +void bcm947xx_map_write8(struct map_info *map, __u8 d, unsigned long adr)
14691 +{
14692 + __raw_writeb(d, map->map_priv_1 + adr);
14693 + mb();
14694 +}
14695 +
14696 +void bcm947xx_map_write16(struct map_info *map, __u16 d, unsigned long adr)
14697 +{
14698 + __raw_writew(d, map->map_priv_1 + adr);
14699 + mb();
14700 +}
14701 +
14702 +void bcm947xx_map_write32(struct map_info *map, __u32 d, unsigned long adr)
14703 +{
14704 + __raw_writel(d, map->map_priv_1 + adr);
14705 + mb();
14706 +}
14707 +
14708 +void bcm947xx_map_copy_to(struct map_info *map, unsigned long to, const void *from, ssize_t len)
14709 +{
14710 + memcpy_toio(map->map_priv_1 + to, from, len);
14711 +}
14712 +
14713 +struct map_info bcm947xx_map = {
14714 + name: "Physically mapped flash",
14715 + size: WINDOW_SIZE,
14716 + buswidth: BUSWIDTH,
14717 + read8: bcm947xx_map_read8,
14718 + read16: bcm947xx_map_read16,
14719 + read32: bcm947xx_map_read32,
14720 + copy_from: bcm947xx_map_copy_from,
14721 + write8: bcm947xx_map_write8,
14722 + write16: bcm947xx_map_write16,
14723 + write32: bcm947xx_map_write32,
14724 + copy_to: bcm947xx_map_copy_to
14725 +};
14726 +
14727 +#if LINUX_VERSION_CODE < 0x20212 && defined(MODULE)
14728 +#define init_bcm947xx_map init_module
14729 +#define cleanup_bcm947xx_map cleanup_module
14730 +#endif
14731 +
14732 +mod_init_t init_bcm947xx_map(void)
14733 +{
14734 + ulong flags;
14735 + uint coreidx;
14736 + chipcregs_t *cc;
14737 + uint32 fltype;
14738 + uint window_addr = 0, window_size = 0;
14739 + size_t size;
14740 + int ret = 0;
14741 +#ifdef CONFIG_MTD_PARTITIONS
14742 + struct mtd_partition *parts;
14743 + int i;
14744 +#endif
14745 +
14746 + spin_lock_irqsave(&sbh_lock, flags);
14747 + coreidx = sb_coreidx(sbh);
14748 +
14749 + /* Check strapping option if chipcommon exists */
14750 + if ((cc = sb_setcore(sbh, SB_CC, 0))) {
14751 + fltype = readl(&cc->capabilities) & CAP_FLASH_MASK;
14752 + if (fltype == PFLASH) {
14753 + bcm947xx_map.map_priv_2 = 1;
14754 + window_addr = 0x1c000000;
14755 + bcm947xx_map.size = window_size = 32 * 1024 * 1024;
14756 + if ((readl(&cc->flash_config) & CC_CFG_DS) == 0)
14757 + bcm947xx_map.buswidth = 1;
14758 + }
14759 + } else {
14760 + fltype = PFLASH;
14761 + bcm947xx_map.map_priv_2 = 0;
14762 + window_addr = WINDOW_ADDR;
14763 + window_size = WINDOW_SIZE;
14764 + }
14765 +
14766 + sb_setcoreidx(sbh, coreidx);
14767 + spin_unlock_irqrestore(&sbh_lock, flags);
14768 +
14769 + if (fltype != PFLASH) {
14770 + printk(KERN_ERR "pflash: found no supported devices\n");
14771 + ret = -ENODEV;
14772 + goto fail;
14773 + }
14774 +
14775 + bcm947xx_map.map_priv_1 = (unsigned long) ioremap(window_addr, window_size);
14776 + if (!bcm947xx_map.map_priv_1) {
14777 + printk(KERN_ERR "pflash: ioremap failed\n");
14778 + ret = -EIO;
14779 + goto fail;
14780 + }
14781 +
14782 + if (!(bcm947xx_mtd = do_map_probe("cfi_probe", &bcm947xx_map))) {
14783 + printk(KERN_ERR "pflash: cfi_probe failed\n");
14784 + ret = -ENXIO;
14785 + goto fail;
14786 + }
14787 +
14788 + bcm947xx_mtd->module = THIS_MODULE;
14789 +
14790 + /* Allow size override for testing */
14791 + size = flash ? : bcm947xx_mtd->size;
14792 +
14793 + printk(KERN_NOTICE "Flash device: 0x%x at 0x%x\n", size, window_addr);
14794 +
14795 +#ifdef CONFIG_MTD_PARTITIONS
14796 + parts = init_mtd_partitions(bcm947xx_mtd, size);
14797 + for (i = 0; parts[i].name; i++);
14798 + ret = add_mtd_partitions(bcm947xx_mtd, parts, i);
14799 + if (ret) {
14800 + printk(KERN_ERR "pflash: add_mtd_partitions failed\n");
14801 + goto fail;
14802 + }
14803 +#endif
14804 +
14805 + return 0;
14806 +
14807 + fail:
14808 + if (bcm947xx_mtd)
14809 + map_destroy(bcm947xx_mtd);
14810 + if (bcm947xx_map.map_priv_1)
14811 + iounmap((void *) bcm947xx_map.map_priv_1);
14812 + bcm947xx_map.map_priv_1 = 0;
14813 + return ret;
14814 +}
14815 +
14816 +mod_exit_t cleanup_bcm947xx_map(void)
14817 +{
14818 +#ifdef CONFIG_MTD_PARTITIONS
14819 + del_mtd_partitions(bcm947xx_mtd);
14820 +#endif
14821 + map_destroy(bcm947xx_mtd);
14822 + iounmap((void *) bcm947xx_map.map_priv_1);
14823 + bcm947xx_map.map_priv_1 = 0;
14824 +}
14825 +
14826 +module_init(init_bcm947xx_map);
14827 +module_exit(cleanup_bcm947xx_map);
14828 diff -urN linux.old/drivers/net/Config.in linux.dev/drivers/net/Config.in
14829 --- linux.old/drivers/net/Config.in 2005-11-07 23:12:51.110920000 +0100
14830 +++ linux.dev/drivers/net/Config.in 2005-11-07 21:57:07.905589500 +0100
14831 @@ -2,6 +2,8 @@
14832 # Network device configuration
14833 #
14834
14835 +tristate 'Broadcom Home Network Division' CONFIG_HND $CONFIG_PCI
14836 +
14837 source drivers/net/arcnet/Config.in
14838
14839 tristate 'Dummy net driver support' CONFIG_DUMMY
14840 @@ -174,6 +176,7 @@
14841
14842 dep_tristate ' Apricot Xen-II on board Ethernet' CONFIG_APRICOT $CONFIG_ISA
14843 dep_tristate ' Broadcom 4400 ethernet support (EXPERIMENTAL)' CONFIG_B44 $CONFIG_PCI $CONFIG_EXPERIMENTAL
14844 + dep_tristate ' Proprietary Broadcom 10/100 Ethernet support' CONFIG_ET $CONFIG_PCI
14845 dep_tristate ' CS89x0 support' CONFIG_CS89x0 $CONFIG_ISA
14846 dep_tristate ' DECchip Tulip (dc21x4x) PCI support' CONFIG_TULIP $CONFIG_PCI
14847 if [ "$CONFIG_TULIP" = "y" -o "$CONFIG_TULIP" = "m" ]; then
14848 diff -urN linux.old/drivers/net/Makefile linux.dev/drivers/net/Makefile
14849 --- linux.old/drivers/net/Makefile 2005-11-07 23:12:51.110920000 +0100
14850 +++ linux.dev/drivers/net/Makefile 2005-11-07 21:57:07.905589500 +0100
14851 @@ -3,6 +3,8 @@
14852 # Makefile for the Linux network (ethercard) device drivers.
14853 #
14854
14855 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include
14856 +
14857 obj-y :=
14858 obj-m :=
14859 obj-n :=
14860 @@ -39,6 +41,9 @@
14861 obj-$(CONFIG_ISDN) += slhc.o
14862 endif
14863
14864 +subdir-$(CONFIG_HND) += hnd
14865 +subdir-$(CONFIG_ET) += et
14866 +subdir-$(CONFIG_WL) += wl
14867 subdir-$(CONFIG_NET_PCMCIA) += pcmcia
14868 subdir-$(CONFIG_NET_WIRELESS) += wireless
14869 subdir-$(CONFIG_TULIP) += tulip
14870 @@ -69,6 +74,16 @@
14871 obj-$(CONFIG_MYRI_SBUS) += myri_sbus.o
14872 obj-$(CONFIG_SUNGEM) += sungem.o
14873
14874 +ifeq ($(CONFIG_HND),y)
14875 + obj-y += hnd/hnd.o
14876 +endif
14877 +ifeq ($(CONFIG_ET),y)
14878 + obj-y += et/et.o
14879 +endif
14880 +ifeq ($(CONFIG_WL),y)
14881 + obj-y += wl/wl.o
14882 +endif
14883 +
14884 obj-$(CONFIG_MACE) += mace.o
14885 obj-$(CONFIG_BMAC) += bmac.o
14886 obj-$(CONFIG_GMAC) += gmac.o
14887 @@ -266,6 +281,7 @@
14888 endif
14889 endif
14890
14891 +
14892 include $(TOPDIR)/Rules.make
14893
14894 clean:
14895 diff -urN linux.old/drivers/net/et/Makefile linux.dev/drivers/net/et/Makefile
14896 --- linux.old/drivers/net/et/Makefile 1970-01-01 01:00:00.000000000 +0100
14897 +++ linux.dev/drivers/net/et/Makefile 2005-11-07 21:57:07.905589500 +0100
14898 @@ -0,0 +1,21 @@
14899 +#
14900 +# Makefile for the Broadcom et driver
14901 +#
14902 +# Copyright 2004, Broadcom Corporation
14903 +# All Rights Reserved.
14904 +#
14905 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14906 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14907 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14908 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14909 +#
14910 +# $Id: Makefile,v 1.1 2005/03/16 13:50:00 wbx Exp $
14911 +#
14912 +
14913 +EXTRA_CFLAGS := -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCM47XX_CHOPS -DDMA -DBCMDRIVER
14914 +
14915 +O_TARGET := et.o
14916 +obj-y := et_linux.o etc.o etc47xx.o etc_robo.o etc_adm.o
14917 +obj-m := $(O_TARGET)
14918 +
14919 +include $(TOPDIR)/Rules.make
14920 diff -urN linux.old/drivers/net/hnd/Makefile linux.dev/drivers/net/hnd/Makefile
14921 --- linux.old/drivers/net/hnd/Makefile 1970-01-01 01:00:00.000000000 +0100
14922 +++ linux.dev/drivers/net/hnd/Makefile 2005-11-07 21:57:07.905589500 +0100
14923 @@ -0,0 +1,19 @@
14924 +#
14925 +# Makefile for the BCM47xx specific kernel interface routines
14926 +# under Linux.
14927 +#
14928 +
14929 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include -DBCMDRIVER
14930 +
14931 +O_TARGET := hnd.o
14932 +
14933 +HND_OBJS := bcmutils.o hnddma.o linux_osl.o sbutils.o bcmsrom.o
14934 +
14935 +export-objs := shared_ksyms.o
14936 +obj-y := shared_ksyms.o $(HND_OBJS)
14937 +obj-m := $(O_TARGET)
14938 +
14939 +include $(TOPDIR)/Rules.make
14940 +
14941 +shared_ksyms.c: shared_ksyms.sh $(HND_OBJS)
14942 + sh -e $< $(HND_OBJS) > $@
14943 diff -urN linux.old/drivers/net/hnd/bcmsrom.c linux.dev/drivers/net/hnd/bcmsrom.c
14944 --- linux.old/drivers/net/hnd/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
14945 +++ linux.dev/drivers/net/hnd/bcmsrom.c 2005-11-07 22:28:05.077337250 +0100
14946 @@ -0,0 +1,936 @@
14947 +/*
14948 + * Misc useful routines to access NIC SROM/OTP .
14949 + *
14950 + * Copyright 2005, Broadcom Corporation
14951 + * All Rights Reserved.
14952 + *
14953 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
14954 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
14955 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
14956 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
14957 + * $Id$
14958 + */
14959 +
14960 +#include <typedefs.h>
14961 +#include <osl.h>
14962 +#include <bcmutils.h>
14963 +#include <bcmsrom.h>
14964 +#include <bcmdevs.h>
14965 +#include <bcmendian.h>
14966 +#include <sbpcmcia.h>
14967 +#include <pcicfg.h>
14968 +#include <sbutils.h>
14969 +#include <bcmnvram.h>
14970 +
14971 +#include <proto/ethernet.h> /* for sprom content groking */
14972 +
14973 +#define VARS_MAX 4096 /* should be reduced */
14974 +
14975 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
14976 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
14977 +
14978 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
14979 +static int initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count);
14980 +static int initvars_flash_sb(void *sbh, char **vars, int *count);
14981 +static int srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count);
14982 +static int sprom_cmd_pcmcia(osl_t *osh, uint8 cmd);
14983 +static int sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data);
14984 +static int sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data);
14985 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
14986 +
14987 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
14988 +static int initvars_flash(osl_t *osh, char **vp, int len, char *devpath);
14989 +
14990 +/*
14991 + * Initialize local vars from the right source for this platform.
14992 + * Return 0 on success, nonzero on error.
14993 + */
14994 +int
14995 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
14996 +{
14997 + ASSERT(bustype == BUSTYPE(bustype));
14998 + if (vars == NULL || count == NULL)
14999 + return (0);
15000 +
15001 + switch (BUSTYPE(bustype)) {
15002 + case SB_BUS:
15003 + case JTAG_BUS:
15004 + return initvars_flash_sb(sbh, vars, count);
15005 +
15006 + case PCI_BUS:
15007 + ASSERT(curmap); /* can not be NULL */
15008 + return initvars_srom_pci(sbh, curmap, vars, count);
15009 +
15010 + case PCMCIA_BUS:
15011 + return initvars_cis_pcmcia(sbh, osh, vars, count);
15012 +
15013 +
15014 + default:
15015 + ASSERT(0);
15016 + }
15017 + return (-1);
15018 +}
15019 +
15020 +/* support only 16-bit word read from srom */
15021 +int
15022 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
15023 +{
15024 + void *srom;
15025 + uint i, off, nw;
15026 +
15027 + ASSERT(bustype == BUSTYPE(bustype));
15028 +
15029 + /* check input - 16-bit access only */
15030 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
15031 + return 1;
15032 +
15033 + off = byteoff / 2;
15034 + nw = nbytes / 2;
15035 +
15036 + if (BUSTYPE(bustype) == PCI_BUS) {
15037 + if (!curmap)
15038 + return 1;
15039 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
15040 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
15041 + return 1;
15042 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
15043 + for (i = 0; i < nw; i++) {
15044 + if (sprom_read_pcmcia(osh, (uint16)(off + i), (uint16*)(buf + i)))
15045 + return 1;
15046 + }
15047 + } else {
15048 + return 1;
15049 + }
15050 +
15051 + return 0;
15052 +}
15053 +
15054 +/* support only 16-bit word write into srom */
15055 +int
15056 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
15057 +{
15058 + uint16 *srom;
15059 + uint i, off, nw, crc_range;
15060 + uint16 image[SPROM_SIZE], *p;
15061 + uint8 crc;
15062 + volatile uint32 val32;
15063 +
15064 + ASSERT(bustype == BUSTYPE(bustype));
15065 +
15066 + /* check input - 16-bit access only */
15067 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
15068 + return 1;
15069 +
15070 + crc_range = (((BUSTYPE(bustype) == PCMCIA_BUS) || (BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
15071 +
15072 + /* if changes made inside crc cover range */
15073 + if (byteoff < crc_range) {
15074 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
15075 + /* read data including entire first 64 words from srom */
15076 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
15077 + return 1;
15078 + /* make changes */
15079 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
15080 + /* calculate crc */
15081 + htol16_buf(image, crc_range);
15082 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
15083 + ltoh16_buf(image, crc_range);
15084 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
15085 + p = image;
15086 + off = 0;
15087 + } else {
15088 + p = buf;
15089 + off = byteoff / 2;
15090 + nw = nbytes / 2;
15091 + }
15092 +
15093 + if (BUSTYPE(bustype) == PCI_BUS) {
15094 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
15095 + /* enable writes to the SPROM */
15096 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
15097 + val32 |= SPROM_WRITEEN;
15098 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
15099 + bcm_mdelay(WRITE_ENABLE_DELAY);
15100 + /* write srom */
15101 + for (i = 0; i < nw; i++) {
15102 + W_REG(&srom[off + i], p[i]);
15103 + bcm_mdelay(WRITE_WORD_DELAY);
15104 + }
15105 + /* disable writes to the SPROM */
15106 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
15107 + } else if (BUSTYPE(bustype) == PCMCIA_BUS) {
15108 + /* enable writes to the SPROM */
15109 + if (sprom_cmd_pcmcia(osh, SROM_WEN))
15110 + return 1;
15111 + bcm_mdelay(WRITE_ENABLE_DELAY);
15112 + /* write srom */
15113 + for (i = 0; i < nw; i++) {
15114 + sprom_write_pcmcia(osh, (uint16)(off + i), p[i]);
15115 + bcm_mdelay(WRITE_WORD_DELAY);
15116 + }
15117 + /* disable writes to the SPROM */
15118 + if (sprom_cmd_pcmcia(osh, SROM_WDS))
15119 + return 1;
15120 + } else {
15121 + return 1;
15122 + }
15123 +
15124 + bcm_mdelay(WRITE_ENABLE_DELAY);
15125 + return 0;
15126 +}
15127 +
15128 +
15129 +static int
15130 +srom_parsecis(osl_t *osh, uint8 *cis, char **vars, int *count)
15131 +{
15132 + char eabuf[32];
15133 + char *vp, *base;
15134 + uint8 tup, tlen, sromrev = 1;
15135 + int i, j;
15136 + uint varsize;
15137 + bool ag_init = FALSE;
15138 + uint32 w32;
15139 +
15140 + ASSERT(vars);
15141 + ASSERT(count);
15142 +
15143 + base = vp = MALLOC(osh, VARS_MAX);
15144 + ASSERT(vp);
15145 + if (!vp)
15146 + return -2;
15147 +
15148 + i = 0;
15149 + do {
15150 + tup = cis[i++];
15151 + tlen = cis[i++];
15152 + if ((i + tlen) >= CIS_SIZE)
15153 + break;
15154 +
15155 + switch (tup) {
15156 + case CISTPL_MANFID:
15157 + vp += sprintf(vp, "manfid=%d", (cis[i + 1] << 8) + cis[i]);
15158 + vp++;
15159 + vp += sprintf(vp, "prodid=%d", (cis[i + 3] << 8) + cis[i + 2]);
15160 + vp++;
15161 + break;
15162 +
15163 + case CISTPL_FUNCE:
15164 + if (cis[i] == LAN_NID) {
15165 + ASSERT(cis[i + 1] == ETHER_ADDR_LEN);
15166 + bcm_ether_ntoa((uchar*)&cis[i + 2], eabuf);
15167 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15168 + vp++;
15169 + }
15170 + break;
15171 +
15172 + case CISTPL_CFTABLE:
15173 + vp += sprintf(vp, "regwindowsz=%d", (cis[i + 7] << 8) | cis[i + 6]);
15174 + vp++;
15175 + break;
15176 +
15177 + case CISTPL_BRCM_HNBU:
15178 + switch (cis[i]) {
15179 + case HNBU_SROMREV:
15180 + sromrev = cis[i + 1];
15181 + break;
15182 +
15183 + case HNBU_CHIPID:
15184 + vp += sprintf(vp, "vendid=%d", (cis[i + 2] << 8) + cis[i + 1]);
15185 + vp++;
15186 + vp += sprintf(vp, "devid=%d", (cis[i + 4] << 8) + cis[i + 3]);
15187 + vp++;
15188 + if (tlen == 7) {
15189 + vp += sprintf(vp, "chiprev=%d", (cis[i + 6] << 8) + cis[i + 5]);
15190 + vp++;
15191 + }
15192 + break;
15193 +
15194 + case HNBU_BOARDREV:
15195 + vp += sprintf(vp, "boardrev=%d", cis[i + 1]);
15196 + vp++;
15197 + break;
15198 +
15199 + case HNBU_AA:
15200 + vp += sprintf(vp, "aa0=%d", cis[i + 1]);
15201 + vp++;
15202 + break;
15203 +
15204 + case HNBU_AG:
15205 + vp += sprintf(vp, "ag0=%d", cis[i + 1]);
15206 + vp++;
15207 + ag_init = TRUE;
15208 + break;
15209 +
15210 + case HNBU_CC:
15211 + ASSERT(sromrev > 1);
15212 + vp += sprintf(vp, "cc=%d", cis[i + 1]);
15213 + vp++;
15214 + break;
15215 +
15216 + case HNBU_PAPARMS:
15217 + if (tlen == 2) {
15218 + ASSERT(sromrev == 1);
15219 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 1]);
15220 + vp++;
15221 + } else if (tlen >= 9) {
15222 + if (tlen == 10) {
15223 + ASSERT(sromrev == 2);
15224 + vp += sprintf(vp, "opo=%d", cis[i + 9]);
15225 + vp++;
15226 + } else
15227 + ASSERT(tlen == 9);
15228 +
15229 + for (j = 0; j < 3; j++) {
15230 + vp += sprintf(vp, "pa0b%d=%d", j,
15231 + (cis[i + (j * 2) + 2] << 8) + cis[i + (j * 2) + 1]);
15232 + vp++;
15233 + }
15234 + vp += sprintf(vp, "pa0itssit=%d", cis[i + 7]);
15235 + vp++;
15236 + vp += sprintf(vp, "pa0maxpwr=%d", cis[i + 8]);
15237 + vp++;
15238 + } else
15239 + ASSERT(tlen >= 9);
15240 + break;
15241 +
15242 + case HNBU_OEM:
15243 + ASSERT(sromrev == 1);
15244 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15245 + cis[i + 1], cis[i + 2], cis[i + 3], cis[i + 4],
15246 + cis[i + 5], cis[i + 6], cis[i + 7], cis[i + 8]);
15247 + vp++;
15248 + break;
15249 +
15250 + case HNBU_BOARDFLAGS:
15251 + w32 = (cis[i + 2] << 8) + cis[i + 1];
15252 + if (tlen == 5)
15253 + w32 |= (cis[i + 4] << 24) + (cis[i + 3] << 16);
15254 + vp += sprintf(vp, "boardflags=0x%x", w32);
15255 + vp++;
15256 + break;
15257 +
15258 + case HNBU_LEDS:
15259 + if (cis[i + 1] != 0xff) {
15260 + vp += sprintf(vp, "wl0gpio0=%d", cis[i + 1]);
15261 + vp++;
15262 + }
15263 + if (cis[i + 2] != 0xff) {
15264 + vp += sprintf(vp, "wl0gpio1=%d", cis[i + 2]);
15265 + vp++;
15266 + }
15267 + if (cis[i + 3] != 0xff) {
15268 + vp += sprintf(vp, "wl0gpio2=%d", cis[i + 3]);
15269 + vp++;
15270 + }
15271 + if (cis[i + 4] != 0xff) {
15272 + vp += sprintf(vp, "wl0gpio3=%d", cis[i + 4]);
15273 + vp++;
15274 + }
15275 + break;
15276 +
15277 + case HNBU_CCODE:
15278 + ASSERT(sromrev > 1);
15279 + vp += sprintf(vp, "ccode=%c%c", cis[i + 1], cis[i + 2]);
15280 + vp++;
15281 + vp += sprintf(vp, "cctl=0x%x", cis[i + 3]);
15282 + vp++;
15283 + break;
15284 +
15285 + case HNBU_CCKPO:
15286 + ASSERT(sromrev > 2);
15287 + vp += sprintf(vp, "cckpo=0x%x", (cis[i + 2] << 8) | cis[i + 1]);
15288 + vp++;
15289 + break;
15290 +
15291 + case HNBU_OFDMPO:
15292 + ASSERT(sromrev > 2);
15293 + vp += sprintf(vp, "ofdmpo=0x%x", (cis[i + 4] << 24) |
15294 + (cis[i + 3] << 16) | (cis[i + 2] << 8) | cis[i + 1]);
15295 + vp++;
15296 + break;
15297 + }
15298 + break;
15299 +
15300 + }
15301 + i += tlen;
15302 + } while (tup != 0xff);
15303 +
15304 + /* Set the srom version */
15305 + vp += sprintf(vp, "sromrev=%d", sromrev);
15306 + vp++;
15307 +
15308 + /* if there is no antenna gain field, set default */
15309 + if (ag_init == FALSE) {
15310 + ASSERT(sromrev == 1);
15311 + vp += sprintf(vp, "ag0=%d", 0xff);
15312 + vp++;
15313 + }
15314 +
15315 + /* final nullbyte terminator */
15316 + *vp++ = '\0';
15317 + varsize = (uint)(vp - base);
15318 +
15319 + ASSERT((vp - base) < VARS_MAX);
15320 +
15321 + if (varsize == VARS_MAX) {
15322 + *vars = base;
15323 + } else {
15324 + vp = MALLOC(osh, varsize);
15325 + ASSERT(vp);
15326 + if (vp)
15327 + bcopy(base, vp, varsize);
15328 + MFREE(osh, base, VARS_MAX);
15329 + *vars = vp;
15330 + if (!vp) {
15331 + *count = 0;
15332 + return -2;
15333 + }
15334 + }
15335 + *count = varsize;
15336 +
15337 + return (0);
15338 +}
15339 +
15340 +
15341 +/* set PCMCIA sprom command register */
15342 +static int
15343 +sprom_cmd_pcmcia(osl_t *osh, uint8 cmd)
15344 +{
15345 + uint8 status = 0;
15346 + uint wait_cnt = 1000;
15347 +
15348 + /* write sprom command register */
15349 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_CS, &cmd, 1);
15350 +
15351 + /* wait status */
15352 + while (wait_cnt--) {
15353 + OSL_PCMCIA_READ_ATTR(osh, SROM_CS, &status, 1);
15354 + if (status & SROM_DONE)
15355 + return 0;
15356 + }
15357 +
15358 + return 1;
15359 +}
15360 +
15361 +/* read a word from the PCMCIA srom */
15362 +static int
15363 +sprom_read_pcmcia(osl_t *osh, uint16 addr, uint16 *data)
15364 +{
15365 + uint8 addr_l, addr_h, data_l, data_h;
15366 +
15367 + addr_l = (uint8)((addr * 2) & 0xff);
15368 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15369 +
15370 + /* set address */
15371 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15372 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15373 +
15374 + /* do read */
15375 + if (sprom_cmd_pcmcia(osh, SROM_READ))
15376 + return 1;
15377 +
15378 + /* read data */
15379 + data_h = data_l = 0;
15380 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAH, &data_h, 1);
15381 + OSL_PCMCIA_READ_ATTR(osh, SROM_DATAL, &data_l, 1);
15382 +
15383 + *data = (data_h << 8) | data_l;
15384 + return 0;
15385 +}
15386 +
15387 +/* write a word to the PCMCIA srom */
15388 +static int
15389 +sprom_write_pcmcia(osl_t *osh, uint16 addr, uint16 data)
15390 +{
15391 + uint8 addr_l, addr_h, data_l, data_h;
15392 +
15393 + addr_l = (uint8)((addr * 2) & 0xff);
15394 + addr_h = (uint8)(((addr * 2) >> 8) & 0xff);
15395 + data_l = (uint8)(data & 0xff);
15396 + data_h = (uint8)((data >> 8) & 0xff);
15397 +
15398 + /* set address */
15399 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRH, &addr_h, 1);
15400 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_ADDRL, &addr_l, 1);
15401 +
15402 + /* write data */
15403 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAH, &data_h, 1);
15404 + OSL_PCMCIA_WRITE_ATTR(osh, SROM_DATAL, &data_l, 1);
15405 +
15406 + /* do write */
15407 + return sprom_cmd_pcmcia(osh, SROM_WRITE);
15408 +}
15409 +
15410 +/*
15411 + * Read in and validate sprom.
15412 + * Return 0 on success, nonzero on error.
15413 + */
15414 +static int
15415 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
15416 +{
15417 + int err = 0;
15418 + uint i;
15419 +
15420 + /* read the sprom */
15421 + for (i = 0; i < nwords; i++)
15422 + buf[i] = R_REG(&sprom[wordoff + i]);
15423 +
15424 + if (check_crc) {
15425 + /* fixup the endianness so crc8 will pass */
15426 + htol16_buf(buf, nwords * 2);
15427 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
15428 + err = 1;
15429 + /* now correct the endianness of the byte array */
15430 + ltoh16_buf(buf, nwords * 2);
15431 + }
15432 +
15433 + return err;
15434 +}
15435 +
15436 +/*
15437 +* Create variable table from memory.
15438 +* Return 0 on success, nonzero on error.
15439 +*/
15440 +static int
15441 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
15442 +{
15443 + int c = (int)(end - start);
15444 +
15445 + /* do it only when there is more than just the null string */
15446 + if (c > 1) {
15447 + char *vp = MALLOC(osh, c);
15448 + ASSERT(vp);
15449 + if (!vp)
15450 + return BCME_NOMEM;
15451 + bcopy(start, vp, c);
15452 + *vars = vp;
15453 + *count = c;
15454 + }
15455 + else {
15456 + *vars = NULL;
15457 + *count = 0;
15458 + }
15459 +
15460 + return 0;
15461 +}
15462 +
15463 +/*
15464 +* Find variables with <devpath> from flash. 'base' points to the beginning
15465 +* of the table upon enter and to the end of the table upon exit when success.
15466 +* Return 0 on success, nonzero on error.
15467 +*/
15468 +static int
15469 +initvars_flash(osl_t *osh, char **base, int size, char *devpath)
15470 +{
15471 + char *vp = *base;
15472 + char *flash;
15473 + int err;
15474 + char *s;
15475 + uint l, dl, copy_len;
15476 +
15477 + /* allocate memory and read in flash */
15478 + if (!(flash = MALLOC(osh, NVRAM_SPACE)))
15479 + return BCME_NOMEM;
15480 + if ((err = BCMINIT(nvram_getall)(flash, NVRAM_SPACE)))
15481 + goto exit;
15482 +
15483 + /* grab vars with the <devpath> prefix in name */
15484 + dl = strlen(devpath);
15485 + for (s = flash; s && *s; s += l + 1) {
15486 + l = strlen(s);
15487 +
15488 + /* skip non-matching variable */
15489 + if (strncmp(s, devpath, dl))
15490 + continue;
15491 +
15492 + /* is there enough room to copy? */
15493 + copy_len = l - dl + 1;
15494 + if (size < (int)copy_len) {
15495 + err = BCME_BUFTOOSHORT;
15496 + goto exit;
15497 + }
15498 +
15499 + /* no prefix, just the name=value */
15500 + strcpy(vp, &s[dl]);
15501 + vp += copy_len;
15502 + size -= copy_len;
15503 + }
15504 +
15505 + /* add null string as terminator */
15506 + if (size < 1) {
15507 + err = BCME_BUFTOOSHORT;
15508 + goto exit;
15509 + }
15510 + *vp++ = '\0';
15511 +
15512 + *base = vp;
15513 +
15514 +exit: MFREE(osh, flash, NVRAM_SPACE);
15515 + return err;
15516 +}
15517 +
15518 +/*
15519 + * Initialize nonvolatile variable table from flash.
15520 + * Return 0 on success, nonzero on error.
15521 + */
15522 +static int
15523 +initvars_flash_sb(void *sbh, char **vars, int *count)
15524 +{
15525 + osl_t *osh = sb_osh(sbh);
15526 + char devpath[SB_DEVPATH_BUFSZ];
15527 + char *vp, *base;
15528 + int err;
15529 +
15530 + ASSERT(vars);
15531 + ASSERT(count);
15532 +
15533 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15534 + return err;
15535 +
15536 + base = vp = MALLOC(osh, VARS_MAX);
15537 + ASSERT(vp);
15538 + if (!vp)
15539 + return BCME_NOMEM;
15540 +
15541 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15542 + goto err;
15543 +
15544 + err = initvars_table(osh, base, vp, vars, count);
15545 +
15546 +err: MFREE(osh, base, VARS_MAX);
15547 + return err;
15548 +}
15549 +
15550 +/*
15551 + * Initialize nonvolatile variable table from sprom.
15552 + * Return 0 on success, nonzero on error.
15553 + */
15554 +static int
15555 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
15556 +{
15557 + uint16 w, b[64];
15558 + uint8 sromrev;
15559 + struct ether_addr ea;
15560 + char eabuf[32];
15561 + uint32 w32;
15562 + int woff, i;
15563 + char *vp, *base;
15564 + osl_t *osh = sb_osh(sbh);
15565 + bool flash = FALSE;
15566 + char name[SB_DEVPATH_BUFSZ+16], *value;
15567 + char devpath[SB_DEVPATH_BUFSZ];
15568 + int err;
15569 +
15570 + /*
15571 + * Apply CRC over SROM content regardless SROM is present or not,
15572 + * and use variable <devpath>sromrev's existance in flash to decide
15573 + * if we should return an error when CRC fails or read SROM variables
15574 + * from flash.
15575 + */
15576 + if (sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE)) {
15577 + if ((err = sb_devpath(sbh, devpath, sizeof(devpath))))
15578 + return err;
15579 + sprintf(name, "%ssromrev", devpath);
15580 + if (!(value = getvar(NULL, name)))
15581 + return (-1);
15582 + sromrev = (uint8)bcm_strtoul(value, NULL, 0);
15583 + flash = TRUE;
15584 + }
15585 + /* srom is good */
15586 + else {
15587 + /* top word of sprom contains version and crc8 */
15588 + sromrev = b[63] & 0xff;
15589 + /* bcm4401 sroms misprogrammed */
15590 + if (sromrev == 0x10)
15591 + sromrev = 1;
15592 + }
15593 +
15594 + /* srom version check */
15595 + if (sromrev > 3)
15596 + return (-2);
15597 +
15598 + ASSERT(vars);
15599 + ASSERT(count);
15600 +
15601 + base = vp = MALLOC(osh, VARS_MAX);
15602 + ASSERT(vp);
15603 + if (!vp)
15604 + return -2;
15605 +
15606 + /* read variables from flash */
15607 + if (flash) {
15608 + if ((err = initvars_flash(osh, &vp, VARS_MAX, devpath)))
15609 + goto err;
15610 + goto done;
15611 + }
15612 +
15613 + vp += sprintf(vp, "sromrev=%d", sromrev);
15614 + vp++;
15615 +
15616 + if (sromrev >= 3) {
15617 + /* New section takes over the 3th hardware function space */
15618 +
15619 + /* Words 22+23 are 11a (mid) ofdm power offsets */
15620 + w32 = ((uint32)b[23] << 16) | b[22];
15621 + vp += sprintf(vp, "ofdmapo=%d", w32);
15622 + vp++;
15623 +
15624 + /* Words 24+25 are 11a (low) ofdm power offsets */
15625 + w32 = ((uint32)b[25] << 16) | b[24];
15626 + vp += sprintf(vp, "ofdmalpo=%d", w32);
15627 + vp++;
15628 +
15629 + /* Words 26+27 are 11a (high) ofdm power offsets */
15630 + w32 = ((uint32)b[27] << 16) | b[26];
15631 + vp += sprintf(vp, "ofdmahpo=%d", w32);
15632 + vp++;
15633 +
15634 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15635 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
15636 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15637 +
15638 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
15639 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
15640 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
15641 + vp += sprintf(vp, "gpiotimerval=%d", w32);
15642 +
15643 + vp++;
15644 + }
15645 +
15646 + if (sromrev >= 2) {
15647 + /* New section takes over the 4th hardware function space */
15648 +
15649 + /* Word 29 is max power 11a high/low */
15650 + w = b[29];
15651 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
15652 + vp++;
15653 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
15654 + vp++;
15655 +
15656 + /* Words 30-32 set the 11alow pa settings,
15657 + * 33-35 are the 11ahigh ones.
15658 + */
15659 + for (i = 0; i < 3; i++) {
15660 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
15661 + vp++;
15662 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
15663 + vp++;
15664 + }
15665 + w = b[59];
15666 + if (w == 0)
15667 + vp += sprintf(vp, "ccode=");
15668 + else
15669 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
15670 + vp++;
15671 +
15672 + }
15673 +
15674 + /* parameter section of sprom starts at byte offset 72 */
15675 + woff = 72/2;
15676 +
15677 + /* first 6 bytes are il0macaddr */
15678 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15679 + ea.octet[1] = b[woff] & 0xff;
15680 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15681 + ea.octet[3] = b[woff+1] & 0xff;
15682 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15683 + ea.octet[5] = b[woff+2] & 0xff;
15684 + woff += ETHER_ADDR_LEN/2 ;
15685 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15686 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
15687 + vp++;
15688 +
15689 + /* next 6 bytes are et0macaddr */
15690 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15691 + ea.octet[1] = b[woff] & 0xff;
15692 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15693 + ea.octet[3] = b[woff+1] & 0xff;
15694 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15695 + ea.octet[5] = b[woff+2] & 0xff;
15696 + woff += ETHER_ADDR_LEN/2 ;
15697 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15698 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
15699 + vp++;
15700 +
15701 + /* next 6 bytes are et1macaddr */
15702 + ea.octet[0] = (b[woff] >> 8) & 0xff;
15703 + ea.octet[1] = b[woff] & 0xff;
15704 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
15705 + ea.octet[3] = b[woff+1] & 0xff;
15706 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
15707 + ea.octet[5] = b[woff+2] & 0xff;
15708 + woff += ETHER_ADDR_LEN/2 ;
15709 + bcm_ether_ntoa((uchar*)&ea, eabuf);
15710 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
15711 + vp++;
15712 +
15713 + /*
15714 + * Enet phy settings one or two singles or a dual
15715 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
15716 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
15717 + * Bit 14 : Mdio for enet0
15718 + * Bit 15 : Mdio for enet1
15719 + */
15720 + w = b[woff];
15721 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
15722 + vp++;
15723 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
15724 + vp++;
15725 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
15726 + vp++;
15727 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
15728 + vp++;
15729 +
15730 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
15731 + w = b[46];
15732 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
15733 + vp++;
15734 +
15735 + if (sromrev > 1)
15736 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
15737 + else
15738 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
15739 + vp++;
15740 +
15741 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
15742 + vp++;
15743 +
15744 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
15745 + vp++;
15746 +
15747 + /* Words 47-49 set the (wl) pa settings */
15748 + woff = 47;
15749 +
15750 + for (i = 0; i < 3; i++) {
15751 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
15752 + vp++;
15753 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
15754 + vp++;
15755 + }
15756 +
15757 + /*
15758 + * Words 50-51 set the customer-configured wl led behavior.
15759 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
15760 + * LED behavior values defined in wlioctl.h .
15761 + */
15762 + w = b[50];
15763 + if ((w != 0) && (w != 0xffff)) {
15764 + /* gpio0 */
15765 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
15766 + vp++;
15767 +
15768 + /* gpio1 */
15769 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
15770 + vp++;
15771 + }
15772 + w = b[51];
15773 + if ((w != 0) && (w != 0xffff)) {
15774 + /* gpio2 */
15775 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
15776 + vp++;
15777 +
15778 + /* gpio3 */
15779 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
15780 + vp++;
15781 + }
15782 +
15783 + /* Word 52 is max power 0/1 */
15784 + w = b[52];
15785 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
15786 + vp++;
15787 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
15788 + vp++;
15789 +
15790 + /* Word 56 is idle tssi target 0/1 */
15791 + w = b[56];
15792 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
15793 + vp++;
15794 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
15795 + vp++;
15796 +
15797 + /* Word 57 is boardflags, if not programmed make it zero */
15798 + w32 = (uint32)b[57];
15799 + if (w32 == 0xffff) w32 = 0;
15800 + if (sromrev > 1) {
15801 + /* Word 28 is the high bits of boardflags */
15802 + w32 |= (uint32)b[28] << 16;
15803 + }
15804 + vp += sprintf(vp, "boardflags=%d", w32);
15805 + vp++;
15806 +
15807 + /* Word 58 is antenna gain 0/1 */
15808 + w = b[58];
15809 + vp += sprintf(vp, "ag0=%d", w & 0xff);
15810 + vp++;
15811 +
15812 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
15813 + vp++;
15814 +
15815 + if (sromrev == 1) {
15816 + /* set the oem string */
15817 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
15818 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
15819 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
15820 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
15821 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
15822 + vp++;
15823 + } else if (sromrev == 2) {
15824 + /* Word 60 OFDM tx power offset from CCK level */
15825 + /* OFDM Power Offset - opo */
15826 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
15827 + vp++;
15828 + } else {
15829 + /* Word 60: cck power offsets */
15830 + vp += sprintf(vp, "cckpo=%d", b[60]);
15831 + vp++;
15832 +
15833 + /* Words 61+62: 11g ofdm power offsets */
15834 + w32 = ((uint32)b[62] << 16) | b[61];
15835 + vp += sprintf(vp, "ofdmgpo=%d", w32);
15836 + vp++;
15837 + }
15838 +
15839 + /* final nullbyte terminator */
15840 + *vp++ = '\0';
15841 +
15842 + ASSERT((vp - base) <= VARS_MAX);
15843 +
15844 +done: err = initvars_table(osh, base, vp, vars, count);
15845 +
15846 +err: MFREE(osh, base, VARS_MAX);
15847 + return err;
15848 +}
15849 +
15850 +/*
15851 + * Read the cis and call parsecis to initialize the vars.
15852 + * Return 0 on success, nonzero on error.
15853 + */
15854 +static int
15855 +initvars_cis_pcmcia(void *sbh, osl_t *osh, char **vars, int *count)
15856 +{
15857 + uint8 *cis = NULL;
15858 + int rc;
15859 + uint data_sz;
15860 +
15861 + data_sz = (sb_pcmciarev(sbh) == 1) ? (SPROM_SIZE * 2) : CIS_SIZE;
15862 +
15863 + if ((cis = MALLOC(osh, data_sz)) == NULL)
15864 + return (-2);
15865 +
15866 + if (sb_pcmciarev(sbh) == 1) {
15867 + if (srom_read(PCMCIA_BUS, (void *)NULL, osh, 0, data_sz, (uint16 *)cis)) {
15868 + MFREE(osh, cis, data_sz);
15869 + return (-1);
15870 + }
15871 + /* fix up endianess for 16-bit data vs 8-bit parsing */
15872 + ltoh16_buf((uint16 *)cis, data_sz);
15873 + } else
15874 + OSL_PCMCIA_READ_ATTR(osh, 0, cis, data_sz);
15875 +
15876 + rc = srom_parsecis(osh, cis, vars, count);
15877 +
15878 + MFREE(osh, cis, data_sz);
15879 +
15880 + return (rc);
15881 +}
15882 +
15883 diff -urN linux.old/drivers/net/hnd/bcmutils.c linux.dev/drivers/net/hnd/bcmutils.c
15884 --- linux.old/drivers/net/hnd/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
15885 +++ linux.dev/drivers/net/hnd/bcmutils.c 2005-11-08 12:52:21.836276500 +0100
15886 @@ -0,0 +1,1081 @@
15887 +/*
15888 + * Misc useful OS-independent routines.
15889 + *
15890 + * Copyright 2005, Broadcom Corporation
15891 + * All Rights Reserved.
15892 + *
15893 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
15894 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
15895 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
15896 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
15897 + * $Id$
15898 + */
15899 +
15900 +#include <typedefs.h>
15901 +#ifdef BCMDRIVER
15902 +#include <osl.h>
15903 +#include <sbutils.h>
15904 +#include <bcmnvram.h>
15905 +#else
15906 +#include <stdio.h>
15907 +#include <string.h>
15908 +#endif
15909 +#include <bcmutils.h>
15910 +#include <bcmendian.h>
15911 +#include <bcmdevs.h>
15912 +
15913 +#ifdef BCMDRIVER
15914 +/* copy a pkt buffer chain into a buffer */
15915 +uint
15916 +pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf)
15917 +{
15918 + uint n, ret = 0;
15919 +
15920 + if (len < 0)
15921 + len = 4096; /* "infinite" */
15922 +
15923 + /* skip 'offset' bytes */
15924 + for (; p && offset; p = PKTNEXT(osh, p)) {
15925 + if (offset < (uint)PKTLEN(osh, p))
15926 + break;
15927 + offset -= PKTLEN(osh, p);
15928 + }
15929 +
15930 + if (!p)
15931 + return 0;
15932 +
15933 + /* copy the data */
15934 + for (; p && len; p = PKTNEXT(osh, p)) {
15935 + n = MIN((uint)PKTLEN(osh, p) - offset, (uint)len);
15936 + bcopy(PKTDATA(osh, p) + offset, buf, n);
15937 + buf += n;
15938 + len -= n;
15939 + ret += n;
15940 + offset = 0;
15941 + }
15942 +
15943 + return ret;
15944 +}
15945 +
15946 +/* return total length of buffer chain */
15947 +uint
15948 +pkttotlen(osl_t *osh, void *p)
15949 +{
15950 + uint total;
15951 +
15952 + total = 0;
15953 + for (; p; p = PKTNEXT(osh, p))
15954 + total += PKTLEN(osh, p);
15955 + return (total);
15956 +}
15957 +
15958 +void
15959 +pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[])
15960 +{
15961 + q->head = q->tail = NULL;
15962 + q->maxlen = maxlen;
15963 + q->len = 0;
15964 + if (prio_map) {
15965 + q->priority = TRUE;
15966 + bcopy(prio_map, q->prio_map, sizeof(q->prio_map));
15967 + }
15968 + else
15969 + q->priority = FALSE;
15970 +}
15971 +
15972 +/* should always check pktq_full before calling pktenq */
15973 +void
15974 +pktenq(struct pktq *q, void *p, bool lifo)
15975 +{
15976 + void *next, *prev;
15977 +
15978 + /* allow 10 pkts slack */
15979 + ASSERT(q->len < (q->maxlen + 10));
15980 +
15981 + /* Queueing chains not allowed */
15982 + ASSERT(PKTLINK(p) == NULL);
15983 +
15984 + /* Queue is empty */
15985 + if (q->tail == NULL) {
15986 + ASSERT(q->head == NULL);
15987 + q->head = q->tail = p;
15988 + }
15989 +
15990 + /* Insert at head or tail */
15991 + else if (q->priority == FALSE) {
15992 + /* Insert at head (LIFO) */
15993 + if (lifo) {
15994 + PKTSETLINK(p, q->head);
15995 + q->head = p;
15996 + }
15997 + /* Insert at tail (FIFO) */
15998 + else {
15999 + ASSERT(PKTLINK(q->tail) == NULL);
16000 + PKTSETLINK(q->tail, p);
16001 + PKTSETLINK(p, NULL);
16002 + q->tail = p;
16003 + }
16004 + }
16005 +
16006 + /* Insert by priority */
16007 + else {
16008 + /* legal priorities 0-7 */
16009 + ASSERT(PKTPRIO(p) <= MAXPRIO);
16010 +
16011 + ASSERT(q->head);
16012 + ASSERT(q->tail);
16013 + /* Shortcut to insertion at tail */
16014 + if (_pktq_pri(q, PKTPRIO(p)) < _pktq_pri(q, PKTPRIO(q->tail)) ||
16015 + (!lifo && _pktq_pri(q, PKTPRIO(p)) <= _pktq_pri(q, PKTPRIO(q->tail)))) {
16016 + prev = q->tail;
16017 + next = NULL;
16018 + }
16019 + /* Insert at head or in the middle */
16020 + else {
16021 + prev = NULL;
16022 + next = q->head;
16023 + }
16024 + /* Walk the queue */
16025 + for (; next; prev = next, next = PKTLINK(next)) {
16026 + /* Priority queue invariant */
16027 + ASSERT(!prev || _pktq_pri(q, PKTPRIO(prev)) >= _pktq_pri(q, PKTPRIO(next)));
16028 + /* Insert at head of string of packets of same priority (LIFO) */
16029 + if (lifo) {
16030 + if (_pktq_pri(q, PKTPRIO(p)) >= _pktq_pri(q, PKTPRIO(next)))
16031 + break;
16032 + }
16033 + /* Insert at tail of string of packets of same priority (FIFO) */
16034 + else {
16035 + if (_pktq_pri(q, PKTPRIO(p)) > _pktq_pri(q, PKTPRIO(next)))
16036 + break;
16037 + }
16038 + }
16039 + /* Insert at tail */
16040 + if (next == NULL) {
16041 + ASSERT(PKTLINK(q->tail) == NULL);
16042 + PKTSETLINK(q->tail, p);
16043 + PKTSETLINK(p, NULL);
16044 + q->tail = p;
16045 + }
16046 + /* Insert in the middle */
16047 + else if (prev) {
16048 + PKTSETLINK(prev, p);
16049 + PKTSETLINK(p, next);
16050 + }
16051 + /* Insert at head */
16052 + else {
16053 + PKTSETLINK(p, q->head);
16054 + q->head = p;
16055 + }
16056 + }
16057 +
16058 + /* List invariants after insertion */
16059 + ASSERT(q->head);
16060 + ASSERT(PKTLINK(q->tail) == NULL);
16061 +
16062 + q->len++;
16063 +}
16064 +
16065 +/* dequeue packet at head */
16066 +void*
16067 +pktdeq(struct pktq *q)
16068 +{
16069 + void *p;
16070 +
16071 + if ((p = q->head)) {
16072 + ASSERT(q->tail);
16073 + q->head = PKTLINK(p);
16074 + PKTSETLINK(p, NULL);
16075 + q->len--;
16076 + if (q->head == NULL)
16077 + q->tail = NULL;
16078 + }
16079 + else {
16080 + ASSERT(q->tail == NULL);
16081 + }
16082 +
16083 + return (p);
16084 +}
16085 +
16086 +/* dequeue packet at tail */
16087 +void*
16088 +pktdeqtail(struct pktq *q)
16089 +{
16090 + void *p;
16091 + void *next, *prev;
16092 +
16093 + if (q->head == q->tail) { /* last packet on queue or queue empty */
16094 + p = q->head;
16095 + q->head = q->tail = NULL;
16096 + q->len = 0;
16097 + return(p);
16098 + }
16099 +
16100 + /* start walk at head */
16101 + prev = NULL;
16102 + next = q->head;
16103 +
16104 + /* Walk the queue to find prev of q->tail */
16105 + for (; next; prev = next, next = PKTLINK(next)) {
16106 + if (next == q->tail)
16107 + break;
16108 + }
16109 +
16110 + ASSERT(prev);
16111 +
16112 + PKTSETLINK(prev, NULL);
16113 + q->tail = prev;
16114 + q->len--;
16115 + p = next;
16116 +
16117 + return (p);
16118 +}
16119 +
16120 +unsigned char bcm_ctype[] = {
16121 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
16122 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
16123 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
16124 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
16125 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
16126 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
16127 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
16128 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
16129 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
16130 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
16131 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
16132 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
16133 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
16134 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
16135 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
16136 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
16137 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
16138 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
16139 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
16140 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
16141 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
16142 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
16143 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
16144 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
16145 +};
16146 +
16147 +uchar
16148 +bcm_toupper(uchar c)
16149 +{
16150 + if (bcm_islower(c))
16151 + c -= 'a'-'A';
16152 + return (c);
16153 +}
16154 +
16155 +ulong
16156 +bcm_strtoul(char *cp, char **endp, uint base)
16157 +{
16158 + ulong result, value;
16159 + bool minus;
16160 +
16161 + minus = FALSE;
16162 +
16163 + while (bcm_isspace(*cp))
16164 + cp++;
16165 +
16166 + if (cp[0] == '+')
16167 + cp++;
16168 + else if (cp[0] == '-') {
16169 + minus = TRUE;
16170 + cp++;
16171 + }
16172 +
16173 + if (base == 0) {
16174 + if (cp[0] == '0') {
16175 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
16176 + base = 16;
16177 + cp = &cp[2];
16178 + } else {
16179 + base = 8;
16180 + cp = &cp[1];
16181 + }
16182 + } else
16183 + base = 10;
16184 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
16185 + cp = &cp[2];
16186 + }
16187 +
16188 + result = 0;
16189 +
16190 + while (bcm_isxdigit(*cp) &&
16191 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
16192 + result = result*base + value;
16193 + cp++;
16194 + }
16195 +
16196 + if (minus)
16197 + result = (ulong)(result * -1);
16198 +
16199 + if (endp)
16200 + *endp = (char *)cp;
16201 +
16202 + return (result);
16203 +}
16204 +
16205 +uint
16206 +bcm_atoi(char *s)
16207 +{
16208 + uint n;
16209 +
16210 + n = 0;
16211 +
16212 + while (bcm_isdigit(*s))
16213 + n = (n * 10) + *s++ - '0';
16214 + return (n);
16215 +}
16216 +
16217 +/* return pointer to location of substring 'needle' in 'haystack' */
16218 +char*
16219 +bcmstrstr(char *haystack, char *needle)
16220 +{
16221 + int len, nlen;
16222 + int i;
16223 +
16224 + if ((haystack == NULL) || (needle == NULL))
16225 + return (haystack);
16226 +
16227 + nlen = strlen(needle);
16228 + len = strlen(haystack) - nlen + 1;
16229 +
16230 + for (i = 0; i < len; i++)
16231 + if (bcmp(needle, &haystack[i], nlen) == 0)
16232 + return (&haystack[i]);
16233 + return (NULL);
16234 +}
16235 +
16236 +char*
16237 +bcmstrcat(char *dest, const char *src)
16238 +{
16239 + strcpy(&dest[strlen(dest)], src);
16240 + return (dest);
16241 +}
16242 +
16243 +#if defined(CONFIG_USBRNDIS_RETAIL) || defined(NDIS_MINIPORT_DRIVER)
16244 +/* registry routine buffer preparation utility functions:
16245 + * parameter order is like strncpy, but returns count
16246 + * of bytes copied. Minimum bytes copied is null char(1)/wchar(2)
16247 + */
16248 +ulong
16249 +wchar2ascii(
16250 + char *abuf,
16251 + ushort *wbuf,
16252 + ushort wbuflen,
16253 + ulong abuflen
16254 +)
16255 +{
16256 + ulong copyct = 1;
16257 + ushort i;
16258 +
16259 + if (abuflen == 0)
16260 + return 0;
16261 +
16262 + /* wbuflen is in bytes */
16263 + wbuflen /= sizeof(ushort);
16264 +
16265 + for (i = 0; i < wbuflen; ++i) {
16266 + if (--abuflen == 0)
16267 + break;
16268 + *abuf++ = (char) *wbuf++;
16269 + ++copyct;
16270 + }
16271 + *abuf = '\0';
16272 +
16273 + return copyct;
16274 +}
16275 +#endif
16276 +
16277 +char*
16278 +bcm_ether_ntoa(char *ea, char *buf)
16279 +{
16280 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
16281 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
16282 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
16283 + return (buf);
16284 +}
16285 +
16286 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
16287 +int
16288 +bcm_ether_atoe(char *p, char *ea)
16289 +{
16290 + int i = 0;
16291 +
16292 + for (;;) {
16293 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
16294 + if (!*p++ || i == 6)
16295 + break;
16296 + }
16297 +
16298 + return (i == 6);
16299 +}
16300 +
16301 +void
16302 +bcm_mdelay(uint ms)
16303 +{
16304 + uint i;
16305 +
16306 + for (i = 0; i < ms; i++) {
16307 + OSL_DELAY(1000);
16308 + }
16309 +}
16310 +
16311 +/*
16312 + * Search the name=value vars for a specific one and return its value.
16313 + * Returns NULL if not found.
16314 + */
16315 +char*
16316 +getvar(char *vars, char *name)
16317 +{
16318 + char *s;
16319 + int len;
16320 +
16321 + len = strlen(name);
16322 +
16323 + /* first look in vars[] */
16324 + for (s = vars; s && *s; ) {
16325 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
16326 + return (&s[len+1]);
16327 +
16328 + while (*s++)
16329 + ;
16330 + }
16331 +
16332 + /* then query nvram */
16333 + return (BCMINIT(nvram_get)(name));
16334 +}
16335 +
16336 +/*
16337 + * Search the vars for a specific one and return its value as
16338 + * an integer. Returns 0 if not found.
16339 + */
16340 +int
16341 +getintvar(char *vars, char *name)
16342 +{
16343 + char *val;
16344 +
16345 + if ((val = getvar(vars, name)) == NULL)
16346 + return (0);
16347 +
16348 + return (bcm_strtoul(val, NULL, 0));
16349 +}
16350 +
16351 +
16352 +/* Search for token in comma separated token-string */
16353 +static int
16354 +findmatch(char *string, char *name)
16355 +{
16356 + uint len;
16357 + char *c;
16358 +
16359 + len = strlen(name);
16360 + while ((c = strchr(string, ',')) != NULL) {
16361 + if (len == (uint)(c - string) && !strncmp(string, name, len))
16362 + return 1;
16363 + string = c + 1;
16364 + }
16365 +
16366 + return (!strcmp(string, name));
16367 +}
16368 +
16369 +/* Return gpio pin number assigned to the named pin */
16370 +/*
16371 +* Variable should be in format:
16372 +*
16373 +* gpio<N>=pin_name,pin_name
16374 +*
16375 +* This format allows multiple features to share the gpio with mutual
16376 +* understanding.
16377 +*
16378 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
16379 +* and if def_pin is not used by others.
16380 +*/
16381 +uint
16382 +getgpiopin(char *vars, char *pin_name, uint def_pin)
16383 +{
16384 + char name[] = "gpioXXXX";
16385 + char *val;
16386 + uint pin;
16387 +
16388 + /* Go thru all possibilities till a match in pin name */
16389 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
16390 + sprintf(name, "gpio%d", pin);
16391 + val = getvar(vars, name);
16392 + if (val && findmatch(val, pin_name))
16393 + return pin;
16394 + }
16395 +
16396 + if (def_pin != GPIO_PIN_NOTDEFINED) {
16397 + /* make sure the default pin is not used by someone else */
16398 + sprintf(name, "gpio%d", def_pin);
16399 + if (getvar(vars, name)) {
16400 + def_pin = GPIO_PIN_NOTDEFINED;
16401 + }
16402 + }
16403 +
16404 + return def_pin;
16405 +}
16406 +
16407 +
16408 +static char bcm_undeferrstr[BCME_STRLEN];
16409 +
16410 +static const char *bcmerrorstrtable[] = \
16411 +{ "OK", /* 0 */
16412 + "Undefined error", /* BCME_ERROR */
16413 + "Bad Argument", /* BCME_BADARG*/
16414 + "Bad Option", /* BCME_BADOPTION*/
16415 + "Not up", /* BCME_NOTUP */
16416 + "Not down", /* BCME_NOTDOWN */
16417 + "Not AP", /* BCME_NOTAP */
16418 + "Not STA", /* BCME_NOTSTA */
16419 + "Bad Key Index", /* BCME_BADKEYIDX */
16420 + "Radio Off", /* BCME_RADIOOFF */
16421 + "Not band locked", /* BCME_NOTBANDLOCKED */
16422 + "No clock", /* BCME_NOCLK */
16423 + "Bad Rate valueset", /* BCME_BADRATESET */
16424 + "Bad Band", /* BCME_BADBAND */
16425 + "Buffer too short", /* BCME_BUFTOOSHORT */
16426 + "Buffer too length", /* BCME_BUFTOOLONG */
16427 + "Busy", /* BCME_BUSY */
16428 + "Not Associated", /* BCME_NOTASSOCIATED */
16429 + "Bad SSID len", /* BCME_BADSSIDLEN */
16430 + "Out of Range Channel", /* BCME_OUTOFRANGECHAN */
16431 + "Bad Channel", /* BCME_BADCHAN */
16432 + "Bad Address", /* BCME_BADADDR */
16433 + "Not Enough Resources", /* BCME_NORESOURCE */
16434 + "Unsupported", /* BCME_UNSUPPORTED */
16435 + "Bad length", /* BCME_BADLENGTH */
16436 + "Not Ready", /* BCME_NOTREADY */
16437 + "Not Permitted", /* BCME_EPERM */
16438 + "No Memory", /* BCME_NOMEM */
16439 + "Associated", /* BCME_ASSOCIATED */
16440 + "Not In Range", /* BCME_RANGE */
16441 + "Not Found" /* BCME_NOTFOUND */
16442 + };
16443 +
16444 +/* Convert the Error codes into related Error strings */
16445 +const char *
16446 +bcmerrorstr(int bcmerror)
16447 +{
16448 + int abs_bcmerror;
16449 +
16450 + abs_bcmerror = ABS(bcmerror);
16451 +
16452 + /* check if someone added a bcmerror code but forgot to add errorstring */
16453 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(bcmerrorstrtable) - 1));
16454 + if ( (bcmerror > 0) || (abs_bcmerror > ABS(BCME_LAST))) {
16455 + sprintf(bcm_undeferrstr, "undefined Error %d", bcmerror);
16456 + return bcm_undeferrstr;
16457 + }
16458 +
16459 + ASSERT((strlen((char*)bcmerrorstrtable[abs_bcmerror])) < BCME_STRLEN);
16460 +
16461 + return bcmerrorstrtable[abs_bcmerror];
16462 +}
16463 +#endif /* #ifdef BCMDRIVER */
16464 +
16465 +
16466 +/*******************************************************************************
16467 + * crc8
16468 + *
16469 + * Computes a crc8 over the input data using the polynomial:
16470 + *
16471 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
16472 + *
16473 + * The caller provides the initial value (either CRC8_INIT_VALUE
16474 + * or the previous returned value) to allow for processing of
16475 + * discontiguous blocks of data. When generating the CRC the
16476 + * caller is responsible for complementing the final return value
16477 + * and inserting it into the byte stream. When checking, a final
16478 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
16479 + *
16480 + * Reference: Dallas Semiconductor Application Note 27
16481 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16482 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16483 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16484 + *
16485 + ******************************************************************************/
16486 +
16487 +static uint8 crc8_table[256] = {
16488 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
16489 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
16490 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
16491 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
16492 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
16493 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
16494 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
16495 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
16496 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
16497 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
16498 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
16499 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
16500 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
16501 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
16502 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
16503 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
16504 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
16505 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
16506 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
16507 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
16508 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
16509 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
16510 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
16511 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
16512 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
16513 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
16514 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
16515 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
16516 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
16517 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
16518 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
16519 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
16520 +};
16521 +
16522 +#define CRC_INNER_LOOP(n, c, x) \
16523 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
16524 +
16525 +uint8
16526 +hndcrc8(
16527 + uint8 *pdata, /* pointer to array of data to process */
16528 + uint nbytes, /* number of input data bytes to process */
16529 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
16530 +)
16531 +{
16532 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
16533 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
16534 + while (nbytes-- > 0)
16535 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
16536 +
16537 + return crc;
16538 +}
16539 +
16540 +/*******************************************************************************
16541 + * crc16
16542 + *
16543 + * Computes a crc16 over the input data using the polynomial:
16544 + *
16545 + * x^16 + x^12 +x^5 + 1
16546 + *
16547 + * The caller provides the initial value (either CRC16_INIT_VALUE
16548 + * or the previous returned value) to allow for processing of
16549 + * discontiguous blocks of data. When generating the CRC the
16550 + * caller is responsible for complementing the final return value
16551 + * and inserting it into the byte stream. When checking, a final
16552 + * return value of CRC16_GOOD_VALUE indicates a valid CRC.
16553 + *
16554 + * Reference: Dallas Semiconductor Application Note 27
16555 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
16556 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
16557 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
16558 + *
16559 + ******************************************************************************/
16560 +
16561 +static uint16 crc16_table[256] = {
16562 + 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
16563 + 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
16564 + 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
16565 + 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
16566 + 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
16567 + 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
16568 + 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
16569 + 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
16570 + 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
16571 + 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
16572 + 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
16573 + 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
16574 + 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
16575 + 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
16576 + 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
16577 + 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
16578 + 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
16579 + 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
16580 + 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
16581 + 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
16582 + 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
16583 + 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
16584 + 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
16585 + 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
16586 + 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
16587 + 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
16588 + 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
16589 + 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
16590 + 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
16591 + 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
16592 + 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
16593 + 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
16594 +};
16595 +
16596 +uint16
16597 +hndcrc16(
16598 + uint8 *pdata, /* pointer to array of data to process */
16599 + uint nbytes, /* number of input data bytes to process */
16600 + uint16 crc /* either CRC16_INIT_VALUE or previous return value */
16601 +)
16602 +{
16603 + while (nbytes-- > 0)
16604 + CRC_INNER_LOOP(16, crc, *pdata++);
16605 + return crc;
16606 +}
16607 +
16608 +static uint32 crc32_table[256] = {
16609 + 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
16610 + 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
16611 + 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
16612 + 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
16613 + 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
16614 + 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
16615 + 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
16616 + 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
16617 + 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
16618 + 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
16619 + 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
16620 + 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
16621 + 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
16622 + 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
16623 + 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
16624 + 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
16625 + 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
16626 + 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
16627 + 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
16628 + 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
16629 + 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
16630 + 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
16631 + 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
16632 + 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
16633 + 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
16634 + 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
16635 + 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
16636 + 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
16637 + 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
16638 + 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
16639 + 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
16640 + 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
16641 + 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
16642 + 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
16643 + 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
16644 + 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
16645 + 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
16646 + 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
16647 + 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
16648 + 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
16649 + 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
16650 + 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
16651 + 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
16652 + 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
16653 + 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
16654 + 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
16655 + 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
16656 + 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
16657 + 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
16658 + 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
16659 + 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
16660 + 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
16661 + 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
16662 + 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
16663 + 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
16664 + 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
16665 + 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
16666 + 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
16667 + 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
16668 + 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
16669 + 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
16670 + 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
16671 + 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
16672 + 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
16673 +};
16674 +
16675 +uint32
16676 +hndcrc32(
16677 + uint8 *pdata, /* pointer to array of data to process */
16678 + uint nbytes, /* number of input data bytes to process */
16679 + uint32 crc /* either CRC32_INIT_VALUE or previous return value */
16680 +)
16681 +{
16682 + uint8 *pend;
16683 +#ifdef __mips__
16684 + uint8 tmp[4];
16685 + ulong *tptr = (ulong *)tmp;
16686 +
16687 + /* in case the beginning of the buffer isn't aligned */
16688 + pend = (uint8 *)((uint)(pdata + 3) & 0xfffffffc);
16689 + nbytes -= (pend - pdata);
16690 + while (pdata < pend)
16691 + CRC_INNER_LOOP(32, crc, *pdata++);
16692 +
16693 + /* handle bulk of data as 32-bit words */
16694 + pend = pdata + (nbytes & 0xfffffffc);
16695 + while (pdata < pend) {
16696 + tptr = *((ulong *) pdata);
16697 + *((ulong *) pdata) += 1;
16698 + CRC_INNER_LOOP(32, crc, tmp[0]);
16699 + CRC_INNER_LOOP(32, crc, tmp[1]);
16700 + CRC_INNER_LOOP(32, crc, tmp[2]);
16701 + CRC_INNER_LOOP(32, crc, tmp[3]);
16702 + }
16703 +
16704 + /* 1-3 bytes at end of buffer */
16705 + pend = pdata + (nbytes & 0x03);
16706 + while (pdata < pend)
16707 + CRC_INNER_LOOP(32, crc, *pdata++);
16708 +#else
16709 + pend = pdata + nbytes;
16710 + while (pdata < pend)
16711 + CRC_INNER_LOOP(32, crc, *pdata++);
16712 +#endif
16713 +
16714 + return crc;
16715 +}
16716 +
16717 +#ifdef notdef
16718 +#define CLEN 1499
16719 +#define CBUFSIZ (CLEN+4)
16720 +#define CNBUFS 5
16721 +
16722 +void testcrc32(void)
16723 +{
16724 + uint j,k,l;
16725 + uint8 *buf;
16726 + uint len[CNBUFS];
16727 + uint32 crcr;
16728 + uint32 crc32tv[CNBUFS] =
16729 + {0xd2cb1faa, 0xd385c8fa, 0xf5b4f3f3, 0x55789e20, 0x00343110};
16730 +
16731 + ASSERT((buf = MALLOC(CBUFSIZ*CNBUFS)) != NULL);
16732 +
16733 + /* step through all possible alignments */
16734 + for (l=0;l<=4;l++) {
16735 + for (j=0; j<CNBUFS; j++) {
16736 + len[j] = CLEN;
16737 + for (k=0; k<len[j]; k++)
16738 + *(buf + j*CBUFSIZ + (k+l)) = (j+k) & 0xff;
16739 + }
16740 +
16741 + for (j=0; j<CNBUFS; j++) {
16742 + crcr = crc32(buf + j*CBUFSIZ + l, len[j], CRC32_INIT_VALUE);
16743 + ASSERT(crcr == crc32tv[j]);
16744 + }
16745 + }
16746 +
16747 + MFREE(buf, CBUFSIZ*CNBUFS);
16748 + return;
16749 +}
16750 +#endif
16751 +
16752 +
16753 +/*
16754 + * Advance from the current 1-byte tag/1-byte length/variable-length value
16755 + * triple, to the next, returning a pointer to the next.
16756 + * If the current or next TLV is invalid (does not fit in given buffer length),
16757 + * NULL is returned.
16758 + * *buflen is not modified if the TLV elt parameter is invalid, or is decremented
16759 + * by the TLV paramter's length if it is valid.
16760 + */
16761 +bcm_tlv_t *
16762 +bcm_next_tlv(bcm_tlv_t *elt, int *buflen)
16763 +{
16764 + int len;
16765 +
16766 + /* validate current elt */
16767 + if (!bcm_valid_tlv(elt, *buflen))
16768 + return NULL;
16769 +
16770 + /* advance to next elt */
16771 + len = elt->len;
16772 + elt = (bcm_tlv_t*)(elt->data + len);
16773 + *buflen -= (2 + len);
16774 +
16775 + /* validate next elt */
16776 + if (!bcm_valid_tlv(elt, *buflen))
16777 + return NULL;
16778 +
16779 + return elt;
16780 +}
16781 +
16782 +/*
16783 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16784 + * triples, returning a pointer to the substring whose first element
16785 + * matches tag
16786 + */
16787 +bcm_tlv_t *
16788 +bcm_parse_tlvs(void *buf, int buflen, uint key)
16789 +{
16790 + bcm_tlv_t *elt;
16791 + int totlen;
16792 +
16793 + elt = (bcm_tlv_t*)buf;
16794 + totlen = buflen;
16795 +
16796 + /* find tagged parameter */
16797 + while (totlen >= 2) {
16798 + int len = elt->len;
16799 +
16800 + /* validate remaining totlen */
16801 + if ((elt->id == key) && (totlen >= (len + 2)))
16802 + return (elt);
16803 +
16804 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16805 + totlen -= (len + 2);
16806 + }
16807 +
16808 + return NULL;
16809 +}
16810 +
16811 +/*
16812 + * Traverse a string of 1-byte tag/1-byte length/variable-length value
16813 + * triples, returning a pointer to the substring whose first element
16814 + * matches tag. Stop parsing when we see an element whose ID is greater
16815 + * than the target key.
16816 + */
16817 +bcm_tlv_t *
16818 +bcm_parse_ordered_tlvs(void *buf, int buflen, uint key)
16819 +{
16820 + bcm_tlv_t *elt;
16821 + int totlen;
16822 +
16823 + elt = (bcm_tlv_t*)buf;
16824 + totlen = buflen;
16825 +
16826 + /* find tagged parameter */
16827 + while (totlen >= 2) {
16828 + uint id = elt->id;
16829 + int len = elt->len;
16830 +
16831 + /* Punt if we start seeing IDs > than target key */
16832 + if (id > key)
16833 + return(NULL);
16834 +
16835 + /* validate remaining totlen */
16836 + if ((id == key) && (totlen >= (len + 2)))
16837 + return (elt);
16838 +
16839 + elt = (bcm_tlv_t*)((uint8*)elt + (len + 2));
16840 + totlen -= (len + 2);
16841 + }
16842 + return NULL;
16843 +}
16844 +/* routine to dump fields in a fileddesc structure */
16845 +
16846 +uint
16847 +bcmdumpfields(readreg_rtn read_rtn, void *arg0, void *arg1, struct fielddesc *fielddesc_array, char *buf, uint32 bufsize)
16848 +{
16849 + uint filled_len;
16850 + uint len;
16851 + struct fielddesc *cur_ptr;
16852 +
16853 + filled_len = 0;
16854 + cur_ptr = fielddesc_array;
16855 +
16856 + while (bufsize > (filled_len + 64)) {
16857 + if (cur_ptr->nameandfmt == NULL)
16858 + break;
16859 + len = sprintf(buf, cur_ptr->nameandfmt, read_rtn(arg0, arg1, cur_ptr->offset));
16860 + buf += len;
16861 + filled_len += len;
16862 + cur_ptr++;
16863 + }
16864 + return filled_len;
16865 +}
16866 +
16867 +uint
16868 +bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
16869 +{
16870 + uint len;
16871 +
16872 + len = strlen(name) + 1;
16873 +
16874 + if ((len + datalen) > buflen)
16875 + return 0;
16876 +
16877 + strcpy(buf, name);
16878 +
16879 + /* append data onto the end of the name string */
16880 + memcpy(&buf[len], data, datalen);
16881 + len += datalen;
16882 +
16883 + return len;
16884 +}
16885 +
16886 +/* Quarter dBm units to mW
16887 + * Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
16888 + * Table is offset so the last entry is largest mW value that fits in
16889 + * a uint16.
16890 + */
16891 +
16892 +#define QDBM_OFFSET 153
16893 +#define QDBM_TABLE_LEN 40
16894 +
16895 +/* Smallest mW value that will round up to the first table entry, QDBM_OFFSET.
16896 + * Value is ( mW(QDBM_OFFSET - 1) + mW(QDBM_OFFSET) ) / 2
16897 + */
16898 +#define QDBM_TABLE_LOW_BOUND 6493
16899 +
16900 +/* Largest mW value that will round down to the last table entry,
16901 + * QDBM_OFFSET + QDBM_TABLE_LEN-1.
16902 + * Value is ( mW(QDBM_OFFSET + QDBM_TABLE_LEN - 1) + mW(QDBM_OFFSET + QDBM_TABLE_LEN) ) / 2.
16903 + */
16904 +#define QDBM_TABLE_HIGH_BOUND 64938
16905 +
16906 +static const uint16 nqdBm_to_mW_map[QDBM_TABLE_LEN] = {
16907 +/* qdBm: +0 +1 +2 +3 +4 +5 +6 +7 */
16908 +/* 153: */ 6683, 7079, 7499, 7943, 8414, 8913, 9441, 10000,
16909 +/* 161: */ 10593, 11220, 11885, 12589, 13335, 14125, 14962, 15849,
16910 +/* 169: */ 16788, 17783, 18836, 19953, 21135, 22387, 23714, 25119,
16911 +/* 177: */ 26607, 28184, 29854, 31623, 33497, 35481, 37584, 39811,
16912 +/* 185: */ 42170, 44668, 47315, 50119, 53088, 56234, 59566, 63096
16913 +};
16914 +
16915 +uint16
16916 +bcm_qdbm_to_mw(uint8 qdbm)
16917 +{
16918 + uint factor = 1;
16919 + int idx = qdbm - QDBM_OFFSET;
16920 +
16921 + if (idx > QDBM_TABLE_LEN) {
16922 + /* clamp to max uint16 mW value */
16923 + return 0xFFFF;
16924 + }
16925 +
16926 + /* scale the qdBm index up to the range of the table 0-40
16927 + * where an offset of 40 qdBm equals a factor of 10 mW.
16928 + */
16929 + while (idx < 0) {
16930 + idx += 40;
16931 + factor *= 10;
16932 + }
16933 +
16934 + /* return the mW value scaled down to the correct factor of 10,
16935 + * adding in factor/2 to get proper rounding. */
16936 + return ((nqdBm_to_mW_map[idx] + factor/2) / factor);
16937 +}
16938 +
16939 +uint8
16940 +bcm_mw_to_qdbm(uint16 mw)
16941 +{
16942 + uint8 qdbm;
16943 + int offset;
16944 + uint mw_uint = mw;
16945 + uint boundary;
16946 +
16947 + /* handle boundary case */
16948 + if (mw_uint <= 1)
16949 + return 0;
16950 +
16951 + offset = QDBM_OFFSET;
16952 +
16953 + /* move mw into the range of the table */
16954 + while (mw_uint < QDBM_TABLE_LOW_BOUND) {
16955 + mw_uint *= 10;
16956 + offset -= 40;
16957 + }
16958 +
16959 + for (qdbm = 0; qdbm < QDBM_TABLE_LEN-1; qdbm++) {
16960 + boundary = nqdBm_to_mW_map[qdbm] + (nqdBm_to_mW_map[qdbm+1] - nqdBm_to_mW_map[qdbm])/2;
16961 + if (mw_uint < boundary) break;
16962 + }
16963 +
16964 + qdbm += (uint8)offset;
16965 +
16966 + return(qdbm);
16967 +}
16968 diff -urN linux.old/drivers/net/hnd/hnddma.c linux.dev/drivers/net/hnd/hnddma.c
16969 --- linux.old/drivers/net/hnd/hnddma.c 1970-01-01 01:00:00.000000000 +0100
16970 +++ linux.dev/drivers/net/hnd/hnddma.c 2005-11-08 16:07:38.846817500 +0100
16971 @@ -0,0 +1,1527 @@
16972 +/*
16973 + * Generic Broadcom Home Networking Division (HND) DMA module.
16974 + * This supports the following chips: BCM42xx, 44xx, 47xx .
16975 + *
16976 + * Copyright 2005, Broadcom Corporation
16977 + * All Rights Reserved.
16978 + *
16979 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
16980 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
16981 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
16982 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
16983 + *
16984 + * $Id$
16985 + */
16986 +
16987 +#include <typedefs.h>
16988 +#include <osl.h>
16989 +#include <bcmendian.h>
16990 +#include <sbconfig.h>
16991 +#include <bcmutils.h>
16992 +#include <bcmdevs.h>
16993 +#include <sbutils.h>
16994 +
16995 +struct dma_info; /* forward declaration */
16996 +#define di_t struct dma_info
16997 +
16998 +#include <sbhnddma.h>
16999 +#include <hnddma.h>
17000 +
17001 +/* debug/trace */
17002 +#define DMA_ERROR(args)
17003 +#define DMA_TRACE(args)
17004 +
17005 +/* default dma message level (if input msg_level pointer is null in dma_attach()) */
17006 +static uint dma_msg_level =
17007 + 0;
17008 +
17009 +#define MAXNAMEL 8
17010 +
17011 +/* dma engine software state */
17012 +typedef struct dma_info {
17013 + hnddma_t hnddma; /* exported structure */
17014 + uint *msg_level; /* message level pointer */
17015 + char name[MAXNAMEL]; /* callers name for diag msgs */
17016 +
17017 + void *osh; /* os handle */
17018 + sb_t *sbh; /* sb handle */
17019 +
17020 + bool dma64; /* dma64 enabled */
17021 + bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
17022 +
17023 + dma32regs_t *d32txregs; /* 32 bits dma tx engine registers */
17024 + dma32regs_t *d32rxregs; /* 32 bits dma rx engine registers */
17025 + dma64regs_t *d64txregs; /* 64 bits dma tx engine registers */
17026 + dma64regs_t *d64rxregs; /* 64 bits dma rx engine registers */
17027 +
17028 + uint32 dma64align; /* either 8k or 4k depends on number of dd */
17029 + dma32dd_t *txd32; /* pointer to dma32 tx descriptor ring */
17030 + dma64dd_t *txd64; /* pointer to dma64 tx descriptor ring */
17031 + uint ntxd; /* # tx descriptors tunable */
17032 + uint txin; /* index of next descriptor to reclaim */
17033 + uint txout; /* index of next descriptor to post */
17034 + uint txavail; /* # free tx descriptors */
17035 + void **txp; /* pointer to parallel array of pointers to packets */
17036 + ulong txdpa; /* physical address of descriptor ring */
17037 + uint txdalign; /* #bytes added to alloc'd mem to align txd */
17038 + uint txdalloc; /* #bytes allocated for the ring */
17039 +
17040 + dma32dd_t *rxd32; /* pointer to dma32 rx descriptor ring */
17041 + dma64dd_t *rxd64; /* pointer to dma64 rx descriptor ring */
17042 + uint nrxd; /* # rx descriptors tunable */
17043 + uint rxin; /* index of next descriptor to reclaim */
17044 + uint rxout; /* index of next descriptor to post */
17045 + void **rxp; /* pointer to parallel array of pointers to packets */
17046 + ulong rxdpa; /* physical address of descriptor ring */
17047 + uint rxdalign; /* #bytes added to alloc'd mem to align rxd */
17048 + uint rxdalloc; /* #bytes allocated for the ring */
17049 +
17050 + /* tunables */
17051 + uint rxbufsize; /* rx buffer size in bytes */
17052 + uint nrxpost; /* # rx buffers to keep posted */
17053 + uint rxoffset; /* rxcontrol offset */
17054 + uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
17055 + uint ddoffsethigh; /* add to get dma address of descriptor ring, high 32 bits */
17056 + uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
17057 + uint dataoffsethigh; /* add to get dma address of data buffer, high 32 bits */
17058 +} dma_info_t;
17059 +
17060 +#ifdef BCMDMA64
17061 +#define DMA64_ENAB(di) ((di)->dma64)
17062 +#else
17063 +#define DMA64_ENAB(di) (0)
17064 +#endif
17065 +
17066 +/* descriptor bumping macros */
17067 +#define XXD(x, n) ((x) & ((n) - 1))
17068 +#define TXD(x) XXD((x), di->ntxd)
17069 +#define RXD(x) XXD((x), di->nrxd)
17070 +#define NEXTTXD(i) TXD(i + 1)
17071 +#define PREVTXD(i) TXD(i - 1)
17072 +#define NEXTRXD(i) RXD(i + 1)
17073 +#define NTXDACTIVE(h, t) TXD(t - h)
17074 +#define NRXDACTIVE(h, t) RXD(t - h)
17075 +
17076 +/* macros to convert between byte offsets and indexes */
17077 +#define B2I(bytes, type) ((bytes) / sizeof(type))
17078 +#define I2B(index, type) ((index) * sizeof(type))
17079 +
17080 +#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
17081 +#define PCI32ADDR_HIGH_SHIFT 30
17082 +
17083 +
17084 +/* prototypes */
17085 +static bool dma_isaddrext(dma_info_t *di);
17086 +static bool dma_alloc(dma_info_t *di, uint direction);
17087 +
17088 +static bool dma32_alloc(dma_info_t *di, uint direction);
17089 +static void dma32_txreset(dma_info_t *di);
17090 +static void dma32_rxreset(dma_info_t *di);
17091 +static bool dma32_txsuspendedidle(dma_info_t *di);
17092 +static int dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags);
17093 +static void* dma32_getnexttxp(dma_info_t *di, bool forceall);
17094 +static void* dma32_getnextrxp(dma_info_t *di, bool forceall);
17095 +static void dma32_txrotate(di_t *di);
17096 +
17097 +/* prototype or stubs */
17098 +#ifdef BCMDMA64
17099 +static bool dma64_alloc(dma_info_t *di, uint direction);
17100 +static void dma64_txreset(dma_info_t *di);
17101 +static void dma64_rxreset(dma_info_t *di);
17102 +static bool dma64_txsuspendedidle(dma_info_t *di);
17103 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags);
17104 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall);
17105 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall);
17106 +static void dma64_txrotate(di_t *di);
17107 +#else
17108 +static bool dma64_alloc(dma_info_t *di, uint direction) { return TRUE; }
17109 +static void dma64_txreset(dma_info_t *di) {}
17110 +static void dma64_rxreset(dma_info_t *di) {}
17111 +static bool dma64_txsuspendedidle(dma_info_t *di) { return TRUE;}
17112 +static int dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags) { return 0; }
17113 +static void* dma64_getnexttxp(dma_info_t *di, bool forceall) { return NULL; }
17114 +static void* dma64_getnextrxp(dma_info_t *di, bool forceall) { return NULL; }
17115 +static void dma64_txrotate(di_t *di) { return; }
17116 +#endif
17117 +
17118 +/* old dmaregs struct for compatibility */
17119 +typedef volatile struct {
17120 + /* transmit channel */
17121 + uint32 xmtcontrol; /* enable, et al */
17122 + uint32 xmtaddr; /* descriptor ring base address (4K aligned) */
17123 + uint32 xmtptr; /* last descriptor posted to chip */
17124 + uint32 xmtstatus; /* current active descriptor, et al */
17125 +
17126 + /* receive channel */
17127 + uint32 rcvcontrol; /* enable, et al */
17128 + uint32 rcvaddr; /* descriptor ring base address (4K aligned) */
17129 + uint32 rcvptr; /* last descriptor posted to chip */
17130 + uint32 rcvstatus; /* current active descriptor, et al */
17131 +} dmaregs_t;
17132 +
17133 +typedef struct {
17134 + uint ddoffset;
17135 + uint dataoffset;
17136 +} compat_data;
17137 +
17138 +static compat_data *ugly_hack = NULL;
17139 +
17140 +void*
17141 +dma_attold(void *drv, void *osh, char *name, dmaregs_t *regs, uint ntxd, uint nrxd,
17142 + uint rxbufsize, uint nrxpost, uint rxoffset, uint ddoffset, uint dataoffset, uint *msg_level)
17143 +{
17144 + dma32regs_t *dtx = regs;
17145 + dma32regs_t *drx = dtx + 1;
17146 +
17147 + ugly_hack = kmalloc(sizeof(ugly_hack), GFP_KERNEL);
17148 + ugly_hack->ddoffset = ddoffset;
17149 + ugly_hack->dataoffset = dataoffset;
17150 + dma_attach((osl_t *) osh, name, NULL, dtx, drx, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, msg_level);
17151 + ugly_hack = NULL;
17152 +}
17153 +
17154 +
17155 +void*
17156 +dma_attach(osl_t *osh, char *name, sb_t *sbh, void *dmaregstx, void *dmaregsrx,
17157 + uint ntxd, uint nrxd, uint rxbufsize, uint nrxpost, uint rxoffset, uint *msg_level)
17158 +{
17159 + dma_info_t *di;
17160 + uint size;
17161 +
17162 + /* allocate private info structure */
17163 + if ((di = MALLOC(osh, sizeof (dma_info_t))) == NULL) {
17164 + return (NULL);
17165 + }
17166 + bzero((char*)di, sizeof (dma_info_t));
17167 +
17168 + di->msg_level = msg_level ? msg_level : &dma_msg_level;
17169 +
17170 + if (sbh != NULL)
17171 + di->dma64 = ((sb_coreflagshi(sbh, 0, 0) & SBTMH_DMA64) == SBTMH_DMA64);
17172 +
17173 +#ifndef BCMDMA64
17174 + if (di->dma64) {
17175 + DMA_ERROR(("dma_attach: driver doesn't have the capability to support 64 bits DMA\n"));
17176 + goto fail;
17177 + }
17178 +#endif
17179 +
17180 + /* check arguments */
17181 + ASSERT(ISPOWEROF2(ntxd));
17182 + ASSERT(ISPOWEROF2(nrxd));
17183 + if (nrxd == 0)
17184 + ASSERT(dmaregsrx == NULL);
17185 + if (ntxd == 0)
17186 + ASSERT(dmaregstx == NULL);
17187 +
17188 +
17189 + /* init dma reg pointer */
17190 + if (di->dma64) {
17191 + ASSERT(ntxd <= D64MAXDD);
17192 + ASSERT(nrxd <= D64MAXDD);
17193 + di->d64txregs = (dma64regs_t *)dmaregstx;
17194 + di->d64rxregs = (dma64regs_t *)dmaregsrx;
17195 +
17196 + di->dma64align = D64RINGALIGN;
17197 + if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
17198 + /* for smaller dd table, HW relax the alignment requirement */
17199 + di->dma64align = D64RINGALIGN / 2;
17200 + }
17201 + } else {
17202 + ASSERT(ntxd <= D32MAXDD);
17203 + ASSERT(nrxd <= D32MAXDD);
17204 + di->d32txregs = (dma32regs_t *)dmaregstx;
17205 + di->d32rxregs = (dma32regs_t *)dmaregsrx;
17206 + }
17207 +
17208 +
17209 + /* make a private copy of our callers name */
17210 + strncpy(di->name, name, MAXNAMEL);
17211 + di->name[MAXNAMEL-1] = '\0';
17212 +
17213 + di->osh = osh;
17214 + di->sbh = sbh;
17215 +
17216 + /* save tunables */
17217 + di->ntxd = ntxd;
17218 + di->nrxd = nrxd;
17219 + di->rxbufsize = rxbufsize;
17220 + di->nrxpost = nrxpost;
17221 + di->rxoffset = rxoffset;
17222 +
17223 + /*
17224 + * figure out the DMA physical address offset for dd and data
17225 + * for old chips w/o sb, use zero
17226 + * for new chips w sb,
17227 + * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
17228 + * Other bus: use zero
17229 + * SB_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
17230 + */
17231 + di->ddoffsetlow = 0;
17232 + di->dataoffsetlow = 0;
17233 + if (ugly_hack != NULL) {
17234 + di->ddoffsetlow = ugly_hack->ddoffset;
17235 + di->dataoffsetlow = ugly_hack->dataoffset;
17236 + di->ddoffsethigh = 0;
17237 + di->dataoffsethigh = 0;
17238 + } else if (sbh != NULL) {
17239 + if (sbh->bustype == PCI_BUS) { /* for pci bus, add offset */
17240 + if ((sbh->buscoretype == SB_PCIE) && di->dma64){
17241 + di->ddoffsetlow = 0;
17242 + di->ddoffsethigh = SB_PCIE_DMA_H32;
17243 + } else {
17244 + di->ddoffsetlow = SB_PCI_DMA;
17245 + di->ddoffsethigh = 0;
17246 + }
17247 + di->dataoffsetlow = di->ddoffsetlow;
17248 + di->dataoffsethigh = di->ddoffsethigh;
17249 + }
17250 +#if defined(__mips__) && defined(IL_BIGENDIAN)
17251 + /* use sdram swapped region for data buffers but not dma descriptors */
17252 + di->dataoffsetlow = di->dataoffsetlow + SB_SDRAM_SWAPPED;
17253 +#endif
17254 + }
17255 +
17256 + di->addrext = ((ugly_hack == NULL) ? dma_isaddrext(di) : 0);
17257 +
17258 + DMA_TRACE(("%s: dma_attach: osh %p ntxd %d nrxd %d rxbufsize %d nrxpost %d rxoffset %d ddoffset 0x%x dataoffset 0x%x\n",
17259 + name, osh, ntxd, nrxd, rxbufsize, nrxpost, rxoffset, di->ddoffsetlow, di->dataoffsetlow));
17260 +
17261 + /* allocate tx packet pointer vector */
17262 + if (ntxd) {
17263 + size = ntxd * sizeof (void*);
17264 + if ((di->txp = MALLOC(osh, size)) == NULL) {
17265 + DMA_ERROR(("%s: dma_attach: out of tx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17266 + goto fail;
17267 + }
17268 + bzero((char*)di->txp, size);
17269 + }
17270 +
17271 + /* allocate rx packet pointer vector */
17272 + if (nrxd) {
17273 + size = nrxd * sizeof (void*);
17274 + if ((di->rxp = MALLOC(osh, size)) == NULL) {
17275 + DMA_ERROR(("%s: dma_attach: out of rx memory, malloced %d bytes\n", di->name, MALLOCED(osh)));
17276 + goto fail;
17277 + }
17278 + bzero((char*)di->rxp, size);
17279 + }
17280 +
17281 + /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
17282 + if (ntxd) {
17283 + if (!dma_alloc(di, DMA_TX))
17284 + goto fail;
17285 + }
17286 +
17287 + /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
17288 + if (nrxd) {
17289 + if (!dma_alloc(di, DMA_RX))
17290 + goto fail;
17291 + }
17292 +
17293 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->txdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17294 + DMA_ERROR(("%s: dma_attach: txdpa 0x%lx: addrext not supported\n", di->name, di->txdpa));
17295 + goto fail;
17296 + }
17297 + if ((di->ddoffsetlow == SB_PCI_DMA) && (di->rxdpa > SB_PCI_DMA_SZ) && !di->addrext) {
17298 + DMA_ERROR(("%s: dma_attach: rxdpa 0x%lx: addrext not supported\n", di->name, di->rxdpa));
17299 + goto fail;
17300 + }
17301 +
17302 + return ((void*)di);
17303 +
17304 +fail:
17305 + dma_detach((void*)di);
17306 + return (NULL);
17307 +}
17308 +
17309 +static bool
17310 +dma_alloc(dma_info_t *di, uint direction)
17311 +{
17312 + if (DMA64_ENAB(di)) {
17313 + return dma64_alloc(di, direction);
17314 + } else {
17315 + return dma32_alloc(di, direction);
17316 + }
17317 +}
17318 +
17319 +/* may be called with core in reset */
17320 +void
17321 +dma_detach(dma_info_t *di)
17322 +{
17323 + if (di == NULL)
17324 + return;
17325 +
17326 + DMA_TRACE(("%s: dma_detach\n", di->name));
17327 +
17328 + /* shouldn't be here if descriptors are unreclaimed */
17329 + ASSERT(di->txin == di->txout);
17330 + ASSERT(di->rxin == di->rxout);
17331 +
17332 + /* free dma descriptor rings */
17333 + if (di->txd32)
17334 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->txd32 - di->txdalign), di->txdalloc, (di->txdpa - di->txdalign));
17335 + if (di->rxd32)
17336 + DMA_FREE_CONSISTENT(di->osh, ((int8*)di->rxd32 - di->rxdalign), di->rxdalloc, (di->rxdpa - di->rxdalign));
17337 +
17338 + /* free packet pointer vectors */
17339 + if (di->txp)
17340 + MFREE(di->osh, (void*)di->txp, (di->ntxd * sizeof (void*)));
17341 + if (di->rxp)
17342 + MFREE(di->osh, (void*)di->rxp, (di->nrxd * sizeof (void*)));
17343 +
17344 + /* free our private info structure */
17345 + MFREE(di->osh, (void*)di, sizeof (dma_info_t));
17346 +}
17347 +
17348 +/* return TRUE if this dma engine supports DmaExtendedAddrChanges, otherwise FALSE */
17349 +static bool
17350 +dma_isaddrext(dma_info_t *di)
17351 +{
17352 + uint32 w;
17353 +
17354 + if (DMA64_ENAB(di)) {
17355 + OR_REG(&di->d64txregs->control, D64_XC_AE);
17356 + w = R_REG(&di->d32txregs->control);
17357 + AND_REG(&di->d32txregs->control, ~D64_XC_AE);
17358 + return ((w & XC_AE) == D64_XC_AE);
17359 + } else {
17360 + OR_REG(&di->d32txregs->control, XC_AE);
17361 + w = R_REG(&di->d32txregs->control);
17362 + AND_REG(&di->d32txregs->control, ~XC_AE);
17363 + return ((w & XC_AE) == XC_AE);
17364 + }
17365 +}
17366 +
17367 +void
17368 +dma_txreset(dma_info_t *di)
17369 +{
17370 + DMA_TRACE(("%s: dma_txreset\n", di->name));
17371 +
17372 + if (DMA64_ENAB(di))
17373 + dma64_txreset(di);
17374 + else
17375 + dma32_txreset(di);
17376 +}
17377 +
17378 +void
17379 +dma_rxreset(dma_info_t *di)
17380 +{
17381 + DMA_TRACE(("%s: dma_rxreset\n", di->name));
17382 +
17383 + if (DMA64_ENAB(di))
17384 + dma64_rxreset(di);
17385 + else
17386 + dma32_rxreset(di);
17387 +}
17388 +
17389 +/* initialize descriptor table base address */
17390 +static void
17391 +dma_ddtable_init(dma_info_t *di, uint direction, ulong pa)
17392 +{
17393 + if (DMA64_ENAB(di)) {
17394 + if (direction == DMA_TX) {
17395 + W_REG(&di->d64txregs->addrlow, pa + di->ddoffsetlow);
17396 + W_REG(&di->d64txregs->addrhigh, di->ddoffsethigh);
17397 + } else {
17398 + W_REG(&di->d64rxregs->addrlow, pa + di->ddoffsetlow);
17399 + W_REG(&di->d64rxregs->addrhigh, di->ddoffsethigh);
17400 + }
17401 + } else {
17402 + uint32 offset = di->ddoffsetlow;
17403 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17404 + if (direction == DMA_TX)
17405 + W_REG(&di->d32txregs->addr, (pa + offset));
17406 + else
17407 + W_REG(&di->d32rxregs->addr, (pa + offset));
17408 + } else {
17409 + /* dma32 address extension */
17410 + uint32 ae;
17411 + ASSERT(di->addrext);
17412 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17413 +
17414 + if (direction == DMA_TX) {
17415 + W_REG(&di->d32txregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17416 + SET_REG(&di->d32txregs->control, XC_AE, (ae << XC_AE_SHIFT));
17417 + } else {
17418 + W_REG(&di->d32rxregs->addr, ((pa & ~PCI32ADDR_HIGH) + offset));
17419 + SET_REG(&di->d32rxregs->control, RC_AE, (ae << RC_AE_SHIFT));
17420 + }
17421 + }
17422 + }
17423 +}
17424 +
17425 +/* init the tx or rx descriptor */
17426 +static INLINE void
17427 +dma32_dd_upd(dma_info_t *di, dma32dd_t *ddring, ulong pa, uint outidx, uint32 *ctrl)
17428 +{
17429 + uint offset = di->dataoffsetlow;
17430 +
17431 + if ((offset != SB_PCI_DMA) || !(pa & PCI32ADDR_HIGH)) {
17432 + W_SM(&ddring[outidx].addr, BUS_SWAP32(pa + offset));
17433 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17434 + } else {
17435 + /* address extension */
17436 + uint32 ae;
17437 + ASSERT(di->addrext);
17438 + ae = (pa & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
17439 +
17440 + *ctrl |= (ae << CTRL_AE_SHIFT);
17441 + W_SM(&ddring[outidx].addr, BUS_SWAP32((pa & ~PCI32ADDR_HIGH) + offset));
17442 + W_SM(&ddring[outidx].ctrl, BUS_SWAP32(*ctrl));
17443 + }
17444 +}
17445 +
17446 +/* init the tx or rx descriptor */
17447 +static INLINE void
17448 +dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, ulong pa, uint outidx, uint32 *flags, uint32 bufcount)
17449 +{
17450 + uint32 bufaddr_low = pa + di->dataoffsetlow;
17451 + uint32 bufaddr_high = 0 + di->dataoffsethigh;
17452 +
17453 + uint32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
17454 +
17455 + W_SM(&ddring[outidx].addrlow, BUS_SWAP32(bufaddr_low));
17456 + W_SM(&ddring[outidx].addrhigh, BUS_SWAP32(bufaddr_high));
17457 + W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
17458 + W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
17459 +}
17460 +
17461 +void
17462 +dma_txinit(dma_info_t *di)
17463 +{
17464 + DMA_TRACE(("%s: dma_txinit\n", di->name));
17465 +
17466 + di->txin = di->txout = 0;
17467 + di->txavail = di->ntxd - 1;
17468 +
17469 + /* clear tx descriptor ring */
17470 + if (DMA64_ENAB(di)) {
17471 + BZERO_SM((void*)di->txd64, (di->ntxd * sizeof (dma64dd_t)));
17472 + W_REG(&di->d64txregs->control, XC_XE);
17473 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17474 + } else {
17475 + BZERO_SM((void*)di->txd32, (di->ntxd * sizeof (dma32dd_t)));
17476 + W_REG(&di->d32txregs->control, XC_XE);
17477 + dma_ddtable_init(di, DMA_TX, di->txdpa);
17478 + }
17479 +}
17480 +
17481 +bool
17482 +dma_txenabled(dma_info_t *di)
17483 +{
17484 + uint32 xc;
17485 +
17486 + /* If the chip is dead, it is not enabled :-) */
17487 + if (DMA64_ENAB(di)) {
17488 + xc = R_REG(&di->d64txregs->control);
17489 + return ((xc != 0xffffffff) && (xc & D64_XC_XE));
17490 + } else {
17491 + xc = R_REG(&di->d32txregs->control);
17492 + return ((xc != 0xffffffff) && (xc & XC_XE));
17493 + }
17494 +}
17495 +
17496 +void
17497 +dma_txsuspend(dma_info_t *di)
17498 +{
17499 + DMA_TRACE(("%s: dma_txsuspend\n", di->name));
17500 + if (DMA64_ENAB(di))
17501 + OR_REG(&di->d64txregs->control, D64_XC_SE);
17502 + else
17503 + OR_REG(&di->d32txregs->control, XC_SE);
17504 +}
17505 +
17506 +void
17507 +dma_txresume(dma_info_t *di)
17508 +{
17509 + DMA_TRACE(("%s: dma_txresume\n", di->name));
17510 + if (DMA64_ENAB(di))
17511 + AND_REG(&di->d64txregs->control, ~D64_XC_SE);
17512 + else
17513 + AND_REG(&di->d32txregs->control, ~XC_SE);
17514 +}
17515 +
17516 +bool
17517 +dma_txsuspendedidle(dma_info_t *di)
17518 +{
17519 + if (DMA64_ENAB(di))
17520 + return dma64_txsuspendedidle(di);
17521 + else
17522 + return dma32_txsuspendedidle(di);
17523 +}
17524 +
17525 +bool
17526 +dma_txsuspended(dma_info_t *di)
17527 +{
17528 + if (DMA64_ENAB(di))
17529 + return ((R_REG(&di->d64txregs->control) & D64_XC_SE) == D64_XC_SE);
17530 + else
17531 + return ((R_REG(&di->d32txregs->control) & XC_SE) == XC_SE);
17532 +}
17533 +
17534 +bool
17535 +dma_txstopped(dma_info_t *di)
17536 +{
17537 + if (DMA64_ENAB(di))
17538 + return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_STOPPED);
17539 + else
17540 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_STOPPED);
17541 +}
17542 +
17543 +bool
17544 +dma_rxstopped(dma_info_t *di)
17545 +{
17546 + if (DMA64_ENAB(di))
17547 + return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) == D64_RS0_RS_STOPPED);
17548 + else
17549 + return ((R_REG(&di->d32rxregs->status) & RS_RS_MASK) == RS_RS_STOPPED);
17550 +}
17551 +
17552 +void
17553 +dma_fifoloopbackenable(dma_info_t *di)
17554 +{
17555 + DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
17556 + if (DMA64_ENAB(di))
17557 + OR_REG(&di->d64txregs->control, D64_XC_LE);
17558 + else
17559 + OR_REG(&di->d32txregs->control, XC_LE);
17560 +}
17561 +
17562 +void
17563 +dma_rxinit(dma_info_t *di)
17564 +{
17565 + DMA_TRACE(("%s: dma_rxinit\n", di->name));
17566 +
17567 + di->rxin = di->rxout = 0;
17568 +
17569 + /* clear rx descriptor ring */
17570 + if (DMA64_ENAB(di)) {
17571 + BZERO_SM((void*)di->rxd64, (di->nrxd * sizeof (dma64dd_t)));
17572 + dma_rxenable(di);
17573 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17574 + } else {
17575 + BZERO_SM((void*)di->rxd32, (di->nrxd * sizeof (dma32dd_t)));
17576 + dma_rxenable(di);
17577 + dma_ddtable_init(di, DMA_RX, di->rxdpa);
17578 + }
17579 +}
17580 +
17581 +void
17582 +dma_rxenable(dma_info_t *di)
17583 +{
17584 + DMA_TRACE(("%s: dma_rxenable\n", di->name));
17585 + if (DMA64_ENAB(di))
17586 + W_REG(&di->d64rxregs->control, ((di->rxoffset << D64_RC_RO_SHIFT) | D64_RC_RE));
17587 + else
17588 + W_REG(&di->d32rxregs->control, ((di->rxoffset << RC_RO_SHIFT) | RC_RE));
17589 +}
17590 +
17591 +bool
17592 +dma_rxenabled(dma_info_t *di)
17593 +{
17594 + uint32 rc;
17595 +
17596 + if (DMA64_ENAB(di)) {
17597 + rc = R_REG(&di->d64rxregs->control);
17598 + return ((rc != 0xffffffff) && (rc & D64_RC_RE));
17599 + } else {
17600 + rc = R_REG(&di->d32rxregs->control);
17601 + return ((rc != 0xffffffff) && (rc & RC_RE));
17602 + }
17603 +}
17604 +
17605 +
17606 +/* !! tx entry routine */
17607 +int
17608 +dma_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17609 +{
17610 + if (DMA64_ENAB(di)) {
17611 + return dma64_txfast(di, p0, coreflags);
17612 + } else {
17613 + return dma32_txfast(di, p0, coreflags);
17614 + }
17615 +}
17616 +
17617 +/* !! rx entry routine, returns a pointer to the next frame received, or NULL if there are no more */
17618 +void*
17619 +dma_rx(dma_info_t *di)
17620 +{
17621 + void *p;
17622 + uint len;
17623 + int skiplen = 0;
17624 +
17625 + while ((p = dma_getnextrxp(di, FALSE))) {
17626 + /* skip giant packets which span multiple rx descriptors */
17627 + if (skiplen > 0) {
17628 + skiplen -= di->rxbufsize;
17629 + if (skiplen < 0)
17630 + skiplen = 0;
17631 + PKTFREE(di->osh, p, FALSE);
17632 + continue;
17633 + }
17634 +
17635 + len = ltoh16(*(uint16*)(PKTDATA(di->osh, p)));
17636 + DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
17637 +
17638 + /* bad frame length check */
17639 + if (len > (di->rxbufsize - di->rxoffset)) {
17640 + DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n", di->name, len));
17641 + if (len > 0)
17642 + skiplen = len - (di->rxbufsize - di->rxoffset);
17643 + PKTFREE(di->osh, p, FALSE);
17644 + di->hnddma.rxgiants++;
17645 + continue;
17646 + }
17647 +
17648 + /* set actual length */
17649 + PKTSETLEN(di->osh, p, (di->rxoffset + len));
17650 +
17651 + break;
17652 + }
17653 +
17654 + return (p);
17655 +}
17656 +
17657 +/* post receive buffers */
17658 +void
17659 +dma_rxfill(dma_info_t *di)
17660 +{
17661 + void *p;
17662 + uint rxin, rxout;
17663 + uint32 ctrl;
17664 + uint n;
17665 + uint i;
17666 + uint32 pa;
17667 + uint rxbufsize;
17668 +
17669 + /*
17670 + * Determine how many receive buffers we're lacking
17671 + * from the full complement, allocate, initialize,
17672 + * and post them, then update the chip rx lastdscr.
17673 + */
17674 +
17675 + rxin = di->rxin;
17676 + rxout = di->rxout;
17677 + rxbufsize = di->rxbufsize;
17678 +
17679 + n = di->nrxpost - NRXDACTIVE(rxin, rxout);
17680 +
17681 + DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
17682 +
17683 + for (i = 0; i < n; i++) {
17684 + if ((p = PKTGET(di->osh, rxbufsize, FALSE)) == NULL) {
17685 + DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n", di->name));
17686 + di->hnddma.rxnobuf++;
17687 + break;
17688 + }
17689 +
17690 + /* Do a cached write instead of uncached write since DMA_MAP
17691 + * will flush the cache. */
17692 + *(uint32*)(PKTDATA(di->osh, p)) = 0;
17693 +
17694 + pa = (uint32) DMA_MAP(di->osh, PKTDATA(di->osh, p), rxbufsize, DMA_RX, p);
17695 + ASSERT(ISALIGNED(pa, 4));
17696 +
17697 + /* save the free packet pointer */
17698 + ASSERT(di->rxp[rxout] == NULL);
17699 + di->rxp[rxout] = p;
17700 +
17701 + if (DMA64_ENAB(di)) {
17702 + /* prep the descriptor control value */
17703 + if (rxout == (di->nrxd - 1))
17704 + ctrl = CTRL_EOT;
17705 +
17706 + dma64_dd_upd(di, di->rxd64, pa, rxout, &ctrl, rxbufsize);
17707 + } else {
17708 + /* prep the descriptor control value */
17709 + ctrl = rxbufsize;
17710 + if (rxout == (di->nrxd - 1))
17711 + ctrl |= CTRL_EOT;
17712 + dma32_dd_upd(di, di->rxd32, pa, rxout, &ctrl);
17713 + }
17714 +
17715 + rxout = NEXTRXD(rxout);
17716 + }
17717 +
17718 + di->rxout = rxout;
17719 +
17720 + /* update the chip lastdscr pointer */
17721 + if (DMA64_ENAB(di)) {
17722 + W_REG(&di->d64rxregs->ptr, I2B(rxout, dma64dd_t));
17723 + } else {
17724 + W_REG(&di->d32rxregs->ptr, I2B(rxout, dma32dd_t));
17725 + }
17726 +}
17727 +
17728 +void
17729 +dma_txreclaim(dma_info_t *di, bool forceall)
17730 +{
17731 + void *p;
17732 +
17733 + DMA_TRACE(("%s: dma_txreclaim %s\n", di->name, forceall ? "all" : ""));
17734 +
17735 + while ((p = dma_getnexttxp(di, forceall)))
17736 + PKTFREE(di->osh, p, TRUE);
17737 +}
17738 +
17739 +/*
17740 + * Reclaim next completed txd (txds if using chained buffers) and
17741 + * return associated packet.
17742 + * If 'force' is true, reclaim txd(s) and return associated packet
17743 + * regardless of the value of the hardware "curr" pointer.
17744 + */
17745 +void*
17746 +dma_getnexttxp(dma_info_t *di, bool forceall)
17747 +{
17748 + if (DMA64_ENAB(di)) {
17749 + return dma64_getnexttxp(di, forceall);
17750 + } else {
17751 + return dma32_getnexttxp(di, forceall);
17752 + }
17753 +}
17754 +
17755 +/* like getnexttxp but no reclaim */
17756 +void*
17757 +dma_peeknexttxp(dma_info_t *di)
17758 +{
17759 + uint end, i;
17760 +
17761 + if (DMA64_ENAB(di)) {
17762 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
17763 + } else {
17764 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
17765 + }
17766 +
17767 + for (i = di->txin; i != end; i = NEXTTXD(i))
17768 + if (di->txp[i])
17769 + return (di->txp[i]);
17770 +
17771 + return (NULL);
17772 +}
17773 +
17774 +/*
17775 + * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
17776 + */
17777 +void
17778 +dma_txrotate(di_t *di)
17779 +{
17780 + if (DMA64_ENAB(di)) {
17781 + dma64_txrotate(di);
17782 + } else {
17783 + dma32_txrotate(di);
17784 + }
17785 +}
17786 +
17787 +void
17788 +dma_rxreclaim(dma_info_t *di)
17789 +{
17790 + void *p;
17791 +
17792 + DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
17793 +
17794 + while ((p = dma_getnextrxp(di, TRUE)))
17795 + PKTFREE(di->osh, p, FALSE);
17796 +}
17797 +
17798 +void *
17799 +dma_getnextrxp(dma_info_t *di, bool forceall)
17800 +{
17801 + if (DMA64_ENAB(di)) {
17802 + return dma64_getnextrxp(di, forceall);
17803 + } else {
17804 + return dma32_getnextrxp(di, forceall);
17805 + }
17806 +}
17807 +
17808 +uintptr
17809 +dma_getvar(dma_info_t *di, char *name)
17810 +{
17811 + if (!strcmp(name, "&txavail"))
17812 + return ((uintptr) &di->txavail);
17813 + else {
17814 + ASSERT(0);
17815 + }
17816 + return (0);
17817 +}
17818 +
17819 +void
17820 +dma_txblock(dma_info_t *di)
17821 +{
17822 + di->txavail = 0;
17823 +}
17824 +
17825 +void
17826 +dma_txunblock(dma_info_t *di)
17827 +{
17828 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
17829 +}
17830 +
17831 +uint
17832 +dma_txactive(dma_info_t *di)
17833 +{
17834 + return (NTXDACTIVE(di->txin, di->txout));
17835 +}
17836 +
17837 +void
17838 +dma_rxpiomode(dma32regs_t *regs)
17839 +{
17840 + W_REG(&regs->control, RC_FM);
17841 +}
17842 +
17843 +void
17844 +dma_txpioloopback(dma32regs_t *regs)
17845 +{
17846 + OR_REG(&regs->control, XC_LE);
17847 +}
17848 +
17849 +
17850 +
17851 +
17852 +/*** 32 bits DMA non-inline functions ***/
17853 +static bool
17854 +dma32_alloc(dma_info_t *di, uint direction)
17855 +{
17856 + uint size;
17857 + uint ddlen;
17858 + void *va;
17859 +
17860 + ddlen = sizeof (dma32dd_t);
17861 +
17862 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
17863 +
17864 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, D32RINGALIGN))
17865 + size += D32RINGALIGN;
17866 +
17867 +
17868 + if (direction == DMA_TX) {
17869 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
17870 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
17871 + return FALSE;
17872 + }
17873 +
17874 + di->txd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17875 + di->txdalign = (uint)((int8*)di->txd32 - (int8*)va);
17876 + di->txdpa += di->txdalign;
17877 + di->txdalloc = size;
17878 + ASSERT(ISALIGNED((uintptr)di->txd32, D32RINGALIGN));
17879 + } else {
17880 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
17881 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
17882 + return FALSE;
17883 + }
17884 + di->rxd32 = (dma32dd_t*) ROUNDUP((uintptr)va, D32RINGALIGN);
17885 + di->rxdalign = (uint)((int8*)di->rxd32 - (int8*)va);
17886 + di->rxdpa += di->rxdalign;
17887 + di->rxdalloc = size;
17888 + ASSERT(ISALIGNED((uintptr)di->rxd32, D32RINGALIGN));
17889 + }
17890 +
17891 + return TRUE;
17892 +}
17893 +
17894 +static void
17895 +dma32_txreset(dma_info_t *di)
17896 +{
17897 + uint32 status;
17898 +
17899 + /* suspend tx DMA first */
17900 + W_REG(&di->d32txregs->control, XC_SE);
17901 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED &&
17902 + status != XS_XS_IDLE &&
17903 + status != XS_XS_STOPPED,
17904 + 10000);
17905 +
17906 + W_REG(&di->d32txregs->control, 0);
17907 + SPINWAIT((status = (R_REG(&di->d32txregs->status) & XS_XS_MASK)) != XS_XS_DISABLED,
17908 + 10000);
17909 +
17910 + if (status != XS_XS_DISABLED) {
17911 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
17912 + }
17913 +
17914 + /* wait for the last transaction to complete */
17915 + OSL_DELAY(300);
17916 +}
17917 +
17918 +static void
17919 +dma32_rxreset(dma_info_t *di)
17920 +{
17921 + uint32 status;
17922 +
17923 + W_REG(&di->d32rxregs->control, 0);
17924 + SPINWAIT((status = (R_REG(&di->d32rxregs->status) & RS_RS_MASK)) != RS_RS_DISABLED,
17925 + 10000);
17926 +
17927 + if (status != RS_RS_DISABLED) {
17928 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
17929 + }
17930 +}
17931 +
17932 +static bool
17933 +dma32_txsuspendedidle(dma_info_t *di)
17934 +{
17935 + if (!(R_REG(&di->d32txregs->control) & XC_SE))
17936 + return 0;
17937 +
17938 + if ((R_REG(&di->d32txregs->status) & XS_XS_MASK) != XS_XS_IDLE)
17939 + return 0;
17940 +
17941 + OSL_DELAY(2);
17942 + return ((R_REG(&di->d32txregs->status) & XS_XS_MASK) == XS_XS_IDLE);
17943 +}
17944 +
17945 +/*
17946 + * supports full 32bit dma engine buffer addressing so
17947 + * dma buffers can cross 4 Kbyte page boundaries.
17948 + */
17949 +static int
17950 +dma32_txfast(dma_info_t *di, void *p0, uint32 coreflags)
17951 +{
17952 + void *p, *next;
17953 + uchar *data;
17954 + uint len;
17955 + uint txout;
17956 + uint32 ctrl;
17957 + uint32 pa;
17958 +
17959 + DMA_TRACE(("%s: dma_txfast\n", di->name));
17960 +
17961 + txout = di->txout;
17962 + ctrl = 0;
17963 +
17964 + /*
17965 + * Walk the chain of packet buffers
17966 + * allocating and initializing transmit descriptor entries.
17967 + */
17968 + for (p = p0; p; p = next) {
17969 + data = PKTDATA(di->osh, p);
17970 + len = PKTLEN(di->osh, p);
17971 + next = PKTNEXT(di->osh, p);
17972 +
17973 + /* return nonzero if out of tx descriptors */
17974 + if (NEXTTXD(txout) == di->txin)
17975 + goto outoftxd;
17976 +
17977 + if (len == 0)
17978 + continue;
17979 +
17980 + /* get physical address of buffer start */
17981 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
17982 +
17983 + /* build the descriptor control value */
17984 + ctrl = len & CTRL_BC_MASK;
17985 +
17986 + ctrl |= coreflags;
17987 +
17988 + if (p == p0)
17989 + ctrl |= CTRL_SOF;
17990 + if (next == NULL)
17991 + ctrl |= (CTRL_IOC | CTRL_EOF);
17992 + if (txout == (di->ntxd - 1))
17993 + ctrl |= CTRL_EOT;
17994 +
17995 + if (DMA64_ENAB(di)) {
17996 + dma64_dd_upd(di, di->txd64, pa, txout, &ctrl, len);
17997 + } else {
17998 + dma32_dd_upd(di, di->txd32, pa, txout, &ctrl);
17999 + }
18000 +
18001 + ASSERT(di->txp[txout] == NULL);
18002 +
18003 + txout = NEXTTXD(txout);
18004 + }
18005 +
18006 + /* if last txd eof not set, fix it */
18007 + if (!(ctrl & CTRL_EOF))
18008 + W_SM(&di->txd32[PREVTXD(txout)].ctrl, BUS_SWAP32(ctrl | CTRL_IOC | CTRL_EOF));
18009 +
18010 + /* save the packet */
18011 + di->txp[PREVTXD(txout)] = p0;
18012 +
18013 + /* bump the tx descriptor index */
18014 + di->txout = txout;
18015 +
18016 + /* kick the chip */
18017 + if (DMA64_ENAB(di)) {
18018 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
18019 + } else {
18020 + W_REG(&di->d32txregs->ptr, I2B(txout, dma32dd_t));
18021 + }
18022 +
18023 + /* tx flow control */
18024 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18025 +
18026 + return (0);
18027 +
18028 + outoftxd:
18029 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18030 + PKTFREE(di->osh, p0, TRUE);
18031 + di->txavail = 0;
18032 + di->hnddma.txnobuf++;
18033 + return (-1);
18034 +}
18035 +
18036 +static void*
18037 +dma32_getnexttxp(dma_info_t *di, bool forceall)
18038 +{
18039 + uint start, end, i;
18040 + void *txp;
18041 +
18042 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18043 +
18044 + txp = NULL;
18045 +
18046 + start = di->txin;
18047 + if (forceall)
18048 + end = di->txout;
18049 + else
18050 + end = B2I(R_REG(&di->d32txregs->status) & XS_CD_MASK, dma32dd_t);
18051 +
18052 + if ((start == 0) && (end > di->txout))
18053 + goto bogus;
18054 +
18055 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18056 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd32[i].addr)) - di->dataoffsetlow),
18057 + (BUS_SWAP32(R_SM(&di->txd32[i].ctrl)) & CTRL_BC_MASK), DMA_TX, di->txp[i]);
18058 +
18059 + W_SM(&di->txd32[i].addr, 0xdeadbeef);
18060 + txp = di->txp[i];
18061 + di->txp[i] = NULL;
18062 + }
18063 +
18064 + di->txin = i;
18065 +
18066 + /* tx flow control */
18067 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18068 +
18069 + return (txp);
18070 +
18071 +bogus:
18072 +/*
18073 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18074 + start, end, di->txout, forceall));
18075 +*/
18076 + return (NULL);
18077 +}
18078 +
18079 +static void *
18080 +dma32_getnextrxp(dma_info_t *di, bool forceall)
18081 +{
18082 + uint i;
18083 + void *rxp;
18084 +
18085 + /* if forcing, dma engine must be disabled */
18086 + ASSERT(!forceall || !dma_rxenabled(di));
18087 +
18088 + i = di->rxin;
18089 +
18090 + /* return if no packets posted */
18091 + if (i == di->rxout)
18092 + return (NULL);
18093 +
18094 + /* ignore curr if forceall */
18095 + if (!forceall && (i == B2I(R_REG(&di->d32rxregs->status) & RS_CD_MASK, dma32dd_t)))
18096 + return (NULL);
18097 +
18098 + /* get the packet pointer that corresponds to the rx descriptor */
18099 + rxp = di->rxp[i];
18100 + ASSERT(rxp);
18101 + di->rxp[i] = NULL;
18102 +
18103 + /* clear this packet from the descriptor ring */
18104 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd32[i].addr)) - di->dataoffsetlow),
18105 + di->rxbufsize, DMA_RX, rxp);
18106 + W_SM(&di->rxd32[i].addr, 0xdeadbeef);
18107 +
18108 + di->rxin = NEXTRXD(i);
18109 +
18110 + return (rxp);
18111 +}
18112 +
18113 +static void
18114 +dma32_txrotate(di_t *di)
18115 +{
18116 + uint ad;
18117 + uint nactive;
18118 + uint rot;
18119 + uint old, new;
18120 + uint32 w;
18121 + uint first, last;
18122 +
18123 + ASSERT(dma_txsuspendedidle(di));
18124 +
18125 + nactive = dma_txactive(di);
18126 + ad = B2I(((R_REG(&di->d32txregs->status) & XS_AD_MASK) >> XS_AD_SHIFT), dma32dd_t);
18127 + rot = TXD(ad - di->txin);
18128 +
18129 + ASSERT(rot < di->ntxd);
18130 +
18131 + /* full-ring case is a lot harder - don't worry about this */
18132 + if (rot >= (di->ntxd - nactive)) {
18133 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18134 + return;
18135 + }
18136 +
18137 + first = di->txin;
18138 + last = PREVTXD(di->txout);
18139 +
18140 + /* move entries starting at last and moving backwards to first */
18141 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18142 + new = TXD(old + rot);
18143 +
18144 + /*
18145 + * Move the tx dma descriptor.
18146 + * EOT is set only in the last entry in the ring.
18147 + */
18148 + w = R_SM(&di->txd32[old].ctrl) & ~CTRL_EOT;
18149 + if (new == (di->ntxd - 1))
18150 + w |= CTRL_EOT;
18151 + W_SM(&di->txd32[new].ctrl, w);
18152 + W_SM(&di->txd32[new].addr, R_SM(&di->txd32[old].addr));
18153 +
18154 + /* zap the old tx dma descriptor address field */
18155 + W_SM(&di->txd32[old].addr, 0xdeadbeef);
18156 +
18157 + /* move the corresponding txp[] entry */
18158 + ASSERT(di->txp[new] == NULL);
18159 + di->txp[new] = di->txp[old];
18160 + di->txp[old] = NULL;
18161 + }
18162 +
18163 + /* update txin and txout */
18164 + di->txin = ad;
18165 + di->txout = TXD(di->txout + rot);
18166 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18167 +
18168 + /* kick the chip */
18169 + W_REG(&di->d32txregs->ptr, I2B(di->txout, dma32dd_t));
18170 +}
18171 +
18172 +/*** 64 bits DMA non-inline functions ***/
18173 +
18174 +#ifdef BCMDMA64
18175 +
18176 +static bool
18177 +dma64_alloc(dma_info_t *di, uint direction)
18178 +{
18179 + uint size;
18180 + uint ddlen;
18181 + uint32 alignbytes;
18182 + void *va;
18183 +
18184 + ddlen = sizeof (dma64dd_t);
18185 +
18186 + size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
18187 +
18188 + alignbytes = di->dma64align;
18189 +
18190 + if (!ISALIGNED(DMA_CONSISTENT_ALIGN, alignbytes))
18191 + size += alignbytes;
18192 +
18193 +
18194 + if (direction == DMA_TX) {
18195 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->txdpa)) == NULL) {
18196 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
18197 + return FALSE;
18198 + }
18199 +
18200 + di->txd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
18201 + di->txdalign = (uint)((int8*)di->txd64 - (int8*)va);
18202 + di->txdpa += di->txdalign;
18203 + di->txdalloc = size;
18204 + ASSERT(ISALIGNED((uintptr)di->txd64, alignbytes));
18205 + } else {
18206 + if ((va = DMA_ALLOC_CONSISTENT(di->osh, size, &di->rxdpa)) == NULL) {
18207 + DMA_ERROR(("%s: dma_attach: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
18208 + return FALSE;
18209 + }
18210 + di->rxd64 = (dma64dd_t*) ROUNDUP((uintptr)va, alignbytes);
18211 + di->rxdalign = (uint)((int8*)di->rxd64 - (int8*)va);
18212 + di->rxdpa += di->rxdalign;
18213 + di->rxdalloc = size;
18214 + ASSERT(ISALIGNED((uintptr)di->rxd64, alignbytes));
18215 + }
18216 +
18217 + return TRUE;
18218 +}
18219 +
18220 +static void
18221 +dma64_txreset(dma_info_t *di)
18222 +{
18223 + uint32 status;
18224 +
18225 + /* suspend tx DMA first */
18226 + W_REG(&di->d64txregs->control, D64_XC_SE);
18227 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED &&
18228 + status != D64_XS0_XS_IDLE &&
18229 + status != D64_XS0_XS_STOPPED,
18230 + 10000);
18231 +
18232 + W_REG(&di->d64txregs->control, 0);
18233 + SPINWAIT((status = (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK)) != D64_XS0_XS_DISABLED,
18234 + 10000);
18235 +
18236 + if (status != D64_XS0_XS_DISABLED) {
18237 + DMA_ERROR(("%s: dma_txreset: dma cannot be stopped\n", di->name));
18238 + }
18239 +
18240 + /* wait for the last transaction to complete */
18241 + OSL_DELAY(300);
18242 +}
18243 +
18244 +static void
18245 +dma64_rxreset(dma_info_t *di)
18246 +{
18247 + uint32 status;
18248 +
18249 + W_REG(&di->d64rxregs->control, 0);
18250 + SPINWAIT((status = (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK)) != D64_RS0_RS_DISABLED,
18251 + 10000);
18252 +
18253 + if (status != D64_RS0_RS_DISABLED) {
18254 + DMA_ERROR(("%s: dma_rxreset: dma cannot be stopped\n", di->name));
18255 + }
18256 +}
18257 +
18258 +static bool
18259 +dma64_txsuspendedidle(dma_info_t *di)
18260 +{
18261 +
18262 + if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
18263 + return 0;
18264 +
18265 + if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) == D64_XS0_XS_IDLE)
18266 + return 1;
18267 +
18268 + return 0;
18269 +}
18270 +
18271 +/*
18272 + * supports full 32bit dma engine buffer addressing so
18273 + * dma buffers can cross 4 Kbyte page boundaries.
18274 + */
18275 +static int
18276 +dma64_txfast(dma_info_t *di, void *p0, uint32 coreflags)
18277 +{
18278 + void *p, *next;
18279 + uchar *data;
18280 + uint len;
18281 + uint txout;
18282 + uint32 flags;
18283 + uint32 pa;
18284 +
18285 + DMA_TRACE(("%s: dma_txfast\n", di->name));
18286 +
18287 + txout = di->txout;
18288 + flags = 0;
18289 +
18290 + /*
18291 + * Walk the chain of packet buffers
18292 + * allocating and initializing transmit descriptor entries.
18293 + */
18294 + for (p = p0; p; p = next) {
18295 + data = PKTDATA(di->osh, p);
18296 + len = PKTLEN(di->osh, p);
18297 + next = PKTNEXT(di->osh, p);
18298 +
18299 + /* return nonzero if out of tx descriptors */
18300 + if (NEXTTXD(txout) == di->txin)
18301 + goto outoftxd;
18302 +
18303 + if (len == 0)
18304 + continue;
18305 +
18306 + /* get physical address of buffer start */
18307 + pa = (uint32) DMA_MAP(di->osh, data, len, DMA_TX, p);
18308 +
18309 + flags = coreflags;
18310 +
18311 + if (p == p0)
18312 + flags |= D64_CTRL1_SOF;
18313 + if (next == NULL)
18314 + flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
18315 + if (txout == (di->ntxd - 1))
18316 + flags |= D64_CTRL1_EOT;
18317 +
18318 + dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
18319 +
18320 + ASSERT(di->txp[txout] == NULL);
18321 +
18322 + txout = NEXTTXD(txout);
18323 + }
18324 +
18325 + /* if last txd eof not set, fix it */
18326 + if (!(flags & D64_CTRL1_EOF))
18327 + W_SM(&di->txd64[PREVTXD(txout)].ctrl1, BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
18328 +
18329 + /* save the packet */
18330 + di->txp[PREVTXD(txout)] = p0;
18331 +
18332 + /* bump the tx descriptor index */
18333 + di->txout = txout;
18334 +
18335 + /* kick the chip */
18336 + W_REG(&di->d64txregs->ptr, I2B(txout, dma64dd_t));
18337 +
18338 + /* tx flow control */
18339 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18340 +
18341 + return (0);
18342 +
18343 +outoftxd:
18344 + DMA_ERROR(("%s: dma_txfast: out of txds\n", di->name));
18345 + PKTFREE(di->osh, p0, TRUE);
18346 + di->txavail = 0;
18347 + di->hnddma.txnobuf++;
18348 + return (-1);
18349 +}
18350 +
18351 +static void*
18352 +dma64_getnexttxp(dma_info_t *di, bool forceall)
18353 +{
18354 + uint start, end, i;
18355 + void *txp;
18356 +
18357 + DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name, forceall ? "all" : ""));
18358 +
18359 + txp = NULL;
18360 +
18361 + start = di->txin;
18362 + if (forceall)
18363 + end = di->txout;
18364 + else
18365 + end = B2I(R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK, dma64dd_t);
18366 +
18367 + if ((start == 0) && (end > di->txout))
18368 + goto bogus;
18369 +
18370 + for (i = start; i != end && !txp; i = NEXTTXD(i)) {
18371 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) - di->dataoffsetlow),
18372 + (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) & D64_CTRL2_BC_MASK), DMA_TX, di->txp[i]);
18373 +
18374 + W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
18375 + W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
18376 +
18377 + txp = di->txp[i];
18378 + di->txp[i] = NULL;
18379 + }
18380 +
18381 + di->txin = i;
18382 +
18383 + /* tx flow control */
18384 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18385 +
18386 + return (txp);
18387 +
18388 +bogus:
18389 +/*
18390 + DMA_ERROR(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n",
18391 + start, end, di->txout, forceall));
18392 +*/
18393 + return (NULL);
18394 +}
18395 +
18396 +static void *
18397 +dma64_getnextrxp(dma_info_t *di, bool forceall)
18398 +{
18399 + uint i;
18400 + void *rxp;
18401 +
18402 + /* if forcing, dma engine must be disabled */
18403 + ASSERT(!forceall || !dma_rxenabled(di));
18404 +
18405 + i = di->rxin;
18406 +
18407 + /* return if no packets posted */
18408 + if (i == di->rxout)
18409 + return (NULL);
18410 +
18411 + /* ignore curr if forceall */
18412 + if (!forceall && (i == B2I(R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK, dma64dd_t)))
18413 + return (NULL);
18414 +
18415 + /* get the packet pointer that corresponds to the rx descriptor */
18416 + rxp = di->rxp[i];
18417 + ASSERT(rxp);
18418 + di->rxp[i] = NULL;
18419 +
18420 + /* clear this packet from the descriptor ring */
18421 + DMA_UNMAP(di->osh, (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) - di->dataoffsetlow),
18422 + di->rxbufsize, DMA_RX, rxp);
18423 +
18424 + W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
18425 + W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
18426 +
18427 + di->rxin = NEXTRXD(i);
18428 +
18429 + return (rxp);
18430 +}
18431 +
18432 +static void
18433 +dma64_txrotate(di_t *di)
18434 +{
18435 + uint ad;
18436 + uint nactive;
18437 + uint rot;
18438 + uint old, new;
18439 + uint32 w;
18440 + uint first, last;
18441 +
18442 + ASSERT(dma_txsuspendedidle(di));
18443 +
18444 + nactive = dma_txactive(di);
18445 + ad = B2I((R_REG(&di->d64txregs->status1) & D64_XS1_AD_MASK), dma64dd_t);
18446 + rot = TXD(ad - di->txin);
18447 +
18448 + ASSERT(rot < di->ntxd);
18449 +
18450 + /* full-ring case is a lot harder - don't worry about this */
18451 + if (rot >= (di->ntxd - nactive)) {
18452 + DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
18453 + return;
18454 + }
18455 +
18456 + first = di->txin;
18457 + last = PREVTXD(di->txout);
18458 +
18459 + /* move entries starting at last and moving backwards to first */
18460 + for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
18461 + new = TXD(old + rot);
18462 +
18463 + /*
18464 + * Move the tx dma descriptor.
18465 + * EOT is set only in the last entry in the ring.
18466 + */
18467 + w = R_SM(&di->txd64[old].ctrl1) & ~D64_CTRL1_EOT;
18468 + if (new == (di->ntxd - 1))
18469 + w |= D64_CTRL1_EOT;
18470 + W_SM(&di->txd64[new].ctrl1, w);
18471 +
18472 + w = R_SM(&di->txd64[old].ctrl2);
18473 + W_SM(&di->txd64[new].ctrl2, w);
18474 +
18475 + W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
18476 + W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
18477 +
18478 + /* zap the old tx dma descriptor address field */
18479 + W_SM(&di->txd64[old].addrlow, 0xdeadbeef);
18480 + W_SM(&di->txd64[old].addrhigh, 0xdeadbeef);
18481 +
18482 + /* move the corresponding txp[] entry */
18483 + ASSERT(di->txp[new] == NULL);
18484 + di->txp[new] = di->txp[old];
18485 + di->txp[old] = NULL;
18486 + }
18487 +
18488 + /* update txin and txout */
18489 + di->txin = ad;
18490 + di->txout = TXD(di->txout + rot);
18491 + di->txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
18492 +
18493 + /* kick the chip */
18494 + W_REG(&di->d64txregs->ptr, I2B(di->txout, dma64dd_t));
18495 +}
18496 +
18497 +#endif
18498 +
18499 diff -urN linux.old/drivers/net/hnd/linux_osl.c linux.dev/drivers/net/hnd/linux_osl.c
18500 --- linux.old/drivers/net/hnd/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
18501 +++ linux.dev/drivers/net/hnd/linux_osl.c 2005-11-07 23:38:26.782893500 +0100
18502 @@ -0,0 +1,708 @@
18503 +/*
18504 + * Linux OS Independent Layer
18505 + *
18506 + * Copyright 2005, Broadcom Corporation
18507 + * All Rights Reserved.
18508 + *
18509 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
18510 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
18511 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
18512 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
18513 + *
18514 + * $Id$
18515 + */
18516 +
18517 +#define LINUX_OSL
18518 +
18519 +#include <typedefs.h>
18520 +#include <bcmendian.h>
18521 +#include <linux/module.h>
18522 +#include <linuxver.h>
18523 +#include <osl.h>
18524 +#include <bcmutils.h>
18525 +#include <linux/delay.h>
18526 +#ifdef mips
18527 +#include <asm/paccess.h>
18528 +#endif
18529 +#include <pcicfg.h>
18530 +
18531 +#define PCI_CFG_RETRY 10
18532 +
18533 +#define OS_HANDLE_MAGIC 0x1234abcd
18534 +#define BCM_MEM_FILENAME_LEN 24
18535 +
18536 +typedef struct bcm_mem_link {
18537 + struct bcm_mem_link *prev;
18538 + struct bcm_mem_link *next;
18539 + uint size;
18540 + int line;
18541 + char file[BCM_MEM_FILENAME_LEN];
18542 +} bcm_mem_link_t;
18543 +
18544 +struct os_handle {
18545 + uint magic;
18546 + void *pdev;
18547 + uint malloced;
18548 + uint failed;
18549 + bcm_mem_link_t *dbgmem_list;
18550 +};
18551 +
18552 +static int16 linuxbcmerrormap[] = \
18553 +{ 0, /* 0 */
18554 + -EINVAL, /* BCME_ERROR */
18555 + -EINVAL, /* BCME_BADARG*/
18556 + -EINVAL, /* BCME_BADOPTION*/
18557 + -EINVAL, /* BCME_NOTUP */
18558 + -EINVAL, /* BCME_NOTDOWN */
18559 + -EINVAL, /* BCME_NOTAP */
18560 + -EINVAL, /* BCME_NOTSTA */
18561 + -EINVAL, /* BCME_BADKEYIDX */
18562 + -EINVAL, /* BCME_RADIOOFF */
18563 + -EINVAL, /* BCME_NOTBANDLOCKED */
18564 + -EINVAL, /* BCME_NOCLK */
18565 + -EINVAL, /* BCME_BADRATESET */
18566 + -EINVAL, /* BCME_BADBAND */
18567 + -E2BIG, /* BCME_BUFTOOSHORT */
18568 + -E2BIG, /* BCME_BUFTOOLONG */
18569 + -EBUSY, /* BCME_BUSY */
18570 + -EINVAL, /* BCME_NOTASSOCIATED */
18571 + -EINVAL, /* BCME_BADSSIDLEN */
18572 + -EINVAL, /* BCME_OUTOFRANGECHAN */
18573 + -EINVAL, /* BCME_BADCHAN */
18574 + -EFAULT, /* BCME_BADADDR */
18575 + -ENOMEM, /* BCME_NORESOURCE */
18576 + -EOPNOTSUPP, /* BCME_UNSUPPORTED */
18577 + -EMSGSIZE, /* BCME_BADLENGTH */
18578 + -EINVAL, /* BCME_NOTREADY */
18579 + -EPERM, /* BCME_NOTPERMITTED */
18580 + -ENOMEM, /* BCME_NOMEM */
18581 + -EINVAL, /* BCME_ASSOCIATED */
18582 + -ERANGE, /* BCME_RANGE */
18583 + -EINVAL /* BCME_NOTFOUND */
18584 +};
18585 +
18586 +/* translate bcmerrors into linux errors*/
18587 +int
18588 +osl_error(int bcmerror)
18589 +{
18590 + int abs_bcmerror;
18591 + int array_size = ARRAYSIZE(linuxbcmerrormap);
18592 +
18593 + abs_bcmerror = ABS(bcmerror);
18594 +
18595 + if (bcmerror > 0)
18596 + abs_bcmerror = 0;
18597 +
18598 + else if (abs_bcmerror >= array_size)
18599 + abs_bcmerror = BCME_ERROR;
18600 +
18601 + return linuxbcmerrormap[abs_bcmerror];
18602 +}
18603 +
18604 +osl_t *
18605 +osl_attach(void *pdev)
18606 +{
18607 + osl_t *osh;
18608 +
18609 + osh = kmalloc(sizeof(osl_t), GFP_ATOMIC);
18610 + ASSERT(osh);
18611 +
18612 + /*
18613 + * check the cases where
18614 + * 1.Error code Added to bcmerror table, but forgot to add it to the OS
18615 + * dependent error code
18616 + * 2. Error code is added to the bcmerror table, but forgot to add the
18617 + * corresponding errorstring(dummy call to bcmerrorstr)
18618 + */
18619 + bcmerrorstr(0);
18620 + ASSERT(ABS(BCME_LAST) == (ARRAYSIZE(linuxbcmerrormap) - 1));
18621 +
18622 + osh->magic = OS_HANDLE_MAGIC;
18623 + osh->malloced = 0;
18624 + osh->failed = 0;
18625 + osh->dbgmem_list = NULL;
18626 + osh->pdev = pdev;
18627 +
18628 + return osh;
18629 +}
18630 +
18631 +void
18632 +osl_detach(osl_t *osh)
18633 +{
18634 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC));
18635 + kfree(osh);
18636 +}
18637 +
18638 +void*
18639 +osl_pktget(osl_t *osh, uint len, bool send)
18640 +{
18641 + struct sk_buff *skb;
18642 +
18643 + if ((skb = dev_alloc_skb(len)) == NULL)
18644 + return (NULL);
18645 +
18646 + skb_put(skb, len);
18647 +
18648 + /* ensure the cookie field is cleared */
18649 + PKTSETCOOKIE(skb, NULL);
18650 +
18651 + return ((void*) skb);
18652 +}
18653 +
18654 +void
18655 +osl_pktfree(void *p)
18656 +{
18657 + struct sk_buff *skb, *nskb;
18658 +
18659 + skb = (struct sk_buff*) p;
18660 +
18661 + /* perversion: we use skb->next to chain multi-skb packets */
18662 + while (skb) {
18663 + nskb = skb->next;
18664 + skb->next = NULL;
18665 + if (skb->destructor) {
18666 + /* cannot kfree_skb() on hard IRQ (net/core/skbuff.c) if destructor exists */
18667 + dev_kfree_skb_any(skb);
18668 + } else {
18669 + /* can free immediately (even in_irq()) if destructor does not exist */
18670 + dev_kfree_skb(skb);
18671 + }
18672 + skb = nskb;
18673 + }
18674 +}
18675 +
18676 +uint32
18677 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
18678 +{
18679 + uint val;
18680 + uint retry=PCI_CFG_RETRY;
18681 +
18682 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18683 +
18684 + /* only 4byte access supported */
18685 + ASSERT(size == 4);
18686 +
18687 + do {
18688 + pci_read_config_dword(osh->pdev, offset, &val);
18689 + if (val != 0xffffffff)
18690 + break;
18691 + } while (retry--);
18692 +
18693 +
18694 + return (val);
18695 +}
18696 +
18697 +void
18698 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
18699 +{
18700 + uint retry=PCI_CFG_RETRY;
18701 +
18702 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18703 +
18704 + /* only 4byte access supported */
18705 + ASSERT(size == 4);
18706 +
18707 + do {
18708 + pci_write_config_dword(osh->pdev, offset, val);
18709 + if (offset!=PCI_BAR0_WIN)
18710 + break;
18711 + if (osl_pci_read_config(osh,offset,size) == val)
18712 + break;
18713 + } while (retry--);
18714 +
18715 +}
18716 +
18717 +/* return bus # for the pci device pointed by osh->pdev */
18718 +uint
18719 +osl_pci_bus(osl_t *osh)
18720 +{
18721 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18722 +
18723 + return ((struct pci_dev *)osh->pdev)->bus->number;
18724 +}
18725 +
18726 +/* return slot # for the pci device pointed by osh->pdev */
18727 +uint
18728 +osl_pci_slot(osl_t *osh)
18729 +{
18730 + ASSERT(osh && (osh->magic == OS_HANDLE_MAGIC) && osh->pdev);
18731 +
18732 + return PCI_SLOT(((struct pci_dev *)osh->pdev)->devfn);
18733 +}
18734 +
18735 +static void
18736 +osl_pcmcia_attr(osl_t *osh, uint offset, char *buf, int size, bool write)
18737 +{
18738 +}
18739 +
18740 +void
18741 +osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size)
18742 +{
18743 + osl_pcmcia_attr(osh, offset, (char *) buf, size, FALSE);
18744 +}
18745 +
18746 +void
18747 +osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size)
18748 +{
18749 + osl_pcmcia_attr(osh, offset, (char *) buf, size, TRUE);
18750 +}
18751 +
18752 +
18753 +#ifdef BCMDBG_MEM
18754 +
18755 +void*
18756 +osl_debug_malloc(osl_t *osh, uint size, int line, char* file)
18757 +{
18758 + bcm_mem_link_t *p;
18759 + char* basename;
18760 +
18761 + ASSERT(size);
18762 +
18763 + if ((p = (bcm_mem_link_t*)osl_malloc(osh, sizeof(bcm_mem_link_t) + size)) == NULL)
18764 + return (NULL);
18765 +
18766 + p->size = size;
18767 + p->line = line;
18768 +
18769 + basename = strrchr(file, '/');
18770 + /* skip the '/' */
18771 + if (basename)
18772 + basename++;
18773 +
18774 + if (!basename)
18775 + basename = file;
18776 +
18777 + strncpy(p->file, basename, BCM_MEM_FILENAME_LEN);
18778 + p->file[BCM_MEM_FILENAME_LEN - 1] = '\0';
18779 +
18780 + /* link this block */
18781 + p->prev = NULL;
18782 + p->next = osh->dbgmem_list;
18783 + if (p->next)
18784 + p->next->prev = p;
18785 + osh->dbgmem_list = p;
18786 +
18787 + return p + 1;
18788 +}
18789 +
18790 +void
18791 +osl_debug_mfree(osl_t *osh, void *addr, uint size, int line, char* file)
18792 +{
18793 + bcm_mem_link_t *p = (bcm_mem_link_t *)((int8*)addr - sizeof(bcm_mem_link_t));
18794 +
18795 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18796 +
18797 + if (p->size == 0) {
18798 + printk("osl_debug_mfree: double free on addr 0x%x size %d at line %d file %s\n",
18799 + (uint)addr, size, line, file);
18800 + ASSERT(p->size);
18801 + return;
18802 + }
18803 +
18804 + if (p->size != size) {
18805 + printk("osl_debug_mfree: dealloc size %d does not match alloc size %d on addr 0x%x at line %d file %s\n",
18806 + size, p->size, (uint)addr, line, file);
18807 + ASSERT(p->size == size);
18808 + return;
18809 + }
18810 +
18811 + /* unlink this block */
18812 + if (p->prev)
18813 + p->prev->next = p->next;
18814 + if (p->next)
18815 + p->next->prev = p->prev;
18816 + if (osh->dbgmem_list == p)
18817 + osh->dbgmem_list = p->next;
18818 + p->next = p->prev = NULL;
18819 +
18820 + osl_mfree(osh, p, size + sizeof(bcm_mem_link_t));
18821 +}
18822 +
18823 +char*
18824 +osl_debug_memdump(osl_t *osh, char *buf, uint sz)
18825 +{
18826 + bcm_mem_link_t *p;
18827 + char *obuf;
18828 +
18829 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18830 + obuf = buf;
18831 +
18832 + buf += sprintf(buf, " Address\tSize\tFile:line\n");
18833 + for (p = osh->dbgmem_list; p && ((buf - obuf) < (sz - 128)); p = p->next)
18834 + buf += sprintf(buf, "0x%08x\t%5d\t%s:%d\n",
18835 + (int)p + sizeof(bcm_mem_link_t), p->size, p->file, p->line);
18836 +
18837 + return (obuf);
18838 +}
18839 +
18840 +#endif /* BCMDBG_MEM */
18841 +
18842 +void*
18843 +osl_malloc(osl_t *osh, uint size)
18844 +{
18845 + void *addr;
18846 +
18847 + /* only ASSERT if osh is defined */
18848 + if (osh)
18849 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18850 +
18851 + if ((addr = kmalloc(size, GFP_ATOMIC)) == NULL) {
18852 + if(osh)
18853 + osh->failed++;
18854 + return (NULL);
18855 + }
18856 + if (osh)
18857 + osh->malloced += size;
18858 +
18859 + return (addr);
18860 +}
18861 +
18862 +void
18863 +osl_mfree(osl_t *osh, void *addr, uint size)
18864 +{
18865 + if (osh) {
18866 + ASSERT(osh->magic == OS_HANDLE_MAGIC);
18867 + osh->malloced -= size;
18868 + }
18869 + kfree(addr);
18870 +}
18871 +
18872 +uint
18873 +osl_malloced(osl_t *osh)
18874 +{
18875 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18876 + return (osh->malloced);
18877 +}
18878 +
18879 +uint osl_malloc_failed(osl_t *osh)
18880 +{
18881 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18882 + return (osh->failed);
18883 +}
18884 +
18885 +void*
18886 +osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap)
18887 +{
18888 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18889 +
18890 + return (pci_alloc_consistent(osh->pdev, size, (dma_addr_t*)pap));
18891 +}
18892 +
18893 +void
18894 +osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa)
18895 +{
18896 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18897 +
18898 + pci_free_consistent(osh->pdev, size, va, (dma_addr_t)pa);
18899 +}
18900 +
18901 +uint
18902 +osl_dma_map(osl_t *osh, void *va, uint size, int direction)
18903 +{
18904 + int dir;
18905 +
18906 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18907 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18908 + return (pci_map_single(osh->pdev, va, size, dir));
18909 +}
18910 +
18911 +void
18912 +osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction)
18913 +{
18914 + int dir;
18915 +
18916 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
18917 + dir = (direction == DMA_TX)? PCI_DMA_TODEVICE: PCI_DMA_FROMDEVICE;
18918 + pci_unmap_single(osh->pdev, (uint32)pa, size, dir);
18919 +}
18920 +
18921 +#if defined(BINOSL)
18922 +void
18923 +osl_assert(char *exp, char *file, int line)
18924 +{
18925 + char tempbuf[255];
18926 +
18927 + sprintf(tempbuf, "assertion \"%s\" failed: file \"%s\", line %d\n", exp, file, line);
18928 + panic(tempbuf);
18929 +}
18930 +#endif /* BCMDBG || BINOSL */
18931 +
18932 +void
18933 +osl_delay(uint usec)
18934 +{
18935 + uint d;
18936 +
18937 + while (usec > 0) {
18938 + d = MIN(usec, 1000);
18939 + udelay(d);
18940 + usec -= d;
18941 + }
18942 +}
18943 +
18944 +/*
18945 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
18946 + */
18947 +#ifdef BINOSL
18948 +
18949 +int
18950 +osl_printf(const char *format, ...)
18951 +{
18952 + va_list args;
18953 + char buf[1024];
18954 + int len;
18955 +
18956 + /* sprintf into a local buffer because there *is* no "vprintk()".. */
18957 + va_start(args, format);
18958 + len = vsprintf(buf, format, args);
18959 + va_end(args);
18960 +
18961 + if (len > sizeof (buf)) {
18962 + printk("osl_printf: buffer overrun\n");
18963 + return (0);
18964 + }
18965 +
18966 + return (printk(buf));
18967 +}
18968 +
18969 +int
18970 +osl_sprintf(char *buf, const char *format, ...)
18971 +{
18972 + va_list args;
18973 + int rc;
18974 +
18975 + va_start(args, format);
18976 + rc = vsprintf(buf, format, args);
18977 + va_end(args);
18978 + return (rc);
18979 +}
18980 +
18981 +int
18982 +osl_strcmp(const char *s1, const char *s2)
18983 +{
18984 + return (strcmp(s1, s2));
18985 +}
18986 +
18987 +int
18988 +osl_strncmp(const char *s1, const char *s2, uint n)
18989 +{
18990 + return (strncmp(s1, s2, n));
18991 +}
18992 +
18993 +int
18994 +osl_strlen(const char *s)
18995 +{
18996 + return (strlen(s));
18997 +}
18998 +
18999 +char*
19000 +osl_strcpy(char *d, const char *s)
19001 +{
19002 + return (strcpy(d, s));
19003 +}
19004 +
19005 +char*
19006 +osl_strncpy(char *d, const char *s, uint n)
19007 +{
19008 + return (strncpy(d, s, n));
19009 +}
19010 +
19011 +void
19012 +bcopy(const void *src, void *dst, int len)
19013 +{
19014 + memcpy(dst, src, len);
19015 +}
19016 +
19017 +int
19018 +bcmp(const void *b1, const void *b2, int len)
19019 +{
19020 + return (memcmp(b1, b2, len));
19021 +}
19022 +
19023 +void
19024 +bzero(void *b, int len)
19025 +{
19026 + memset(b, '\0', len);
19027 +}
19028 +
19029 +uint32
19030 +osl_readl(volatile uint32 *r)
19031 +{
19032 + return (readl(r));
19033 +}
19034 +
19035 +uint16
19036 +osl_readw(volatile uint16 *r)
19037 +{
19038 + return (readw(r));
19039 +}
19040 +
19041 +uint8
19042 +osl_readb(volatile uint8 *r)
19043 +{
19044 + return (readb(r));
19045 +}
19046 +
19047 +void
19048 +osl_writel(uint32 v, volatile uint32 *r)
19049 +{
19050 + writel(v, r);
19051 +}
19052 +
19053 +void
19054 +osl_writew(uint16 v, volatile uint16 *r)
19055 +{
19056 + writew(v, r);
19057 +}
19058 +
19059 +void
19060 +osl_writeb(uint8 v, volatile uint8 *r)
19061 +{
19062 + writeb(v, r);
19063 +}
19064 +
19065 +void *
19066 +osl_uncached(void *va)
19067 +{
19068 +#ifdef mips
19069 + return ((void*)KSEG1ADDR(va));
19070 +#else
19071 + return ((void*)va);
19072 +#endif
19073 +}
19074 +
19075 +uint
19076 +osl_getcycles(void)
19077 +{
19078 + uint cycles;
19079 +
19080 +#if defined(mips)
19081 + cycles = read_c0_count() * 2;
19082 +#elif defined(__i386__)
19083 + rdtscl(cycles);
19084 +#else
19085 + cycles = 0;
19086 +#endif
19087 + return cycles;
19088 +}
19089 +
19090 +void *
19091 +osl_reg_map(uint32 pa, uint size)
19092 +{
19093 + return (ioremap_nocache((unsigned long)pa, (unsigned long)size));
19094 +}
19095 +
19096 +void
19097 +osl_reg_unmap(void *va)
19098 +{
19099 + iounmap(va);
19100 +}
19101 +
19102 +int
19103 +osl_busprobe(uint32 *val, uint32 addr)
19104 +{
19105 +#ifdef mips
19106 + return get_dbe(*val, (uint32*)addr);
19107 +#else
19108 + *val = readl(addr);
19109 + return 0;
19110 +#endif
19111 +}
19112 +
19113 +uchar*
19114 +osl_pktdata(osl_t *osh, void *skb)
19115 +{
19116 + return (((struct sk_buff*)skb)->data);
19117 +}
19118 +
19119 +uint
19120 +osl_pktlen(osl_t *osh, void *skb)
19121 +{
19122 + return (((struct sk_buff*)skb)->len);
19123 +}
19124 +
19125 +uint
19126 +osl_pktheadroom(osl_t *osh, void *skb)
19127 +{
19128 + return (uint) skb_headroom((struct sk_buff *) skb);
19129 +}
19130 +
19131 +uint
19132 +osl_pkttailroom(osl_t *osh, void *skb)
19133 +{
19134 + return (uint) skb_tailroom((struct sk_buff *) skb);
19135 +}
19136 +
19137 +void*
19138 +osl_pktnext(osl_t *osh, void *skb)
19139 +{
19140 + return (((struct sk_buff*)skb)->next);
19141 +}
19142 +
19143 +void
19144 +osl_pktsetnext(void *skb, void *x)
19145 +{
19146 + ((struct sk_buff*)skb)->next = (struct sk_buff*)x;
19147 +}
19148 +
19149 +void
19150 +osl_pktsetlen(osl_t *osh, void *skb, uint len)
19151 +{
19152 + __skb_trim((struct sk_buff*)skb, len);
19153 +}
19154 +
19155 +uchar*
19156 +osl_pktpush(osl_t *osh, void *skb, int bytes)
19157 +{
19158 + return (skb_push((struct sk_buff*)skb, bytes));
19159 +}
19160 +
19161 +uchar*
19162 +osl_pktpull(osl_t *osh, void *skb, int bytes)
19163 +{
19164 + return (skb_pull((struct sk_buff*)skb, bytes));
19165 +}
19166 +
19167 +void*
19168 +osl_pktdup(osl_t *osh, void *skb)
19169 +{
19170 + return (skb_clone((struct sk_buff*)skb, GFP_ATOMIC));
19171 +}
19172 +
19173 +void*
19174 +osl_pktcookie(void *skb)
19175 +{
19176 + return ((void*)((struct sk_buff*)skb)->csum);
19177 +}
19178 +
19179 +void
19180 +osl_pktsetcookie(void *skb, void *x)
19181 +{
19182 + ((struct sk_buff*)skb)->csum = (uint)x;
19183 +}
19184 +
19185 +void*
19186 +osl_pktlink(void *skb)
19187 +{
19188 + return (((struct sk_buff*)skb)->prev);
19189 +}
19190 +
19191 +void
19192 +osl_pktsetlink(void *skb, void *x)
19193 +{
19194 + ((struct sk_buff*)skb)->prev = (struct sk_buff*)x;
19195 +}
19196 +
19197 +uint
19198 +osl_pktprio(void *skb)
19199 +{
19200 + return (((struct sk_buff*)skb)->priority);
19201 +}
19202 +
19203 +void
19204 +osl_pktsetprio(void *skb, uint x)
19205 +{
19206 + ((struct sk_buff*)skb)->priority = x;
19207 +}
19208 +
19209 +
19210 +#endif /* BINOSL */
19211 diff -urN linux.old/drivers/net/hnd/sbutils.c linux.dev/drivers/net/hnd/sbutils.c
19212 --- linux.old/drivers/net/hnd/sbutils.c 1970-01-01 01:00:00.000000000 +0100
19213 +++ linux.dev/drivers/net/hnd/sbutils.c 2005-11-08 12:54:06.123274250 +0100
19214 @@ -0,0 +1,2823 @@
19215 +/*
19216 + * Misc utility routines for accessing chip-specific features
19217 + * of the SiliconBackplane-based Broadcom chips.
19218 + *
19219 + * Copyright 2005, Broadcom Corporation
19220 + * All Rights Reserved.
19221 + *
19222 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
19223 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
19224 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
19225 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
19226 + * $Id$
19227 + */
19228 +
19229 +#include <typedefs.h>
19230 +#include <osl.h>
19231 +#include <sbutils.h>
19232 +#include <bcmutils.h>
19233 +#include <bcmdevs.h>
19234 +#include <sbconfig.h>
19235 +#include <sbchipc.h>
19236 +#include <sbpci.h>
19237 +#include <sbpcie.h>
19238 +#include <pcicfg.h>
19239 +#include <sbpcmcia.h>
19240 +#include <sbextif.h>
19241 +#include <bcmsrom.h>
19242 +
19243 +/* debug/trace */
19244 +#define SB_ERROR(args)
19245 +
19246 +
19247 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
19248 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
19249 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
19250 +
19251 +/* misc sb info needed by some of the routines */
19252 +typedef struct sb_info {
19253 +
19254 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
19255 +
19256 + void *osh; /* osl os handle */
19257 + void *sdh; /* bcmsdh handle */
19258 +
19259 + void *curmap; /* current regs va */
19260 + void *regs[SB_MAXCORES]; /* other regs va */
19261 +
19262 + uint curidx; /* current core index */
19263 + uint dev_coreid; /* the core provides driver functions */
19264 +
19265 + bool memseg; /* flag to toggle MEM_SEG register */
19266 +
19267 + uint gpioidx; /* gpio control core index */
19268 + uint gpioid; /* gpio control coretype */
19269 +
19270 + uint numcores; /* # discovered cores */
19271 + uint coreid[SB_MAXCORES]; /* id of each core */
19272 +
19273 + void *intr_arg; /* interrupt callback function arg */
19274 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
19275 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
19276 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
19277 +
19278 +} sb_info_t;
19279 +
19280 +/* local prototypes */
19281 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19282 + uint bustype, void *sdh, char **vars, int *varsz);
19283 +static void BCMINIT(sb_scan)(sb_info_t *si);
19284 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
19285 +static uint _sb_coreidx(sb_info_t *si);
19286 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
19287 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
19288 +static uint BCMINIT(sb_chip2numcores)(uint chip);
19289 +static bool sb_ispcie(sb_info_t *si);
19290 +static bool sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen);
19291 +static int sb_pci_fixcfg(sb_info_t *si);
19292 +
19293 +/* routines to access mdio slave device registers */
19294 +static int sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint readdr, uint val);
19295 +static void BCMINIT(sb_war30841)(sb_info_t *si);
19296 +
19297 +/* delay needed between the mdio control/ mdiodata register data access */
19298 +#define PR28829_DELAY() OSL_DELAY(10)
19299 +
19300 +
19301 +/* global variable to indicate reservation/release of gpio's*/
19302 +static uint32 sb_gpioreservation = 0;
19303 +
19304 +#define SB_INFO(sbh) (sb_info_t*)sbh
19305 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
19306 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
19307 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
19308 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
19309 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
19310 +#define BADIDX (SB_MAXCORES+1)
19311 +#define NOREV -1
19312 +
19313 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
19314 +#define PCIE(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCIE))
19315 +
19316 +/* sonicsrev */
19317 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
19318 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
19319 +
19320 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
19321 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
19322 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
19323 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
19324 +
19325 +/*
19326 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
19327 + * after core switching to avoid invalid register accesss inside ISR.
19328 + */
19329 +#define INTR_OFF(si, intr_val) \
19330 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19331 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
19332 +#define INTR_RESTORE(si, intr_val) \
19333 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
19334 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
19335 +
19336 +/* dynamic clock control defines */
19337 +#define LPOMINFREQ 25000 /* low power oscillator min */
19338 +#define LPOMAXFREQ 43000 /* low power oscillator max */
19339 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
19340 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
19341 +#define PCIMINFREQ 25000000 /* 25 MHz */
19342 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
19343 +
19344 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
19345 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
19346 +
19347 +#define MIN_DUMPBUFLEN 32 /* debug */
19348 +
19349 +/* different register spaces to access thr'u pcie indirect access*/
19350 +#define PCIE_CONFIGREGS 1
19351 +#define PCIE_PCIEREGS 2
19352 +
19353 +/* GPIO Based LED powersave defines */
19354 +#define DEFAULT_GPIO_ONTIME 10
19355 +#define DEFAULT_GPIO_OFFTIME 90
19356 +
19357 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
19358 +
19359 +static uint32
19360 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
19361 +{
19362 + uint8 tmp;
19363 + uint32 val, intr_val = 0;
19364 +
19365 +
19366 + /*
19367 + * compact flash only has 11 bits address, while we needs 12 bits address.
19368 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19369 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19370 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19371 + */
19372 + if(si->memseg) {
19373 + INTR_OFF(si, intr_val);
19374 + tmp = 1;
19375 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19376 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19377 + }
19378 +
19379 + val = R_REG(sbr);
19380 +
19381 + if(si->memseg) {
19382 + tmp = 0;
19383 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19384 + INTR_RESTORE(si, intr_val);
19385 + }
19386 +
19387 + return (val);
19388 +}
19389 +
19390 +static void
19391 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
19392 +{
19393 + uint8 tmp;
19394 + volatile uint32 dummy;
19395 + uint32 intr_val = 0;
19396 +
19397 +
19398 + /*
19399 + * compact flash only has 11 bits address, while we needs 12 bits address.
19400 + * MEM_SEG will be OR'd with other 11 bits address in hardware,
19401 + * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
19402 + * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
19403 + */
19404 + if(si->memseg) {
19405 + INTR_OFF(si, intr_val);
19406 + tmp = 1;
19407 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19408 + sbr = (uint32) ((uintptr) sbr & ~(1 << 11)); /* mask out bit 11*/
19409 + }
19410 +
19411 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19412 +#ifdef IL_BIGENDIAN
19413 + dummy = R_REG(sbr);
19414 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19415 + dummy = R_REG(sbr);
19416 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19417 +#else
19418 + dummy = R_REG(sbr);
19419 + W_REG((volatile uint16 *)sbr, (uint16)(v & 0xffff));
19420 + dummy = R_REG(sbr);
19421 + W_REG(((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
19422 +#endif
19423 + } else
19424 + W_REG(sbr, v);
19425 +
19426 + if(si->memseg) {
19427 + tmp = 0;
19428 + OSL_PCMCIA_WRITE_ATTR(si->osh, MEM_SEG, &tmp, 1);
19429 + INTR_RESTORE(si, intr_val);
19430 + }
19431 +}
19432 +
19433 +/*
19434 + * Allocate a sb handle.
19435 + * devid - pci device id (used to determine chip#)
19436 + * osh - opaque OS handle
19437 + * regs - virtual address of initial core registers
19438 + * bustype - pci/pcmcia/sb/sdio/etc
19439 + * vars - pointer to a pointer area for "environment" variables
19440 + * varsz - pointer to int to return the size of the vars
19441 + */
19442 +sb_t *
19443 +BCMINITFN(sb_attach)(uint devid, osl_t *osh, void *regs,
19444 + uint bustype, void *sdh, char **vars, int *varsz)
19445 +{
19446 + sb_info_t *si;
19447 +
19448 + /* alloc sb_info_t */
19449 + if ((si = MALLOC(osh, sizeof (sb_info_t))) == NULL) {
19450 + SB_ERROR(("sb_attach: malloc failed! malloced %d bytes\n", MALLOCED(osh)));
19451 + return (NULL);
19452 + }
19453 +
19454 + if (BCMINIT(sb_doattach)(si, devid, osh, regs, bustype, sdh, vars, varsz) == NULL) {
19455 + MFREE(osh, si, sizeof (sb_info_t));
19456 + return (NULL);
19457 + }
19458 + return (sb_t *)si;
19459 +}
19460 +
19461 +/* Using sb_kattach depends on SB_BUS support, either implicit */
19462 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
19463 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
19464 +
19465 +/* global kernel resource */
19466 +static sb_info_t ksi;
19467 +
19468 +/* generic kernel variant of sb_attach() */
19469 +sb_t *
19470 +BCMINITFN(sb_kattach)()
19471 +{
19472 + uint32 *regs;
19473 +
19474 + if (ksi.curmap == NULL) {
19475 + uint32 cid;
19476 +
19477 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
19478 + cid = R_REG((uint32 *)regs);
19479 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
19480 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
19481 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
19482 + uint32 *scc, val;
19483 +
19484 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
19485 + val = R_REG(scc);
19486 + SB_ERROR((" initial scc = 0x%x\n", val));
19487 + val |= SCC_SS_XTAL;
19488 + W_REG(scc, val);
19489 + }
19490 +
19491 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
19492 + SB_BUS, NULL, NULL, NULL) == NULL) {
19493 + return NULL;
19494 + }
19495 + }
19496 +
19497 + return (sb_t *)&ksi;
19498 +}
19499 +#endif
19500 +
19501 +static sb_info_t *
19502 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
19503 + uint bustype, void *sdh, char **vars, int *varsz)
19504 +{
19505 + uint origidx;
19506 + chipcregs_t *cc;
19507 + sbconfig_t *sb;
19508 + uint32 w;
19509 +
19510 + ASSERT(GOODREGS(regs));
19511 +
19512 + bzero((uchar*)si, sizeof (sb_info_t));
19513 +
19514 + si->sb.buscoreidx = si->gpioidx = BADIDX;
19515 +
19516 + si->osh = osh;
19517 + si->curmap = regs;
19518 + si->sdh = sdh;
19519 +
19520 + /* check to see if we are a sb core mimic'ing a pci core */
19521 + if (bustype == PCI_BUS) {
19522 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
19523 + bustype = SB_BUS;
19524 + else
19525 + bustype = PCI_BUS;
19526 + }
19527 +
19528 + si->sb.bustype = bustype;
19529 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
19530 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
19531 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
19532 + return NULL;
19533 + }
19534 +
19535 + /* need to set memseg flag for CF card first before any sb registers access */
19536 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19537 + si->memseg = TRUE;
19538 +
19539 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
19540 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
19541 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
19542 +
19543 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19544 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
19545 + if (!GOODCOREADDR(w))
19546 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
19547 + }
19548 +
19549 + /* initialize current core index value */
19550 + si->curidx = _sb_coreidx(si);
19551 +
19552 + if (si->curidx == BADIDX) {
19553 + SB_ERROR(("sb_doattach: bad core index\n"));
19554 + return NULL;
19555 + }
19556 +
19557 + /* get sonics backplane revision */
19558 + sb = REGS2SB(si->curmap);
19559 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
19560 +
19561 + /* keep and reuse the initial register mapping */
19562 + origidx = si->curidx;
19563 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
19564 + si->regs[origidx] = regs;
19565 +
19566 + /* is core-0 a chipcommon core? */
19567 + si->numcores = 1;
19568 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
19569 + if (sb_coreid(&si->sb) != SB_CC)
19570 + cc = NULL;
19571 +
19572 + /* determine chip id and rev */
19573 + if (cc) {
19574 + /* chip common core found! */
19575 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
19576 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
19577 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
19578 + } else {
19579 + /* The only pcmcia chip without a chipcommon core is a 4301 */
19580 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS)
19581 + devid = BCM4301_DEVICE_ID;
19582 +
19583 + /* no chip common core -- must convert device id to chip id */
19584 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
19585 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
19586 + sb_setcoreidx(&si->sb, origidx);
19587 + return NULL;
19588 + }
19589 + }
19590 +
19591 + /* get chipcommon rev */
19592 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
19593 +
19594 + /* determine numcores */
19595 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
19596 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
19597 + else
19598 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
19599 +
19600 + /* return to original core */
19601 + sb_setcoreidx(&si->sb, origidx);
19602 +
19603 + /* sanity checks */
19604 + ASSERT(si->sb.chip);
19605 +
19606 + /* scan for cores */
19607 + BCMINIT(sb_scan)(si);
19608 +
19609 + /* fixup necessary chip/core configurations */
19610 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19611 + if (sb_pci_fixcfg(si)) {
19612 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
19613 + return NULL;
19614 + }
19615 + }
19616 +
19617 + /* srom_var_init() depends on sb_scan() info */
19618 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
19619 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
19620 + return (NULL);
19621 + }
19622 +
19623 + if (cc == NULL) {
19624 + /*
19625 + * The chip revision number is hardwired into all
19626 + * of the pci function config rev fields and is
19627 + * independent from the individual core revision numbers.
19628 + * For example, the "A0" silicon of each chip is chip rev 0.
19629 + * For PCMCIA we get it from the CIS instead.
19630 + */
19631 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19632 + ASSERT(vars);
19633 + si->sb.chiprev = getintvar(*vars, "chiprev");
19634 + } else if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
19635 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
19636 + si->sb.chiprev = w & 0xff;
19637 + } else
19638 + si->sb.chiprev = 0;
19639 + }
19640 +
19641 + if (BUSTYPE(si->sb.bustype) == PCMCIA_BUS) {
19642 + w = getintvar(*vars, "regwindowsz");
19643 + si->memseg = (w <= CFTABLE_REGWIN_2K) ? TRUE : FALSE;
19644 + }
19645 +
19646 + /* gpio control core is required */
19647 + if (!GOODIDX(si->gpioidx)) {
19648 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
19649 + return NULL;
19650 + }
19651 +
19652 + /* get boardtype and boardrev */
19653 + switch (BUSTYPE(si->sb.bustype)) {
19654 + case PCI_BUS:
19655 + /* do a pci config read to get subsystem id and subvendor id */
19656 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
19657 + si->sb.boardvendor = w & 0xffff;
19658 + si->sb.boardtype = (w >> 16) & 0xffff;
19659 + break;
19660 +
19661 + case PCMCIA_BUS:
19662 + case SDIO_BUS:
19663 + si->sb.boardvendor = getintvar(*vars, "manfid");
19664 + si->sb.boardtype = getintvar(*vars, "prodid");
19665 + break;
19666 +
19667 + case SB_BUS:
19668 + case JTAG_BUS:
19669 + si->sb.boardvendor = VENDOR_BROADCOM;
19670 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
19671 + si->sb.boardtype = 0xffff;
19672 + break;
19673 + }
19674 +
19675 + if (si->sb.boardtype == 0) {
19676 + SB_ERROR(("sb_doattach: unknown board type\n"));
19677 + ASSERT(si->sb.boardtype);
19678 + }
19679 +
19680 + /* setup the GPIO based LED powersave register */
19681 + if (si->sb.ccrev >= 16) {
19682 + w = getintvar(*vars, "gpiotimerval");
19683 + if (!w)
19684 + w = DEFAULT_GPIOTIMERVAL;
19685 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
19686 + }
19687 +
19688 +
19689 + return (si);
19690 +}
19691 +
19692 +uint
19693 +sb_coreid(sb_t *sbh)
19694 +{
19695 + sb_info_t *si;
19696 + sbconfig_t *sb;
19697 +
19698 + si = SB_INFO(sbh);
19699 + sb = REGS2SB(si->curmap);
19700 +
19701 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
19702 +}
19703 +
19704 +uint
19705 +sb_coreidx(sb_t *sbh)
19706 +{
19707 + sb_info_t *si;
19708 +
19709 + si = SB_INFO(sbh);
19710 + return (si->curidx);
19711 +}
19712 +
19713 +/* return current index of core */
19714 +static uint
19715 +_sb_coreidx(sb_info_t *si)
19716 +{
19717 + sbconfig_t *sb;
19718 + uint32 sbaddr = 0;
19719 +
19720 + ASSERT(si);
19721 +
19722 + switch (BUSTYPE(si->sb.bustype)) {
19723 + case SB_BUS:
19724 + sb = REGS2SB(si->curmap);
19725 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
19726 + break;
19727 +
19728 + case PCI_BUS:
19729 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
19730 + break;
19731 +
19732 + case PCMCIA_BUS: {
19733 + uint8 tmp = 0;
19734 +
19735 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
19736 + sbaddr = (uint)tmp << 12;
19737 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
19738 + sbaddr |= (uint)tmp << 16;
19739 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
19740 + sbaddr |= (uint)tmp << 24;
19741 + break;
19742 + }
19743 +
19744 +#ifdef BCMJTAG
19745 + case JTAG_BUS:
19746 + sbaddr = (uint32)si->curmap;
19747 + break;
19748 +#endif /* BCMJTAG */
19749 +
19750 + default:
19751 + ASSERT(0);
19752 + }
19753 +
19754 + if (!GOODCOREADDR(sbaddr))
19755 + return BADIDX;
19756 +
19757 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
19758 +}
19759 +
19760 +uint
19761 +sb_corevendor(sb_t *sbh)
19762 +{
19763 + sb_info_t *si;
19764 + sbconfig_t *sb;
19765 +
19766 + si = SB_INFO(sbh);
19767 + sb = REGS2SB(si->curmap);
19768 +
19769 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
19770 +}
19771 +
19772 +uint
19773 +sb_corerev(sb_t *sbh)
19774 +{
19775 + sb_info_t *si;
19776 + sbconfig_t *sb;
19777 + uint sbidh;
19778 +
19779 + si = SB_INFO(sbh);
19780 + sb = REGS2SB(si->curmap);
19781 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
19782 +
19783 + return (SBCOREREV(sbidh));
19784 +}
19785 +
19786 +void *
19787 +sb_osh(sb_t *sbh)
19788 +{
19789 + sb_info_t *si;
19790 +
19791 + si = SB_INFO(sbh);
19792 + return si->osh;
19793 +}
19794 +
19795 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
19796 +
19797 +/* set/clear sbtmstatelow core-specific flags */
19798 +uint32
19799 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
19800 +{
19801 + sb_info_t *si;
19802 + sbconfig_t *sb;
19803 + uint32 w;
19804 +
19805 + si = SB_INFO(sbh);
19806 + sb = REGS2SB(si->curmap);
19807 +
19808 + ASSERT((val & ~mask) == 0);
19809 + ASSERT((mask & ~SBTML_ALLOW) == 0);
19810 +
19811 + /* mask and set */
19812 + if (mask || val) {
19813 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
19814 + W_SBREG(si, &sb->sbtmstatelow, w);
19815 + }
19816 +
19817 + /* return the new value */
19818 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
19819 +}
19820 +
19821 +/* set/clear sbtmstatehigh core-specific flags */
19822 +uint32
19823 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
19824 +{
19825 + sb_info_t *si;
19826 + sbconfig_t *sb;
19827 + uint32 w;
19828 +
19829 + si = SB_INFO(sbh);
19830 + sb = REGS2SB(si->curmap);
19831 +
19832 + ASSERT((val & ~mask) == 0);
19833 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
19834 +
19835 + /* mask and set */
19836 + if (mask || val) {
19837 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
19838 + W_SBREG(si, &sb->sbtmstatehigh, w);
19839 + }
19840 +
19841 + /* return the new value */
19842 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
19843 +}
19844 +
19845 +/* caller needs to take care of core-specific bist hazards */
19846 +int
19847 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
19848 +{
19849 + uint32 sblo;
19850 + uint coreidx;
19851 + sb_info_t *si;
19852 + int result = 0;
19853 +
19854 + si = SB_INFO(sbh);
19855 +
19856 + coreidx = sb_findcoreidx(si, coreid, coreunit);
19857 + if (!GOODIDX(coreidx))
19858 + result = BCME_ERROR;
19859 + else {
19860 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
19861 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
19862 +
19863 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
19864 +
19865 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
19866 + result = BCME_ERROR;
19867 +
19868 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
19869 + }
19870 +
19871 + return result;
19872 +}
19873 +
19874 +bool
19875 +sb_iscoreup(sb_t *sbh)
19876 +{
19877 + sb_info_t *si;
19878 + sbconfig_t *sb;
19879 +
19880 + si = SB_INFO(sbh);
19881 + sb = REGS2SB(si->curmap);
19882 +
19883 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
19884 +}
19885 +
19886 +/*
19887 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
19888 + * switch back to the original core, and return the new value.
19889 + */
19890 +static uint
19891 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
19892 +{
19893 + uint origidx;
19894 + uint32 *r;
19895 + uint w;
19896 + uint intr_val = 0;
19897 +
19898 + ASSERT(GOODIDX(coreidx));
19899 + ASSERT(regoff < SB_CORE_SIZE);
19900 + ASSERT((val & ~mask) == 0);
19901 +
19902 + INTR_OFF(si, intr_val);
19903 +
19904 + /* save current core index */
19905 + origidx = sb_coreidx(&si->sb);
19906 +
19907 + /* switch core */
19908 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
19909 +
19910 + /* mask and set */
19911 + if (mask || val) {
19912 + if (regoff >= SBCONFIGOFF) {
19913 + w = (R_SBREG(si, r) & ~mask) | val;
19914 + W_SBREG(si, r, w);
19915 + } else {
19916 + w = (R_REG(r) & ~mask) | val;
19917 + W_REG(r, w);
19918 + }
19919 + }
19920 +
19921 + /* readback */
19922 + if (regoff >= SBCONFIGOFF)
19923 + w = R_SBREG(si, r);
19924 + else
19925 + w = R_REG(r);
19926 +
19927 + /* restore core index */
19928 + if (origidx != coreidx)
19929 + sb_setcoreidx(&si->sb, origidx);
19930 +
19931 + INTR_RESTORE(si, intr_val);
19932 + return (w);
19933 +}
19934 +
19935 +#define DWORD_ALIGN(x) (x & ~(0x03))
19936 +#define BYTE_POS(x) (x & 0x3)
19937 +#define WORD_POS(x) (x & 0x1)
19938 +
19939 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
19940 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
19941 +
19942 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
19943 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
19944 +
19945 +#define read_pci_cfg_byte(a) \
19946 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
19947 +
19948 +#define read_pci_cfg_write(a) \
19949 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
19950 +
19951 +
19952 +/* return TRUE if requested capability exists in the PCI config space */
19953 +static bool
19954 +sb_find_pci_capability(sb_info_t *si, uint8 req_cap_id, uchar *buf, uint32 *buflen)
19955 +{
19956 + uint8 cap_id;
19957 + uint8 cap_ptr;
19958 + uint32 bufsize;
19959 + uint8 byte_val;
19960 +
19961 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
19962 + return FALSE;
19963 +
19964 + /* check for Header type 0*/
19965 + byte_val = read_pci_cfg_byte(PCI_CFG_HDR);
19966 + if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
19967 + return FALSE;
19968 +
19969 + /* check if the capability pointer field exists */
19970 + byte_val = read_pci_cfg_byte(PCI_CFG_STAT);
19971 + if (!(byte_val & PCI_CAPPTR_PRESENT))
19972 + return FALSE;
19973 +
19974 + cap_ptr = read_pci_cfg_byte(PCI_CFG_CAPPTR);
19975 + /* check if the capability pointer is 0x00 */
19976 + if (cap_ptr == 0x00)
19977 + return FALSE;
19978 +
19979 +
19980 + /* loop thr'u the capability list and see if the pcie capabilty exists */
19981 +
19982 + cap_id = read_pci_cfg_byte(cap_ptr);
19983 +
19984 + while (cap_id != req_cap_id) {
19985 + cap_ptr = read_pci_cfg_byte((cap_ptr+1));
19986 + if (cap_ptr == 0x00) break;
19987 + cap_id = read_pci_cfg_byte(cap_ptr);
19988 + }
19989 + if (cap_id != req_cap_id) {
19990 + return FALSE;
19991 + }
19992 + /* found the caller requested capability */
19993 + if ((buf != NULL) && (buflen != NULL)) {
19994 + bufsize = *buflen;
19995 + if (!bufsize) goto end;
19996 + *buflen = 0;
19997 + /* copy the cpability data excluding cap ID and next ptr */
19998 + cap_ptr += 2;
19999 + if ((bufsize + cap_ptr) > SZPCR)
20000 + bufsize = SZPCR - cap_ptr;
20001 + *buflen = bufsize;
20002 + while (bufsize--) {
20003 + *buf = read_pci_cfg_byte(cap_ptr);
20004 + cap_ptr++;
20005 + buf++;
20006 + }
20007 + }
20008 +end:
20009 + return TRUE;
20010 +}
20011 +
20012 +/* return TRUE if PCIE capability exists the pci config space */
20013 +static bool
20014 +sb_ispcie(sb_info_t *si)
20015 +{
20016 + return(sb_find_pci_capability(si, PCI_CAP_PCIECAP_ID, NULL, NULL));
20017 +}
20018 +
20019 +/* scan the sb enumerated space to identify all cores */
20020 +static void
20021 +BCMINITFN(sb_scan)(sb_info_t *si)
20022 +{
20023 + uint origidx;
20024 + uint i;
20025 + bool pci;
20026 + bool pcie;
20027 + uint pciidx;
20028 + uint pcieidx;
20029 + uint pcirev;
20030 + uint pcierev;
20031 +
20032 +
20033 +
20034 + /* numcores should already be set */
20035 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
20036 +
20037 + /* save current core index */
20038 + origidx = sb_coreidx(&si->sb);
20039 +
20040 + si->sb.buscorerev = NOREV;
20041 + si->sb.buscoreidx = BADIDX;
20042 +
20043 + si->gpioidx = BADIDX;
20044 +
20045 + pci = pcie = FALSE;
20046 + pcirev = pcierev = NOREV;
20047 + pciidx = pcieidx = BADIDX;
20048 +
20049 + for (i = 0; i < si->numcores; i++) {
20050 + sb_setcoreidx(&si->sb, i);
20051 + si->coreid[i] = sb_coreid(&si->sb);
20052 +
20053 + if (si->coreid[i] == SB_PCI) {
20054 + pciidx = i;
20055 + pcirev = sb_corerev(&si->sb);
20056 + pci = TRUE;
20057 + } else if (si->coreid[i] == SB_PCIE) {
20058 + pcieidx = i;
20059 + pcierev = sb_corerev(&si->sb);
20060 + pcie = TRUE;
20061 + } else if (si->coreid[i] == SB_PCMCIA) {
20062 + si->sb.buscorerev = sb_corerev(&si->sb);
20063 + si->sb.buscoretype = si->coreid[i];
20064 + si->sb.buscoreidx = i;
20065 + }
20066 + }
20067 + if (pci && pcie) {
20068 + if (sb_ispcie(si))
20069 + pci = FALSE;
20070 + else
20071 + pcie = FALSE;
20072 + }
20073 + if (pci) {
20074 + si->sb.buscoretype = SB_PCI;
20075 + si->sb.buscorerev = pcirev;
20076 + si->sb.buscoreidx = pciidx;
20077 + }
20078 + else if (pcie) {
20079 + si->sb.buscoretype = SB_PCIE;
20080 + si->sb.buscorerev = pcierev;
20081 + si->sb.buscoreidx = pcieidx;
20082 + }
20083 +
20084 + /*
20085 + * Find the gpio "controlling core" type and index.
20086 + * Precedence:
20087 + * - if there's a chip common core - use that
20088 + * - else if there's a pci core (rev >= 2) - use that
20089 + * - else there had better be an extif core (4710 only)
20090 + */
20091 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
20092 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
20093 + si->gpioid = SB_CC;
20094 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
20095 + si->gpioidx = si->sb.buscoreidx;
20096 + si->gpioid = SB_PCI;
20097 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
20098 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
20099 + si->gpioid = SB_EXTIF;
20100 + } else
20101 + ASSERT(si->gpioidx != BADIDX);
20102 +
20103 + /* return to original core index */
20104 + sb_setcoreidx(&si->sb, origidx);
20105 +}
20106 +
20107 +/* may be called with core in reset */
20108 +void
20109 +sb_detach(sb_t *sbh)
20110 +{
20111 + sb_info_t *si;
20112 + uint idx;
20113 +
20114 + si = SB_INFO(sbh);
20115 +
20116 + if (si == NULL)
20117 + return;
20118 +
20119 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
20120 + for (idx = 0; idx < SB_MAXCORES; idx++)
20121 + if (si->regs[idx]) {
20122 + REG_UNMAP(si->regs[idx]);
20123 + si->regs[idx] = NULL;
20124 + }
20125 +
20126 + if (si != &ksi)
20127 + MFREE(si->osh, si, sizeof (sb_info_t));
20128 +}
20129 +
20130 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
20131 +static uint
20132 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
20133 +{
20134 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
20135 + return (BCM4710_DEVICE_ID);
20136 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
20137 + return (BCM4402_DEVICE_ID);
20138 + if (pcidev == BCM4401_ENET_ID)
20139 + return (BCM4402_DEVICE_ID);
20140 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
20141 + return (BCM4307_DEVICE_ID);
20142 + if (pcidev == BCM4301_DEVICE_ID)
20143 + return (BCM4301_DEVICE_ID);
20144 +
20145 + return (0);
20146 +}
20147 +
20148 +/* convert chip number to number of i/o cores */
20149 +static uint
20150 +BCMINITFN(sb_chip2numcores)(uint chip)
20151 +{
20152 + if (chip == BCM4710_DEVICE_ID)
20153 + return (9);
20154 + if (chip == BCM4402_DEVICE_ID)
20155 + return (3);
20156 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
20157 + return (5);
20158 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
20159 + return (6);
20160 + if (chip == BCM4704_DEVICE_ID)
20161 + return (9);
20162 + if (chip == BCM5365_DEVICE_ID)
20163 + return (7);
20164 +
20165 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
20166 + ASSERT(0);
20167 + return (1);
20168 +}
20169 +
20170 +/* return index of coreid or BADIDX if not found */
20171 +static uint
20172 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
20173 +{
20174 + uint found;
20175 + uint i;
20176 +
20177 + found = 0;
20178 +
20179 + for (i = 0; i < si->numcores; i++)
20180 + if (si->coreid[i] == coreid) {
20181 + if (found == coreunit)
20182 + return (i);
20183 + found++;
20184 + }
20185 +
20186 + return (BADIDX);
20187 +}
20188 +
20189 +/*
20190 + * this function changes logical "focus" to the indiciated core,
20191 + * must be called with interrupt off.
20192 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20193 + */
20194 +void*
20195 +sb_setcoreidx(sb_t *sbh, uint coreidx)
20196 +{
20197 + sb_info_t *si;
20198 + uint32 sbaddr;
20199 + uint8 tmp;
20200 +
20201 + si = SB_INFO(sbh);
20202 +
20203 + if (coreidx >= si->numcores)
20204 + return (NULL);
20205 +
20206 + /*
20207 + * If the user has provided an interrupt mask enabled function,
20208 + * then assert interrupts are disabled before switching the core.
20209 + */
20210 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
20211 +
20212 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
20213 +
20214 + switch (BUSTYPE(si->sb.bustype)) {
20215 + case SB_BUS:
20216 + /* map new one */
20217 + if (!si->regs[coreidx]) {
20218 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
20219 + ASSERT(GOODREGS(si->regs[coreidx]));
20220 + }
20221 + si->curmap = si->regs[coreidx];
20222 + break;
20223 +
20224 + case PCI_BUS:
20225 + /* point bar0 window */
20226 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
20227 + break;
20228 +
20229 + case PCMCIA_BUS:
20230 + tmp = (sbaddr >> 12) & 0x0f;
20231 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR0, &tmp, 1);
20232 + tmp = (sbaddr >> 16) & 0xff;
20233 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR1, &tmp, 1);
20234 + tmp = (sbaddr >> 24) & 0xff;
20235 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_ADDR2, &tmp, 1);
20236 + break;
20237 +#ifdef BCMJTAG
20238 + case JTAG_BUS:
20239 + /* map new one */
20240 + if (!si->regs[coreidx]) {
20241 + si->regs[coreidx] = (void *)sbaddr;
20242 + ASSERT(GOODREGS(si->regs[coreidx]));
20243 + }
20244 + si->curmap = si->regs[coreidx];
20245 + break;
20246 +#endif /* BCMJTAG */
20247 + }
20248 +
20249 + si->curidx = coreidx;
20250 +
20251 + return (si->curmap);
20252 +}
20253 +
20254 +/*
20255 + * this function changes logical "focus" to the indiciated core,
20256 + * must be called with interrupt off.
20257 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
20258 + */
20259 +void*
20260 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
20261 +{
20262 + sb_info_t *si;
20263 + uint idx;
20264 +
20265 + si = SB_INFO(sbh);
20266 + idx = sb_findcoreidx(si, coreid, coreunit);
20267 + if (!GOODIDX(idx))
20268 + return (NULL);
20269 +
20270 + return (sb_setcoreidx(sbh, idx));
20271 +}
20272 +
20273 +/* return chip number */
20274 +uint
20275 +BCMINITFN(sb_chip)(sb_t *sbh)
20276 +{
20277 + sb_info_t *si;
20278 +
20279 + si = SB_INFO(sbh);
20280 + return (si->sb.chip);
20281 +}
20282 +
20283 +/* return chip revision number */
20284 +uint
20285 +BCMINITFN(sb_chiprev)(sb_t *sbh)
20286 +{
20287 + sb_info_t *si;
20288 +
20289 + si = SB_INFO(sbh);
20290 + return (si->sb.chiprev);
20291 +}
20292 +
20293 +/* return chip common revision number */
20294 +uint
20295 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
20296 +{
20297 + sb_info_t *si;
20298 +
20299 + si = SB_INFO(sbh);
20300 + return (si->sb.ccrev);
20301 +}
20302 +
20303 +/* return chip package option */
20304 +uint
20305 +BCMINITFN(sb_chippkg)(sb_t *sbh)
20306 +{
20307 + sb_info_t *si;
20308 +
20309 + si = SB_INFO(sbh);
20310 + return (si->sb.chippkg);
20311 +}
20312 +
20313 +/* return PCI core rev. */
20314 +uint
20315 +BCMINITFN(sb_pcirev)(sb_t *sbh)
20316 +{
20317 + sb_info_t *si;
20318 +
20319 + si = SB_INFO(sbh);
20320 + return (si->sb.buscorerev);
20321 +}
20322 +
20323 +bool
20324 +BCMINITFN(sb_war16165)(sb_t *sbh)
20325 +{
20326 + sb_info_t *si;
20327 +
20328 + si = SB_INFO(sbh);
20329 +
20330 + return (PCI(si) && (si->sb.buscorerev <= 10));
20331 +}
20332 +
20333 +static void
20334 +BCMINITFN(sb_war30841)(sb_info_t *si)
20335 +{
20336 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
20337 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
20338 + sb_pcie_mdiowrite(si, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
20339 +}
20340 +
20341 +/* return PCMCIA core rev. */
20342 +uint
20343 +BCMINITFN(sb_pcmciarev)(sb_t *sbh)
20344 +{
20345 + sb_info_t *si;
20346 +
20347 + si = SB_INFO(sbh);
20348 + return (si->sb.buscorerev);
20349 +}
20350 +
20351 +/* return board vendor id */
20352 +uint
20353 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
20354 +{
20355 + sb_info_t *si;
20356 +
20357 + si = SB_INFO(sbh);
20358 + return (si->sb.boardvendor);
20359 +}
20360 +
20361 +/* return boardtype */
20362 +uint
20363 +BCMINITFN(sb_boardtype)(sb_t *sbh)
20364 +{
20365 + sb_info_t *si;
20366 + char *var;
20367 +
20368 + si = SB_INFO(sbh);
20369 +
20370 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
20371 + /* boardtype format is a hex string */
20372 + si->sb.boardtype = getintvar(NULL, "boardtype");
20373 +
20374 + /* backward compatibility for older boardtype string format */
20375 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
20376 + if (!strcmp(var, "bcm94710dev"))
20377 + si->sb.boardtype = BCM94710D_BOARD;
20378 + else if (!strcmp(var, "bcm94710ap"))
20379 + si->sb.boardtype = BCM94710AP_BOARD;
20380 + else if (!strcmp(var, "bu4710"))
20381 + si->sb.boardtype = BU4710_BOARD;
20382 + else if (!strcmp(var, "bcm94702mn"))
20383 + si->sb.boardtype = BCM94702MN_BOARD;
20384 + else if (!strcmp(var, "bcm94710r1"))
20385 + si->sb.boardtype = BCM94710R1_BOARD;
20386 + else if (!strcmp(var, "bcm94710r4"))
20387 + si->sb.boardtype = BCM94710R4_BOARD;
20388 + else if (!strcmp(var, "bcm94702cpci"))
20389 + si->sb.boardtype = BCM94702CPCI_BOARD;
20390 + else if (!strcmp(var, "bcm95380_rr"))
20391 + si->sb.boardtype = BCM95380RR_BOARD;
20392 + }
20393 + }
20394 +
20395 + return (si->sb.boardtype);
20396 +}
20397 +
20398 +/* return bus type of sbh device */
20399 +uint
20400 +sb_bus(sb_t *sbh)
20401 +{
20402 + sb_info_t *si;
20403 +
20404 + si = SB_INFO(sbh);
20405 + return (si->sb.bustype);
20406 +}
20407 +
20408 +/* return bus core type */
20409 +uint
20410 +sb_buscoretype(sb_t *sbh)
20411 +{
20412 + sb_info_t *si;
20413 +
20414 + si = SB_INFO(sbh);
20415 +
20416 + return (si->sb.buscoretype);
20417 +}
20418 +
20419 +/* return bus core revision */
20420 +uint
20421 +sb_buscorerev(sb_t *sbh)
20422 +{
20423 + sb_info_t *si;
20424 + si = SB_INFO(sbh);
20425 +
20426 + return (si->sb.buscorerev);
20427 +}
20428 +
20429 +/* return list of found cores */
20430 +uint
20431 +sb_corelist(sb_t *sbh, uint coreid[])
20432 +{
20433 + sb_info_t *si;
20434 +
20435 + si = SB_INFO(sbh);
20436 +
20437 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
20438 + return (si->numcores);
20439 +}
20440 +
20441 +/* return current register mapping */
20442 +void *
20443 +sb_coreregs(sb_t *sbh)
20444 +{
20445 + sb_info_t *si;
20446 +
20447 + si = SB_INFO(sbh);
20448 + ASSERT(GOODREGS(si->curmap));
20449 +
20450 + return (si->curmap);
20451 +}
20452 +
20453 +
20454 +/* do buffered registers update */
20455 +void
20456 +sb_commit(sb_t *sbh)
20457 +{
20458 + sb_info_t *si;
20459 + uint origidx;
20460 + uint intr_val = 0;
20461 +
20462 + si = SB_INFO(sbh);
20463 +
20464 + origidx = si->curidx;
20465 + ASSERT(GOODIDX(origidx));
20466 +
20467 + INTR_OFF(si, intr_val);
20468 +
20469 + /* switch over to chipcommon core if there is one, else use pci */
20470 + if (si->sb.ccrev != NOREV) {
20471 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
20472 +
20473 + /* do the buffer registers update */
20474 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
20475 + W_REG(&ccregs->broadcastdata, 0x0);
20476 + } else if (PCI(si)) {
20477 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
20478 +
20479 + /* do the buffer registers update */
20480 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
20481 + W_REG(&pciregs->bcastdata, 0x0);
20482 + } else
20483 + ASSERT(0);
20484 +
20485 + /* restore core index */
20486 + sb_setcoreidx(sbh, origidx);
20487 + INTR_RESTORE(si, intr_val);
20488 +}
20489 +
20490 +/* reset and re-enable a core */
20491 +void
20492 +sb_core_reset(sb_t *sbh, uint32 bits)
20493 +{
20494 + sb_info_t *si;
20495 + sbconfig_t *sb;
20496 + volatile uint32 dummy;
20497 +
20498 + si = SB_INFO(sbh);
20499 + ASSERT(GOODREGS(si->curmap));
20500 + sb = REGS2SB(si->curmap);
20501 +
20502 + /*
20503 + * Must do the disable sequence first to work for arbitrary current core state.
20504 + */
20505 + sb_core_disable(sbh, bits);
20506 +
20507 + /*
20508 + * Now do the initialization sequence.
20509 + */
20510 +
20511 + /* set reset while enabling the clock and forcing them on throughout the core */
20512 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
20513 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20514 + OSL_DELAY(1);
20515 +
20516 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
20517 + W_SBREG(si, &sb->sbtmstatehigh, 0);
20518 + }
20519 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
20520 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
20521 + }
20522 +
20523 + /* clear reset and allow it to propagate throughout the core */
20524 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
20525 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20526 + OSL_DELAY(1);
20527 +
20528 + /* leave clock enabled */
20529 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
20530 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20531 + OSL_DELAY(1);
20532 +}
20533 +
20534 +void
20535 +sb_core_tofixup(sb_t *sbh)
20536 +{
20537 + sb_info_t *si;
20538 + sbconfig_t *sb;
20539 +
20540 + si = SB_INFO(sbh);
20541 +
20542 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || PCIE(si) || (PCI(si) && (si->sb.buscorerev >= 5)) )
20543 + return;
20544 +
20545 + ASSERT(GOODREGS(si->curmap));
20546 + sb = REGS2SB(si->curmap);
20547 +
20548 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
20549 + SET_SBREG(si, &sb->sbimconfiglow,
20550 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20551 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
20552 + } else {
20553 + if (sb_coreid(sbh) == SB_PCI) {
20554 + SET_SBREG(si, &sb->sbimconfiglow,
20555 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20556 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20557 + } else {
20558 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
20559 + }
20560 + }
20561 +
20562 + sb_commit(sbh);
20563 +}
20564 +
20565 +/*
20566 + * Set the initiator timeout for the "master core".
20567 + * The master core is defined to be the core in control
20568 + * of the chip and so it issues accesses to non-memory
20569 + * locations (Because of dma *any* core can access memeory).
20570 + *
20571 + * The routine uses the bus to decide who is the master:
20572 + * SB_BUS => mips
20573 + * JTAG_BUS => chipc
20574 + * PCI_BUS => pci or pcie
20575 + * PCMCIA_BUS => pcmcia
20576 + * SDIO_BUS => pcmcia
20577 + *
20578 + * This routine exists so callers can disable initiator
20579 + * timeouts so accesses to very slow devices like otp
20580 + * won't cause an abort. The routine allows arbitrary
20581 + * settings of the service and request timeouts, though.
20582 + *
20583 + * Returns the timeout state before changing it or -1
20584 + * on error.
20585 + */
20586 +
20587 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
20588 +
20589 +uint32
20590 +sb_set_initiator_to(sb_t *sbh, uint32 to)
20591 +{
20592 + sb_info_t *si;
20593 + uint origidx, idx;
20594 + uint intr_val = 0;
20595 + uint32 tmp, ret = 0xffffffff;
20596 + sbconfig_t *sb;
20597 +
20598 + si = SB_INFO(sbh);
20599 +
20600 + if ((to & ~TO_MASK) != 0)
20601 + return ret;
20602 +
20603 + /* Figure out the master core */
20604 + idx = BADIDX;
20605 + switch (BUSTYPE(si->sb.bustype)) {
20606 + case PCI_BUS:
20607 + idx = si->sb.buscoreidx;
20608 + break;
20609 + case JTAG_BUS:
20610 + idx = SB_CC_IDX;
20611 + break;
20612 + case PCMCIA_BUS:
20613 + case SDIO_BUS:
20614 + idx = sb_findcoreidx(si, SB_PCMCIA, 0);
20615 + break;
20616 + case SB_BUS:
20617 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
20618 + idx = sb_findcoreidx(si, SB_MIPS, 0);
20619 + break;
20620 + default:
20621 + ASSERT(0);
20622 + }
20623 + if (idx == BADIDX)
20624 + return ret;
20625 +
20626 + INTR_OFF(si, intr_val);
20627 + origidx = sb_coreidx(sbh);
20628 +
20629 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
20630 +
20631 + tmp = R_SBREG(si, &sb->sbimconfiglow);
20632 + ret = tmp & TO_MASK;
20633 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
20634 +
20635 + sb_commit(sbh);
20636 + sb_setcoreidx(sbh, origidx);
20637 + INTR_RESTORE(si, intr_val);
20638 + return ret;
20639 +}
20640 +
20641 +void
20642 +sb_core_disable(sb_t *sbh, uint32 bits)
20643 +{
20644 + sb_info_t *si;
20645 + volatile uint32 dummy;
20646 + uint32 rej;
20647 + sbconfig_t *sb;
20648 +
20649 + si = SB_INFO(sbh);
20650 +
20651 + ASSERT(GOODREGS(si->curmap));
20652 + sb = REGS2SB(si->curmap);
20653 +
20654 + /* if core is already in reset, just return */
20655 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
20656 + return;
20657 +
20658 + /* reject value changed between sonics 2.2 and 2.3 */
20659 + if (si->sb.sonicsrev == SONICS_2_2)
20660 + rej = (1 << SBTML_REJ_SHIFT);
20661 + else
20662 + rej = (2 << SBTML_REJ_SHIFT);
20663 +
20664 + /* if clocks are not enabled, put into reset and return */
20665 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
20666 + goto disable;
20667 +
20668 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
20669 + OR_SBREG(si, &sb->sbtmstatelow, rej);
20670 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20671 + OSL_DELAY(1);
20672 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
20673 +
20674 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
20675 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
20676 + dummy = R_SBREG(si, &sb->sbimstate);
20677 + OSL_DELAY(1);
20678 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
20679 + }
20680 +
20681 + /* set reset and reject while enabling the clocks */
20682 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
20683 + dummy = R_SBREG(si, &sb->sbtmstatelow);
20684 + OSL_DELAY(10);
20685 +
20686 + /* don't forget to clear the initiator reject bit */
20687 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
20688 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
20689 +
20690 +disable:
20691 + /* leave reset and reject asserted */
20692 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
20693 + OSL_DELAY(1);
20694 +}
20695 +
20696 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
20697 +void
20698 +sb_watchdog(sb_t *sbh, uint ticks)
20699 +{
20700 + sb_info_t *si = SB_INFO(sbh);
20701 +
20702 + /* instant NMI */
20703 + switch (si->gpioid) {
20704 + case SB_CC:
20705 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
20706 + break;
20707 + case SB_EXTIF:
20708 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
20709 + break;
20710 + }
20711 +}
20712 +
20713 +/* initialize the pcmcia core */
20714 +void
20715 +sb_pcmcia_init(sb_t *sbh)
20716 +{
20717 + sb_info_t *si;
20718 + uint8 cor;
20719 +
20720 + si = SB_INFO(sbh);
20721 +
20722 + /* enable d11 mac interrupts */
20723 + if (si->sb.chip == BCM4301_DEVICE_ID) {
20724 + /* Have to use FCR2 in 4301 */
20725 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20726 + cor |= COR_IRQEN | COR_FUNEN;
20727 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR2 + PCMCIA_COR, &cor, 1);
20728 + } else {
20729 + OSL_PCMCIA_READ_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20730 + cor |= COR_IRQEN | COR_FUNEN;
20731 + OSL_PCMCIA_WRITE_ATTR(si->osh, PCMCIA_FCR0 + PCMCIA_COR, &cor, 1);
20732 + }
20733 +
20734 +}
20735 +
20736 +
20737 +/*
20738 + * Configure the pci core for pci client (NIC) action
20739 + * coremask is the bitvec of cores by index to be enabled.
20740 + */
20741 +void
20742 +sb_pci_setup(sb_t *sbh, uint coremask)
20743 +{
20744 + sb_info_t *si;
20745 + sbconfig_t *sb;
20746 + sbpciregs_t *pciregs;
20747 + uint32 sbflag;
20748 + uint32 w;
20749 + uint idx;
20750 + int reg_val;
20751 +
20752 + si = SB_INFO(sbh);
20753 +
20754 + /* if not pci bus, we're done */
20755 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
20756 + return;
20757 +
20758 + ASSERT(PCI(si) || PCIE(si));
20759 + ASSERT(si->sb.buscoreidx != BADIDX);
20760 +
20761 + /* get current core index */
20762 + idx = si->curidx;
20763 +
20764 + /* we interrupt on this backplane flag number */
20765 + ASSERT(GOODREGS(si->curmap));
20766 + sb = REGS2SB(si->curmap);
20767 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
20768 +
20769 + /* switch over to pci core */
20770 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
20771 + sb = REGS2SB(pciregs);
20772 +
20773 + /*
20774 + * Enable sb->pci interrupts. Assume
20775 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
20776 + */
20777 + if (PCIE(si) || (PCI(si) && ((si->sb.buscorerev) >= 6))) {
20778 + /* pci config write to set this core bit in PCIIntMask */
20779 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
20780 + w |= (coremask << PCI_SBIM_SHIFT);
20781 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
20782 + } else {
20783 + /* set sbintvec bit for our flag number */
20784 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
20785 + }
20786 +
20787 + if (PCI(si)) {
20788 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
20789 + if (si->sb.buscorerev >= 11)
20790 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
20791 + if (si->sb.buscorerev < 5) {
20792 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
20793 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
20794 + sb_commit(sbh);
20795 + }
20796 + }
20797 +
20798 + if (PCIE(si) && (si->sb.buscorerev == 0)) {
20799 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG);
20800 + reg_val |= 0x8;
20801 + sb_pcie_writereg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_TLP_WORKAROUNDSREG, reg_val);
20802 +
20803 + reg_val = sb_pcie_readreg((void *)sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG);
20804 + reg_val &= ~(0x40);
20805 + sb_pcie_writereg(sbh, (void *)PCIE_PCIEREGS, PCIE_DLLP_LCREG, reg_val);
20806 +
20807 + BCMINIT(sb_war30841)(si);
20808 + }
20809 +
20810 + /* switch back to previous core */
20811 + sb_setcoreidx(sbh, idx);
20812 +}
20813 +
20814 +uint32
20815 +sb_base(uint32 admatch)
20816 +{
20817 + uint32 base;
20818 + uint type;
20819 +
20820 + type = admatch & SBAM_TYPE_MASK;
20821 + ASSERT(type < 3);
20822 +
20823 + base = 0;
20824 +
20825 + if (type == 0) {
20826 + base = admatch & SBAM_BASE0_MASK;
20827 + } else if (type == 1) {
20828 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20829 + base = admatch & SBAM_BASE1_MASK;
20830 + } else if (type == 2) {
20831 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20832 + base = admatch & SBAM_BASE2_MASK;
20833 + }
20834 +
20835 + return (base);
20836 +}
20837 +
20838 +uint32
20839 +sb_size(uint32 admatch)
20840 +{
20841 + uint32 size;
20842 + uint type;
20843 +
20844 + type = admatch & SBAM_TYPE_MASK;
20845 + ASSERT(type < 3);
20846 +
20847 + size = 0;
20848 +
20849 + if (type == 0) {
20850 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
20851 + } else if (type == 1) {
20852 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20853 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
20854 + } else if (type == 2) {
20855 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
20856 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
20857 + }
20858 +
20859 + return (size);
20860 +}
20861 +
20862 +/* return the core-type instantiation # of the current core */
20863 +uint
20864 +sb_coreunit(sb_t *sbh)
20865 +{
20866 + sb_info_t *si;
20867 + uint idx;
20868 + uint coreid;
20869 + uint coreunit;
20870 + uint i;
20871 +
20872 + si = SB_INFO(sbh);
20873 + coreunit = 0;
20874 +
20875 + idx = si->curidx;
20876 +
20877 + ASSERT(GOODREGS(si->curmap));
20878 + coreid = sb_coreid(sbh);
20879 +
20880 + /* count the cores of our type */
20881 + for (i = 0; i < idx; i++)
20882 + if (si->coreid[i] == coreid)
20883 + coreunit++;
20884 +
20885 + return (coreunit);
20886 +}
20887 +
20888 +static INLINE uint32
20889 +factor6(uint32 x)
20890 +{
20891 + switch (x) {
20892 + case CC_F6_2: return 2;
20893 + case CC_F6_3: return 3;
20894 + case CC_F6_4: return 4;
20895 + case CC_F6_5: return 5;
20896 + case CC_F6_6: return 6;
20897 + case CC_F6_7: return 7;
20898 + default: return 0;
20899 + }
20900 +}
20901 +
20902 +/* calculate the speed the SB would run at given a set of clockcontrol values */
20903 +uint32
20904 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
20905 +{
20906 + uint32 n1, n2, clock, m1, m2, m3, mc;
20907 +
20908 + n1 = n & CN_N1_MASK;
20909 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
20910 +
20911 + if (pll_type == PLL_TYPE6) {
20912 + if (m & CC_T6_MMASK)
20913 + return CC_T6_M1;
20914 + else
20915 + return CC_T6_M0;
20916 + } else if ((pll_type == PLL_TYPE1) ||
20917 + (pll_type == PLL_TYPE3) ||
20918 + (pll_type == PLL_TYPE4) ||
20919 + (pll_type == PLL_TYPE7)) {
20920 + n1 = factor6(n1);
20921 + n2 += CC_F5_BIAS;
20922 + } else if (pll_type == PLL_TYPE2) {
20923 + n1 += CC_T2_BIAS;
20924 + n2 += CC_T2_BIAS;
20925 + ASSERT((n1 >= 2) && (n1 <= 7));
20926 + ASSERT((n2 >= 5) && (n2 <= 23));
20927 + } else if (pll_type == PLL_TYPE5) {
20928 + return (100000000);
20929 + } else
20930 + ASSERT(0);
20931 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
20932 + if ((pll_type == PLL_TYPE3) ||
20933 + (pll_type == PLL_TYPE7)) {
20934 + clock = CC_CLOCK_BASE2 * n1 * n2;
20935 + }
20936 + else
20937 + clock = CC_CLOCK_BASE1 * n1 * n2;
20938 +
20939 + if (clock == 0)
20940 + return 0;
20941 +
20942 + m1 = m & CC_M1_MASK;
20943 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
20944 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
20945 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
20946 +
20947 + if ((pll_type == PLL_TYPE1) ||
20948 + (pll_type == PLL_TYPE3) ||
20949 + (pll_type == PLL_TYPE4) ||
20950 + (pll_type == PLL_TYPE7)) {
20951 + m1 = factor6(m1);
20952 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
20953 + m2 += CC_F5_BIAS;
20954 + else
20955 + m2 = factor6(m2);
20956 + m3 = factor6(m3);
20957 +
20958 + switch (mc) {
20959 + case CC_MC_BYPASS: return (clock);
20960 + case CC_MC_M1: return (clock / m1);
20961 + case CC_MC_M1M2: return (clock / (m1 * m2));
20962 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
20963 + case CC_MC_M1M3: return (clock / (m1 * m3));
20964 + default: return (0);
20965 + }
20966 + } else {
20967 + ASSERT(pll_type == PLL_TYPE2);
20968 +
20969 + m1 += CC_T2_BIAS;
20970 + m2 += CC_T2M2_BIAS;
20971 + m3 += CC_T2_BIAS;
20972 + ASSERT((m1 >= 2) && (m1 <= 7));
20973 + ASSERT((m2 >= 3) && (m2 <= 10));
20974 + ASSERT((m3 >= 2) && (m3 <= 7));
20975 +
20976 + if ((mc & CC_T2MC_M1BYP) == 0)
20977 + clock /= m1;
20978 + if ((mc & CC_T2MC_M2BYP) == 0)
20979 + clock /= m2;
20980 + if ((mc & CC_T2MC_M3BYP) == 0)
20981 + clock /= m3;
20982 +
20983 + return(clock);
20984 + }
20985 +}
20986 +
20987 +/* returns the current speed the SB is running at */
20988 +uint32
20989 +sb_clock(sb_t *sbh)
20990 +{
20991 + sb_info_t *si;
20992 + extifregs_t *eir;
20993 + chipcregs_t *cc;
20994 + uint32 n, m;
20995 + uint idx;
20996 + uint32 pll_type, rate;
20997 + uint intr_val = 0;
20998 +
20999 + si = SB_INFO(sbh);
21000 + idx = si->curidx;
21001 + pll_type = PLL_TYPE1;
21002 +
21003 + INTR_OFF(si, intr_val);
21004 +
21005 + /* switch to extif or chipc core */
21006 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
21007 + n = R_REG(&eir->clockcontrol_n);
21008 + m = R_REG(&eir->clockcontrol_sb);
21009 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
21010 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
21011 + n = R_REG(&cc->clockcontrol_n);
21012 + if (pll_type == PLL_TYPE6)
21013 + m = R_REG(&cc->clockcontrol_mips);
21014 + else if (pll_type == PLL_TYPE3)
21015 + {
21016 + // Added by Chen-I for 5365
21017 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
21018 + m = R_REG(&cc->clockcontrol_sb);
21019 + else
21020 + m = R_REG(&cc->clockcontrol_m2);
21021 + }
21022 + else
21023 + m = R_REG(&cc->clockcontrol_sb);
21024 + } else {
21025 + INTR_RESTORE(si, intr_val);
21026 + return 0;
21027 + }
21028 +
21029 + // Added by Chen-I for 5365
21030 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
21031 + {
21032 + rate = 100000000;
21033 + }
21034 + else
21035 + {
21036 + /* calculate rate */
21037 + rate = sb_clock_rate(pll_type, n, m);
21038 + if (pll_type == PLL_TYPE3)
21039 + rate = rate / 2;
21040 + }
21041 +
21042 + /* switch back to previous core */
21043 + sb_setcoreidx(sbh, idx);
21044 +
21045 + INTR_RESTORE(si, intr_val);
21046 +
21047 + return rate;
21048 +}
21049 +
21050 +/* change logical "focus" to the gpio core for optimized access */
21051 +void*
21052 +sb_gpiosetcore(sb_t *sbh)
21053 +{
21054 + sb_info_t *si;
21055 +
21056 + si = SB_INFO(sbh);
21057 +
21058 + return (sb_setcoreidx(sbh, si->gpioidx));
21059 +}
21060 +
21061 +/* mask&set gpiocontrol bits */
21062 +uint32
21063 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21064 +{
21065 + sb_info_t *si;
21066 + uint regoff;
21067 +
21068 + si = SB_INFO(sbh);
21069 + regoff = 0;
21070 +
21071 + /* gpios could be shared on router platforms */
21072 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21073 + mask = priority ? (sb_gpioreservation & mask) :
21074 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21075 + val &= mask;
21076 + }
21077 +
21078 + switch (si->gpioid) {
21079 + case SB_CC:
21080 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
21081 + break;
21082 +
21083 + case SB_PCI:
21084 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
21085 + break;
21086 +
21087 + case SB_EXTIF:
21088 + return (0);
21089 + }
21090 +
21091 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21092 +}
21093 +
21094 +/* mask&set gpio output enable bits */
21095 +uint32
21096 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21097 +{
21098 + sb_info_t *si;
21099 + uint regoff;
21100 +
21101 + si = SB_INFO(sbh);
21102 + regoff = 0;
21103 +
21104 + /* gpios could be shared on router platforms */
21105 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21106 + mask = priority ? (sb_gpioreservation & mask) :
21107 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21108 + val &= mask;
21109 + }
21110 +
21111 + switch (si->gpioid) {
21112 + case SB_CC:
21113 + regoff = OFFSETOF(chipcregs_t, gpioouten);
21114 + break;
21115 +
21116 + case SB_PCI:
21117 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
21118 + break;
21119 +
21120 + case SB_EXTIF:
21121 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
21122 + break;
21123 + }
21124 +
21125 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21126 +}
21127 +
21128 +/* mask&set gpio output bits */
21129 +uint32
21130 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21131 +{
21132 + sb_info_t *si;
21133 + uint regoff;
21134 +
21135 + si = SB_INFO(sbh);
21136 + regoff = 0;
21137 +
21138 + /* gpios could be shared on router platforms */
21139 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21140 + mask = priority ? (sb_gpioreservation & mask) :
21141 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21142 + val &= mask;
21143 + }
21144 +
21145 + switch (si->gpioid) {
21146 + case SB_CC:
21147 + regoff = OFFSETOF(chipcregs_t, gpioout);
21148 + break;
21149 +
21150 + case SB_PCI:
21151 + regoff = OFFSETOF(sbpciregs_t, gpioout);
21152 + break;
21153 +
21154 + case SB_EXTIF:
21155 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
21156 + break;
21157 + }
21158 +
21159 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21160 +}
21161 +
21162 +/* reserve one gpio */
21163 +uint32
21164 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
21165 +{
21166 + sb_info_t *si;
21167 +
21168 + si = SB_INFO(sbh);
21169 +
21170 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
21171 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
21172 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
21173 + return -1;
21174 + }
21175 + /* make sure only one bit is set */
21176 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
21177 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
21178 + return -1;
21179 + }
21180 +
21181 + /* already reserved */
21182 + if (sb_gpioreservation & gpio_bitmask)
21183 + return -1;
21184 + /* set reservation */
21185 + sb_gpioreservation |= gpio_bitmask;
21186 +
21187 + return sb_gpioreservation;
21188 +}
21189 +
21190 +/* release one gpio */
21191 +/*
21192 + * releasing the gpio doesn't change the current value on the GPIO last write value
21193 + * persists till some one overwrites it
21194 +*/
21195 +
21196 +uint32
21197 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
21198 +{
21199 + sb_info_t *si;
21200 +
21201 + si = SB_INFO(sbh);
21202 +
21203 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
21204 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
21205 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
21206 + return -1;
21207 + }
21208 + /* make sure only one bit is set */
21209 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
21210 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
21211 + return -1;
21212 + }
21213 +
21214 + /* already released */
21215 + if (!(sb_gpioreservation & gpio_bitmask))
21216 + return -1;
21217 +
21218 + /* clear reservation */
21219 + sb_gpioreservation &= ~gpio_bitmask;
21220 +
21221 + return sb_gpioreservation;
21222 +}
21223 +
21224 +/* return the current gpioin register value */
21225 +uint32
21226 +sb_gpioin(sb_t *sbh)
21227 +{
21228 + sb_info_t *si;
21229 + uint regoff;
21230 +
21231 + si = SB_INFO(sbh);
21232 + regoff = 0;
21233 +
21234 + switch (si->gpioid) {
21235 + case SB_CC:
21236 + regoff = OFFSETOF(chipcregs_t, gpioin);
21237 + break;
21238 +
21239 + case SB_PCI:
21240 + regoff = OFFSETOF(sbpciregs_t, gpioin);
21241 + break;
21242 +
21243 + case SB_EXTIF:
21244 + regoff = OFFSETOF(extifregs_t, gpioin);
21245 + break;
21246 + }
21247 +
21248 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
21249 +}
21250 +
21251 +/* mask&set gpio interrupt polarity bits */
21252 +uint32
21253 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21254 +{
21255 + sb_info_t *si;
21256 + uint regoff;
21257 +
21258 + si = SB_INFO(sbh);
21259 + regoff = 0;
21260 +
21261 + /* gpios could be shared on router platforms */
21262 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21263 + mask = priority ? (sb_gpioreservation & mask) :
21264 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21265 + val &= mask;
21266 + }
21267 +
21268 + switch (si->gpioid) {
21269 + case SB_CC:
21270 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
21271 + break;
21272 +
21273 + case SB_PCI:
21274 + /* pci gpio implementation does not support interrupt polarity */
21275 + ASSERT(0);
21276 + break;
21277 +
21278 + case SB_EXTIF:
21279 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
21280 + break;
21281 + }
21282 +
21283 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21284 +}
21285 +
21286 +/* mask&set gpio interrupt mask bits */
21287 +uint32
21288 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
21289 +{
21290 + sb_info_t *si;
21291 + uint regoff;
21292 +
21293 + si = SB_INFO(sbh);
21294 + regoff = 0;
21295 +
21296 + /* gpios could be shared on router platforms */
21297 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
21298 + mask = priority ? (sb_gpioreservation & mask) :
21299 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
21300 + val &= mask;
21301 + }
21302 +
21303 + switch (si->gpioid) {
21304 + case SB_CC:
21305 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
21306 + break;
21307 +
21308 + case SB_PCI:
21309 + /* pci gpio implementation does not support interrupt mask */
21310 + ASSERT(0);
21311 + break;
21312 +
21313 + case SB_EXTIF:
21314 + regoff = OFFSETOF(extifregs_t, gpiointmask);
21315 + break;
21316 + }
21317 +
21318 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
21319 +}
21320 +
21321 +/* assign the gpio to an led */
21322 +uint32
21323 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
21324 +{
21325 + sb_info_t *si;
21326 +
21327 + si = SB_INFO(sbh);
21328 + if (si->sb.ccrev < 16)
21329 + return -1;
21330 +
21331 + /* gpio led powersave reg */
21332 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
21333 +}
21334 +
21335 +/* mask&set gpio timer val */
21336 +uint32
21337 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
21338 +{
21339 + sb_info_t *si;
21340 + si = SB_INFO(sbh);
21341 +
21342 + if (si->sb.ccrev < 16)
21343 + return -1;
21344 +
21345 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
21346 +}
21347 +
21348 +
21349 +/* return the slow clock source - LPO, XTAL, or PCI */
21350 +static uint
21351 +sb_slowclk_src(sb_info_t *si)
21352 +{
21353 + chipcregs_t *cc;
21354 +
21355 +
21356 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21357 +
21358 + if (si->sb.ccrev < 6) {
21359 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
21360 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
21361 + return (SCC_SS_PCI);
21362 + else
21363 + return (SCC_SS_XTAL);
21364 + } else if (si->sb.ccrev < 10) {
21365 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21366 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
21367 + } else /* Insta-clock */
21368 + return (SCC_SS_XTAL);
21369 +}
21370 +
21371 +/* return the ILP (slowclock) min or max frequency */
21372 +static uint
21373 +sb_slowclk_freq(sb_info_t *si, bool max)
21374 +{
21375 + chipcregs_t *cc;
21376 + uint32 slowclk;
21377 + uint div;
21378 +
21379 +
21380 + ASSERT(sb_coreid(&si->sb) == SB_CC);
21381 +
21382 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
21383 +
21384 + /* shouldn't be here unless we've established the chip has dynamic clk control */
21385 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
21386 +
21387 + slowclk = sb_slowclk_src(si);
21388 + if (si->sb.ccrev < 6) {
21389 + if (slowclk == SCC_SS_PCI)
21390 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
21391 + else
21392 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
21393 + } else if (si->sb.ccrev < 10) {
21394 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21395 + if (slowclk == SCC_SS_LPO)
21396 + return (max? LPOMAXFREQ : LPOMINFREQ);
21397 + else if (slowclk == SCC_SS_XTAL)
21398 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
21399 + else if (slowclk == SCC_SS_PCI)
21400 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
21401 + else
21402 + ASSERT(0);
21403 + } else {
21404 + /* Chipc rev 10 is InstaClock */
21405 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
21406 + div = 4 * (div + 1);
21407 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
21408 + }
21409 + return (0);
21410 +}
21411 +
21412 +static void
21413 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
21414 +{
21415 + chipcregs_t * cc;
21416 + uint slowmaxfreq, pll_delay, slowclk;
21417 + uint pll_on_delay, fref_sel_delay;
21418 +
21419 + pll_delay = PLL_DELAY;
21420 +
21421 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
21422 + * since the xtal will also be powered down by dynamic clk control logic.
21423 + */
21424 + slowclk = sb_slowclk_src(si);
21425 + if (slowclk != SCC_SS_XTAL)
21426 + pll_delay += XTAL_ON_DELAY;
21427 +
21428 + /* Starting with 4318 it is ILP that is used for the delays */
21429 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
21430 +
21431 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
21432 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
21433 +
21434 + cc = (chipcregs_t *)chipcregs;
21435 + W_REG(&cc->pll_on_delay, pll_on_delay);
21436 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
21437 +}
21438 +
21439 +int
21440 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
21441 +{
21442 + sb_info_t *si;
21443 + uint origidx;
21444 + chipcregs_t *cc;
21445 + uint intr_val = 0;
21446 + uint err = 0;
21447 +
21448 + si = SB_INFO(sbh);
21449 +
21450 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
21451 + if (si->sb.ccrev < 6)
21452 + return 1;
21453 +
21454 + /* chipcommon cores rev10 are a whole new ball game */
21455 + if (si->sb.ccrev >= 10)
21456 + return 1;
21457 +
21458 + if (set && ((*div % 4) || (*div < 4)))
21459 + return 2;
21460 +
21461 + INTR_OFF(si, intr_val);
21462 + origidx = si->curidx;
21463 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21464 + ASSERT(cc != NULL);
21465 +
21466 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
21467 + err = 3;
21468 + goto done;
21469 + }
21470 +
21471 + if (set) {
21472 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
21473 + sb_clkctl_setdelay(sbh, (void *)cc);
21474 + } else
21475 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
21476 +
21477 +done:
21478 + sb_setcoreidx(sbh, origidx);
21479 + INTR_RESTORE(si, intr_val);
21480 + return err;
21481 +}
21482 +
21483 +/* initialize power control delay registers */
21484 +void sb_clkctl_init(sb_t *sbh)
21485 +{
21486 + sb_info_t *si;
21487 + uint origidx;
21488 + chipcregs_t *cc;
21489 +
21490 + si = SB_INFO(sbh);
21491 +
21492 + origidx = si->curidx;
21493 +
21494 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21495 + return;
21496 +
21497 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21498 + goto done;
21499 +
21500 + /* 4317pc does not work with SlowClock less than 5 MHz */
21501 + if ((BUSTYPE(si->sb.bustype) == PCMCIA_BUS) && (si->sb.ccrev >= 6) && (si->sb.ccrev < 10))
21502 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, (ILP_DIV_5MHZ << SCC_CD_SHIFT));
21503 +
21504 + /* set all Instaclk chip ILP to 1 MHz */
21505 + else if (si->sb.ccrev >= 10)
21506 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
21507 +
21508 + sb_clkctl_setdelay(si, (void *)cc);
21509 +
21510 +done:
21511 + sb_setcoreidx(sbh, origidx);
21512 +}
21513 +void sb_pwrctl_init(sb_t *sbh)
21514 +{
21515 +sb_clkctl_init(sbh);
21516 +}
21517 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
21518 +uint16
21519 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
21520 +{
21521 + sb_info_t *si;
21522 + uint origidx;
21523 + chipcregs_t *cc;
21524 + uint slowminfreq;
21525 + uint16 fpdelay;
21526 + uint intr_val = 0;
21527 +
21528 + si = SB_INFO(sbh);
21529 + fpdelay = 0;
21530 + origidx = si->curidx;
21531 +
21532 + INTR_OFF(si, intr_val);
21533 +
21534 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
21535 + goto done;
21536 +
21537 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21538 + goto done;
21539 +
21540 + slowminfreq = sb_slowclk_freq(si, FALSE);
21541 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
21542 +
21543 +done:
21544 + sb_setcoreidx(sbh, origidx);
21545 + INTR_RESTORE(si, intr_val);
21546 + return (fpdelay);
21547 +}
21548 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
21549 +{
21550 +return sb_clkctl_fast_pwrup_delay(sbh);
21551 +}
21552 +/* turn primary xtal and/or pll off/on */
21553 +int
21554 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
21555 +{
21556 + sb_info_t *si;
21557 + uint32 in, out, outen;
21558 +
21559 + si = SB_INFO(sbh);
21560 +
21561 + switch (BUSTYPE(si->sb.bustype)) {
21562 +
21563 +
21564 + case PCMCIA_BUS:
21565 + return (0);
21566 +
21567 +
21568 + case PCI_BUS:
21569 +
21570 + /* pcie core doesn't have any mapping to control the xtal pu */
21571 + if (PCIE(si))
21572 + return -1;
21573 +
21574 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
21575 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
21576 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
21577 +
21578 + /*
21579 + * Avoid glitching the clock if GPRS is already using it.
21580 + * We can't actually read the state of the PLLPD so we infer it
21581 + * by the value of XTAL_PU which *is* readable via gpioin.
21582 + */
21583 + if (on && (in & PCI_CFG_GPIO_XTAL))
21584 + return (0);
21585 +
21586 + if (what & XTAL)
21587 + outen |= PCI_CFG_GPIO_XTAL;
21588 + if (what & PLL)
21589 + outen |= PCI_CFG_GPIO_PLL;
21590 +
21591 + if (on) {
21592 + /* turn primary xtal on */
21593 + if (what & XTAL) {
21594 + out |= PCI_CFG_GPIO_XTAL;
21595 + if (what & PLL)
21596 + out |= PCI_CFG_GPIO_PLL;
21597 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21598 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21599 + OSL_DELAY(XTAL_ON_DELAY);
21600 + }
21601 +
21602 + /* turn pll on */
21603 + if (what & PLL) {
21604 + out &= ~PCI_CFG_GPIO_PLL;
21605 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21606 + OSL_DELAY(2000);
21607 + }
21608 + } else {
21609 + if (what & XTAL)
21610 + out &= ~PCI_CFG_GPIO_XTAL;
21611 + if (what & PLL)
21612 + out |= PCI_CFG_GPIO_PLL;
21613 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
21614 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
21615 + }
21616 +
21617 + default:
21618 + return (-1);
21619 + }
21620 +
21621 + return (0);
21622 +}
21623 +
21624 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
21625 +{
21626 +return sb_clkctl_xtal(sbh,what,on);
21627 +}
21628 +
21629 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
21630 +/* returns true if ignore pll off is set and false if it is not */
21631 +bool
21632 +sb_clkctl_clk(sb_t *sbh, uint mode)
21633 +{
21634 + sb_info_t *si;
21635 + uint origidx;
21636 + chipcregs_t *cc;
21637 + uint32 scc;
21638 + bool forcefastclk=FALSE;
21639 + uint intr_val = 0;
21640 +
21641 + si = SB_INFO(sbh);
21642 +
21643 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
21644 + if (si->sb.ccrev < 6)
21645 + return (FALSE);
21646 +
21647 + /* chipcommon cores rev10 are a whole new ball game */
21648 + if (si->sb.ccrev >= 10)
21649 + return (FALSE);
21650 +
21651 + INTR_OFF(si, intr_val);
21652 +
21653 + origidx = si->curidx;
21654 +
21655 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
21656 + ASSERT(cc != NULL);
21657 +
21658 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
21659 + goto done;
21660 +
21661 + switch (mode) {
21662 + case CLK_FAST: /* force fast (pll) clock */
21663 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
21664 + sb_clkctl_xtal(&si->sb, XTAL, ON);
21665 +
21666 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
21667 + break;
21668 +
21669 + case CLK_DYNAMIC: /* enable dynamic clock control */
21670 + scc = R_REG(&cc->slow_clk_ctl);
21671 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
21672 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
21673 + scc |= SCC_XC;
21674 + W_REG(&cc->slow_clk_ctl, scc);
21675 +
21676 + /* for dynamic control, we have to release our xtal_pu "force on" */
21677 + if (scc & SCC_XC)
21678 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
21679 + break;
21680 +
21681 + default:
21682 + ASSERT(0);
21683 + }
21684 +
21685 + /* Is the h/w forcing the use of the fast clk */
21686 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
21687 +
21688 +done:
21689 + sb_setcoreidx(sbh, origidx);
21690 + INTR_RESTORE(si, intr_val);
21691 + return (forcefastclk);
21692 +}
21693 +
21694 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
21695 +{
21696 +return sb_clkctl_clk(sbh, mode);
21697 +}
21698 +/* register driver interrupt disabling and restoring callback functions */
21699 +void
21700 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
21701 +{
21702 + sb_info_t *si;
21703 +
21704 + si = SB_INFO(sbh);
21705 + si->intr_arg = intr_arg;
21706 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
21707 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
21708 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
21709 + /* save current core id. when this function called, the current core
21710 + * must be the core which provides driver functions(il, et, wl, etc.)
21711 + */
21712 + si->dev_coreid = si->coreid[si->curidx];
21713 +}
21714 +
21715 +
21716 +void
21717 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
21718 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
21719 +{
21720 + uint vendor, core, unit;
21721 + uint chip, chippkg;
21722 + char varname[8];
21723 + uint8 class, subclass, progif;
21724 +
21725 + vendor = sb_corevendor(sbh);
21726 + core = sb_coreid(sbh);
21727 + unit = sb_coreunit(sbh);
21728 +
21729 + chip = BCMINIT(sb_chip)(sbh);
21730 + chippkg = BCMINIT(sb_chippkg)(sbh);
21731 +
21732 + progif = 0;
21733 +
21734 + /* Known vendor translations */
21735 + switch (vendor) {
21736 + case SB_VEND_BCM:
21737 + vendor = VENDOR_BROADCOM;
21738 + break;
21739 + }
21740 +
21741 + /* Determine class based on known core codes */
21742 + switch (core) {
21743 + case SB_ILINE20:
21744 + class = PCI_CLASS_NET;
21745 + subclass = PCI_NET_ETHER;
21746 + core = BCM47XX_ILINE_ID;
21747 + break;
21748 + case SB_ENET:
21749 + class = PCI_CLASS_NET;
21750 + subclass = PCI_NET_ETHER;
21751 + core = BCM47XX_ENET_ID;
21752 + break;
21753 + case SB_SDRAM:
21754 + case SB_MEMC:
21755 + class = PCI_CLASS_MEMORY;
21756 + subclass = PCI_MEMORY_RAM;
21757 + break;
21758 + case SB_PCI:
21759 + case SB_PCIE:
21760 + class = PCI_CLASS_BRIDGE;
21761 + subclass = PCI_BRIDGE_PCI;
21762 + break;
21763 + case SB_MIPS:
21764 + case SB_MIPS33:
21765 + class = PCI_CLASS_CPU;
21766 + subclass = PCI_CPU_MIPS;
21767 + break;
21768 + case SB_CODEC:
21769 + class = PCI_CLASS_COMM;
21770 + subclass = PCI_COMM_MODEM;
21771 + core = BCM47XX_V90_ID;
21772 + break;
21773 + case SB_USB:
21774 + class = PCI_CLASS_SERIAL;
21775 + subclass = PCI_SERIAL_USB;
21776 + progif = 0x10; /* OHCI */
21777 + core = BCM47XX_USB_ID;
21778 + break;
21779 + case SB_USB11H:
21780 + class = PCI_CLASS_SERIAL;
21781 + subclass = PCI_SERIAL_USB;
21782 + progif = 0x10; /* OHCI */
21783 + core = BCM47XX_USBH_ID;
21784 + break;
21785 + case SB_USB11D:
21786 + class = PCI_CLASS_SERIAL;
21787 + subclass = PCI_SERIAL_USB;
21788 + core = BCM47XX_USBD_ID;
21789 + break;
21790 + case SB_IPSEC:
21791 + class = PCI_CLASS_CRYPT;
21792 + subclass = PCI_CRYPT_NETWORK;
21793 + core = BCM47XX_IPSEC_ID;
21794 + break;
21795 + case SB_ROBO:
21796 + class = PCI_CLASS_NET;
21797 + subclass = PCI_NET_OTHER;
21798 + core = BCM47XX_ROBO_ID;
21799 + break;
21800 + case SB_EXTIF:
21801 + case SB_CC:
21802 + class = PCI_CLASS_MEMORY;
21803 + subclass = PCI_MEMORY_FLASH;
21804 + break;
21805 + case SB_D11:
21806 + class = PCI_CLASS_NET;
21807 + subclass = PCI_NET_OTHER;
21808 + /* Let an nvram variable override this */
21809 + sprintf(varname, "wl%did", unit);
21810 + if ((core = getintvar(NULL, varname)) == 0) {
21811 + if (chip == BCM4712_DEVICE_ID) {
21812 + if (chippkg == BCM4712SMALL_PKG_ID)
21813 + core = BCM4306_D11G_ID;
21814 + else
21815 + core = BCM4306_D11DUAL_ID;
21816 + }
21817 + }
21818 + break;
21819 +
21820 + default:
21821 + class = subclass = progif = 0xff;
21822 + break;
21823 + }
21824 +
21825 + *pcivendor = (uint16)vendor;
21826 + *pcidevice = (uint16)core;
21827 + *pciclass = class;
21828 + *pcisubclass = subclass;
21829 + *pciprogif = progif;
21830 +}
21831 +
21832 +
21833 +
21834 +
21835 +/* use the mdio interface to write to mdio slaves */
21836 +static int
21837 +sb_pcie_mdiowrite(sb_info_t *si, uint physmedia, uint regaddr, uint val)
21838 +{
21839 + uint mdiodata;
21840 + uint i = 0;
21841 + sbpcieregs_t *pcieregs;
21842 +
21843 + pcieregs = (sbpcieregs_t*) sb_setcoreidx(&si->sb, si->sb.buscoreidx);
21844 + ASSERT (pcieregs);
21845 +
21846 + /* enable mdio access to SERDES */
21847 + W_REG((&pcieregs->mdiocontrol), MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
21848 +
21849 + mdiodata = MDIODATA_START | MDIODATA_WRITE |
21850 + (physmedia << MDIODATA_DEVADDR_SHF) |
21851 + (regaddr << MDIODATA_REGADDR_SHF) | MDIODATA_TA | val;
21852 +
21853 + W_REG((&pcieregs->mdiodata), mdiodata);
21854 +
21855 + PR28829_DELAY();
21856 +
21857 + /* retry till the transaction is complete */
21858 + while ( i < 10 ) {
21859 + if (R_REG(&(pcieregs->mdiocontrol)) & MDIOCTL_ACCESS_DONE) {
21860 + /* Disable mdio access to SERDES */
21861 + W_REG((&pcieregs->mdiocontrol), 0);
21862 + return 0;
21863 + }
21864 + OSL_DELAY(1000);
21865 + i++;
21866 + }
21867 +
21868 + SB_ERROR(("sb_pcie_mdiowrite: timed out\n"));
21869 + /* Disable mdio access to SERDES */
21870 + W_REG((&pcieregs->mdiocontrol), 0);
21871 + ASSERT(0);
21872 + return 1;
21873 +
21874 +}
21875 +
21876 +/* indirect way to read pcie config regs*/
21877 +uint
21878 +sb_pcie_readreg(void *sb, void* arg1, uint offset)
21879 +{
21880 + sb_info_t *si;
21881 + sb_t *sbh;
21882 + uint retval = 0xFFFFFFFF;
21883 + sbpcieregs_t *pcieregs;
21884 + uint addrtype;
21885 +
21886 + sbh = (sb_t *)sb;
21887 + si = SB_INFO(sbh);
21888 + ASSERT (PCIE(si));
21889 +
21890 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21891 + ASSERT (pcieregs);
21892 +
21893 + addrtype = (uint)((uintptr)arg1);
21894 + switch(addrtype) {
21895 + case PCIE_CONFIGREGS:
21896 + W_REG((&pcieregs->configaddr),offset);
21897 + retval = R_REG(&(pcieregs->configdata));
21898 + break;
21899 + case PCIE_PCIEREGS:
21900 + W_REG(&(pcieregs->pcieaddr),offset);
21901 + retval = R_REG(&(pcieregs->pciedata));
21902 + break;
21903 + default:
21904 + ASSERT(0);
21905 + break;
21906 + }
21907 + return retval;
21908 +}
21909 +
21910 +/* indirect way to write pcie config/mdio/pciecore regs*/
21911 +uint
21912 +sb_pcie_writereg(sb_t *sbh, void *arg1, uint offset, uint val)
21913 +{
21914 + sb_info_t *si;
21915 + sbpcieregs_t *pcieregs;
21916 + uint addrtype;
21917 +
21918 + si = SB_INFO(sbh);
21919 + ASSERT (PCIE(si));
21920 +
21921 + pcieregs = (sbpcieregs_t *)sb_setcore(sbh, SB_PCIE, 0);
21922 + ASSERT (pcieregs);
21923 +
21924 + addrtype = (uint)((uintptr)arg1);
21925 +
21926 + switch(addrtype) {
21927 + case PCIE_CONFIGREGS:
21928 + W_REG((&pcieregs->configaddr),offset);
21929 + W_REG((&pcieregs->configdata),val);
21930 + break;
21931 + case PCIE_PCIEREGS:
21932 + W_REG((&pcieregs->pcieaddr),offset);
21933 + W_REG((&pcieregs->pciedata),val);
21934 + break;
21935 + default:
21936 + ASSERT(0);
21937 + break;
21938 + }
21939 + return 0;
21940 +}
21941 +
21942 +
21943 +/* Build device path. Support SB, PCI, and JTAG for now. */
21944 +int
21945 +sb_devpath(sb_t *sbh, char *path, int size)
21946 +{
21947 + ASSERT(path);
21948 + ASSERT(size >= SB_DEVPATH_BUFSZ);
21949 +
21950 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
21951 + case SB_BUS:
21952 + case JTAG_BUS:
21953 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
21954 + break;
21955 + case PCI_BUS:
21956 + ASSERT((SB_INFO(sbh))->osh);
21957 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
21958 + OSL_PCI_SLOT((SB_INFO(sbh))->osh));
21959 + break;
21960 + case PCMCIA_BUS:
21961 + SB_ERROR(("sb_devpath: OSL_PCMCIA_BUS() not implemented, bus 1 assumed\n"));
21962 + SB_ERROR(("sb_devpath: OSL_PCMCIA_SLOT() not implemented, slot 1 assumed\n"));
21963 + sprintf(path, "pc/%u/%u/", 1, 1);
21964 + break;
21965 + case SDIO_BUS:
21966 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
21967 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
21968 + break;
21969 + default:
21970 + ASSERT(0);
21971 + break;
21972 + }
21973 +
21974 + return 0;
21975 +}
21976 +
21977 +/* Fix chip's configuration. The current core may be changed upon return */
21978 +static int
21979 +sb_pci_fixcfg(sb_info_t *si)
21980 +{
21981 + uint origidx, pciidx;
21982 + sbpciregs_t *pciregs;
21983 + sbpcieregs_t *pcieregs;
21984 + uint16 val16, *reg16;
21985 + char name[SB_DEVPATH_BUFSZ+16], *value;
21986 + char devpath[SB_DEVPATH_BUFSZ];
21987 +
21988 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
21989 +
21990 + /* Fix PCI(e) SROM shadow area */
21991 + /* save the current index */
21992 + origidx = sb_coreidx(&si->sb);
21993 +
21994 + /* check 'pi' is correct and fix it if not */
21995 + if (si->sb.buscoretype == SB_PCIE) {
21996 + pcieregs = (sbpcieregs_t *)sb_setcore(&si->sb, SB_PCIE, 0);
21997 + ASSERT(pcieregs);
21998 + reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
21999 + }
22000 + else if (si->sb.buscoretype == SB_PCI) {
22001 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
22002 + ASSERT(pciregs);
22003 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
22004 + }
22005 + else {
22006 + ASSERT(0);
22007 + return -1;
22008 + }
22009 + pciidx = sb_coreidx(&si->sb);
22010 + val16 = R_REG(reg16);
22011 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
22012 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
22013 + W_REG(reg16, val16);
22014 + }
22015 +
22016 + /* restore the original index */
22017 + sb_setcoreidx(&si->sb, origidx);
22018 +
22019 + /* Fix bar0window */
22020 + /* !do it last, it changes the current core! */
22021 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
22022 + return -1;
22023 + sprintf(name, "%sb0w", devpath);
22024 + if ((value = getvar(NULL, name))) {
22025 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
22026 + bcm_strtoul(value, NULL, 16));
22027 + /* update curidx since the current core is changed */
22028 + si->curidx = _sb_coreidx(si);
22029 + if (si->curidx == BADIDX) {
22030 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
22031 + return -1;
22032 + }
22033 + }
22034 +
22035 + return 0;
22036 +}
22037 +
22038 diff -urN linux.old/drivers/net/hnd/shared_ksyms.sh linux.dev/drivers/net/hnd/shared_ksyms.sh
22039 --- linux.old/drivers/net/hnd/shared_ksyms.sh 1970-01-01 01:00:00.000000000 +0100
22040 +++ linux.dev/drivers/net/hnd/shared_ksyms.sh 2005-11-07 21:57:07.917590250 +0100
22041 @@ -0,0 +1,21 @@
22042 +#!/bin/sh
22043 +#
22044 +# Copyright 2004, Broadcom Corporation
22045 +# All Rights Reserved.
22046 +#
22047 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22048 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22049 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22050 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22051 +#
22052 +# $Id: shared_ksyms.sh,v 1.1 2005/03/16 13:50:00 wbx Exp $
22053 +#
22054 +
22055 +cat <<EOF
22056 +#include <linux/config.h>
22057 +#include <linux/module.h>
22058 +EOF
22059 +
22060 +for file in $* ; do
22061 + ${NM} $file | sed -ne 's/[0-9A-Fa-f]* [DT] \([^ ]*\)/extern void \1; EXPORT_SYMBOL(\1);/p'
22062 +done
22063 diff -urN linux.old/drivers/net/wireless/Config.in linux.dev/drivers/net/wireless/Config.in
22064 --- linux.old/drivers/net/wireless/Config.in 2005-11-07 23:12:51.258929250 +0100
22065 +++ linux.dev/drivers/net/wireless/Config.in 2005-11-07 21:57:07.941591750 +0100
22066 @@ -13,6 +13,7 @@
22067 fi
22068
22069 if [ "$CONFIG_PCI" = "y" ]; then
22070 + dep_tristate ' Proprietary Broadcom BCM43xx 802.11 Wireless support' CONFIG_WL
22071 dep_tristate ' Hermes in PLX9052 based PCI adaptor support (Netgear MA301 etc.) (EXPERIMENTAL)' CONFIG_PLX_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
22072 dep_tristate ' Hermes in TMD7160/NCP130 based PCI adaptor support (Pheecom WL-PCI etc.) (EXPERIMENTAL)' CONFIG_TMD_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
22073 dep_tristate ' Prism 2.5 PCI 802.11b adaptor support (EXPERIMENTAL)' CONFIG_PCI_HERMES $CONFIG_HERMES $CONFIG_EXPERIMENTAL
22074 diff -urN linux.old/drivers/net/wl/Makefile linux.dev/drivers/net/wl/Makefile
22075 --- linux.old/drivers/net/wl/Makefile 1970-01-01 01:00:00.000000000 +0100
22076 +++ linux.dev/drivers/net/wl/Makefile 2005-11-07 21:57:07.941591750 +0100
22077 @@ -0,0 +1,26 @@
22078 +#
22079 +# Makefile for the Broadcom wl driver
22080 +#
22081 +# Copyright 2004, Broadcom Corporation
22082 +# All Rights Reserved.
22083 +#
22084 +# THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22085 +# KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22086 +# SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22087 +# FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22088 +#
22089 +# $Id: Makefile,v 1.2 2005/03/29 03:32:18 mbm Exp $
22090 +
22091 +EXTRA_CFLAGS += -I$(TOPDIR)/arch/mips/bcm947xx/include
22092 +
22093 +O_TARGET := wl.o
22094 +
22095 +obj-y := apsta_aeskeywrap.o apsta_aes.o apsta_bcmwpa.o apsta_d11ucode.o
22096 +obj-y += apsta_hmac.o apsta_md5.o apsta_passhash.o apsta_prf.o apsta_rc4.o
22097 +obj-y += apsta_rijndael-alg-fst.o apsta_sha1.o apsta_tkhash.o apsta_wlc_led.o
22098 +obj-y += apsta_wlc_phy.o apsta_wlc_rate.o apsta_wlc_security.o
22099 +obj-y += apsta_wlc_sup.o apsta_wlc_wet.o apsta_wl_linux.o apsta_wlc.o
22100 +
22101 +obj-m := $(O_TARGET)
22102 +
22103 +include $(TOPDIR)/Rules.make
22104 diff -urN linux.old/drivers/parport/Config.in linux.dev/drivers/parport/Config.in
22105 --- linux.old/drivers/parport/Config.in 2005-11-07 23:12:51.306932250 +0100
22106 +++ linux.dev/drivers/parport/Config.in 2005-11-07 21:57:07.941591750 +0100
22107 @@ -11,6 +11,7 @@
22108 tristate 'Parallel port support' CONFIG_PARPORT
22109 if [ "$CONFIG_PARPORT" != "n" ]; then
22110 dep_tristate ' PC-style hardware' CONFIG_PARPORT_PC $CONFIG_PARPORT
22111 + dep_tristate ' Asus WL500g parallel port' CONFIG_PARPORT_SPLINK $CONFIG_PARPORT
22112 if [ "$CONFIG_PARPORT_PC" != "n" -a "$CONFIG_SERIAL" != "n" ]; then
22113 if [ "$CONFIG_SERIAL" = "m" ]; then
22114 define_tristate CONFIG_PARPORT_PC_CML1 m
22115 diff -urN linux.old/drivers/parport/Makefile linux.dev/drivers/parport/Makefile
22116 --- linux.old/drivers/parport/Makefile 2005-11-07 23:12:51.318933000 +0100
22117 +++ linux.dev/drivers/parport/Makefile 2005-11-07 21:57:07.941591750 +0100
22118 @@ -22,6 +22,7 @@
22119
22120 obj-$(CONFIG_PARPORT) += parport.o
22121 obj-$(CONFIG_PARPORT_PC) += parport_pc.o
22122 +obj-$(CONFIG_PARPORT_SPLINK) += parport_splink.o
22123 obj-$(CONFIG_PARPORT_PC_PCMCIA) += parport_cs.o
22124 obj-$(CONFIG_PARPORT_AMIGA) += parport_amiga.o
22125 obj-$(CONFIG_PARPORT_MFC3) += parport_mfc3.o
22126 diff -urN linux.old/drivers/parport/parport_splink.c linux.dev/drivers/parport/parport_splink.c
22127 --- linux.old/drivers/parport/parport_splink.c 1970-01-01 01:00:00.000000000 +0100
22128 +++ linux.dev/drivers/parport/parport_splink.c 2005-11-07 21:57:07.941591750 +0100
22129 @@ -0,0 +1,345 @@
22130 +/* Low-level parallel port routines for the ASUS WL-500g built-in port
22131 + *
22132 + * Author: Nuno Grilo <nuno.grilo@netcabo.pt>
22133 + * Based on parport_pc source
22134 + */
22135 +
22136 +#include <linux/config.h>
22137 +#include <linux/module.h>
22138 +#include <linux/init.h>
22139 +#include <linux/ioport.h>
22140 +#include <linux/kernel.h>
22141 +#include <linux/slab.h>
22142 +#include <linux/parport.h>
22143 +#include <linux/parport_pc.h>
22144 +
22145 +#define SPLINK_ADDRESS 0xBF800010
22146 +
22147 +#undef DEBUG
22148 +
22149 +#ifdef DEBUG
22150 +#define DPRINTK printk
22151 +#else
22152 +#define DPRINTK(stuff...)
22153 +#endif
22154 +
22155 +
22156 +/* __parport_splink_frob_control differs from parport_splink_frob_control in that
22157 + * it doesn't do any extra masking. */
22158 +static __inline__ unsigned char __parport_splink_frob_control (struct parport *p,
22159 + unsigned char mask,
22160 + unsigned char val)
22161 +{
22162 + struct parport_pc_private *priv = p->physport->private_data;
22163 + unsigned char *io = (unsigned char *) p->base;
22164 + unsigned char ctr = priv->ctr;
22165 +#ifdef DEBUG_PARPORT
22166 + printk (KERN_DEBUG
22167 + "__parport_splink_frob_control(%02x,%02x): %02x -> %02x\n",
22168 + mask, val, ctr, ((ctr & ~mask) ^ val) & priv->ctr_writable);
22169 +#endif
22170 + ctr = (ctr & ~mask) ^ val;
22171 + ctr &= priv->ctr_writable; /* only write writable bits. */
22172 + *(io+2) = ctr;
22173 + priv->ctr = ctr; /* Update soft copy */
22174 + return ctr;
22175 +}
22176 +
22177 +
22178 +
22179 +static void parport_splink_data_forward (struct parport *p)
22180 +{
22181 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
22182 + __parport_splink_frob_control (p, 0x20, 0);
22183 +}
22184 +
22185 +static void parport_splink_data_reverse (struct parport *p)
22186 +{
22187 + DPRINTK(KERN_DEBUG "parport_splink: parport_data_forward called\n");
22188 + __parport_splink_frob_control (p, 0x20, 0x20);
22189 +}
22190 +
22191 +/*
22192 +static void parport_splink_interrupt(int irq, void *dev_id, struct pt_regs *regs)
22193 +{
22194 + DPRINTK(KERN_DEBUG "parport_splink: IRQ handler called\n");
22195 + parport_generic_irq(irq, (struct parport *) dev_id, regs);
22196 +}
22197 +*/
22198 +
22199 +static void parport_splink_enable_irq(struct parport *p)
22200 +{
22201 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_enable_irq called\n");
22202 + __parport_splink_frob_control (p, 0x10, 0x10);
22203 +}
22204 +
22205 +static void parport_splink_disable_irq(struct parport *p)
22206 +{
22207 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_disable_irq called\n");
22208 + __parport_splink_frob_control (p, 0x10, 0);
22209 +}
22210 +
22211 +static void parport_splink_init_state(struct pardevice *dev, struct parport_state *s)
22212 +{
22213 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_init_state called\n");
22214 + s->u.pc.ctr = 0xc | (dev->irq_func ? 0x10 : 0x0);
22215 + if (dev->irq_func &&
22216 + dev->port->irq != PARPORT_IRQ_NONE)
22217 + /* Set ackIntEn */
22218 + s->u.pc.ctr |= 0x10;
22219 +}
22220 +
22221 +static void parport_splink_save_state(struct parport *p, struct parport_state *s)
22222 +{
22223 + const struct parport_pc_private *priv = p->physport->private_data;
22224 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_save_state called\n");
22225 + s->u.pc.ctr = priv->ctr;
22226 +}
22227 +
22228 +static void parport_splink_restore_state(struct parport *p, struct parport_state *s)
22229 +{
22230 + struct parport_pc_private *priv = p->physport->private_data;
22231 + unsigned char *io = (unsigned char *) p->base;
22232 + unsigned char ctr = s->u.pc.ctr;
22233 +
22234 + DPRINTK(KERN_DEBUG "parport_splink: parport_splink_restore_state called\n");
22235 + *(io+2) = ctr;
22236 + priv->ctr = ctr;
22237 +}
22238 +
22239 +static void parport_splink_setup_interrupt(void) {
22240 + return;
22241 +}
22242 +
22243 +static void parport_splink_write_data(struct parport *p, unsigned char d) {
22244 + DPRINTK(KERN_DEBUG "parport_splink: write data called\n");
22245 + unsigned char *io = (unsigned char *) p->base;
22246 + *io = d;
22247 +}
22248 +
22249 +static unsigned char parport_splink_read_data(struct parport *p) {
22250 + DPRINTK(KERN_DEBUG "parport_splink: read data called\n");
22251 + unsigned char *io = (unsigned char *) p->base;
22252 + return *io;
22253 +}
22254 +
22255 +static void parport_splink_write_control(struct parport *p, unsigned char d)
22256 +{
22257 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22258 + PARPORT_CONTROL_AUTOFD |
22259 + PARPORT_CONTROL_INIT |
22260 + PARPORT_CONTROL_SELECT);
22261 +
22262 + DPRINTK(KERN_DEBUG "parport_splink: write control called\n");
22263 + /* Take this out when drivers have adapted to the newer interface. */
22264 + if (d & 0x20) {
22265 + printk (KERN_DEBUG "%s (%s): use data_reverse for this!\n",
22266 + p->name, p->cad->name);
22267 + parport_splink_data_reverse (p);
22268 + }
22269 +
22270 + __parport_splink_frob_control (p, wm, d & wm);
22271 +}
22272 +
22273 +static unsigned char parport_splink_read_control(struct parport *p)
22274 +{
22275 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22276 + PARPORT_CONTROL_AUTOFD |
22277 + PARPORT_CONTROL_INIT |
22278 + PARPORT_CONTROL_SELECT);
22279 + DPRINTK(KERN_DEBUG "parport_splink: read control called\n");
22280 + const struct parport_pc_private *priv = p->physport->private_data;
22281 + return priv->ctr & wm; /* Use soft copy */
22282 +}
22283 +
22284 +static unsigned char parport_splink_frob_control (struct parport *p, unsigned char mask,
22285 + unsigned char val)
22286 +{
22287 + const unsigned char wm = (PARPORT_CONTROL_STROBE |
22288 + PARPORT_CONTROL_AUTOFD |
22289 + PARPORT_CONTROL_INIT |
22290 + PARPORT_CONTROL_SELECT);
22291 +
22292 + DPRINTK(KERN_DEBUG "parport_splink: frob control called\n");
22293 + /* Take this out when drivers have adapted to the newer interface. */
22294 + if (mask & 0x20) {
22295 + printk (KERN_DEBUG "%s (%s): use data_%s for this!\n",
22296 + p->name, p->cad->name,
22297 + (val & 0x20) ? "reverse" : "forward");
22298 + if (val & 0x20)
22299 + parport_splink_data_reverse (p);
22300 + else
22301 + parport_splink_data_forward (p);
22302 + }
22303 +
22304 + /* Restrict mask and val to control lines. */
22305 + mask &= wm;
22306 + val &= wm;
22307 +
22308 + return __parport_splink_frob_control (p, mask, val);
22309 +}
22310 +
22311 +static unsigned char parport_splink_read_status(struct parport *p)
22312 +{
22313 + DPRINTK(KERN_DEBUG "parport_splink: read status called\n");
22314 + unsigned char *io = (unsigned char *) p->base;
22315 + return *(io+1);
22316 +}
22317 +
22318 +static void parport_splink_inc_use_count(void)
22319 +{
22320 +#ifdef MODULE
22321 + MOD_INC_USE_COUNT;
22322 +#endif
22323 +}
22324 +
22325 +static void parport_splink_dec_use_count(void)
22326 +{
22327 +#ifdef MODULE
22328 + MOD_DEC_USE_COUNT;
22329 +#endif
22330 +}
22331 +
22332 +static struct parport_operations parport_splink_ops =
22333 +{
22334 + parport_splink_write_data,
22335 + parport_splink_read_data,
22336 +
22337 + parport_splink_write_control,
22338 + parport_splink_read_control,
22339 + parport_splink_frob_control,
22340 +
22341 + parport_splink_read_status,
22342 +
22343 + parport_splink_enable_irq,
22344 + parport_splink_disable_irq,
22345 +
22346 + parport_splink_data_forward,
22347 + parport_splink_data_reverse,
22348 +
22349 + parport_splink_init_state,
22350 + parport_splink_save_state,
22351 + parport_splink_restore_state,
22352 +
22353 + parport_splink_inc_use_count,
22354 + parport_splink_dec_use_count,
22355 +
22356 + parport_ieee1284_epp_write_data,
22357 + parport_ieee1284_epp_read_data,
22358 + parport_ieee1284_epp_write_addr,
22359 + parport_ieee1284_epp_read_addr,
22360 +
22361 + parport_ieee1284_ecp_write_data,
22362 + parport_ieee1284_ecp_read_data,
22363 + parport_ieee1284_ecp_write_addr,
22364 +
22365 + parport_ieee1284_write_compat,
22366 + parport_ieee1284_read_nibble,
22367 + parport_ieee1284_read_byte,
22368 +};
22369 +
22370 +/* --- Initialisation code -------------------------------- */
22371 +
22372 +static struct parport *parport_splink_probe_port (unsigned long int base)
22373 +{
22374 + struct parport_pc_private *priv;
22375 + struct parport_operations *ops;
22376 + struct parport *p;
22377 +
22378 + if (check_mem_region(base, 3)) {
22379 + printk (KERN_DEBUG "parport (0x%lx): iomem region not available\n", base);
22380 + return NULL;
22381 + }
22382 + priv = kmalloc (sizeof (struct parport_pc_private), GFP_KERNEL);
22383 + if (!priv) {
22384 + printk (KERN_DEBUG "parport (0x%lx): no memory!\n", base);
22385 + return NULL;
22386 + }
22387 + ops = kmalloc (sizeof (struct parport_operations), GFP_KERNEL);
22388 + if (!ops) {
22389 + printk (KERN_DEBUG "parport (0x%lx): no memory for ops!\n",
22390 + base);
22391 + kfree (priv);
22392 + return NULL;
22393 + }
22394 + memcpy (ops, &parport_splink_ops, sizeof (struct parport_operations));
22395 + priv->ctr = 0xc;
22396 + priv->ctr_writable = 0xff;
22397 +
22398 + if (!(p = parport_register_port(base, PARPORT_IRQ_NONE,
22399 + PARPORT_DMA_NONE, ops))) {
22400 + printk (KERN_DEBUG "parport (0x%lx): registration failed!\n",
22401 + base);
22402 + kfree (priv);
22403 + kfree (ops);
22404 + return NULL;
22405 + }
22406 +
22407 + p->modes = PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT;
22408 + p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
22409 + p->private_data = priv;
22410 +
22411 + parport_proc_register(p);
22412 + request_mem_region (p->base, 3, p->name);
22413 +
22414 + /* Done probing. Now put the port into a sensible start-up state. */
22415 + parport_splink_write_data(p, 0);
22416 + parport_splink_data_forward (p);
22417 +
22418 + /* Now that we've told the sharing engine about the port, and
22419 + found out its characteristics, let the high-level drivers
22420 + know about it. */
22421 + parport_announce_port (p);
22422 +
22423 + DPRINTK(KERN_DEBUG "parport (0x%lx): init ok!\n",
22424 + base);
22425 + return p;
22426 +}
22427 +
22428 +static void parport_splink_unregister_port(struct parport *p) {
22429 + struct parport_pc_private *priv = p->private_data;
22430 + struct parport_operations *ops = p->ops;
22431 +
22432 + if (p->irq != PARPORT_IRQ_NONE)
22433 + free_irq(p->irq, p);
22434 + release_mem_region(p->base, 3);
22435 + parport_proc_unregister(p);
22436 + kfree (priv);
22437 + parport_unregister_port(p);
22438 + kfree (ops);
22439 +}
22440 +
22441 +
22442 +int parport_splink_init(void)
22443 +{
22444 + int ret;
22445 +
22446 + DPRINTK(KERN_DEBUG "parport_splink init called\n");
22447 + parport_splink_setup_interrupt();
22448 + ret = !parport_splink_probe_port(SPLINK_ADDRESS);
22449 +
22450 + return ret;
22451 +}
22452 +
22453 +void parport_splink_cleanup(void) {
22454 + struct parport *p = parport_enumerate(), *tmp;
22455 + DPRINTK(KERN_DEBUG "parport_splink cleanup called\n");
22456 + if (p->size) {
22457 + if (p->modes & PARPORT_MODE_PCSPP) {
22458 + while(p) {
22459 + tmp = p->next;
22460 + parport_splink_unregister_port(p);
22461 + p = tmp;
22462 + }
22463 + }
22464 + }
22465 +}
22466 +
22467 +MODULE_AUTHOR("Nuno Grilo <nuno.grilo@netcabo.pt>");
22468 +MODULE_DESCRIPTION("Parport Driver for ASUS WL-500g router builtin Port");
22469 +MODULE_SUPPORTED_DEVICE("ASUS WL-500g builtin Parallel Port");
22470 +MODULE_LICENSE("GPL");
22471 +
22472 +module_init(parport_splink_init)
22473 +module_exit(parport_splink_cleanup)
22474 +
22475 diff -urN linux.old/drivers/pcmcia/Makefile linux.dev/drivers/pcmcia/Makefile
22476 --- linux.old/drivers/pcmcia/Makefile 2005-11-07 23:12:51.350935000 +0100
22477 +++ linux.dev/drivers/pcmcia/Makefile 2005-11-07 21:57:07.941591750 +0100
22478 @@ -74,6 +74,10 @@
22479 au1000_ss-objs-$(CONFIG_MIPS_HYDROGEN3) += au1000_hydrogen3.o
22480 au1000_ss-objs-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o
22481
22482 +obj-$(CONFIG_PCMCIA_BCM4710) += bcm4710_ss.o
22483 +bcm4710_ss-objs := bcm4710_generic.o
22484 +bcm4710_ss-objs += bcm4710_pcmcia.o
22485 +
22486 obj-$(CONFIG_PCMCIA_SA1100) += sa1100_cs.o
22487 obj-$(CONFIG_PCMCIA_M8XX) += m8xx_pcmcia.o
22488 obj-$(CONFIG_PCMCIA_SIBYTE) += sibyte_generic.o
22489 @@ -112,5 +116,8 @@
22490 au1x00_ss.o: $(au1000_ss-objs-y)
22491 $(LD) -r -o $@ $(au1000_ss-objs-y)
22492
22493 +bcm4710_ss.o: $(bcm4710_ss-objs)
22494 + $(LD) -r -o $@ $(bcm4710_ss-objs)
22495 +
22496 yenta_socket.o: $(yenta_socket-objs)
22497 $(LD) $(LD_RFLAG) -r -o $@ $(yenta_socket-objs)
22498 diff -urN linux.old/drivers/pcmcia/bcm4710_generic.c linux.dev/drivers/pcmcia/bcm4710_generic.c
22499 --- linux.old/drivers/pcmcia/bcm4710_generic.c 1970-01-01 01:00:00.000000000 +0100
22500 +++ linux.dev/drivers/pcmcia/bcm4710_generic.c 2005-11-07 21:57:07.945592000 +0100
22501 @@ -0,0 +1,912 @@
22502 +/*
22503 + *
22504 + * bcm47xx pcmcia driver
22505 + *
22506 + * Copyright 2004, Broadcom Corporation
22507 + * All Rights Reserved.
22508 + *
22509 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
22510 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
22511 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
22512 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22513 + *
22514 + * Based on sa1100_generic.c from www.handhelds.org,
22515 + * and au1000_generic.c from oss.sgi.com.
22516 + *
22517 + * $Id: bcm4710_generic.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
22518 + */
22519 +#include <linux/module.h>
22520 +#include <linux/init.h>
22521 +#include <linux/config.h>
22522 +#include <linux/delay.h>
22523 +#include <linux/ioport.h>
22524 +#include <linux/kernel.h>
22525 +#include <linux/tqueue.h>
22526 +#include <linux/timer.h>
22527 +#include <linux/mm.h>
22528 +#include <linux/proc_fs.h>
22529 +#include <linux/version.h>
22530 +#include <linux/types.h>
22531 +#include <linux/vmalloc.h>
22532 +
22533 +#include <pcmcia/version.h>
22534 +#include <pcmcia/cs_types.h>
22535 +#include <pcmcia/cs.h>
22536 +#include <pcmcia/ss.h>
22537 +#include <pcmcia/bulkmem.h>
22538 +#include <pcmcia/cistpl.h>
22539 +#include <pcmcia/bus_ops.h>
22540 +#include "cs_internal.h"
22541 +
22542 +#include <asm/io.h>
22543 +#include <asm/irq.h>
22544 +#include <asm/system.h>
22545 +
22546 +#include <typedefs.h>
22547 +#include <bcm4710.h>
22548 +#include <sbextif.h>
22549 +
22550 +#include "bcm4710pcmcia.h"
22551 +
22552 +#ifdef PCMCIA_DEBUG
22553 +static int pc_debug = PCMCIA_DEBUG;
22554 +#endif
22555 +
22556 +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm47xx Socket Controller");
22557 +
22558 +/* This structure maintains housekeeping state for each socket, such
22559 + * as the last known values of the card detect pins, or the Card Services
22560 + * callback value associated with the socket:
22561 + */
22562 +static struct bcm47xx_pcmcia_socket *pcmcia_socket;
22563 +static int socket_count;
22564 +
22565 +
22566 +/* Returned by the low-level PCMCIA interface: */
22567 +static struct pcmcia_low_level *pcmcia_low_level;
22568 +
22569 +/* Event poll timer structure */
22570 +static struct timer_list poll_timer;
22571 +
22572 +
22573 +/* Prototypes for routines which are used internally: */
22574 +
22575 +static int bcm47xx_pcmcia_driver_init(void);
22576 +static void bcm47xx_pcmcia_driver_shutdown(void);
22577 +static void bcm47xx_pcmcia_task_handler(void *data);
22578 +static void bcm47xx_pcmcia_poll_event(unsigned long data);
22579 +static void bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs);
22580 +static struct tq_struct bcm47xx_pcmcia_task;
22581 +
22582 +#ifdef CONFIG_PROC_FS
22583 +static int bcm47xx_pcmcia_proc_status(char *buf, char **start,
22584 + off_t pos, int count, int *eof, void *data);
22585 +#endif
22586 +
22587 +
22588 +/* Prototypes for operations which are exported to the
22589 + * in-kernel PCMCIA core:
22590 + */
22591 +
22592 +static int bcm47xx_pcmcia_init(unsigned int sock);
22593 +static int bcm47xx_pcmcia_suspend(unsigned int sock);
22594 +static int bcm47xx_pcmcia_register_callback(unsigned int sock,
22595 + void (*handler)(void *, unsigned int), void *info);
22596 +static int bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap);
22597 +static int bcm47xx_pcmcia_get_status(unsigned int sock, u_int *value);
22598 +static int bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state);
22599 +static int bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state);
22600 +static int bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *io);
22601 +static int bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *io);
22602 +static int bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22603 +static int bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *mem);
22604 +#ifdef CONFIG_PROC_FS
22605 +static void bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base);
22606 +#endif
22607 +
22608 +static struct pccard_operations bcm47xx_pcmcia_operations = {
22609 + bcm47xx_pcmcia_init,
22610 + bcm47xx_pcmcia_suspend,
22611 + bcm47xx_pcmcia_register_callback,
22612 + bcm47xx_pcmcia_inquire_socket,
22613 + bcm47xx_pcmcia_get_status,
22614 + bcm47xx_pcmcia_get_socket,
22615 + bcm47xx_pcmcia_set_socket,
22616 + bcm47xx_pcmcia_get_io_map,
22617 + bcm47xx_pcmcia_set_io_map,
22618 + bcm47xx_pcmcia_get_mem_map,
22619 + bcm47xx_pcmcia_set_mem_map,
22620 +#ifdef CONFIG_PROC_FS
22621 + bcm47xx_pcmcia_proc_setup
22622 +#endif
22623 +};
22624 +
22625 +
22626 +/*
22627 + * bcm47xx_pcmcia_driver_init()
22628 + *
22629 + * This routine performs a basic sanity check to ensure that this
22630 + * kernel has been built with the appropriate board-specific low-level
22631 + * PCMCIA support, performs low-level PCMCIA initialization, registers
22632 + * this socket driver with Card Services, and then spawns the daemon
22633 + * thread which is the real workhorse of the socket driver.
22634 + *
22635 + * Please see linux/Documentation/arm/SA1100/PCMCIA for more information
22636 + * on the low-level kernel interface.
22637 + *
22638 + * Returns: 0 on success, -1 on error
22639 + */
22640 +static int __init bcm47xx_pcmcia_driver_init(void)
22641 +{
22642 + servinfo_t info;
22643 + struct pcmcia_init pcmcia_init;
22644 + struct pcmcia_state state;
22645 + unsigned int i;
22646 + unsigned long tmp;
22647 +
22648 +
22649 + printk("\nBCM47XX PCMCIA (CS release %s)\n", CS_RELEASE);
22650 +
22651 + CardServices(GetCardServicesInfo, &info);
22652 +
22653 + if (info.Revision != CS_RELEASE_CODE) {
22654 + printk(KERN_ERR "Card Services release codes do not match\n");
22655 + return -1;
22656 + }
22657 +
22658 +#ifdef CONFIG_BCM4710
22659 + pcmcia_low_level=&bcm4710_pcmcia_ops;
22660 +#else
22661 +#error Unsupported Broadcom BCM47XX board.
22662 +#endif
22663 +
22664 + pcmcia_init.handler=bcm47xx_pcmcia_interrupt;
22665 +
22666 + if ((socket_count = pcmcia_low_level->init(&pcmcia_init)) < 0) {
22667 + printk(KERN_ERR "Unable to initialize PCMCIA service.\n");
22668 + return -EIO;
22669 + } else {
22670 + printk("\t%d PCMCIA sockets initialized.\n", socket_count);
22671 + }
22672 +
22673 + pcmcia_socket =
22674 + kmalloc(sizeof(struct bcm47xx_pcmcia_socket) * socket_count,
22675 + GFP_KERNEL);
22676 + memset(pcmcia_socket, 0,
22677 + sizeof(struct bcm47xx_pcmcia_socket) * socket_count);
22678 + if (!pcmcia_socket) {
22679 + printk(KERN_ERR "Card Services can't get memory \n");
22680 + return -1;
22681 + }
22682 +
22683 + for (i = 0; i < socket_count; i++) {
22684 + if (pcmcia_low_level->socket_state(i, &state) < 0) {
22685 + printk(KERN_ERR "Unable to get PCMCIA status\n");
22686 + return -EIO;
22687 + }
22688 + pcmcia_socket[i].k_state = state;
22689 + pcmcia_socket[i].cs_state.csc_mask = SS_DETECT;
22690 +
22691 + if (i == 0) {
22692 + pcmcia_socket[i].virt_io =
22693 + (unsigned long)ioremap_nocache(EXTIF_PCMCIA_IOBASE(BCM4710_EXTIF), 0x1000);
22694 + /* Substract ioport base which gets added by in/out */
22695 + pcmcia_socket[i].virt_io -= mips_io_port_base;
22696 + pcmcia_socket[i].phys_attr =
22697 + (unsigned long)EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF);
22698 + pcmcia_socket[i].phys_mem =
22699 + (unsigned long)EXTIF_PCMCIA_MEMBASE(BCM4710_EXTIF);
22700 + } else {
22701 + printk(KERN_ERR "bcm4710: socket 1 not supported\n");
22702 + return 1;
22703 + }
22704 + }
22705 +
22706 + /* Only advertise as many sockets as we can detect: */
22707 + if (register_ss_entry(socket_count, &bcm47xx_pcmcia_operations) < 0) {
22708 + printk(KERN_ERR "Unable to register socket service routine\n");
22709 + return -ENXIO;
22710 + }
22711 +
22712 + /* Start the event poll timer.
22713 + * It will reschedule by itself afterwards.
22714 + */
22715 + bcm47xx_pcmcia_poll_event(0);
22716 +
22717 + DEBUG(1, "bcm4710: initialization complete\n");
22718 + return 0;
22719 +
22720 +}
22721 +
22722 +module_init(bcm47xx_pcmcia_driver_init);
22723 +
22724 +
22725 +/*
22726 + * bcm47xx_pcmcia_driver_shutdown()
22727 + *
22728 + * Invokes the low-level kernel service to free IRQs associated with this
22729 + * socket controller and reset GPIO edge detection.
22730 + */
22731 +static void __exit bcm47xx_pcmcia_driver_shutdown(void)
22732 +{
22733 + int i;
22734 +
22735 + del_timer_sync(&poll_timer);
22736 + unregister_ss_entry(&bcm47xx_pcmcia_operations);
22737 + pcmcia_low_level->shutdown();
22738 + flush_scheduled_tasks();
22739 + for (i = 0; i < socket_count; i++) {
22740 + if (pcmcia_socket[i].virt_io)
22741 + iounmap((void *)pcmcia_socket[i].virt_io);
22742 + if (pcmcia_socket[i].phys_attr)
22743 + iounmap((void *)pcmcia_socket[i].phys_attr);
22744 + if (pcmcia_socket[i].phys_mem)
22745 + iounmap((void *)pcmcia_socket[i].phys_mem);
22746 + }
22747 + DEBUG(1, "bcm4710: shutdown complete\n");
22748 +}
22749 +
22750 +module_exit(bcm47xx_pcmcia_driver_shutdown);
22751 +
22752 +/*
22753 + * bcm47xx_pcmcia_init()
22754 + * We perform all of the interesting initialization tasks in
22755 + * bcm47xx_pcmcia_driver_init().
22756 + *
22757 + * Returns: 0
22758 + */
22759 +static int bcm47xx_pcmcia_init(unsigned int sock)
22760 +{
22761 + DEBUG(1, "%s(): initializing socket %u\n", __FUNCTION__, sock);
22762 +
22763 + return 0;
22764 +}
22765 +
22766 +/*
22767 + * bcm47xx_pcmcia_suspend()
22768 + *
22769 + * We don't currently perform any actions on a suspend.
22770 + *
22771 + * Returns: 0
22772 + */
22773 +static int bcm47xx_pcmcia_suspend(unsigned int sock)
22774 +{
22775 + DEBUG(1, "%s(): suspending socket %u\n", __FUNCTION__, sock);
22776 +
22777 + return 0;
22778 +}
22779 +
22780 +
22781 +/*
22782 + * bcm47xx_pcmcia_events()
22783 + *
22784 + * Helper routine to generate a Card Services event mask based on
22785 + * state information obtained from the kernel low-level PCMCIA layer
22786 + * in a recent (and previous) sampling. Updates `prev_state'.
22787 + *
22788 + * Returns: an event mask for the given socket state.
22789 + */
22790 +static inline unsigned
22791 +bcm47xx_pcmcia_events(struct pcmcia_state *state,
22792 + struct pcmcia_state *prev_state,
22793 + unsigned int mask, unsigned int flags)
22794 +{
22795 + unsigned int events=0;
22796 +
22797 + if (state->bvd1 != prev_state->bvd1) {
22798 +
22799 + DEBUG(3, "%s(): card BVD1 value %u\n", __FUNCTION__, state->bvd1);
22800 +
22801 + events |= mask & (flags & SS_IOCARD) ? SS_STSCHG : SS_BATDEAD;
22802 + }
22803 +
22804 + if (state->bvd2 != prev_state->bvd2) {
22805 +
22806 + DEBUG(3, "%s(): card BVD2 value %u\n", __FUNCTION__, state->bvd2);
22807 +
22808 + events |= mask & (flags & SS_IOCARD) ? 0 : SS_BATWARN;
22809 + }
22810 +
22811 + if (state->detect != prev_state->detect) {
22812 +
22813 + DEBUG(3, "%s(): card detect value %u\n", __FUNCTION__, state->detect);
22814 +
22815 + events |= mask & SS_DETECT;
22816 + }
22817 +
22818 +
22819 + if (state->ready != prev_state->ready) {
22820 +
22821 + DEBUG(3, "%s(): card ready value %u\n", __FUNCTION__, state->ready);
22822 +
22823 + events |= mask & ((flags & SS_IOCARD) ? 0 : SS_READY);
22824 + }
22825 +
22826 + if (events != 0) {
22827 + DEBUG(2, "events: %s%s%s%s%s\n",
22828 + (events & SS_DETECT) ? "DETECT " : "",
22829 + (events & SS_READY) ? "READY " : "",
22830 + (events & SS_BATDEAD) ? "BATDEAD " : "",
22831 + (events & SS_BATWARN) ? "BATWARN " : "",
22832 + (events & SS_STSCHG) ? "STSCHG " : "");
22833 + }
22834 +
22835 + *prev_state=*state;
22836 + return events;
22837 +}
22838 +
22839 +
22840 +/*
22841 + * bcm47xx_pcmcia_task_handler()
22842 + *
22843 + * Processes serviceable socket events using the "eventd" thread context.
22844 + *
22845 + * Event processing (specifically, the invocation of the Card Services event
22846 + * callback) occurs in this thread rather than in the actual interrupt
22847 + * handler due to the use of scheduling operations in the PCMCIA core.
22848 + */
22849 +static void bcm47xx_pcmcia_task_handler(void *data)
22850 +{
22851 + struct pcmcia_state state;
22852 + int i, events, irq_status;
22853 +
22854 + DEBUG(4, "%s(): entering PCMCIA monitoring thread\n", __FUNCTION__);
22855 +
22856 + for (i = 0; i < socket_count; i++) {
22857 + if ((irq_status = pcmcia_low_level->socket_state(i, &state)) < 0)
22858 + printk(KERN_ERR "Error in kernel low-level PCMCIA service.\n");
22859 +
22860 + events = bcm47xx_pcmcia_events(&state,
22861 + &pcmcia_socket[i].k_state,
22862 + pcmcia_socket[i].cs_state.csc_mask,
22863 + pcmcia_socket[i].cs_state.flags);
22864 +
22865 + if (pcmcia_socket[i].handler != NULL) {
22866 + pcmcia_socket[i].handler(pcmcia_socket[i].handler_info,
22867 + events);
22868 + }
22869 + }
22870 +}
22871 +
22872 +static struct tq_struct bcm47xx_pcmcia_task = {
22873 + routine: bcm47xx_pcmcia_task_handler
22874 +};
22875 +
22876 +
22877 +/*
22878 + * bcm47xx_pcmcia_poll_event()
22879 + *
22880 + * Let's poll for events in addition to IRQs since IRQ only is unreliable...
22881 + */
22882 +static void bcm47xx_pcmcia_poll_event(unsigned long dummy)
22883 +{
22884 + DEBUG(4, "%s(): polling for events\n", __FUNCTION__);
22885 +
22886 + poll_timer.function = bcm47xx_pcmcia_poll_event;
22887 + poll_timer.expires = jiffies + BCM47XX_PCMCIA_POLL_PERIOD;
22888 + add_timer(&poll_timer);
22889 + schedule_task(&bcm47xx_pcmcia_task);
22890 +}
22891 +
22892 +
22893 +/*
22894 + * bcm47xx_pcmcia_interrupt()
22895 + *
22896 + * Service routine for socket driver interrupts (requested by the
22897 + * low-level PCMCIA init() operation via bcm47xx_pcmcia_thread()).
22898 + *
22899 + * The actual interrupt-servicing work is performed by
22900 + * bcm47xx_pcmcia_task(), largely because the Card Services event-
22901 + * handling code performs scheduling operations which cannot be
22902 + * executed from within an interrupt context.
22903 + */
22904 +static void
22905 +bcm47xx_pcmcia_interrupt(int irq, void *dev, struct pt_regs *regs)
22906 +{
22907 + DEBUG(3, "%s(): servicing IRQ %d\n", __FUNCTION__, irq);
22908 + schedule_task(&bcm47xx_pcmcia_task);
22909 +}
22910 +
22911 +
22912 +/*
22913 + * bcm47xx_pcmcia_register_callback()
22914 + *
22915 + * Implements the register_callback() operation for the in-kernel
22916 + * PCMCIA service (formerly SS_RegisterCallback in Card Services). If
22917 + * the function pointer `handler' is not NULL, remember the callback
22918 + * location in the state for `sock', and increment the usage counter
22919 + * for the driver module. (The callback is invoked from the interrupt
22920 + * service routine, bcm47xx_pcmcia_interrupt(), to notify Card Services
22921 + * of interesting events.) Otherwise, clear the callback pointer in the
22922 + * socket state and decrement the module usage count.
22923 + *
22924 + * Returns: 0
22925 + */
22926 +static int
22927 +bcm47xx_pcmcia_register_callback(unsigned int sock,
22928 + void (*handler)(void *, unsigned int), void *info)
22929 +{
22930 + if (handler == NULL) {
22931 + pcmcia_socket[sock].handler = NULL;
22932 + MOD_DEC_USE_COUNT;
22933 + } else {
22934 + MOD_INC_USE_COUNT;
22935 + pcmcia_socket[sock].handler = handler;
22936 + pcmcia_socket[sock].handler_info = info;
22937 + }
22938 + return 0;
22939 +}
22940 +
22941 +
22942 +/*
22943 + * bcm47xx_pcmcia_inquire_socket()
22944 + *
22945 + * Implements the inquire_socket() operation for the in-kernel PCMCIA
22946 + * service (formerly SS_InquireSocket in Card Services). Of note is
22947 + * the setting of the SS_CAP_PAGE_REGS bit in the `features' field of
22948 + * `cap' to "trick" Card Services into tolerating large "I/O memory"
22949 + * addresses. Also set is SS_CAP_STATIC_MAP, which disables the memory
22950 + * resource database check. (Mapped memory is set up within the socket
22951 + * driver itself.)
22952 + *
22953 + * In conjunction with the STATIC_MAP capability is a new field,
22954 + * `io_offset', recommended by David Hinds. Rather than go through
22955 + * the SetIOMap interface (which is not quite suited for communicating
22956 + * window locations up from the socket driver), we just pass up
22957 + * an offset which is applied to client-requested base I/O addresses
22958 + * in alloc_io_space().
22959 + *
22960 + * Returns: 0 on success, -1 if no pin has been configured for `sock'
22961 + */
22962 +static int
22963 +bcm47xx_pcmcia_inquire_socket(unsigned int sock, socket_cap_t *cap)
22964 +{
22965 + struct pcmcia_irq_info irq_info;
22966 +
22967 + if (sock >= socket_count) {
22968 + printk(KERN_ERR "bcm47xx: socket %u not configured\n", sock);
22969 + return -1;
22970 + }
22971 +
22972 + /* SS_CAP_PAGE_REGS: used by setup_cis_mem() in cistpl.c to set the
22973 + * force_low argument to validate_mem() in rsrc_mgr.c -- since in
22974 + * general, the mapped * addresses of the PCMCIA memory regions
22975 + * will not be within 0xffff, setting force_low would be
22976 + * undesirable.
22977 + *
22978 + * SS_CAP_STATIC_MAP: don't bother with the (user-configured) memory
22979 + * resource database; we instead pass up physical address ranges
22980 + * and allow other parts of Card Services to deal with remapping.
22981 + *
22982 + * SS_CAP_PCCARD: we can deal with 16-bit PCMCIA & CF cards, but
22983 + * not 32-bit CardBus devices.
22984 + */
22985 + cap->features = (SS_CAP_PAGE_REGS | SS_CAP_STATIC_MAP | SS_CAP_PCCARD);
22986 +
22987 + irq_info.sock = sock;
22988 + irq_info.irq = -1;
22989 +
22990 + if (pcmcia_low_level->get_irq_info(&irq_info) < 0) {
22991 + printk(KERN_ERR "Error obtaining IRQ info socket %u\n", sock);
22992 + return -1;
22993 + }
22994 +
22995 + cap->irq_mask = 0;
22996 + cap->map_size = PAGE_SIZE;
22997 + cap->pci_irq = irq_info.irq;
22998 + cap->io_offset = pcmcia_socket[sock].virt_io;
22999 +
23000 + return 0;
23001 +}
23002 +
23003 +
23004 +/*
23005 + * bcm47xx_pcmcia_get_status()
23006 + *
23007 + * Implements the get_status() operation for the in-kernel PCMCIA
23008 + * service (formerly SS_GetStatus in Card Services). Essentially just
23009 + * fills in bits in `status' according to internal driver state or
23010 + * the value of the voltage detect chipselect register.
23011 + *
23012 + * As a debugging note, during card startup, the PCMCIA core issues
23013 + * three set_socket() commands in a row the first with RESET deasserted,
23014 + * the second with RESET asserted, and the last with RESET deasserted
23015 + * again. Following the third set_socket(), a get_status() command will
23016 + * be issued. The kernel is looking for the SS_READY flag (see
23017 + * setup_socket(), reset_socket(), and unreset_socket() in cs.c).
23018 + *
23019 + * Returns: 0
23020 + */
23021 +static int
23022 +bcm47xx_pcmcia_get_status(unsigned int sock, unsigned int *status)
23023 +{
23024 + struct pcmcia_state state;
23025 +
23026 +
23027 + if ((pcmcia_low_level->socket_state(sock, &state)) < 0) {
23028 + printk(KERN_ERR "Unable to get PCMCIA status from kernel.\n");
23029 + return -1;
23030 + }
23031 +
23032 + pcmcia_socket[sock].k_state = state;
23033 +
23034 + *status = state.detect ? SS_DETECT : 0;
23035 +
23036 + *status |= state.ready ? SS_READY : 0;
23037 +
23038 + /* The power status of individual sockets is not available
23039 + * explicitly from the hardware, so we just remember the state
23040 + * and regurgitate it upon request:
23041 + */
23042 + *status |= pcmcia_socket[sock].cs_state.Vcc ? SS_POWERON : 0;
23043 +
23044 + if (pcmcia_socket[sock].cs_state.flags & SS_IOCARD)
23045 + *status |= state.bvd1 ? SS_STSCHG : 0;
23046 + else {
23047 + if (state.bvd1 == 0)
23048 + *status |= SS_BATDEAD;
23049 + else if (state.bvd2 == 0)
23050 + *status |= SS_BATWARN;
23051 + }
23052 +
23053 + *status |= state.vs_3v ? SS_3VCARD : 0;
23054 +
23055 + *status |= state.vs_Xv ? SS_XVCARD : 0;
23056 +
23057 + DEBUG(2, "\tstatus: %s%s%s%s%s%s%s%s\n",
23058 + (*status&SS_DETECT)?"DETECT ":"",
23059 + (*status&SS_READY)?"READY ":"",
23060 + (*status&SS_BATDEAD)?"BATDEAD ":"",
23061 + (*status&SS_BATWARN)?"BATWARN ":"",
23062 + (*status&SS_POWERON)?"POWERON ":"",
23063 + (*status&SS_STSCHG)?"STSCHG ":"",
23064 + (*status&SS_3VCARD)?"3VCARD ":"",
23065 + (*status&SS_XVCARD)?"XVCARD ":"");
23066 +
23067 + return 0;
23068 +}
23069 +
23070 +
23071 +/*
23072 + * bcm47xx_pcmcia_get_socket()
23073 + *
23074 + * Implements the get_socket() operation for the in-kernel PCMCIA
23075 + * service (formerly SS_GetSocket in Card Services). Not a very
23076 + * exciting routine.
23077 + *
23078 + * Returns: 0
23079 + */
23080 +static int
23081 +bcm47xx_pcmcia_get_socket(unsigned int sock, socket_state_t *state)
23082 +{
23083 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
23084 +
23085 + /* This information was given to us in an earlier call to set_socket(),
23086 + * so we're just regurgitating it here:
23087 + */
23088 + *state = pcmcia_socket[sock].cs_state;
23089 + return 0;
23090 +}
23091 +
23092 +
23093 +/*
23094 + * bcm47xx_pcmcia_set_socket()
23095 + *
23096 + * Implements the set_socket() operation for the in-kernel PCMCIA
23097 + * service (formerly SS_SetSocket in Card Services). We more or
23098 + * less punt all of this work and let the kernel handle the details
23099 + * of power configuration, reset, &c. We also record the value of
23100 + * `state' in order to regurgitate it to the PCMCIA core later.
23101 + *
23102 + * Returns: 0
23103 + */
23104 +static int
23105 +bcm47xx_pcmcia_set_socket(unsigned int sock, socket_state_t *state)
23106 +{
23107 + struct pcmcia_configure configure;
23108 +
23109 + DEBUG(2, "\tmask: %s%s%s%s%s%s\n\tflags: %s%s%s%s%s%s\n"
23110 + "\tVcc %d Vpp %d irq %d\n",
23111 + (state->csc_mask == 0) ? "<NONE>" : "",
23112 + (state->csc_mask & SS_DETECT) ? "DETECT " : "",
23113 + (state->csc_mask & SS_READY) ? "READY " : "",
23114 + (state->csc_mask & SS_BATDEAD) ? "BATDEAD " : "",
23115 + (state->csc_mask & SS_BATWARN) ? "BATWARN " : "",
23116 + (state->csc_mask & SS_STSCHG) ? "STSCHG " : "",
23117 + (state->flags == 0) ? "<NONE>" : "",
23118 + (state->flags & SS_PWR_AUTO) ? "PWR_AUTO " : "",
23119 + (state->flags & SS_IOCARD) ? "IOCARD " : "",
23120 + (state->flags & SS_RESET) ? "RESET " : "",
23121 + (state->flags & SS_SPKR_ENA) ? "SPKR_ENA " : "",
23122 + (state->flags & SS_OUTPUT_ENA) ? "OUTPUT_ENA " : "",
23123 + state->Vcc, state->Vpp, state->io_irq);
23124 +
23125 + configure.sock = sock;
23126 + configure.vcc = state->Vcc;
23127 + configure.vpp = state->Vpp;
23128 + configure.output = (state->flags & SS_OUTPUT_ENA) ? 1 : 0;
23129 + configure.speaker = (state->flags & SS_SPKR_ENA) ? 1 : 0;
23130 + configure.reset = (state->flags & SS_RESET) ? 1 : 0;
23131 +
23132 + if (pcmcia_low_level->configure_socket(&configure) < 0) {
23133 + printk(KERN_ERR "Unable to configure socket %u\n", sock);
23134 + return -1;
23135 + }
23136 +
23137 + pcmcia_socket[sock].cs_state = *state;
23138 + return 0;
23139 +}
23140 +
23141 +
23142 +/*
23143 + * bcm47xx_pcmcia_get_io_map()
23144 + *
23145 + * Implements the get_io_map() operation for the in-kernel PCMCIA
23146 + * service (formerly SS_GetIOMap in Card Services). Just returns an
23147 + * I/O map descriptor which was assigned earlier by a set_io_map().
23148 + *
23149 + * Returns: 0 on success, -1 if the map index was out of range
23150 + */
23151 +static int
23152 +bcm47xx_pcmcia_get_io_map(unsigned int sock, struct pccard_io_map *map)
23153 +{
23154 + DEBUG(2, "bcm47xx_pcmcia_get_io_map: sock %d\n", sock);
23155 +
23156 + if (map->map >= MAX_IO_WIN) {
23157 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23158 + __FUNCTION__, map->map);
23159 + return -1;
23160 + }
23161 +
23162 + *map = pcmcia_socket[sock].io_map[map->map];
23163 + return 0;
23164 +}
23165 +
23166 +
23167 +/*
23168 + * bcm47xx_pcmcia_set_io_map()
23169 + *
23170 + * Implements the set_io_map() operation for the in-kernel PCMCIA
23171 + * service (formerly SS_SetIOMap in Card Services). We configure
23172 + * the map speed as requested, but override the address ranges
23173 + * supplied by Card Services.
23174 + *
23175 + * Returns: 0 on success, -1 on error
23176 + */
23177 +int
23178 +bcm47xx_pcmcia_set_io_map(unsigned int sock, struct pccard_io_map *map)
23179 +{
23180 + unsigned int speed;
23181 + unsigned long start;
23182 +
23183 + DEBUG(2, "\tmap %u speed %u\n\tstart 0x%08lx stop 0x%08lx\n"
23184 + "\tflags: %s%s%s%s%s%s%s%s\n",
23185 + map->map, map->speed, map->start, map->stop,
23186 + (map->flags == 0) ? "<NONE>" : "",
23187 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23188 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23189 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23190 + (map->flags & MAP_0WS) ? "0WS " : "",
23191 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23192 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "",
23193 + (map->flags & MAP_PREFETCH) ? "PREFETCH " : "");
23194 +
23195 + if (map->map >= MAX_IO_WIN) {
23196 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23197 + __FUNCTION__, map->map);
23198 + return -1;
23199 + }
23200 +
23201 + if (map->flags & MAP_ACTIVE) {
23202 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_IO_SPEED;
23203 + pcmcia_socket[sock].speed_io = speed;
23204 + }
23205 +
23206 + start = map->start;
23207 +
23208 + if (map->stop == 1) {
23209 + map->stop = PAGE_SIZE - 1;
23210 + }
23211 +
23212 + map->start = pcmcia_socket[sock].virt_io;
23213 + map->stop = map->start + (map->stop - start);
23214 + pcmcia_socket[sock].io_map[map->map] = *map;
23215 + DEBUG(2, "set_io_map %d start %x stop %x\n",
23216 + map->map, map->start, map->stop);
23217 + return 0;
23218 +}
23219 +
23220 +
23221 +/*
23222 + * bcm47xx_pcmcia_get_mem_map()
23223 + *
23224 + * Implements the get_mem_map() operation for the in-kernel PCMCIA
23225 + * service (formerly SS_GetMemMap in Card Services). Just returns a
23226 + * memory map descriptor which was assigned earlier by a
23227 + * set_mem_map() request.
23228 + *
23229 + * Returns: 0 on success, -1 if the map index was out of range
23230 + */
23231 +static int
23232 +bcm47xx_pcmcia_get_mem_map(unsigned int sock, struct pccard_mem_map *map)
23233 +{
23234 + DEBUG(2, "%s() for sock %u\n", __FUNCTION__, sock);
23235 +
23236 + if (map->map >= MAX_WIN) {
23237 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23238 + __FUNCTION__, map->map);
23239 + return -1;
23240 + }
23241 +
23242 + *map = pcmcia_socket[sock].mem_map[map->map];
23243 + return 0;
23244 +}
23245 +
23246 +
23247 +/*
23248 + * bcm47xx_pcmcia_set_mem_map()
23249 + *
23250 + * Implements the set_mem_map() operation for the in-kernel PCMCIA
23251 + * service (formerly SS_SetMemMap in Card Services). We configure
23252 + * the map speed as requested, but override the address ranges
23253 + * supplied by Card Services.
23254 + *
23255 + * Returns: 0 on success, -1 on error
23256 + */
23257 +static int
23258 +bcm47xx_pcmcia_set_mem_map(unsigned int sock, struct pccard_mem_map *map)
23259 +{
23260 + unsigned int speed;
23261 + unsigned long start;
23262 + u_long flags;
23263 +
23264 + if (map->map >= MAX_WIN) {
23265 + printk(KERN_ERR "%s(): map (%d) out of range\n",
23266 + __FUNCTION__, map->map);
23267 + return -1;
23268 + }
23269 +
23270 + DEBUG(2, "\tmap %u speed %u\n\tsys_start %#lx\n"
23271 + "\tsys_stop %#lx\n\tcard_start %#x\n"
23272 + "\tflags: %s%s%s%s%s%s%s%s\n",
23273 + map->map, map->speed, map->sys_start, map->sys_stop,
23274 + map->card_start, (map->flags == 0) ? "<NONE>" : "",
23275 + (map->flags & MAP_ACTIVE) ? "ACTIVE " : "",
23276 + (map->flags & MAP_16BIT) ? "16BIT " : "",
23277 + (map->flags & MAP_AUTOSZ) ? "AUTOSZ " : "",
23278 + (map->flags & MAP_0WS) ? "0WS " : "",
23279 + (map->flags & MAP_WRPROT) ? "WRPROT " : "",
23280 + (map->flags & MAP_ATTRIB) ? "ATTRIB " : "",
23281 + (map->flags & MAP_USE_WAIT) ? "USE_WAIT " : "");
23282 +
23283 + if (map->flags & MAP_ACTIVE) {
23284 + /* When clients issue RequestMap, the access speed is not always
23285 + * properly configured:
23286 + */
23287 + speed = (map->speed > 0) ? map->speed : BCM47XX_PCMCIA_MEM_SPEED;
23288 +
23289 + /* TBD */
23290 + if (map->flags & MAP_ATTRIB) {
23291 + pcmcia_socket[sock].speed_attr = speed;
23292 + } else {
23293 + pcmcia_socket[sock].speed_mem = speed;
23294 + }
23295 + }
23296 +
23297 + save_flags(flags);
23298 + cli();
23299 + start = map->sys_start;
23300 +
23301 + if (map->sys_stop == 0)
23302 + map->sys_stop = PAGE_SIZE - 1;
23303 +
23304 + if (map->flags & MAP_ATTRIB) {
23305 + map->sys_start = pcmcia_socket[sock].phys_attr +
23306 + map->card_start;
23307 + } else {
23308 + map->sys_start = pcmcia_socket[sock].phys_mem +
23309 + map->card_start;
23310 + }
23311 +
23312 + map->sys_stop = map->sys_start + (map->sys_stop - start);
23313 + pcmcia_socket[sock].mem_map[map->map] = *map;
23314 + restore_flags(flags);
23315 + DEBUG(2, "set_mem_map %d start %x stop %x card_start %x\n",
23316 + map->map, map->sys_start, map->sys_stop,
23317 + map->card_start);
23318 + return 0;
23319 +}
23320 +
23321 +
23322 +#if defined(CONFIG_PROC_FS)
23323 +
23324 +/*
23325 + * bcm47xx_pcmcia_proc_setup()
23326 + *
23327 + * Implements the proc_setup() operation for the in-kernel PCMCIA
23328 + * service (formerly SS_ProcSetup in Card Services).
23329 + *
23330 + * Returns: 0 on success, -1 on error
23331 + */
23332 +static void
23333 +bcm47xx_pcmcia_proc_setup(unsigned int sock, struct proc_dir_entry *base)
23334 +{
23335 + struct proc_dir_entry *entry;
23336 +
23337 + if ((entry = create_proc_entry("status", 0, base)) == NULL) {
23338 + printk(KERN_ERR "Unable to install \"status\" procfs entry\n");
23339 + return;
23340 + }
23341 +
23342 + entry->read_proc = bcm47xx_pcmcia_proc_status;
23343 + entry->data = (void *)sock;
23344 +}
23345 +
23346 +
23347 +/*
23348 + * bcm47xx_pcmcia_proc_status()
23349 + *
23350 + * Implements the /proc/bus/pccard/??/status file.
23351 + *
23352 + * Returns: the number of characters added to the buffer
23353 + */
23354 +static int
23355 +bcm47xx_pcmcia_proc_status(char *buf, char **start, off_t pos,
23356 + int count, int *eof, void *data)
23357 +{
23358 + char *p = buf;
23359 + unsigned int sock = (unsigned int)data;
23360 +
23361 + p += sprintf(p, "k_flags : %s%s%s%s%s%s%s\n",
23362 + pcmcia_socket[sock].k_state.detect ? "detect " : "",
23363 + pcmcia_socket[sock].k_state.ready ? "ready " : "",
23364 + pcmcia_socket[sock].k_state.bvd1 ? "bvd1 " : "",
23365 + pcmcia_socket[sock].k_state.bvd2 ? "bvd2 " : "",
23366 + pcmcia_socket[sock].k_state.wrprot ? "wrprot " : "",
23367 + pcmcia_socket[sock].k_state.vs_3v ? "vs_3v " : "",
23368 + pcmcia_socket[sock].k_state.vs_Xv ? "vs_Xv " : "");
23369 +
23370 + p += sprintf(p, "status : %s%s%s%s%s%s%s%s%s\n",
23371 + pcmcia_socket[sock].k_state.detect ? "SS_DETECT " : "",
23372 + pcmcia_socket[sock].k_state.ready ? "SS_READY " : "",
23373 + pcmcia_socket[sock].cs_state.Vcc ? "SS_POWERON " : "",
23374 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ? "SS_IOCARD " : "",
23375 + (pcmcia_socket[sock].cs_state.flags & SS_IOCARD &&
23376 + pcmcia_socket[sock].k_state.bvd1) ? "SS_STSCHG " : "",
23377 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23378 + (pcmcia_socket[sock].k_state.bvd1 == 0)) ? "SS_BATDEAD " : "",
23379 + ((pcmcia_socket[sock].cs_state.flags & SS_IOCARD) == 0 &&
23380 + (pcmcia_socket[sock].k_state.bvd2 == 0)) ? "SS_BATWARN " : "",
23381 + pcmcia_socket[sock].k_state.vs_3v ? "SS_3VCARD " : "",
23382 + pcmcia_socket[sock].k_state.vs_Xv ? "SS_XVCARD " : "");
23383 +
23384 + p += sprintf(p, "mask : %s%s%s%s%s\n",
23385 + pcmcia_socket[sock].cs_state.csc_mask & SS_DETECT ? "SS_DETECT " : "",
23386 + pcmcia_socket[sock].cs_state.csc_mask & SS_READY ? "SS_READY " : "",
23387 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATDEAD ? "SS_BATDEAD " : "",
23388 + pcmcia_socket[sock].cs_state.csc_mask & SS_BATWARN ? "SS_BATWARN " : "",
23389 + pcmcia_socket[sock].cs_state.csc_mask & SS_STSCHG ? "SS_STSCHG " : "");
23390 +
23391 + p += sprintf(p, "cs_flags : %s%s%s%s%s\n",
23392 + pcmcia_socket[sock].cs_state.flags & SS_PWR_AUTO ?
23393 + "SS_PWR_AUTO " : "",
23394 + pcmcia_socket[sock].cs_state.flags & SS_IOCARD ?
23395 + "SS_IOCARD " : "",
23396 + pcmcia_socket[sock].cs_state.flags & SS_RESET ?
23397 + "SS_RESET " : "",
23398 + pcmcia_socket[sock].cs_state.flags & SS_SPKR_ENA ?
23399 + "SS_SPKR_ENA " : "",
23400 + pcmcia_socket[sock].cs_state.flags & SS_OUTPUT_ENA ?
23401 + "SS_OUTPUT_ENA " : "");
23402 +
23403 + p += sprintf(p, "Vcc : %d\n", pcmcia_socket[sock].cs_state.Vcc);
23404 + p += sprintf(p, "Vpp : %d\n", pcmcia_socket[sock].cs_state.Vpp);
23405 + p += sprintf(p, "irq : %d\n", pcmcia_socket[sock].cs_state.io_irq);
23406 + p += sprintf(p, "I/O : %u\n", pcmcia_socket[sock].speed_io);
23407 + p += sprintf(p, "attribute: %u\n", pcmcia_socket[sock].speed_attr);
23408 + p += sprintf(p, "common : %u\n", pcmcia_socket[sock].speed_mem);
23409 + return p-buf;
23410 +}
23411 +
23412 +
23413 +#endif /* defined(CONFIG_PROC_FS) */
23414 diff -urN linux.old/drivers/pcmcia/bcm4710_pcmcia.c linux.dev/drivers/pcmcia/bcm4710_pcmcia.c
23415 --- linux.old/drivers/pcmcia/bcm4710_pcmcia.c 1970-01-01 01:00:00.000000000 +0100
23416 +++ linux.dev/drivers/pcmcia/bcm4710_pcmcia.c 2005-11-07 21:57:07.945592000 +0100
23417 @@ -0,0 +1,266 @@
23418 +/*
23419 + * BCM4710 specific pcmcia routines.
23420 + *
23421 + * Copyright 2004, Broadcom Corporation
23422 + * All Rights Reserved.
23423 + *
23424 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23425 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23426 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23427 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23428 + *
23429 + * $Id: bcm4710_pcmcia.c,v 1.1 2005/03/16 13:50:00 wbx Exp $
23430 + */
23431 +#include <linux/module.h>
23432 +#include <linux/init.h>
23433 +#include <linux/config.h>
23434 +#include <linux/delay.h>
23435 +#include <linux/ioport.h>
23436 +#include <linux/kernel.h>
23437 +#include <linux/tqueue.h>
23438 +#include <linux/timer.h>
23439 +#include <linux/mm.h>
23440 +#include <linux/proc_fs.h>
23441 +#include <linux/version.h>
23442 +#include <linux/types.h>
23443 +#include <linux/pci.h>
23444 +
23445 +#include <pcmcia/version.h>
23446 +#include <pcmcia/cs_types.h>
23447 +#include <pcmcia/cs.h>
23448 +#include <pcmcia/ss.h>
23449 +#include <pcmcia/bulkmem.h>
23450 +#include <pcmcia/cistpl.h>
23451 +#include <pcmcia/bus_ops.h>
23452 +#include "cs_internal.h"
23453 +
23454 +#include <asm/io.h>
23455 +#include <asm/irq.h>
23456 +#include <asm/system.h>
23457 +
23458 +
23459 +#include <typedefs.h>
23460 +#include <bcmdevs.h>
23461 +#include <bcm4710.h>
23462 +#include <sbconfig.h>
23463 +#include <sbextif.h>
23464 +
23465 +#include "bcm4710pcmcia.h"
23466 +
23467 +/* Use a static var for irq dev_id */
23468 +static int bcm47xx_pcmcia_dev_id;
23469 +
23470 +/* Do we think we have a card or not? */
23471 +static int bcm47xx_pcmcia_present = 0;
23472 +
23473 +
23474 +static void bcm4710_pcmcia_reset(void)
23475 +{
23476 + extifregs_t *eir;
23477 + unsigned long s;
23478 + uint32 out0, out1, outen;
23479 +
23480 +
23481 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23482 +
23483 + save_and_cli(s);
23484 +
23485 + /* Use gpio7 to reset the pcmcia slot */
23486 + outen = readl(&eir->gpio[0].outen);
23487 + outen |= BCM47XX_PCMCIA_RESET;
23488 + out0 = readl(&eir->gpio[0].out);
23489 + out0 &= ~(BCM47XX_PCMCIA_RESET);
23490 + out1 = out0 | BCM47XX_PCMCIA_RESET;
23491 +
23492 + writel(out0, &eir->gpio[0].out);
23493 + writel(outen, &eir->gpio[0].outen);
23494 + mdelay(1);
23495 + writel(out1, &eir->gpio[0].out);
23496 + mdelay(1);
23497 + writel(out0, &eir->gpio[0].out);
23498 +
23499 + restore_flags(s);
23500 +}
23501 +
23502 +
23503 +static int bcm4710_pcmcia_init(struct pcmcia_init *init)
23504 +{
23505 + struct pci_dev *pdev;
23506 + extifregs_t *eir;
23507 + uint32 outen, intp, intm, tmp;
23508 + uint16 *attrsp;
23509 + int rc = 0, i;
23510 + extern unsigned long bcm4710_cpu_cycle;
23511 +
23512 +
23513 + if (!(pdev = pci_find_device(VENDOR_BROADCOM, SB_EXTIF, NULL))) {
23514 + printk(KERN_ERR "bcm4710_pcmcia: extif not found\n");
23515 + return -ENODEV;
23516 + }
23517 + eir = (extifregs_t *) ioremap_nocache(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
23518 +
23519 + /* Initialize the pcmcia i/f: 16bit no swap */
23520 + writel(CF_EM_PCMCIA | CF_DS | CF_EN, &eir->pcmcia_config);
23521 +
23522 +#ifdef notYet
23523 +
23524 + /* Set the timing for memory accesses */
23525 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23526 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23527 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23528 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23529 + writel(tmp, &eir->pcmcia_memwait); /* 0x01020a0c for a 100Mhz clock */
23530 +
23531 + /* Set the timing for I/O accesses */
23532 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23533 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23534 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23535 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23536 + writel(tmp, &eir->pcmcia_iowait); /* 0x01020a0c for a 100Mhz clock */
23537 +
23538 + /* Set the timing for attribute accesses */
23539 + tmp = (19 / bcm4710_cpu_cycle) << 24; /* W3 = 10nS */
23540 + tmp = tmp | ((29 / bcm4710_cpu_cycle) << 16); /* W2 = 20nS */
23541 + tmp = tmp | ((109 / bcm4710_cpu_cycle) << 8); /* W1 = 100nS */
23542 + tmp = tmp | (129 / bcm4710_cpu_cycle); /* W0 = 120nS */
23543 + writel(tmp, &eir->pcmcia_attrwait); /* 0x01020a0c for a 100Mhz clock */
23544 +
23545 +#endif
23546 + /* Make sure gpio0 and gpio5 are inputs */
23547 + outen = readl(&eir->gpio[0].outen);
23548 + outen &= ~(BCM47XX_PCMCIA_WP | BCM47XX_PCMCIA_STSCHG | BCM47XX_PCMCIA_RESET);
23549 + writel(outen, &eir->gpio[0].outen);
23550 +
23551 + /* Issue a reset to the pcmcia socket */
23552 + bcm4710_pcmcia_reset();
23553 +
23554 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23555 + /* Setup gpio5 to be the STSCHG interrupt */
23556 + intp = readl(&eir->gpiointpolarity);
23557 + writel(intp | BCM47XX_PCMCIA_STSCHG, &eir->gpiointpolarity); /* Active low */
23558 + intm = readl(&eir->gpiointmask);
23559 + writel(intm | BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Enable it */
23560 +#endif
23561 +
23562 + DEBUG(2, "bcm4710_pcmcia after reset:\n");
23563 + DEBUG(2, "\textstatus\t= 0x%08x:\n", readl(&eir->extstatus));
23564 + DEBUG(2, "\tpcmcia_config\t= 0x%08x:\n", readl(&eir->pcmcia_config));
23565 + DEBUG(2, "\tpcmcia_memwait\t= 0x%08x:\n", readl(&eir->pcmcia_memwait));
23566 + DEBUG(2, "\tpcmcia_attrwait\t= 0x%08x:\n", readl(&eir->pcmcia_attrwait));
23567 + DEBUG(2, "\tpcmcia_iowait\t= 0x%08x:\n", readl(&eir->pcmcia_iowait));
23568 + DEBUG(2, "\tgpioin\t\t= 0x%08x:\n", readl(&eir->gpioin));
23569 + DEBUG(2, "\tgpio_outen0\t= 0x%08x:\n", readl(&eir->gpio[0].outen));
23570 + DEBUG(2, "\tgpio_out0\t= 0x%08x:\n", readl(&eir->gpio[0].out));
23571 + DEBUG(2, "\tgpiointpolarity\t= 0x%08x:\n", readl(&eir->gpiointpolarity));
23572 + DEBUG(2, "\tgpiointmask\t= 0x%08x:\n", readl(&eir->gpiointmask));
23573 +
23574 +#ifdef DO_BCM47XX_PCMCIA_INTERRUPTS
23575 + /* Request pcmcia interrupt */
23576 + rc = request_irq(BCM47XX_PCMCIA_IRQ, init->handler, SA_INTERRUPT,
23577 + "PCMCIA Interrupt", &bcm47xx_pcmcia_dev_id);
23578 +#endif
23579 +
23580 + attrsp = (uint16 *)ioremap_nocache(EXTIF_PCMCIA_CFGBASE(BCM4710_EXTIF), 0x1000);
23581 + tmp = readw(&attrsp[0]);
23582 + DEBUG(2, "\tattr[0] = 0x%04x\n", tmp);
23583 + if ((tmp == 0x7fff) || (tmp == 0x7f00)) {
23584 + bcm47xx_pcmcia_present = 0;
23585 + } else {
23586 + bcm47xx_pcmcia_present = 1;
23587 + }
23588 +
23589 + /* There's only one socket */
23590 + return 1;
23591 +}
23592 +
23593 +static int bcm4710_pcmcia_shutdown(void)
23594 +{
23595 + extifregs_t *eir;
23596 + uint32 intm;
23597 +
23598 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23599 +
23600 + /* Disable the pcmcia i/f */
23601 + writel(0, &eir->pcmcia_config);
23602 +
23603 + /* Reset gpio's */
23604 + intm = readl(&eir->gpiointmask);
23605 + writel(intm & ~BCM47XX_PCMCIA_STSCHG, &eir->gpiointmask); /* Disable it */
23606 +
23607 + free_irq(BCM47XX_PCMCIA_IRQ, &bcm47xx_pcmcia_dev_id);
23608 +
23609 + return 0;
23610 +}
23611 +
23612 +static int
23613 +bcm4710_pcmcia_socket_state(unsigned sock, struct pcmcia_state *state)
23614 +{
23615 + extifregs_t *eir;
23616 +
23617 + eir = (extifregs_t *) ioremap_nocache(BCM4710_REG_EXTIF, sizeof(extifregs_t));
23618 +
23619 +
23620 + if (sock != 0) {
23621 + printk(KERN_ERR "bcm4710 socket_state bad sock %d\n", sock);
23622 + return -1;
23623 + }
23624 +
23625 + if (bcm47xx_pcmcia_present) {
23626 + state->detect = 1;
23627 + state->ready = 1;
23628 + state->bvd1 = 1;
23629 + state->bvd2 = 1;
23630 + state->wrprot = (readl(&eir->gpioin) & BCM47XX_PCMCIA_WP) == BCM47XX_PCMCIA_WP;
23631 + state->vs_3v = 0;
23632 + state->vs_Xv = 0;
23633 + } else {
23634 + state->detect = 0;
23635 + state->ready = 0;
23636 + }
23637 +
23638 + return 1;
23639 +}
23640 +
23641 +
23642 +static int bcm4710_pcmcia_get_irq_info(struct pcmcia_irq_info *info)
23643 +{
23644 + if (info->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23645 +
23646 + info->irq = BCM47XX_PCMCIA_IRQ;
23647 +
23648 + return 0;
23649 +}
23650 +
23651 +
23652 +static int
23653 +bcm4710_pcmcia_configure_socket(const struct pcmcia_configure *configure)
23654 +{
23655 + if (configure->sock >= BCM47XX_PCMCIA_MAX_SOCK) return -1;
23656 +
23657 +
23658 + DEBUG(2, "Vcc %dV Vpp %dV output %d speaker %d reset %d\n", configure->vcc,
23659 + configure->vpp, configure->output, configure->speaker, configure->reset);
23660 +
23661 + if ((configure->vcc != 50) || (configure->vpp != 50)) {
23662 + printk("%s: bad Vcc/Vpp (%d:%d)\n", __FUNCTION__, configure->vcc,
23663 + configure->vpp);
23664 + }
23665 +
23666 + if (configure->reset) {
23667 + /* Issue a reset to the pcmcia socket */
23668 + DEBUG(1, "%s: Reseting socket\n", __FUNCTION__);
23669 + bcm4710_pcmcia_reset();
23670 + }
23671 +
23672 +
23673 + return 0;
23674 +}
23675 +
23676 +struct pcmcia_low_level bcm4710_pcmcia_ops = {
23677 + bcm4710_pcmcia_init,
23678 + bcm4710_pcmcia_shutdown,
23679 + bcm4710_pcmcia_socket_state,
23680 + bcm4710_pcmcia_get_irq_info,
23681 + bcm4710_pcmcia_configure_socket
23682 +};
23683 +
23684 diff -urN linux.old/drivers/pcmcia/bcm4710pcmcia.h linux.dev/drivers/pcmcia/bcm4710pcmcia.h
23685 --- linux.old/drivers/pcmcia/bcm4710pcmcia.h 1970-01-01 01:00:00.000000000 +0100
23686 +++ linux.dev/drivers/pcmcia/bcm4710pcmcia.h 2005-11-07 21:57:07.945592000 +0100
23687 @@ -0,0 +1,118 @@
23688 +/*
23689 + *
23690 + * bcm47xx pcmcia driver
23691 + *
23692 + * Copyright 2004, Broadcom Corporation
23693 + * All Rights Reserved.
23694 + *
23695 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
23696 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
23697 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
23698 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
23699 + *
23700 + * Based on sa1100.h and include/asm-arm/arch-sa1100/pcmica.h
23701 + * from www.handhelds.org,
23702 + * and au1000_generic.c from oss.sgi.com.
23703 + *
23704 + * $Id: bcm4710pcmcia.h,v 1.1 2005/03/16 13:50:00 wbx Exp $
23705 + */
23706 +
23707 +#if !defined(_BCM4710PCMCIA_H)
23708 +#define _BCM4710PCMCIA_H
23709 +
23710 +#include <pcmcia/cs_types.h>
23711 +#include <pcmcia/ss.h>
23712 +#include <pcmcia/bulkmem.h>
23713 +#include <pcmcia/cistpl.h>
23714 +#include "cs_internal.h"
23715 +
23716 +
23717 +/* The 47xx can only support one socket */
23718 +#define BCM47XX_PCMCIA_MAX_SOCK 1
23719 +
23720 +/* In the bcm947xx gpio's are used for some pcmcia functions */
23721 +#define BCM47XX_PCMCIA_WP 0x01 /* Bit 0 is WP input */
23722 +#define BCM47XX_PCMCIA_STSCHG 0x20 /* Bit 5 is STSCHG input/interrupt */
23723 +#define BCM47XX_PCMCIA_RESET 0x80 /* Bit 7 is RESET */
23724 +
23725 +#define BCM47XX_PCMCIA_IRQ 2
23726 +
23727 +/* The socket driver actually works nicely in interrupt-driven form,
23728 + * so the (relatively infrequent) polling is "just to be sure."
23729 + */
23730 +#define BCM47XX_PCMCIA_POLL_PERIOD (2 * HZ)
23731 +
23732 +#define BCM47XX_PCMCIA_IO_SPEED (255)
23733 +#define BCM47XX_PCMCIA_MEM_SPEED (300)
23734 +
23735 +
23736 +struct pcmcia_state {
23737 + unsigned detect: 1,
23738 + ready: 1,
23739 + bvd1: 1,
23740 + bvd2: 1,
23741 + wrprot: 1,
23742 + vs_3v: 1,
23743 + vs_Xv: 1;
23744 +};
23745 +
23746 +
23747 +struct pcmcia_configure {
23748 + unsigned sock: 8,
23749 + vcc: 8,
23750 + vpp: 8,
23751 + output: 1,
23752 + speaker: 1,
23753 + reset: 1;
23754 +};
23755 +
23756 +struct pcmcia_irq_info {
23757 + unsigned int sock;
23758 + unsigned int irq;
23759 +};
23760 +
23761 +/* This structure encapsulates per-socket state which we might need to
23762 + * use when responding to a Card Services query of some kind.
23763 + */
23764 +struct bcm47xx_pcmcia_socket {
23765 + socket_state_t cs_state;
23766 + struct pcmcia_state k_state;
23767 + unsigned int irq;
23768 + void (*handler)(void *, unsigned int);
23769 + void *handler_info;
23770 + pccard_io_map io_map[MAX_IO_WIN];
23771 + pccard_mem_map mem_map[MAX_WIN];
23772 + ioaddr_t virt_io, phys_attr, phys_mem;
23773 + unsigned short speed_io, speed_attr, speed_mem;
23774 +};
23775 +
23776 +struct pcmcia_init {
23777 + void (*handler)(int irq, void *dev, struct pt_regs *regs);
23778 +};
23779 +
23780 +struct pcmcia_low_level {
23781 + int (*init)(struct pcmcia_init *);
23782 + int (*shutdown)(void);
23783 + int (*socket_state)(unsigned sock, struct pcmcia_state *);
23784 + int (*get_irq_info)(struct pcmcia_irq_info *);
23785 + int (*configure_socket)(const struct pcmcia_configure *);
23786 +};
23787 +
23788 +extern struct pcmcia_low_level bcm47xx_pcmcia_ops;
23789 +
23790 +/* I/O pins replacing memory pins
23791 + * (PCMCIA System Architecture, 2nd ed., by Don Anderson, p.75)
23792 + *
23793 + * These signals change meaning when going from memory-only to
23794 + * memory-or-I/O interface:
23795 + */
23796 +#define iostschg bvd1
23797 +#define iospkr bvd2
23798 +
23799 +
23800 +/*
23801 + * Declaration for implementation specific low_level operations.
23802 + */
23803 +extern struct pcmcia_low_level bcm4710_pcmcia_ops;
23804 +
23805 +#endif /* !defined(_BCM4710PCMCIA_H) */
23806 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
23807 --- linux.old/include/asm-mips/bootinfo.h 2005-11-07 23:12:51.434940250 +0100
23808 +++ linux.dev/include/asm-mips/bootinfo.h 2005-11-07 21:57:07.945592000 +0100
23809 @@ -37,6 +37,7 @@
23810 #define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
23811 #define MACH_GROUP_LASAT 21
23812 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
23813 +#define MACH_GROUP_BRCM 23 /* Broadcom */
23814
23815 /*
23816 * Valid machtype values for group unknown (low order halfword of mips_machtype)
23817 @@ -197,6 +198,15 @@
23818 #define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
23819
23820 /*
23821 + * Valid machtypes for group Broadcom
23822 + */
23823 +#define MACH_BCM93725 0
23824 +#define MACH_BCM93725_VJ 1
23825 +#define MACH_BCM93730 2
23826 +#define MACH_BCM947XX 3
23827 +#define MACH_BCM933XX 4
23828 +
23829 +/*
23830 * Valid machtype for group TITAN
23831 */
23832 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
23833 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
23834 --- linux.old/include/asm-mips/cpu.h 2005-11-07 23:12:51.434940250 +0100
23835 +++ linux.dev/include/asm-mips/cpu.h 2005-11-07 21:57:07.965593250 +0100
23836 @@ -22,6 +22,11 @@
23837 spec.
23838 */
23839
23840 +#define PRID_COPT_MASK 0xff000000
23841 +#define PRID_COMP_MASK 0x00ff0000
23842 +#define PRID_IMP_MASK 0x0000ff00
23843 +#define PRID_REV_MASK 0x000000ff
23844 +
23845 #define PRID_COMP_LEGACY 0x000000
23846 #define PRID_COMP_MIPS 0x010000
23847 #define PRID_COMP_BROADCOM 0x020000
23848 @@ -58,6 +63,7 @@
23849 #define PRID_IMP_RM7000 0x2700
23850 #define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
23851 #define PRID_IMP_RM9000 0x3400
23852 +#define PRID_IMP_BCM4710 0x4000
23853 #define PRID_IMP_R5432 0x5400
23854 #define PRID_IMP_R5500 0x5500
23855 #define PRID_IMP_4KC 0x8000
23856 @@ -66,10 +72,16 @@
23857 #define PRID_IMP_4KEC 0x8400
23858 #define PRID_IMP_4KSC 0x8600
23859 #define PRID_IMP_25KF 0x8800
23860 +#define PRID_IMP_BCM3302 0x9000
23861 +#define PRID_IMP_BCM3303 0x9100
23862 #define PRID_IMP_24K 0x9300
23863
23864 #define PRID_IMP_UNKNOWN 0xff00
23865
23866 +#define BCM330X(id) \
23867 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
23868 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
23869 +
23870 /*
23871 * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
23872 */
23873 @@ -174,7 +186,9 @@
23874 #define CPU_AU1550 57
23875 #define CPU_24K 58
23876 #define CPU_AU1200 59
23877 -#define CPU_LAST 59
23878 +#define CPU_BCM4710 60
23879 +#define CPU_BCM3302 61
23880 +#define CPU_LAST 61
23881
23882 /*
23883 * ISA Level encodings
23884 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
23885 --- linux.old/include/asm-mips/r4kcache.h 2005-11-07 23:12:51.438940500 +0100
23886 +++ linux.dev/include/asm-mips/r4kcache.h 2005-11-07 21:57:08.161605500 +0100
23887 @@ -658,4 +658,17 @@
23888 cache128_unroll32(addr|ws,Index_Writeback_Inv_SD);
23889 }
23890
23891 +extern inline void fill_icache_line(unsigned long addr)
23892 +{
23893 + __asm__ __volatile__(
23894 + ".set noreorder\n\t"
23895 + ".set mips3\n\t"
23896 + "cache %1, (%0)\n\t"
23897 + ".set mips0\n\t"
23898 + ".set reorder"
23899 + :
23900 + : "r" (addr),
23901 + "i" (Fill));
23902 +}
23903 +
23904 #endif /* __ASM_R4KCACHE_H */
23905 diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h
23906 --- linux.old/include/asm-mips/serial.h 2005-11-07 23:12:51.442940750 +0100
23907 +++ linux.dev/include/asm-mips/serial.h 2005-11-07 21:57:07.993595000 +0100
23908 @@ -223,6 +223,13 @@
23909 #define TXX927_SERIAL_PORT_DEFNS
23910 #endif
23911
23912 +#ifdef CONFIG_BCM947XX
23913 +/* reserve 4 ports to be configured at runtime */
23914 +#define BCM947XX_SERIAL_PORT_DEFNS { 0, }, { 0, }, { 0, }, { 0, },
23915 +#else
23916 +#define BCM947XX_SERIAL_PORT_DEFNS
23917 +#endif
23918 +
23919 #ifdef CONFIG_HAVE_STD_PC_SERIAL_PORT
23920 #define STD_SERIAL_PORT_DEFNS \
23921 /* UART CLK PORT IRQ FLAGS */ \
23922 @@ -470,6 +477,7 @@
23923 #define SERIAL_PORT_DFNS \
23924 ATLAS_SERIAL_PORT_DEFNS \
23925 AU1000_SERIAL_PORT_DEFNS \
23926 + BCM947XX_SERIAL_PORT_DEFNS \
23927 COBALT_SERIAL_PORT_DEFNS \
23928 DDB5477_SERIAL_PORT_DEFNS \
23929 EV96100_SERIAL_PORT_DEFNS \
23930 diff -urN linux.old/init/do_mounts.c linux.dev/init/do_mounts.c
23931 --- linux.old/init/do_mounts.c 2005-11-07 23:12:51.458941750 +0100
23932 +++ linux.dev/init/do_mounts.c 2005-11-07 21:57:07.993595000 +0100
23933 @@ -254,7 +254,13 @@
23934 { "ftlb", 0x2c08 },
23935 { "ftlc", 0x2c10 },
23936 { "ftld", 0x2c18 },
23937 +#if defined(CONFIG_MTD_BLOCK) || defined(CONFIG_MTD_BLOCK_RO)
23938 { "mtdblock", 0x1f00 },
23939 + { "mtdblock0",0x1f00 },
23940 + { "mtdblock1",0x1f01 },
23941 + { "mtdblock2",0x1f02 },
23942 + { "mtdblock3",0x1f03 },
23943 +#endif
23944 { "nb", 0x2b00 },
23945 { NULL, 0 }
23946 };
Personal OpenWRT clone
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