openwrt/target/linux/brcm-2.4/patches/008-b44_bcm47xx_support.patch

   1 diff -urN linux.old/drivers/net/b44.c linux.dev/drivers/net/b44.c
   2 --- linux.old/drivers/net/b44.c 2006-01-12 17:27:45.920623500 +0100
   3 +++ linux.dev/drivers/net/b44.c 2006-01-13 13:29:18.782391750 +0100
   4 @@ -1,7 +1,9 @@
   5  /* b44.c: Broadcom 4400 device driver.
   6   *
   7   * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   8 - * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   9 + * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
  10 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
  11 + * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
  12   *
  13   * Distribute under GPL.
  14   */
  15 @@ -25,6 +27,41 @@
  16
  17  #include "b44.h"
  18
  19 +#include <typedefs.h>
  20 +#include <bcmdevs.h>
  21 +#include <bcmutils.h>
  22 +#include <osl.h>
  23 +#include <bcmutils.h>
  24 +#include <bcmnvram.h>
  25 +#include <sbconfig.h>
  26 +#include <sbchipc.h>
  27 +#include <sflash.h>
  28 +
  29 +#ifdef CONFIG_BCM947XX
  30 +#define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
  31 +
  32 +static inline void e_aton(char *str, char *dest)
  33 +{
  34 +       int i = 0;
  35 +       u16 *d = (u16 *) dest;
  36 +
  37 +       if (str == NULL) {
  38 +               memset(dest, 0, 6);
  39 +               return;
  40 +       }
  41 +
  42 +       for (;;) {
  43 +               dest[i++] = (char) simple_strtoul(str, NULL, 16);
  44 +               str += 2;
  45 +               if (!*str++ || i == 6)
  46 +                       break;
  47 +       }
  48 +}
  49 +
  50 +static int instance = 0;
  51 +#endif
  52 +
  53 +
  54  #define DRV_MODULE_NAME                "b44"
  55  #define PFX DRV_MODULE_NAME    ": "
  56  #define DRV_MODULE_VERSION     "0.93"
  57 @@ -75,7 +112,7 @@
  58         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  59
  60  MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
  61 -MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  62 +MODULE_DESCRIPTION("Broadcom 4400/47xx 10/100 PCI ethernet driver");
  63  MODULE_LICENSE("GPL");
  64  MODULE_PARM(b44_debug, "i");
  65  MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  66 @@ -89,6 +126,8 @@
  67           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  68         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  69           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  70 +       { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4713,
  71 +         PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  72         { }     /* terminate list with empty entry */
  73  };
  74
  75 @@ -236,6 +275,8 @@
  76         udelay(1);
  77  }
  78
  79 +static int b44_4713_instance;
  80 +
  81  static int ssb_core_unit(struct b44 *bp)
  82  {
  83  #if 0
  84 @@ -258,6 +299,9 @@
  85                 break;
  86         };
  87  #endif
  88 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
  89 +               return b44_4713_instance++;
  90 +       else
  91         return 0;
  92  }
  93
  94 @@ -267,6 +311,28 @@
  95                 == SBTMSLOW_CLOCK);
  96  }
  97
  98 +static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
  99 +{
 100 +       u32 val;
 101 +
 102 +       bw32(B44_CAM_CTRL, (CAM_CTRL_READ |
 103 +                           (index << CAM_CTRL_INDEX_SHIFT)));
 104 +
 105 +       b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 106 +
 107 +       val = br32(B44_CAM_DATA_LO);
 108 +
 109 +       data[2] = (val >> 24) & 0xFF;
 110 +       data[3] = (val >> 16) & 0xFF;
 111 +       data[4] = (val >> 8) & 0xFF;
 112 +       data[5] = (val >> 0) & 0xFF;
 113 +
 114 +       val = br32(B44_CAM_DATA_HI);
 115 +
 116 +       data[0] = (val >> 8) & 0xFF;
 117 +       data[1] = (val >> 0) & 0xFF;
 118 +}
 119 +
 120  static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 121  {
 122         u32 val;
 123 @@ -303,14 +369,14 @@
 124         bw32(B44_IMASK, bp->imask);
 125  }
 126
 127 -static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 128 +static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
 129  {
 130         int err;
 131
 132         bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 133         bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 134                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 135 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 136 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 137                              (reg << MDIO_DATA_RA_SHIFT) |
 138                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 139         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 140 @@ -319,23 +385,42 @@
 141         return err;
 142  }
 143
 144 -static int b44_writephy(struct b44 *bp, int reg, u32 val)
 145 +static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 146 +{
 147 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 148 +               return 0;
 149 +
 150 +       return __b44_readphy(bp, bp->phy_addr, reg, val);
 151 +}
 152 +
 153 +static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
 154  {
 155         bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 156         bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 157                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 158 -                            (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 159 +                            (phy_addr << MDIO_DATA_PMD_SHIFT) |
 160                              (reg << MDIO_DATA_RA_SHIFT) |
 161                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 162                              (val & MDIO_DATA_DATA)));
 163         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 164  }
 165
 166 +static int b44_writephy(struct b44 *bp, int reg, u32 val)
 167 +{
 168 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 169 +               return 0;
 170 +
 171 +       return __b44_writephy(bp, bp->phy_addr, reg, val);
 172 +}
 173 +
 174  static int b44_phy_reset(struct b44 *bp)
 175  {
 176         u32 val;
 177         int err;
 178
 179 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 180 +               return 0;
 181 +
 182         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 183         if (err)
 184                 return err;
 185 @@ -405,6 +490,18 @@
 186  {
 187         u32 val;
 188         int err;
 189 +       char *s;
 190 +
 191 +       if ((s = nvram_get("boardnum")) && (s != NULL) && \
 192 +                       !strncmp(s, "2", 1) && \
 193 +                       (__b44_readphy(bp, 0, MII_BMCR, &val) != 0) && \
 194 +                       (val & BMCR_ISOLATE) && \
 195 +                       (__b44_writephy(bp, 0, MII_BMCR, val & ~BMCR_ISOLATE) != 0)) {
 196 +               printk(KERN_WARNING PFX "PHY: cannot reset MII transceiver isolate bit.\n");
 197 +       }
 198 +
 199 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY)
 200 +               return 0;
 201
 202         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 203                 goto out;
 204 @@ -498,6 +595,19 @@
 205  {
 206         u32 bmsr, aux;
 207
 208 +       if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
 209 +               bp->flags |= B44_FLAG_100_BASE_T;
 210 +               bp->flags |= B44_FLAG_FULL_DUPLEX;
 211 +               if (!netif_carrier_ok(bp->dev)) {
 212 +                       u32 val = br32(B44_TX_CTRL);
 213 +                       val |= TX_CTRL_DUPLEX;
 214 +                       bw32(B44_TX_CTRL, val);
 215 +                       netif_carrier_on(bp->dev);
 216 +                       b44_link_report(bp);
 217 +               }
 218 +               return;
 219 +       }
 220 +
 221         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 222             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 223             (bmsr != 0xffff)) {
 224 @@ -1092,6 +1202,8 @@
 225  /* bp->lock is held. */
 226  static void b44_chip_reset(struct b44 *bp)
 227  {
 228 +       unsigned int sb_clock;
 229 +
 230         if (ssb_is_core_up(bp)) {
 231                 bw32(B44_RCV_LAZY, 0);
 232                 bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
 233 @@ -1105,9 +1217,10 @@
 234                 bw32(B44_DMARX_CTRL, 0);
 235                 bp->rx_prod = bp->rx_cons = 0;
 236         } else {
 237 -               ssb_pci_setup(bp, (bp->core_unit == 0 ?
 238 -                                  SBINTVEC_ENET0 :
 239 -                                  SBINTVEC_ENET1));
 240 +               /*if (bp->pdev->device != PCI_DEVICE_ID_BCM4713)*/
 241 +                       ssb_pci_setup(bp, (bp->core_unit == 0 ?
 242 +                                       SBINTVEC_ENET0 :
 243 +                                       SBINTVEC_ENET1));
 244         }
 245
 246         ssb_core_reset(bp);
 247 @@ -1115,6 +1228,11 @@
 248         b44_clear_stats(bp);
 249
 250         /* Make PHY accessible. */
 251 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713)
 252 +               sb_clock = 100000000; /* 100 MHz */
 253 +       else
 254 +               sb_clock = 62500000; /* 62.5 MHz */
 255 +
 256         bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
 257                              (0x0d & MDIO_CTRL_MAXF_MASK)));
 258         br32(B44_MDIO_CTRL);
 259 @@ -1628,7 +1746,7 @@
 260                 u32 mii_regval;
 261
 262                 spin_lock_irq(&bp->lock);
 263 -               err = b44_readphy(bp, data->reg_num & 0x1f, &mii_regval);
 264 +               err = __b44_readphy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, &mii_regval);
 265                 spin_unlock_irq(&bp->lock);
 266
 267                 data->val_out = mii_regval;
 268 @@ -1641,7 +1759,7 @@
 269                         return -EPERM;
 270
 271                 spin_lock_irq(&bp->lock);
 272 -               err = b44_writephy(bp, data->reg_num & 0x1f, data->val_in);
 273 +               err = __b44_writephy(bp, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
 274                 spin_unlock_irq(&bp->lock);
 275
 276                 return err;
 277 @@ -1668,21 +1786,52 @@
 278  static int __devinit b44_get_invariants(struct b44 *bp)
 279  {
 280         u8 eeprom[128];
 281 +       u8 buf[32];
 282         int err;
 283 +       unsigned long flags;
 284
 285 -       err = b44_read_eeprom(bp, &eeprom[0]);
 286 -       if (err)
 287 -               goto out;
 288 -
 289 -       bp->dev->dev_addr[0] = eeprom[79];
 290 -       bp->dev->dev_addr[1] = eeprom[78];
 291 -       bp->dev->dev_addr[2] = eeprom[81];
 292 -       bp->dev->dev_addr[3] = eeprom[80];
 293 -       bp->dev->dev_addr[4] = eeprom[83];
 294 -       bp->dev->dev_addr[5] = eeprom[82];
 295 -
 296 -       bp->phy_addr = eeprom[90] & 0x1f;
 297 -       bp->mdc_port = (eeprom[90] >> 14) & 0x1;
 298 +       if (bp->pdev->device == PCI_DEVICE_ID_BCM4713) {
 299 +#ifdef CONFIG_BCM947XX
 300 +               sprintf(buf, "et%dmacaddr", instance - 1);
 301 +               e_aton(nvram_get(buf), bp->dev->dev_addr);
 302 +
 303 +               sprintf(buf, "et%dphyaddr", instance - 1);
 304 +               bp->phy_addr = B44_PHY_ADDR_NO_PHY;
 305 +#else
 306 +               /*
 307 +                * BCM47xx boards don't have a EEPROM. The MAC is stored in
 308 +                * a NVRAM area somewhere in the flash memory. As we don't
 309 +                * know the location and/or the format of the NVRAM area
 310 +                * here, we simply rely on the bootloader to write the
 311 +                * MAC into the CAM.
 312 +                */
 313 +               spin_lock_irqsave(&bp->lock, flags);
 314 +               __b44_cam_read(bp, bp->dev->dev_addr, 0);
 315 +               spin_unlock_irqrestore(&bp->lock, flags);
 316 +
 317 +               /*
 318 +                * BCM47xx boards don't have a PHY. Usually there is a switch
 319 +                * chip with multiple PHYs connected to the PHY port.
 320 +                */
 321 +               bp->phy_addr = B44_PHY_ADDR_NO_PHY;
 322 +#endif
 323 +               bp->dma_offset = 0;
 324 +       } else {
 325 +               err = b44_read_eeprom(bp, &eeprom[0]);
 326 +               if (err)
 327 +                       return err;
 328 +
 329 +               bp->dev->dev_addr[0] = eeprom[79];
 330 +               bp->dev->dev_addr[1] = eeprom[78];
 331 +               bp->dev->dev_addr[2] = eeprom[81];
 332 +               bp->dev->dev_addr[3] = eeprom[80];
 333 +               bp->dev->dev_addr[4] = eeprom[83];
 334 +               bp->dev->dev_addr[5] = eeprom[82];
 335 +
 336 +               bp->phy_addr = eeprom[90] & 0x1f;
 337 +               bp->dma_offset = SB_PCI_DMA;
 338 +               bp->mdc_port = (eeprom[90] >> 14) & 0x1;
 339 +       }
 340
 341         /* With this, plus the rx_header prepended to the data by the
 342          * hardware, we'll land the ethernet header on a 2-byte boundary.
 343 @@ -1692,13 +1841,12 @@
 344         bp->imask = IMASK_DEF;
 345
 346         bp->core_unit = ssb_core_unit(bp);
 347 -       bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
 348
 349         /* XXX - really required?
 350            bp->flags |= B44_FLAG_BUGGY_TXPTR;
 351           */
 352 -out:
 353 -       return err;
 354 +
 355 +       return 0;
 356  }
 357
 358  static int __devinit b44_init_one(struct pci_dev *pdev,
 359 @@ -1710,6 +1858,10 @@
 360         struct b44 *bp;
 361         int err, i;
 362
 363 +#ifdef CONFIG_BCM947XX
 364 +       instance++;
 365 +#endif
 366 +
 367         if (b44_version_printed++ == 0)
 368                 printk(KERN_INFO "%s", version);
 369
 370 @@ -1819,11 +1971,17 @@
 371
 372         pci_save_state(bp->pdev, bp->pci_cfg_state);
 373
 374 -       printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
 375 +       printk(KERN_INFO "%s: Broadcom %s 10/100BaseT Ethernet ", dev->name,
 376 +               (pdev->device == PCI_DEVICE_ID_BCM4713) ? "47xx" : "4400");
 377         for (i = 0; i < 6; i++)
 378                 printk("%2.2x%c", dev->dev_addr[i],
 379                        i == 5 ? '\n' : ':');
 380
 381 +       /* Initialize phy */
 382 +       spin_lock_irq(&bp->lock);
 383 +       b44_chip_reset(bp);
 384 +       spin_unlock_irq(&bp->lock);
 385 +
 386         return 0;
 387
 388  err_out_iounmap:
 389 diff -urN linux.old/drivers/net/b44.h linux.dev/drivers/net/b44.h
 390 --- linux.old/drivers/net/b44.h 2006-01-12 17:26:13.234831000 +0100
 391 +++ linux.dev/drivers/net/b44.h 2006-01-12 17:22:01.043070000 +0100
 392 @@ -229,8 +229,6 @@
 393  #define  SBIPSFLAG_IMASK4      0x3f000000 /* Which sbflags --> mips interrupt 4 */
 394  #define  SBIPSFLAG_ISHIFT4     24
 395  #define B44_SBTPSFLAG  0x0F18UL /* SB Target Port OCP Slave Flag */
 396 -#define  SBTPS_NUM0_MASK       0x0000003f
 397 -#define  SBTPS_F0EN0           0x00000040
 398  #define B44_SBADMATCH3 0x0F60UL /* SB Address Match 3 */
 399  #define B44_SBADMATCH2 0x0F68UL /* SB Address Match 2 */
 400  #define B44_SBADMATCH1 0x0F70UL /* SB Address Match 1 */
 401 @@ -461,6 +459,8 @@
 402  };
 403
 404  #define B44_MCAST_TABLE_SIZE   32
 405 +#define B44_PHY_ADDR_NO_PHY    30
 406 +#define B44_MDC_RATIO          5000000
 407
 408  /* SW copy of device statistics, kept up to date by periodic timer
 409   * which probes HW values.  Must have same relative layout as HW
 410 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
 411 --- linux.old/include/linux/pci_ids.h   2006-01-12 17:26:13.250832000 +0100
 412 +++ linux.dev/include/linux/pci_ids.h   2006-01-12 17:22:01.071071750 +0100
 413 @@ -1735,6 +1735,7 @@
 414  #define PCI_DEVICE_ID_TIGON3_5901_2    0x170e
 415  #define PCI_DEVICE_ID_BCM4401          0x4401
 416  #define PCI_DEVICE_ID_BCM4401B0                0x4402
 417 +#define PCI_DEVICE_ID_BCM4713          0x4713
 418
 419  #define PCI_VENDOR_ID_ENE              0x1524
 420  #define PCI_DEVICE_ID_ENE_1211         0x1211