package/rt2x00/src/rt2x00reg.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2x00
  23         Abstract: rt2x00 generic register information.
  24  */
  25
  26 #ifndef RT2X00REG_H
  27 #define RT2X00REG_H
  28
  29 /*
  30  * TX result flags.
  31  */
  32 enum TX_STATUS {
  33         TX_SUCCESS = 0,
  34         TX_SUCCESS_RETRY = 1,
  35         TX_FAIL_RETRY = 2,
  36         TX_FAIL_INVALID = 3,
  37         TX_FAIL_OTHER = 4,
  38 };
  39
  40 /*
  41  * Antenna values
  42  */
  43 enum antenna {
  44         ANTENNA_SW_DIVERSITY = 0,
  45         ANTENNA_A = 1,
  46         ANTENNA_B = 2,
  47         ANTENNA_HW_DIVERSITY = 3,
  48 };
  49
  50 /*
  51  * Led mode values.
  52  */
  53 enum led_mode {
  54         LED_MODE_DEFAULT = 0,
  55         LED_MODE_TXRX_ACTIVITY = 1,
  56         LED_MODE_SIGNAL_STRENGTH = 2,
  57         LED_MODE_ASUS = 3,
  58         LED_MODE_ALPHA = 4,
  59 };
  60
  61 /*
  62  * TSF sync values
  63  */
  64 enum tsf_sync {
  65         TSF_SYNC_NONE = 0,
  66         TSF_SYNC_INFRA = 1,
  67         TSF_SYNC_BEACON = 2,
  68 };
  69
  70 /*
  71  * Device states
  72  */
  73 enum dev_state {
  74         STATE_DEEP_SLEEP = 0,
  75         STATE_SLEEP = 1,
  76         STATE_STANDBY = 2,
  77         STATE_AWAKE = 3,
  78
  79 /*
  80  * Additional device states, these values are
  81  * not strict since they are not directly passed
  82  * into the device.
  83  */
  84         STATE_RADIO_ON,
  85         STATE_RADIO_OFF,
  86         STATE_RADIO_RX_ON,
  87         STATE_RADIO_RX_OFF,
  88         STATE_RADIO_IRQ_ON,
  89         STATE_RADIO_IRQ_OFF,
  90 };
  91
  92 /*
  93  * IFS backoff values
  94  */
  95 enum ifs {
  96         IFS_BACKOFF = 0,
  97         IFS_SIFS = 1,
  98         IFS_NEW_BACKOFF = 2,
  99         IFS_NONE = 3,
 100 };
 101
 102 /*
 103  * Cipher types for hardware encryption
 104  */
 105 enum cipher {
 106         CIPHER_NONE = 0,
 107         CIPHER_WEP64 = 1,
 108         CIPHER_WEP128 = 2,
 109         CIPHER_TKIP = 3,
 110         CIPHER_AES = 4,
 111 /*
 112  * The following fields were added by rt61pci and rt73usb.
 113  */
 114         CIPHER_CKIP64 = 5,
 115         CIPHER_CKIP128 = 6,
 116         CIPHER_TKIP_NO_MIC = 7,
 117 };
 118
 119 /*
 120  * Register handlers.
 121  * We store the position of a register field inside a field structure,
 122  * This will simplify the process of setting and reading a certain field
 123  * inside the register while making sure the process remains byte order safe.
 124  */
 125 struct rt2x00_field8 {
 126         u8 bit_offset;
 127         u8 bit_mask;
 128 };
 129
 130 struct rt2x00_field16 {
 131         u16 bit_offset;
 132         u16 bit_mask;
 133 };
 134
 135 struct rt2x00_field32 {
 136         u32 bit_offset;
 137         u32 bit_mask;
 138 };
 139
 140 /*
 141  * Power of two check, this will check
 142  * if the mask that has been given contains
 143  * and contiguous set of bits.
 144  */
 145 #define is_power_of_two(x)      ( !((x) & ((x)-1)) )
 146 #define low_bit_mask(x)         ( ((x)-1) & ~(x) )
 147 #define is_valid_mask(x)        is_power_of_two(1 + (x) + low_bit_mask(x))
 148
 149 #define FIELD8(__mask)                          \
 150 ({                                              \
 151         BUILD_BUG_ON(!(__mask) ||               \
 152                      !is_valid_mask(__mask) ||  \
 153                      (__mask) != (u8)(__mask)); \
 154         (struct rt2x00_field8) {                \
 155                 __ffs(__mask), (__mask)         \
 156         };                                      \
 157 })
 158
 159 #define FIELD16(__mask)                         \
 160 ({                                              \
 161         BUILD_BUG_ON(!(__mask) ||               \
 162                      !is_valid_mask(__mask) ||  \
 163                      (__mask) != (u16)(__mask));\
 164         (struct rt2x00_field16) {               \
 165                 __ffs(__mask), (__mask)         \
 166         };                                      \
 167 })
 168
 169 #define FIELD32(__mask)                         \
 170 ({                                              \
 171         BUILD_BUG_ON(!(__mask) ||               \
 172                      !is_valid_mask(__mask) ||  \
 173                      (__mask) != (u32)(__mask));\
 174         (struct rt2x00_field32) {               \
 175                 __ffs(__mask), (__mask)         \
 176         };                                      \
 177 })
 178
 179 static inline void rt2x00_set_field32(u32 *reg,
 180                                       const struct rt2x00_field32 field,
 181                                       const u32 value)
 182 {
 183         *reg &= ~(field.bit_mask);
 184         *reg |= (value << field.bit_offset) & field.bit_mask;
 185 }
 186
 187 static inline u32 rt2x00_get_field32(const u32 reg,
 188                                      const struct rt2x00_field32 field)
 189 {
 190         return (reg & field.bit_mask) >> field.bit_offset;
 191 }
 192
 193 static inline void rt2x00_set_field16(u16 *reg,
 194                                       const struct rt2x00_field16 field,
 195                                       const u16 value)
 196 {
 197         *reg &= ~(field.bit_mask);
 198         *reg |= (value << field.bit_offset) & field.bit_mask;
 199 }
 200
 201 static inline u16 rt2x00_get_field16(const u16 reg,
 202                                      const struct rt2x00_field16 field)
 203 {
 204         return (reg & field.bit_mask) >> field.bit_offset;
 205 }
 206
 207 static inline void rt2x00_set_field8(u8 *reg,
 208                                      const struct rt2x00_field8 field,
 209                                      const u8 value)
 210 {
 211         *reg &= ~(field.bit_mask);
 212         *reg |= (value << field.bit_offset) & field.bit_mask;
 213 }
 214
 215 static inline u8 rt2x00_get_field8(const u8 reg,
 216                                    const struct rt2x00_field8 field)
 217 {
 218         return (reg & field.bit_mask) >> field.bit_offset;
 219 }
 220
 221 /*
 222  * Device specific rate value.
 223  * We will have to create the device specific rate value
 224  * passed to the ieee80211 kernel. We need to make it a consist of
 225  * multiple fields because we want to store more then 1 device specific
 226  * values inside the value.
 227  *      1 - rate, stored as 100 kbit/s.
 228  *      2 - preamble, short_preamble enabled flag.
 229  *      3 - MASK_RATE, which rates are enabled in this mode, this mask
 230  *      corresponds with the TX register format for the current device.
 231  *      4 - plcp, 802.11b rates are device specific,
 232  *      802.11g rates are set according to the ieee802.11a-1999 p.14.
 233  * The bit to enable preamble is set in a seperate define.
 234  */
 235 #define DEV_RATE        FIELD32(0x000007ff)
 236 #define DEV_PREAMBLE    FIELD32(0x00000800)
 237 #define DEV_RATEMASK    FIELD32(0x00fff000)
 238 #define DEV_PLCP        FIELD32(0xff000000)
 239
 240 /*
 241  * Bitfields
 242  */
 243 #define DEV_RATEBIT_1MB         ( 1 << 0 )
 244 #define DEV_RATEBIT_2MB         ( 1 << 1 )
 245 #define DEV_RATEBIT_5_5MB       ( 1 << 2 )
 246 #define DEV_RATEBIT_11MB        ( 1 << 3 )
 247 #define DEV_RATEBIT_6MB         ( 1 << 4 )
 248 #define DEV_RATEBIT_9MB         ( 1 << 5 )
 249 #define DEV_RATEBIT_12MB        ( 1 << 6 )
 250 #define DEV_RATEBIT_18MB        ( 1 << 7 )
 251 #define DEV_RATEBIT_24MB        ( 1 << 8 )
 252 #define DEV_RATEBIT_36MB        ( 1 << 9 )
 253 #define DEV_RATEBIT_48MB        ( 1 << 10 )
 254 #define DEV_RATEBIT_54MB        ( 1 << 11 )
 255
 256 /*
 257  * Bitmasks for DEV_RATEMASK
 258  */
 259 #define DEV_RATEMASK_1MB        ( (DEV_RATEBIT_1MB << 1) -1 )
 260 #define DEV_RATEMASK_2MB        ( (DEV_RATEBIT_2MB << 1) -1 )
 261 #define DEV_RATEMASK_5_5MB      ( (DEV_RATEBIT_5_5MB << 1) -1 )
 262 #define DEV_RATEMASK_11MB       ( (DEV_RATEBIT_11MB << 1) -1 )
 263 #define DEV_RATEMASK_6MB        ( (DEV_RATEBIT_6MB << 1) -1 )
 264 #define DEV_RATEMASK_9MB        ( (DEV_RATEBIT_9MB << 1) -1 )
 265 #define DEV_RATEMASK_12MB       ( (DEV_RATEBIT_12MB << 1) -1 )
 266 #define DEV_RATEMASK_18MB       ( (DEV_RATEBIT_18MB << 1) -1 )
 267 #define DEV_RATEMASK_24MB       ( (DEV_RATEBIT_24MB << 1) -1 )
 268 #define DEV_RATEMASK_36MB       ( (DEV_RATEBIT_36MB << 1) -1 )
 269 #define DEV_RATEMASK_48MB       ( (DEV_RATEBIT_48MB << 1) -1 )
 270 #define DEV_RATEMASK_54MB       ( (DEV_RATEBIT_54MB << 1) -1 )
 271
 272 /*
 273  * Bitmask groups of bitrates
 274  */
 275 #define DEV_BASIC_RATEMASK \
 276         ( DEV_RATEMASK_11MB | \
 277           DEV_RATEBIT_6MB | DEV_RATEBIT_12MB | DEV_RATEBIT_24MB )
 278
 279 #define DEV_CCK_RATEMASK        ( DEV_RATEMASK_11MB )
 280 #define DEV_OFDM_RATEMASK       ( DEV_RATEMASK_54MB & ~DEV_CCK_RATEMASK )
 281
 282 /*
 283  * Macro's to set and get specific fields from the device specific val and val2
 284  * fields inside the ieee80211_rate entry.
 285  */
 286 #define DEVICE_SET_RATE_FIELD(__value, __mask) \
 287         (int)( ((__value) << DEV_##__mask.bit_offset) & DEV_##__mask.bit_mask )
 288
 289 #define DEVICE_GET_RATE_FIELD(__value, __mask) \
 290         (int)( ((__value) & DEV_##__mask.bit_mask) >> DEV_##__mask.bit_offset )
 291
 292 #endif /* RT2X00REG_H */