1 /* Smedia Glamo 336x/337x driver
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/workqueue.h>
36 #include <linux/wait.h>
37 #include <linux/platform_device.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/spinlock.h>
40 #include <linux/glamofb.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/host.h>
43 #include <linux/mfd/core.h>
46 #include <asm/uaccess.h>
47 #include <asm/div64.h>
53 #include "glamo-regs.h"
54 #include "glamo-core.h"
56 #define GLAMO_MEM_REFRESH_COUNT 0x100
59 * Glamo internal settings
61 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
62 * above. Couple of GTA02 users report trouble with memory bus when they
63 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
64 * scheme if their Glamo chip needs it.
66 * you can override the faster default on kernel commandline using
68 * glamo3362.slow_memory=1
73 static int slow_memory
= 0;
74 module_param(slow_memory
, int, 0644);
82 struct reg_range reg_range
[] = {
83 { 0x0000, 0x76, "General", 1 },
84 { 0x0200, 0x16, "Host Bus", 1 },
85 { 0x0300, 0x38, "Memory", 1 },
86 /* { 0x0400, 0x100, "Sensor", 0 }, */
87 /* { 0x0500, 0x300, "ISP", 0 }, */
88 /* { 0x0800, 0x400, "JPEG", 0 }, */
89 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
90 { 0x1100, 0xb2, "LCD 1", 1 },
91 { 0x1200, 0x64, "LCD 2", 1 },
92 { 0x1400, 0x40, "MMC", 1 },
93 /* { 0x1500, 0x080, "MPU 0", 0 },
94 { 0x1580, 0x080, "MPU 1", 0 },
95 { 0x1600, 0x080, "Cmd Queue", 0 },
96 { 0x1680, 0x080, "RISC CPU", 0 },
97 { 0x1700, 0x400, "2D Unit", 0 },
98 { 0x1b00, 0x900, "3D Unit", 0 }, */
101 static struct glamo_core
*glamo_handle
;
103 static inline void __reg_write(struct glamo_core
*glamo
,
104 u_int16_t reg
, u_int16_t val
)
106 writew(val
, glamo
->base
+ reg
);
109 static inline u_int16_t
__reg_read(struct glamo_core
*glamo
,
112 return readw(glamo
->base
+ reg
);
115 static void __reg_set_bit_mask(struct glamo_core
*glamo
,
116 u_int16_t reg
, u_int16_t mask
,
123 tmp
= __reg_read(glamo
, reg
);
126 __reg_write(glamo
, reg
, tmp
);
129 static void reg_set_bit_mask(struct glamo_core
*glamo
,
130 u_int16_t reg
, u_int16_t mask
,
133 spin_lock(&glamo
->lock
);
134 __reg_set_bit_mask(glamo
, reg
, mask
, val
);
135 spin_unlock(&glamo
->lock
);
138 static inline void __reg_set_bit(struct glamo_core
*glamo
,
139 u_int16_t reg
, u_int16_t bit
)
141 __reg_set_bit_mask(glamo
, reg
, bit
, 0xffff);
144 static inline void __reg_clear_bit(struct glamo_core
*glamo
,
145 u_int16_t reg
, u_int16_t bit
)
147 __reg_set_bit_mask(glamo
, reg
, bit
, 0);
150 /***********************************************************************
151 * resources of sibling devices
152 ***********************************************************************/
154 static struct resource glamo_fb_resources
[] = {
156 .name
= "glamo-fb-regs",
157 .start
= GLAMO_REGOFS_LCD
,
158 .end
= GLAMO_REGOFS_MMC
- 1,
159 .flags
= IORESOURCE_MEM
,
161 .name
= "glamo-fb-mem",
162 .start
= GLAMO_OFFSET_FB
,
163 .end
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
- 1,
164 .flags
= IORESOURCE_MEM
,
168 static struct resource glamo_mmc_resources
[] = {
170 .start
= GLAMO_REGOFS_MMC
,
171 .end
= GLAMO_REGOFS_MPROC0
- 1,
172 .flags
= IORESOURCE_MEM
174 .start
= IRQ_GLAMO_MMC
,
175 .end
= IRQ_GLAMO_MMC
,
176 .flags
= IORESOURCE_IRQ
,
177 }, { /* our data buffer for MMC transfers */
178 .start
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
,
179 .end
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
+
180 GLAMO_MMC_BUFFER_SIZE
- 1,
181 .flags
= IORESOURCE_MEM
185 static struct glamo_mci_pdata glamo_mci_def_pdata
= {
187 .glamo_can_set_mci_power
= NULL
, /* filled in from MFD platform data */
188 .glamo_irq_is_wired
= NULL
, /* filled in from MFD platform data */
189 .mci_suspending
= NULL
, /* filled in from MFD platform data */
190 .mci_all_dependencies_resumed
= NULL
, /* filled in from MFD platform data */
199 static struct mfd_cell glamo_cells
[] = {
202 .num_resources
= ARRAY_SIZE(glamo_fb_resources
),
203 .resources
= glamo_fb_resources
,
207 .num_resources
= ARRAY_SIZE(glamo_mmc_resources
),
208 .resources
= glamo_mmc_resources
,
210 [GLAMO_CELL_SPI_GPIO
] = {
211 .name
= "glamo-spi-gpio",
216 /***********************************************************************
218 ***********************************************************************/
219 #define irq2glamo(x) (x - IRQ_GLAMO(0))
221 static void glamo_ack_irq(unsigned int irq
)
223 /* clear interrupt source */
224 __reg_write(glamo_handle
, GLAMO_REG_IRQ_CLEAR
,
225 1 << irq2glamo(irq
));
228 static void glamo_mask_irq(unsigned int irq
)
232 /* clear bit in enable register */
233 tmp
= __reg_read(glamo_handle
, GLAMO_REG_IRQ_ENABLE
);
234 tmp
&= ~(1 << irq2glamo(irq
));
235 __reg_write(glamo_handle
, GLAMO_REG_IRQ_ENABLE
, tmp
);
238 static void glamo_unmask_irq(unsigned int irq
)
242 /* set bit in enable register */
243 tmp
= __reg_read(glamo_handle
, GLAMO_REG_IRQ_ENABLE
);
244 tmp
|= (1 << irq2glamo(irq
));
245 __reg_write(glamo_handle
, GLAMO_REG_IRQ_ENABLE
, tmp
);
248 static struct irq_chip glamo_irq_chip
= {
249 .ack
= glamo_ack_irq
,
250 .mask
= glamo_mask_irq
,
251 .unmask
= glamo_unmask_irq
,
254 static void glamo_irq_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
256 desc
->status
&= ~(IRQ_REPLAY
| IRQ_WAITING
);
258 if (unlikely(desc
->status
& IRQ_INPROGRESS
)) {
259 desc
->status
|= (IRQ_PENDING
| IRQ_MASKED
);
260 desc
->chip
->mask(irq
);
261 desc
->chip
->ack(irq
);
264 kstat_incr_irqs_this_cpu(irq
, desc
);
266 desc
->chip
->ack(irq
);
267 desc
->status
|= IRQ_INPROGRESS
;
273 if (unlikely((desc
->status
&
274 (IRQ_PENDING
| IRQ_MASKED
| IRQ_DISABLED
)) ==
275 (IRQ_PENDING
| IRQ_MASKED
))) {
276 /* dealing with pending IRQ, unmasking */
277 desc
->chip
->unmask(irq
);
278 desc
->status
&= ~IRQ_MASKED
;
281 desc
->status
&= ~IRQ_PENDING
;
283 /* read IRQ status register */
284 irqstatus
= __reg_read(glamo_handle
, GLAMO_REG_IRQ_STATUS
);
285 for (i
= 0; i
< 9; i
++)
286 if (irqstatus
& (1 << i
))
287 desc_handle_irq(IRQ_GLAMO(i
),
288 irq_desc
+IRQ_GLAMO(i
));
290 } while ((desc
->status
& (IRQ_PENDING
| IRQ_DISABLED
)) == IRQ_PENDING
);
292 desc
->status
&= ~IRQ_INPROGRESS
;
296 static ssize_t
regs_write(struct device
*dev
, struct device_attribute
*attr
,
297 const char *buf
, size_t count
)
299 unsigned long reg
= simple_strtoul(buf
, NULL
, 10);
300 struct glamo_core
*glamo
= dev_get_drvdata(dev
);
302 while (*buf
&& (*buf
!= ' '))
306 while (*buf
&& (*buf
== ' '))
311 printk(KERN_INFO
"reg 0x%02lX <-- 0x%04lX\n",
312 reg
, simple_strtoul(buf
, NULL
, 10));
314 __reg_write(glamo
, reg
, simple_strtoul(buf
, NULL
, 10));
319 static ssize_t
regs_read(struct device
*dev
, struct device_attribute
*attr
,
322 struct glamo_core
*glamo
= dev_get_drvdata(dev
);
326 spin_lock(&glamo
->lock
);
328 for (r
= 0; r
< ARRAY_SIZE(reg_range
); r
++) {
329 if (!reg_range
[r
].dump
)
332 end
+= sprintf(end
, "\n%s\n", reg_range
[r
].name
);
333 for (n
= reg_range
[r
].start
;
334 n
< reg_range
[r
].start
+ reg_range
[r
].count
; n
+= 2) {
335 if (((n1
++) & 7) == 0)
336 end
+= sprintf(end
, "\n%04X: ", n
);
337 end
+= sprintf(end
, "%04x ", __reg_read(glamo
, n
));
339 end
+= sprintf(end
, "\n");
345 spin_unlock(&glamo
->lock
);
350 static DEVICE_ATTR(regs
, 0644, regs_read
, regs_write
);
351 static struct attribute
*glamo_sysfs_entries
[] = {
355 static struct attribute_group glamo_attr_group
= {
357 .attrs
= glamo_sysfs_entries
,
362 /***********************************************************************
364 ***********************************************************************/
366 int __glamo_engine_enable(struct glamo_core
*glamo
, enum glamo_engine engine
)
369 case GLAMO_ENGINE_LCD
:
370 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
371 GLAMO_HOSTBUS2_MMIO_EN_LCD
,
372 GLAMO_HOSTBUS2_MMIO_EN_LCD
);
373 __reg_write(glamo
, GLAMO_REG_CLOCK_LCD
,
374 GLAMO_CLOCK_LCD_EN_M5CLK
|
375 GLAMO_CLOCK_LCD_EN_DHCLK
|
376 GLAMO_CLOCK_LCD_EN_DMCLK
|
377 GLAMO_CLOCK_LCD_EN_DCLK
|
378 GLAMO_CLOCK_LCD_DG_M5CLK
|
379 GLAMO_CLOCK_LCD_DG_DMCLK
);
380 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
381 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK
|
382 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK
|
383 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
, 0xffff);
385 case GLAMO_ENGINE_MMC
:
386 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
387 GLAMO_HOSTBUS2_MMIO_EN_MMC
,
388 GLAMO_HOSTBUS2_MMIO_EN_MMC
);
389 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_MMC
,
390 GLAMO_CLOCK_MMC_EN_M9CLK
|
391 GLAMO_CLOCK_MMC_EN_TCLK
|
392 GLAMO_CLOCK_MMC_DG_M9CLK
|
393 GLAMO_CLOCK_MMC_DG_TCLK
, 0xffff);
394 /* enable the TCLK divider clk input */
395 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
396 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
,
397 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
);
399 case GLAMO_ENGINE_2D
:
400 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
401 GLAMO_CLOCK_2D_EN_M7CLK
|
402 GLAMO_CLOCK_2D_EN_GCLK
|
403 GLAMO_CLOCK_2D_DG_M7CLK
|
404 GLAMO_CLOCK_2D_DG_GCLK
, 0xffff);
405 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
406 GLAMO_HOSTBUS2_MMIO_EN_2D
,
407 GLAMO_HOSTBUS2_MMIO_EN_2D
);
408 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
409 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
412 case GLAMO_ENGINE_CMDQ
:
413 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
414 GLAMO_CLOCK_2D_EN_M6CLK
, 0xffff);
415 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
416 GLAMO_HOSTBUS2_MMIO_EN_CQ
,
417 GLAMO_HOSTBUS2_MMIO_EN_CQ
);
418 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
419 GLAMO_CLOCK_GEN51_EN_DIV_MCLK
,
422 /* FIXME: Implementation */
427 glamo
->engine_enabled_bitfield
|= 1 << engine
;
432 int glamo_engine_enable(struct glamo_core
*glamo
, enum glamo_engine engine
)
436 spin_lock(&glamo
->lock
);
438 ret
= __glamo_engine_enable(glamo
, engine
);
440 spin_unlock(&glamo
->lock
);
444 EXPORT_SYMBOL_GPL(glamo_engine_enable
);
446 int __glamo_engine_disable(struct glamo_core
*glamo
, enum glamo_engine engine
)
449 case GLAMO_ENGINE_LCD
:
450 /* remove pixel clock to LCM */
451 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
452 GLAMO_CLOCK_LCD_EN_DCLK
, 0);
453 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
454 GLAMO_CLOCK_LCD_EN_DHCLK
|
455 GLAMO_CLOCK_LCD_EN_DMCLK
, 0);
456 /* kill memory clock */
457 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
458 GLAMO_CLOCK_LCD_EN_M5CLK
, 0);
459 /* stop dividing the clocks */
460 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
461 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK
|
462 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK
|
463 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
, 0);
466 case GLAMO_ENGINE_MMC
:
467 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_MMC
,
468 GLAMO_CLOCK_MMC_EN_M9CLK
|
469 GLAMO_CLOCK_MMC_EN_TCLK
|
470 GLAMO_CLOCK_MMC_DG_M9CLK
|
471 GLAMO_CLOCK_MMC_DG_TCLK
, 0);
472 /* disable the TCLK divider clk input */
473 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
474 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
, 0);
476 case GLAMO_ENGINE_CMDQ
:
477 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
478 GLAMO_CLOCK_2D_EN_M6CLK
,
480 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
481 GLAMO_HOSTBUS2_MMIO_EN_CQ
,
482 GLAMO_HOSTBUS2_MMIO_EN_CQ
);
483 /* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
484 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
487 case GLAMO_ENGINE_2D
:
488 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
489 GLAMO_CLOCK_2D_EN_M7CLK
|
490 GLAMO_CLOCK_2D_EN_GCLK
|
491 GLAMO_CLOCK_2D_DG_M7CLK
|
492 GLAMO_CLOCK_2D_DG_GCLK
,
494 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
495 GLAMO_HOSTBUS2_MMIO_EN_2D
,
496 GLAMO_HOSTBUS2_MMIO_EN_2D
);
497 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
498 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
505 glamo
->engine_enabled_bitfield
&= ~(1 << engine
);
509 int glamo_engine_disable(struct glamo_core
*glamo
, enum glamo_engine engine
)
513 spin_lock(&glamo
->lock
);
515 ret
= __glamo_engine_disable(glamo
, engine
);
517 spin_unlock(&glamo
->lock
);
521 EXPORT_SYMBOL_GPL(glamo_engine_disable
);
523 static const u_int16_t engine_clock_regs
[__NUM_GLAMO_ENGINES
] = {
524 [GLAMO_ENGINE_LCD
] = GLAMO_REG_CLOCK_LCD
,
525 [GLAMO_ENGINE_MMC
] = GLAMO_REG_CLOCK_MMC
,
526 [GLAMO_ENGINE_ISP
] = GLAMO_REG_CLOCK_ISP
,
527 [GLAMO_ENGINE_JPEG
] = GLAMO_REG_CLOCK_JPEG
,
528 [GLAMO_ENGINE_3D
] = GLAMO_REG_CLOCK_3D
,
529 [GLAMO_ENGINE_2D
] = GLAMO_REG_CLOCK_2D
,
530 [GLAMO_ENGINE_MPEG_ENC
] = GLAMO_REG_CLOCK_MPEG
,
531 [GLAMO_ENGINE_MPEG_DEC
] = GLAMO_REG_CLOCK_MPEG
,
534 void glamo_engine_clkreg_set(struct glamo_core
*glamo
,
535 enum glamo_engine engine
,
536 u_int16_t mask
, u_int16_t val
)
538 reg_set_bit_mask(glamo
, engine_clock_regs
[engine
], mask
, val
);
540 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set
);
542 u_int16_t
glamo_engine_clkreg_get(struct glamo_core
*glamo
,
543 enum glamo_engine engine
)
547 spin_lock(&glamo
->lock
);
548 val
= __reg_read(glamo
, engine_clock_regs
[engine
]);
549 spin_unlock(&glamo
->lock
);
553 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get
);
555 struct glamo_script reset_regs
[] = {
556 [GLAMO_ENGINE_LCD
] = {
557 GLAMO_REG_CLOCK_LCD
, GLAMO_CLOCK_LCD_RESET
560 [GLAMO_ENGINE_HOST
] = {
561 GLAMO_REG_CLOCK_HOST
, GLAMO_CLOCK_HOST_RESET
563 [GLAMO_ENGINE_MEM
] = {
564 GLAMO_REG_CLOCK_MEM
, GLAMO_CLOCK_MEM_RESET
567 [GLAMO_ENGINE_MMC
] = {
568 GLAMO_REG_CLOCK_MMC
, GLAMO_CLOCK_MMC_RESET
570 [GLAMO_ENGINE_CMDQ
] = {
571 GLAMO_REG_CLOCK_2D
, GLAMO_CLOCK_2D_CQ_RESET
573 [GLAMO_ENGINE_2D
] = {
574 GLAMO_REG_CLOCK_2D
, GLAMO_CLOCK_2D_RESET
576 [GLAMO_ENGINE_JPEG
] = {
577 GLAMO_REG_CLOCK_JPEG
, GLAMO_CLOCK_JPEG_RESET
581 void glamo_engine_reset(struct glamo_core
*glamo
, enum glamo_engine engine
)
583 struct glamo_script
*rst
;
585 if (engine
>= ARRAY_SIZE(reset_regs
)) {
586 dev_warn(&glamo
->pdev
->dev
, "unknown engine %u ", engine
);
590 rst
= &reset_regs
[engine
];
592 spin_lock(&glamo
->lock
);
593 __reg_set_bit(glamo
, rst
->reg
, rst
->val
);
594 __reg_clear_bit(glamo
, rst
->reg
, rst
->val
);
595 spin_unlock(&glamo
->lock
);
597 EXPORT_SYMBOL_GPL(glamo_engine_reset
);
599 void glamo_lcm_reset(int level
)
604 glamo_gpio_setpin(glamo_handle
, GLAMO_GPIO4
, level
);
605 glamo_gpio_cfgpin(glamo_handle
, GLAMO_GPIO4_OUTPUT
);
608 EXPORT_SYMBOL_GPL(glamo_lcm_reset
);
615 static int glamo_pll_rate(struct glamo_core
*glamo
,
619 unsigned int div
= 512;
620 /* FIXME: move osci into platform_data */
621 unsigned int osci
= 32768;
628 reg
= __reg_read(glamo
, GLAMO_REG_PLL_GEN1
);
631 reg
= __reg_read(glamo
, GLAMO_REG_PLL_GEN3
);
636 return (osci
/div
)*reg
;
639 int glamo_engine_reclock(struct glamo_core
*glamo
,
640 enum glamo_engine engine
,
644 u_int16_t reg
, mask
, val
= 0;
650 case GLAMO_ENGINE_LCD
:
652 reg
= GLAMO_REG_CLOCK_GEN7
;
656 dev_warn(&glamo
->pdev
->dev
,
657 "reclock of engine 0x%x not supported\n", engine
);
662 pll
= glamo_pll_rate(glamo
, pll
);
663 khz
= 1000000000UL / ps
;
666 val
= (pll
/ khz
) / 1000;
668 dev_dbg(&glamo
->pdev
->dev
,
669 "PLL %d, kHZ %d, div %d\n", pll
, khz
, val
);
673 reg_set_bit_mask(glamo
, reg
, mask
, val
);
674 mdelay(5); /* wait some time to stabilize */
681 EXPORT_SYMBOL_GPL(glamo_engine_reclock
);
683 /***********************************************************************
685 ***********************************************************************/
687 int glamo_run_script(struct glamo_core
*glamo
, struct glamo_script
*script
,
688 int len
, int may_sleep
)
692 for (i
= 0; i
< len
; i
++) {
693 struct glamo_script
*line
= &script
[i
];
702 mdelay(line
->val
* 4);
705 /* spin until PLLs lock */
706 while ((__reg_read(glamo
, GLAMO_REG_PLL_GEN5
) & 3) != 3)
711 * couple of people reported artefacts with 2.6.28 changes, this
712 * allows reversion to 2.6.24 settings
716 switch (slow_memory
) {
717 /* choice 1 is the most conservative */
718 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
719 __reg_write(glamo
, script
[i
].reg
, 0xef0);
721 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
722 __reg_write(glamo
, script
[i
].reg
, 0xea0);
724 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
725 __reg_write(glamo
, script
[i
].reg
, 0xe50);
727 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
728 __reg_write(glamo
, script
[i
].reg
, 0xe00);
731 /* using PLL2 for memory bus increases CPU bandwidth significantly */
732 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
733 __reg_write(glamo
, script
[i
].reg
, 0xef3);
735 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
736 __reg_write(glamo
, script
[i
].reg
, 0xea3);
738 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
739 __reg_write(glamo
, script
[i
].reg
, 0xe53);
741 /* default of 0 or >7 is fastest */
742 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
743 __reg_write(glamo
, script
[i
].reg
, 0xe03);
749 __reg_write(glamo
, script
[i
].reg
, script
[i
].val
);
756 EXPORT_SYMBOL(glamo_run_script
);
758 static struct glamo_script glamo_init_script
[] = {
759 { GLAMO_REG_CLOCK_HOST
, 0x1000 },
761 { GLAMO_REG_CLOCK_MEMORY
, 0x1000 },
762 { GLAMO_REG_CLOCK_MEMORY
, 0x2000 },
763 { GLAMO_REG_CLOCK_LCD
, 0x1000 },
764 { GLAMO_REG_CLOCK_MMC
, 0x1000 },
765 { GLAMO_REG_CLOCK_ISP
, 0x1000 },
766 { GLAMO_REG_CLOCK_ISP
, 0x3000 },
767 { GLAMO_REG_CLOCK_JPEG
, 0x1000 },
768 { GLAMO_REG_CLOCK_3D
, 0x1000 },
769 { GLAMO_REG_CLOCK_3D
, 0x3000 },
770 { GLAMO_REG_CLOCK_2D
, 0x1000 },
771 { GLAMO_REG_CLOCK_2D
, 0x3000 },
772 { GLAMO_REG_CLOCK_RISC1
, 0x1000 },
773 { GLAMO_REG_CLOCK_MPEG
, 0x3000 },
774 { GLAMO_REG_CLOCK_MPEG
, 0x3000 },
775 { GLAMO_REG_CLOCK_MPROC
, 0x1000 /*0x100f*/ },
777 { GLAMO_REG_CLOCK_HOST
, 0x0000 },
778 { GLAMO_REG_CLOCK_MEMORY
, 0x0000 },
779 { GLAMO_REG_CLOCK_LCD
, 0x0000 },
780 { GLAMO_REG_CLOCK_MMC
, 0x0000 },
782 /* unused engines must be left in reset to stop MMC block read "blackouts" */
783 { GLAMO_REG_CLOCK_ISP
, 0x0000 },
784 { GLAMO_REG_CLOCK_ISP
, 0x0000 },
785 { GLAMO_REG_CLOCK_JPEG
, 0x0000 },
786 { GLAMO_REG_CLOCK_3D
, 0x0000 },
787 { GLAMO_REG_CLOCK_3D
, 0x0000 },
788 { GLAMO_REG_CLOCK_2D
, 0x0000 },
789 { GLAMO_REG_CLOCK_2D
, 0x0000 },
790 { GLAMO_REG_CLOCK_RISC1
, 0x0000 },
791 { GLAMO_REG_CLOCK_MPEG
, 0x0000 },
792 { GLAMO_REG_CLOCK_MPEG
, 0x0000 },
794 { GLAMO_REG_PLL_GEN1
, 0x05db }, /* 48MHz */
795 { GLAMO_REG_PLL_GEN3
, 0x0aba }, /* 90MHz */
798 * b9 of this register MUST be zero to get any interrupts on INT#
799 * the other set bits enable all the engine interrupt sources
801 { GLAMO_REG_IRQ_ENABLE
, 0x01ff },
802 { GLAMO_REG_CLOCK_GEN6
, 0x2000 },
803 { GLAMO_REG_CLOCK_GEN7
, 0x0101 },
804 { GLAMO_REG_CLOCK_GEN8
, 0x0100 },
805 { GLAMO_REG_CLOCK_HOST
, 0x000d },
807 * b7..b4 = 0 = no wait states on read or write
808 * b0 = 1 select PLL2 for Host interface, b1 = enable it
810 { 0x200, 0x0e03 /* this is replaced by script parser */ },
816 /* S-Media recommended "set tiling mode to 512 mode for memory access
817 * more efficiency when 640x480" */
818 { GLAMO_REG_MEM_TYPE
, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
819 { GLAMO_REG_MEM_GEN
, 0xafaf }, /* 63 grants min + max */
821 { GLAMO_REGOFS_HOSTBUS
+ 2, 0xffff }, /* enable on MMIO*/
823 { GLAMO_REG_MEM_TIMING1
, 0x0108 },
824 { GLAMO_REG_MEM_TIMING2
, 0x0010 }, /* Taa = 3 MCLK */
825 { GLAMO_REG_MEM_TIMING3
, 0x0000 },
826 { GLAMO_REG_MEM_TIMING4
, 0x0000 }, /* CE1# delay fall/rise */
827 { GLAMO_REG_MEM_TIMING5
, 0x0000 }, /* UB# LB# */
828 { GLAMO_REG_MEM_TIMING6
, 0x0000 }, /* OE# */
829 { GLAMO_REG_MEM_TIMING7
, 0x0000 }, /* WE# */
830 { GLAMO_REG_MEM_TIMING8
, 0x1002 }, /* MCLK delay, was 0x1000 */
831 { GLAMO_REG_MEM_TIMING9
, 0x6006 },
832 { GLAMO_REG_MEM_TIMING10
, 0x00ff },
833 { GLAMO_REG_MEM_TIMING11
, 0x0001 },
834 { GLAMO_REG_MEM_POWER1
, 0x0020 },
835 { GLAMO_REG_MEM_POWER2
, 0x0000 },
836 { GLAMO_REG_MEM_DRAM1
, 0x0000 },
838 { GLAMO_REG_MEM_DRAM1
, 0xc100 },
840 { GLAMO_REG_MEM_DRAM1
, 0xe100 },
841 { GLAMO_REG_MEM_DRAM2
, 0x01d6 },
842 { GLAMO_REG_CLOCK_MEMORY
, 0x000b },
843 { GLAMO_REG_GPIO_GEN1
, 0x000f },
844 { GLAMO_REG_GPIO_GEN2
, 0x111e },
845 { GLAMO_REG_GPIO_GEN3
, 0xccc3 },
846 { GLAMO_REG_GPIO_GEN4
, 0x111e },
847 { GLAMO_REG_GPIO_GEN5
, 0x000f },
850 static struct glamo_script glamo_resume_script
[] = {
852 { GLAMO_REG_PLL_GEN1
, 0x05db }, /* 48MHz */
853 { GLAMO_REG_PLL_GEN3
, 0x0aba }, /* 90MHz */
854 { GLAMO_REG_DFT_GEN6
, 1 },
860 * b9 of this register MUST be zero to get any interrupts on INT#
861 * the other set bits enable all the engine interrupt sources
863 { GLAMO_REG_IRQ_ENABLE
, 0x01ff },
864 { GLAMO_REG_CLOCK_HOST
, 0x0018 },
865 { GLAMO_REG_CLOCK_GEN5_1
, 0x18b1 },
867 { GLAMO_REG_MEM_DRAM1
, 0x0000 },
869 { GLAMO_REG_MEM_DRAM1
, 0xc100 },
871 { GLAMO_REG_MEM_DRAM1
, 0xe100 },
872 { GLAMO_REG_MEM_DRAM2
, 0x01d6 },
873 { GLAMO_REG_CLOCK_MEMORY
, 0x000b },
882 static void glamo_power(struct glamo_core
*glamo
,
883 enum glamo_power new_state
)
888 spin_lock_irqsave(&glamo
->lock
, flags
);
890 dev_info(&glamo
->pdev
->dev
, "***** glamo_power -> %d\n", new_state
);
894 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
896 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
897 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
898 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
899 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
900 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
903 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
905 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
906 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
907 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
908 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
911 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
913 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
914 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
915 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
916 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
924 * glamo state on resume is nondeterministic in some
925 * fundamental way, it has also been observed that the
926 * Glamo reset pin can get asserted by, eg, touching it with
927 * a scope probe. So the only answer is to roll with it and
928 * force an external reset on the Glamo during resume.
931 (glamo
->pdata
->glamo_external_reset
)(0);
933 (glamo
->pdata
->glamo_external_reset
)(1);
936 glamo_run_script(glamo
, glamo_init_script
,
937 ARRAY_SIZE(glamo_init_script
), 0);
941 case GLAMO_POWER_SUSPEND
:
943 /* nuke interrupts */
944 __reg_write(glamo
, GLAMO_REG_IRQ_ENABLE
, 0x200);
946 /* stash a copy of which engines were running */
947 glamo
->engine_enabled_bitfield_suspend
=
948 glamo
->engine_enabled_bitfield
;
950 /* take down each engine before we kill mem and pll */
951 for (n
= 0; n
< __NUM_GLAMO_ENGINES
; n
++)
952 if (glamo
->engine_enabled_bitfield
& (1 << n
))
953 __glamo_engine_disable(glamo
, n
);
955 /* enable self-refresh */
957 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
,
958 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH
|
959 GLAMO_MEM_DRAM1_EN_GATE_CKE
|
960 GLAMO_MEM_DRAM1_SELF_REFRESH
|
961 GLAMO_MEM_REFRESH_COUNT
);
962 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
,
963 GLAMO_MEM_DRAM1_EN_MODEREG_SET
|
964 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH
|
965 GLAMO_MEM_DRAM1_EN_GATE_CKE
|
966 GLAMO_MEM_DRAM1_SELF_REFRESH
|
967 GLAMO_MEM_REFRESH_COUNT
);
969 /* force RAM into deep powerdown */
971 __reg_write(glamo
, GLAMO_REG_MEM_DRAM2
,
972 GLAMO_MEM_DRAM2_DEEP_PWRDOWN
|
975 (1 << 2) | /* tRCD */
976 2); /* CAS latency */
978 /* disable clocks to memory */
979 __reg_write(glamo
, GLAMO_REG_CLOCK_MEMORY
, 0);
981 /* all dividers from OSCI */
982 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
, 0x400, 0x400);
984 /* PLL2 into bypass */
985 __reg_set_bit_mask(glamo
, GLAMO_REG_PLL_GEN3
, 1 << 12, 1 << 12);
987 __reg_write(glamo
, 0x200, 0x0e00);
990 /* kill PLLS 1 then 2 */
991 __reg_write(glamo
, GLAMO_REG_DFT_GEN5
, 0x0001);
992 __reg_set_bit_mask(glamo
, GLAMO_REG_PLL_GEN3
, 1 << 13, 1 << 13);
997 spin_unlock_irqrestore(&glamo
->lock
, flags
);
1001 #define MEMDETECT_RETRY 6
1002 static unsigned int detect_memsize(struct glamo_core
*glamo
)
1006 /*static const u_int16_t pattern[] = {
1007 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1008 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1009 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1010 0x7777, 0x2a2a, 0x8888, 0x1a1a
1013 for (i
= 0; i
< MEMDETECT_RETRY
; i
++) {
1014 switch (glamo
->type
) {
1016 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
, 0x0072);
1017 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xc100);
1020 switch (glamo
->revision
) {
1021 case GLAMO_CORE_REV_A0
:
1023 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1026 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1029 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0x0000);
1031 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xc100);
1035 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1038 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1041 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0x0000);
1043 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xe100);
1054 /* FIXME: finish implementation */
1055 for (j
= 0; j
< 8; j
++) {
1064 /* Find out if we can support this version of the Glamo chip */
1065 static int glamo_supported(struct glamo_core
*glamo
)
1067 u_int16_t dev_id
, rev_id
; /*, memsize; */
1069 dev_id
= __reg_read(glamo
, GLAMO_REG_DEVICE_ID
);
1070 rev_id
= __reg_read(glamo
, GLAMO_REG_REVISION_ID
);
1075 case GLAMO_CORE_REV_A2
:
1077 case GLAMO_CORE_REV_A0
:
1078 case GLAMO_CORE_REV_A1
:
1079 case GLAMO_CORE_REV_A3
:
1080 dev_warn(&glamo
->pdev
->dev
, "untested core revision "
1081 "%04x, your mileage may vary\n", rev_id
);
1084 dev_warn(&glamo
->pdev
->dev
, "unknown glamo revision "
1085 "%04x, your mileage may vary\n", rev_id
);
1086 /* maybe should abort ? */
1092 dev_err(&glamo
->pdev
->dev
, "unsupported Glamo device %04x\n",
1097 dev_dbg(&glamo
->pdev
->dev
, "Detected Glamo core %04x Revision %04x "
1098 "(%uHz CPU / %uHz Memory)\n", dev_id
, rev_id
,
1099 glamo_pll_rate(glamo
, GLAMO_PLL1
),
1100 glamo_pll_rate(glamo
, GLAMO_PLL2
));
1105 static int __init
glamo_probe(struct platform_device
*pdev
)
1108 struct glamo_core
*glamo
;
1112 "This driver supports only one instance\n");
1116 glamo
= kmalloc(GFP_KERNEL
, sizeof(*glamo
));
1120 spin_lock_init(&glamo
->lock
);
1121 glamo_handle
= glamo
;
1123 glamo
->mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1124 glamo
->irq
= platform_get_irq(pdev
, 0);
1125 glamo
->pdata
= pdev
->dev
.platform_data
;
1126 if (!glamo
->mem
|| !glamo
->pdata
) {
1127 dev_err(&pdev
->dev
, "platform device with no MEM/PDATA ?\n");
1132 /* register a number of sibling devices whoise IOMEM resources
1133 * are siblings of pdev's IOMEM resource */
1135 /* only remap the generic, hostbus and memory controller registers */
1136 glamo
->base
= ioremap(glamo
->mem
->start
, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1138 dev_err(&pdev
->dev
, "failed to ioremap() memory region\n");
1142 platform_set_drvdata(pdev
, glamo
);
1144 (glamo
->pdata
->glamo_external_reset
)(0);
1146 (glamo
->pdata
->glamo_external_reset
)(1);
1150 * finally set the mfd interrupts up
1151 * can't do them earlier or sibling probes blow up
1154 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1155 set_irq_chip(irq
, &glamo_irq_chip
);
1156 set_irq_handler(irq
, handle_level_irq
);
1157 set_irq_flags(irq
, IRQF_VALID
);
1160 if (glamo
->pdata
->glamo_irq_is_wired
&&
1161 !glamo
->pdata
->glamo_irq_is_wired()) {
1162 set_irq_chained_handler(glamo
->irq
, glamo_irq_demux_handler
);
1163 set_irq_type(glamo
->irq
, IRQ_TYPE_EDGE_FALLING
);
1164 dev_info(&pdev
->dev
, "Glamo interrupt registered\n");
1165 glamo
->irq_works
= 1;
1167 dev_err(&pdev
->dev
, "Glamo interrupt not used\n");
1168 glamo
->irq_works
= 0;
1171 /* confirm it isn't insane version */
1172 if (!glamo_supported(glamo
)) {
1173 dev_err(&pdev
->dev
, "This Glamo is not supported\n");
1178 rc
= sysfs_create_group(&pdev
->dev
.kobj
, &glamo_attr_group
);
1180 dev_err(&pdev
->dev
, "cannot create sysfs group\n");
1184 /* init the chip with canned register set */
1186 dev_dbg(&glamo
->pdev
->dev
, "running init script\n");
1187 glamo_run_script(glamo
, glamo_init_script
,
1188 ARRAY_SIZE(glamo_init_script
), 1);
1190 dev_info(&glamo
->pdev
->dev
, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1191 glamo_pll_rate(glamo
, GLAMO_PLL1
),
1192 glamo_pll_rate(glamo
, GLAMO_PLL2
));
1194 glamo
->pdata
->glamo
= glamo
;
1196 /* bring MCI specific stuff over from our MFD platform data */
1197 glamo_mci_def_pdata
.glamo_can_set_mci_power
=
1198 glamo
->pdata
->glamo_can_set_mci_power
;
1199 glamo_mci_def_pdata
.glamo_mci_use_slow
=
1200 glamo
->pdata
->glamo_mci_use_slow
;
1201 glamo_mci_def_pdata
.glamo_irq_is_wired
=
1202 glamo
->pdata
->glamo_irq_is_wired
;
1203 glamo_mci_def_pdata
.pglamo
= glamo
;
1205 /* register siblings */
1206 glamo_cells
[GLAMO_CELL_MMC
].platform_data
= &glamo_mci_def_pdata
;
1207 glamo_cells
[GLAMO_CELL_MMC
].data_size
= sizeof(glamo_mci_def_pdata
);
1209 glamo_cells
[GLAMO_CELL_FB
].platform_data
= glamo
->pdata
;
1210 glamo_cells
[GLAMO_CELL_FB
].data_size
= sizeof(struct glamofb_platform_data
);
1212 glamo
->pdata
->spigpio_info
->glamo
= glamo
;
1213 glamo_cells
[GLAMO_CELL_SPI_GPIO
].platform_data
= glamo
->pdata
->spigpio_info
;
1214 glamo_cells
[GLAMO_CELL_SPI_GPIO
].data_size
=
1215 sizeof(struct glamo_spigpio_info
);
1217 mfd_add_devices(&pdev
->dev
, pdev
->id
, glamo_cells
,
1218 ARRAY_SIZE(glamo_cells
),
1221 /* only request the generic, hostbus and memory controller MMIO */
1222 glamo
->mem
= request_mem_region(glamo
->mem
->start
,
1223 GLAMO_REGOFS_VIDCAP
, "glamo-core");
1225 dev_err(&pdev
->dev
, "failed to request memory region\n");
1232 disable_irq(glamo
->irq
);
1233 set_irq_chained_handler(glamo
->irq
, NULL
);
1235 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1236 set_irq_flags(irq
, 0);
1237 set_irq_chip(irq
, NULL
);
1240 iounmap(glamo
->base
);
1242 platform_set_drvdata(pdev
, NULL
);
1243 glamo_handle
= NULL
;
1249 static int glamo_remove(struct platform_device
*pdev
)
1251 struct glamo_core
*glamo
= platform_get_drvdata(pdev
);
1254 disable_irq(glamo
->irq
);
1255 set_irq_chained_handler(glamo
->irq
, NULL
);
1257 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1258 set_irq_flags(irq
, 0);
1259 set_irq_chip(irq
, NULL
);
1262 platform_set_drvdata(pdev
, NULL
);
1263 mfd_remove_devices(&pdev
->dev
);
1264 iounmap(glamo
->base
);
1265 release_mem_region(glamo
->mem
->start
, GLAMO_REGOFS_VIDCAP
);
1266 glamo_handle
= NULL
;
1274 static int glamo_suspend(struct platform_device
*pdev
, pm_message_t state
)
1276 glamo_handle
->suspending
= 1;
1277 glamo_power(glamo_handle
, GLAMO_POWER_SUSPEND
);
1282 static int glamo_resume(struct platform_device
*pdev
)
1284 glamo_power(glamo_handle
, GLAMO_POWER_ON
);
1285 glamo_handle
->suspending
= 0;
1291 #define glamo_suspend NULL
1292 #define glamo_resume NULL
1295 static struct platform_driver glamo_driver
= {
1296 .probe
= glamo_probe
,
1297 .remove
= glamo_remove
,
1298 .suspend
= glamo_suspend
,
1299 .resume
= glamo_resume
,
1301 .name
= "glamo3362",
1302 .owner
= THIS_MODULE
,
1306 static int __devinit
glamo_init(void)
1308 return platform_driver_register(&glamo_driver
);
1311 static void __exit
glamo_cleanup(void)
1313 platform_driver_unregister(&glamo_driver
);
1316 module_init(glamo_init
);
1317 module_exit(glamo_cleanup
);
1319 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1320 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1321 MODULE_LICENSE("GPL");