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ramips: use uncached address in detect_mem_size
[openwrt.git] / target / linux / generic / patches-2.6.38 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -557,7 +558,7 @@ error:
21 }
22
23 /* Needs ssb_buses_lock() */
24 -static int ssb_attach_queued_buses(void)
25 +static int __devinit ssb_attach_queued_buses(void)
26 {
27 struct ssb_bus *bus, *n;
28 int err = 0;
29 @@ -768,9 +769,9 @@ out:
30 return err;
31 }
32
33 -static int ssb_bus_register(struct ssb_bus *bus,
34 - ssb_invariants_func_t get_invariants,
35 - unsigned long baseaddr)
36 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
37 + ssb_invariants_func_t get_invariants,
38 + unsigned long baseaddr)
39 {
40 int err;
41
42 @@ -851,8 +852,8 @@ err_disable_xtal:
43 }
44
45 #ifdef CONFIG_SSB_PCIHOST
46 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
47 - struct pci_dev *host_pci)
48 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
49 + struct pci_dev *host_pci)
50 {
51 int err;
52
53 @@ -875,9 +876,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
54 #endif /* CONFIG_SSB_PCIHOST */
55
56 #ifdef CONFIG_SSB_PCMCIAHOST
57 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
58 - struct pcmcia_device *pcmcia_dev,
59 - unsigned long baseaddr)
60 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
61 + struct pcmcia_device *pcmcia_dev,
62 + unsigned long baseaddr)
63 {
64 int err;
65
66 @@ -897,8 +898,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
67 #endif /* CONFIG_SSB_PCMCIAHOST */
68
69 #ifdef CONFIG_SSB_SDIOHOST
70 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
71 - unsigned int quirks)
72 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
73 + struct sdio_func *func,
74 + unsigned int quirks)
75 {
76 int err;
77
78 @@ -918,9 +920,9 @@ int ssb_bus_sdiobus_register(struct ssb_
79 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
80 #endif /* CONFIG_SSB_PCMCIAHOST */
81
82 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
83 - unsigned long baseaddr,
84 - ssb_invariants_func_t get_invariants)
85 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
86 + unsigned long baseaddr,
87 + ssb_invariants_func_t get_invariants)
88 {
89 int err;
90
91 @@ -1001,8 +1003,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
92 switch (plltype) {
93 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
94 if (m & SSB_CHIPCO_CLK_T6_MMASK)
95 - return SSB_CHIPCO_CLK_T6_M0;
96 - return SSB_CHIPCO_CLK_T6_M1;
97 + return SSB_CHIPCO_CLK_T6_M1;
98 + return SSB_CHIPCO_CLK_T6_M0;
99 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
100 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
101 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
102 @@ -1117,23 +1119,22 @@ static u32 ssb_tmslow_reject_bitmask(str
103 {
104 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
105
106 - /* The REJECT bit changed position in TMSLOW between
107 - * Backplane revisions. */
108 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
109 switch (rev) {
110 case SSB_IDLOW_SSBREV_22:
111 - return SSB_TMSLOW_REJECT_22;
112 + case SSB_IDLOW_SSBREV_24:
113 + case SSB_IDLOW_SSBREV_26:
114 + return SSB_TMSLOW_REJECT;
115 case SSB_IDLOW_SSBREV_23:
116 return SSB_TMSLOW_REJECT_23;
117 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
118 - case SSB_IDLOW_SSBREV_25: /* same here */
119 - case SSB_IDLOW_SSBREV_26: /* same here */
120 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
121 case SSB_IDLOW_SSBREV_27: /* same here */
122 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
123 + return SSB_TMSLOW_REJECT; /* this is a guess */
124 default:
125 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
126 WARN_ON(1);
127 }
128 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
129 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
130 }
131
132 int ssb_device_is_enabled(struct ssb_device *dev)
133 @@ -1192,10 +1193,10 @@ void ssb_device_enable(struct ssb_device
134 }
135 EXPORT_SYMBOL(ssb_device_enable);
136
137 -/* Wait for a bit in a register to get set or unset.
138 +/* Wait for bitmask in a register to get set or cleared.
139 * timeout is in units of ten-microseconds */
140 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
141 - int timeout, int set)
142 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
143 + int timeout, int set)
144 {
145 int i;
146 u32 val;
147 @@ -1203,7 +1204,7 @@ static int ssb_wait_bit(struct ssb_devic
148 for (i = 0; i < timeout; i++) {
149 val = ssb_read32(dev, reg);
150 if (set) {
151 - if (val & bitmask)
152 + if ((val & bitmask) == bitmask)
153 return 0;
154 } else {
155 if (!(val & bitmask))
156 @@ -1220,20 +1221,38 @@ static int ssb_wait_bit(struct ssb_devic
157
158 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
159 {
160 - u32 reject;
161 + u32 reject, val;
162
163 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
164 return;
165
166 reject = ssb_tmslow_reject_bitmask(dev);
167 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
168 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
169 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
170 - ssb_write32(dev, SSB_TMSLOW,
171 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
172 - reject | SSB_TMSLOW_RESET |
173 - core_specific_flags);
174 - ssb_flush_tmslow(dev);
175 +
176 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
177 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
178 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
179 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
180 +
181 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
182 + val = ssb_read32(dev, SSB_IMSTATE);
183 + val |= SSB_IMSTATE_REJECT;
184 + ssb_write32(dev, SSB_IMSTATE, val);
185 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
186 + 0);
187 + }
188 +
189 + ssb_write32(dev, SSB_TMSLOW,
190 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
191 + reject | SSB_TMSLOW_RESET |
192 + core_specific_flags);
193 + ssb_flush_tmslow(dev);
194 +
195 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
196 + val = ssb_read32(dev, SSB_IMSTATE);
197 + val &= ~SSB_IMSTATE_REJECT;
198 + ssb_write32(dev, SSB_IMSTATE, val);
199 + }
200 + }
201
202 ssb_write32(dev, SSB_TMSLOW,
203 reject | SSB_TMSLOW_RESET |
204 @@ -1242,13 +1261,34 @@ void ssb_device_disable(struct ssb_devic
205 }
206 EXPORT_SYMBOL(ssb_device_disable);
207
208 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
209 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
210 +{
211 + u16 chip_id = dev->bus->chip_id;
212 +
213 + if (dev->id.coreid == SSB_DEV_80211) {
214 + return (chip_id == 0x4322 || chip_id == 43221 ||
215 + chip_id == 43231 || chip_id == 43222);
216 + }
217 +
218 + return 0;
219 +}
220 +
221 u32 ssb_dma_translation(struct ssb_device *dev)
222 {
223 switch (dev->bus->bustype) {
224 case SSB_BUSTYPE_SSB:
225 return 0;
226 case SSB_BUSTYPE_PCI:
227 - return SSB_PCI_DMA;
228 + if (pci_is_pcie(dev->bus->host_pci) &&
229 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
230 + return SSB_PCIE_DMA_H32;
231 + } else {
232 + if (ssb_dma_translation_special_bit(dev))
233 + return SSB_PCIE_DMA_H32;
234 + else
235 + return SSB_PCI_DMA;
236 + }
237 default:
238 __ssb_dma_not_implemented(dev);
239 }
240 @@ -1291,20 +1331,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
241
242 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
243 {
244 - struct ssb_chipcommon *cc;
245 int err;
246 enum ssb_clkmode mode;
247
248 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
249 if (err)
250 goto error;
251 - cc = &bus->chipco;
252 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
253 - ssb_chipco_set_clockmode(cc, mode);
254
255 #ifdef CONFIG_SSB_DEBUG
256 bus->powered_up = 1;
257 #endif
258 +
259 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
260 + ssb_chipco_set_clockmode(&bus->chipco, mode);
261 +
262 return 0;
263 error:
264 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
265 @@ -1312,6 +1352,37 @@ error:
266 }
267 EXPORT_SYMBOL(ssb_bus_powerup);
268
269 +static void ssb_broadcast_value(struct ssb_device *dev,
270 + u32 address, u32 data)
271 +{
272 +#ifdef CONFIG_SSB_DRIVER_PCICORE
273 + /* This is used for both, PCI and ChipCommon core, so be careful. */
274 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
275 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
276 +#endif
277 +
278 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
279 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
280 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
281 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
282 +}
283 +
284 +void ssb_commit_settings(struct ssb_bus *bus)
285 +{
286 + struct ssb_device *dev;
287 +
288 +#ifdef CONFIG_SSB_DRIVER_PCICORE
289 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
290 +#else
291 + dev = bus->chipco.dev;
292 +#endif
293 + if (WARN_ON(!dev))
294 + return;
295 + /* This forces an update of the cached registers. */
296 + ssb_broadcast_value(dev, 0xFD8, 0);
297 +}
298 +EXPORT_SYMBOL(ssb_commit_settings);
299 +
300 u32 ssb_admatch_base(u32 adm)
301 {
302 u32 base = 0;
303 --- a/drivers/ssb/pci.c
304 +++ b/drivers/ssb/pci.c
305 @@ -1,7 +1,7 @@
306 /*
307 * Sonics Silicon Backplane PCI-Hostbus related functions.
308 *
309 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
310 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
311 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
312 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
313 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
314 @@ -468,10 +468,14 @@ static void sprom_extract_r45(struct ssb
315 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
316 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
317 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
318 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
319 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
320 } else {
321 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
322 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
323 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
324 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
325 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
326 }
327 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
328 SSB_SPROM4_ANTAVAIL_A_SHIFT);
329 @@ -519,7 +523,13 @@ static void sprom_extract_r45(struct ssb
330 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
331 {
332 int i;
333 - u16 v;
334 + u16 v, o;
335 + u16 pwr_info_offset[] = {
336 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
337 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
338 + };
339 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
340 + ARRAY_SIZE(out->core_pwr_info));
341
342 /* extract the MAC address */
343 for (i = 0; i < 3; i++) {
344 @@ -603,6 +613,61 @@ static void sprom_extract_r8(struct ssb_
345 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
346 sizeof(out->antenna_gain.ghz5));
347
348 + /* Extract cores power info info */
349 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
350 + o = pwr_info_offset[i];
351 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
352 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
353 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
354 + SSB_SPROM8_2G_MAXP, 0);
355 +
356 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
357 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
358 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
359 +
360 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
361 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
362 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
363 + SSB_SPROM8_5G_MAXP, 0);
364 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
365 + SSB_SPROM8_5GH_MAXP, 0);
366 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
367 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
368 +
369 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
370 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
371 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
372 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
373 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
374 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
375 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
376 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
377 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
378 + }
379 +
380 + /* Extract FEM info */
381 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
382 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
383 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
384 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
385 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
386 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
387 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
388 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
389 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
390 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
391 +
392 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
393 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
394 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
395 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
396 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
397 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
398 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
399 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
400 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
401 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
402 +
403 sprom_extract_r458(out, in);
404
405 /* TODO - get remaining rev 8 stuff needed */
406 @@ -641,7 +706,7 @@ static int sprom_extract(struct ssb_bus
407 break;
408 default:
409 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
410 - " revision %d detected. Will extract"
411 + " revision %d detected. Will extract"
412 " v1\n", out->revision);
413 out->revision = 1;
414 sprom_extract_r123(out, in);
415 @@ -658,7 +723,6 @@ static int sprom_extract(struct ssb_bus
416 static int ssb_pci_sprom_get(struct ssb_bus *bus,
417 struct ssb_sprom *sprom)
418 {
419 - const struct ssb_sprom *fallback;
420 int err;
421 u16 *buf;
422
423 @@ -666,7 +730,7 @@ static int ssb_pci_sprom_get(struct ssb_
424 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
425 return -ENODEV;
426 }
427 - if (bus->chipco.dev) { /* can be unavailible! */
428 + if (bus->chipco.dev) { /* can be unavailable! */
429 /*
430 * get SPROM offset: SSB_SPROM_BASE1 except for
431 * chipcommon rev >= 31 or chip ID is 0x4312 and
432 @@ -703,10 +767,17 @@ static int ssb_pci_sprom_get(struct ssb_
433 if (err) {
434 /* All CRC attempts failed.
435 * Maybe there is no SPROM on the device?
436 - * If we have a fallback, use that. */
437 - fallback = ssb_get_fallback_sprom();
438 - if (fallback) {
439 - memcpy(sprom, fallback, sizeof(*sprom));
440 + * Now we ask the arch code if there is some sprom
441 + * available for this device in some other storage */
442 + err = ssb_fill_sprom_with_fallback(bus, sprom);
443 + if (err) {
444 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
445 + " fallback SPROM failed (err %d)\n",
446 + err);
447 + } else {
448 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
449 + " revision %d provided by"
450 + " platform.\n", sprom->revision);
451 err = 0;
452 goto out_free;
453 }
454 @@ -724,12 +795,9 @@ out_free:
455 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
456 struct ssb_boardinfo *bi)
457 {
458 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
459 - &bi->vendor);
460 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
461 - &bi->type);
462 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
463 - &bi->rev);
464 + bi->vendor = bus->host_pci->subsystem_vendor;
465 + bi->type = bus->host_pci->subsystem_device;
466 + bi->rev = bus->host_pci->revision;
467 }
468
469 int ssb_pci_get_invariants(struct ssb_bus *bus,
470 --- a/include/linux/ssb/ssb_regs.h
471 +++ b/include/linux/ssb/ssb_regs.h
472 @@ -85,6 +85,8 @@
473 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
474 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
475 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
476 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
477 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
478 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
479 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
480 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
481 @@ -95,9 +97,8 @@
482 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
483 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
484 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
485 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
486 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
487 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
488 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
489 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
490 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
491 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
492 @@ -268,6 +269,8 @@
493 /* SPROM Revision 4 */
494 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
495 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
496 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
497 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
498 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
499 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
500 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
501 @@ -358,6 +361,8 @@
502 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
503 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
504 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
505 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
506 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
507 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
508 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
509 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
510 @@ -427,6 +432,56 @@
511 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
512 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
513 #define SSB_SPROM8_RXPO5G_SHIFT 8
514 +#define SSB_SPROM8_FEM2G 0x00AE
515 +#define SSB_SPROM8_FEM5G 0x00B0
516 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
517 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
518 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
519 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
520 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
521 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
522 +#define SSB_SROM8_FEM_TR_ISO 0x0700
523 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
524 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
525 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
526 +#define SSB_SPROM8_THERMAL 0x00B2
527 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
528 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
529 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
530 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
531 +
532 +/* There are 4 blocks with power info sharing the same layout */
533 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
534 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
535 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
536 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
537 +
538 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
539 +#define SSB_SPROM8_2G_MAXP 0x00FF
540 +#define SSB_SPROM8_2G_ITSSI 0xFF00
541 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
542 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
543 +#define SSB_SROM8_2G_PA_1 0x04
544 +#define SSB_SROM8_2G_PA_2 0x06
545 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
546 +#define SSB_SPROM8_5G_MAXP 0x00FF
547 +#define SSB_SPROM8_5G_ITSSI 0xFF00
548 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
549 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
550 +#define SSB_SPROM8_5GH_MAXP 0x00FF
551 +#define SSB_SPROM8_5GL_MAXP 0xFF00
552 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
553 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
554 +#define SSB_SROM8_5G_PA_1 0x0E
555 +#define SSB_SROM8_5G_PA_2 0x10
556 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
557 +#define SSB_SROM8_5GL_PA_1 0x14
558 +#define SSB_SROM8_5GL_PA_2 0x16
559 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
560 +#define SSB_SROM8_5GH_PA_1 0x1A
561 +#define SSB_SROM8_5GH_PA_2 0x1C
562 +
563 +/* TODO: Make it deprecated */
564 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
565 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
566 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
567 @@ -451,12 +506,53 @@
568 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
569 #define SSB_SPROM8_PA1HIB1 0x00DA
570 #define SSB_SPROM8_PA1HIB2 0x00DC
571 +
572 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
573 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
574 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
575 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
576 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
577
578 +/* Values for boardflags_lo read from SPROM */
579 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
580 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
581 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
582 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
583 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
584 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
585 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
586 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
587 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
588 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
589 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
590 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
591 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
592 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
593 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
594 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
595 +
596 +/* Values for boardflags_hi read from SPROM */
597 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
598 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
599 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
600 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
601 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
602 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
603 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
604 +
605 +/* Values for boardflags2_lo read from SPROM */
606 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
607 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
608 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
609 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
610 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
611 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
612 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
613 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
614 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
615 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
616 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
617 +
618 /* Values for SSB_SPROM1_BINF_CCODE */
619 enum {
620 SSB_SPROM1CCODE_WORLD = 0,
621 --- a/drivers/ssb/driver_chipcommon.c
622 +++ b/drivers/ssb/driver_chipcommon.c
623 @@ -3,7 +3,7 @@
624 * Broadcom ChipCommon core driver
625 *
626 * Copyright 2005, Broadcom Corporation
627 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
628 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
629 *
630 * Licensed under the GNU/GPL. See COPYING for details.
631 */
632 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
633 if (!ccdev)
634 return;
635 bus = ccdev->bus;
636 +
637 + /* We support SLOW only on 6..9 */
638 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
639 + mode = SSB_CLKMODE_DYNAMIC;
640 +
641 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
642 + return; /* PMU controls clockmode, separated function needed */
643 + SSB_WARN_ON(ccdev->id.revision >= 20);
644 +
645 /* chipcommon cores prior to rev6 don't support dynamic clock control */
646 if (ccdev->id.revision < 6)
647 return;
648 - /* chipcommon cores rev10 are a whole new ball game */
649 +
650 + /* ChipCommon cores rev10+ need testing */
651 if (ccdev->id.revision >= 10)
652 return;
653 +
654 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
655 return;
656
657 switch (mode) {
658 - case SSB_CLKMODE_SLOW:
659 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
660 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
661 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
662 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
663 break;
664 case SSB_CLKMODE_FAST:
665 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
666 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
667 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
668 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
669 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
670 + if (ccdev->id.revision < 10) {
671 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
672 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
673 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
674 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
675 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
676 + } else {
677 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
678 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
679 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
680 + /* udelay(150); TODO: not available in early init */
681 + }
682 break;
683 case SSB_CLKMODE_DYNAMIC:
684 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
685 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
686 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
687 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
688 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
689 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
690 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
691 -
692 - /* for dynamic control, we have to release our xtal_pu "force on" */
693 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
694 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
695 + if (ccdev->id.revision < 10) {
696 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
697 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
698 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
699 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
700 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
701 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
702 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
703 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
704 +
705 + /* For dynamic control, we have to release our xtal_pu
706 + * "force on" */
707 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
708 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
709 + } else {
710 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
711 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
712 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
713 + }
714 break;
715 default:
716 SSB_WARN_ON(1);
717 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
718 if (cc->dev->id.revision >= 11)
719 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
720 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
721 +
722 + if (cc->dev->id.revision >= 20) {
723 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
724 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
725 + }
726 +
727 ssb_pmu_init(cc);
728 chipco_powercontrol_init(cc);
729 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
730 --- a/drivers/ssb/driver_chipcommon_pmu.c
731 +++ b/drivers/ssb/driver_chipcommon_pmu.c
732 @@ -2,7 +2,7 @@
733 * Sonics Silicon Backplane
734 * Broadcom ChipCommon Power Management Unit driver
735 *
736 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
737 + * Copyright 2009, Michael Buesch <m@bues.ch>
738 * Copyright 2007, Broadcom Corporation
739 *
740 * Licensed under the GNU/GPL. See COPYING for details.
741 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
742 u32 min_msk = 0, max_msk = 0;
743 unsigned int i;
744 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
745 - unsigned int updown_tab_size;
746 + unsigned int updown_tab_size = 0;
747 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
748 - unsigned int depend_tab_size;
749 + unsigned int depend_tab_size = 0;
750
751 switch (bus->chip_id) {
752 case 0x4312:
753 + min_msk = 0xCBB;
754 + break;
755 case 0x4322:
756 /* We keep the default settings:
757 * min_msk = 0xCBB
758 --- a/drivers/ssb/driver_gige.c
759 +++ b/drivers/ssb/driver_gige.c
760 @@ -3,7 +3,7 @@
761 * Broadcom Gigabit Ethernet core driver
762 *
763 * Copyright 2008, Broadcom Corporation
764 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
765 + * Copyright 2008, Michael Buesch <m@bues.ch>
766 *
767 * Licensed under the GNU/GPL. See COPYING for details.
768 */
769 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
770 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
771 }
772
773 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
774 - int reg, int size, u32 *val)
775 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
776 + unsigned int devfn, int reg,
777 + int size, u32 *val)
778 {
779 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
780 unsigned long flags;
781 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
782 return PCIBIOS_SUCCESSFUL;
783 }
784
785 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
786 - int reg, int size, u32 val)
787 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
788 + unsigned int devfn, int reg,
789 + int size, u32 val)
790 {
791 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
792 unsigned long flags;
793 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
794 return PCIBIOS_SUCCESSFUL;
795 }
796
797 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
798 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
799 + const struct ssb_device_id *id)
800 {
801 struct ssb_gige *dev;
802 u32 base, tmslow, tmshigh;
803 --- a/drivers/ssb/driver_pcicore.c
804 +++ b/drivers/ssb/driver_pcicore.c
805 @@ -3,7 +3,7 @@
806 * Broadcom PCI-core driver
807 *
808 * Copyright 2005, Broadcom Corporation
809 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
810 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
811 *
812 * Licensed under the GNU/GPL. See COPYING for details.
813 */
814 @@ -15,6 +15,11 @@
815
816 #include "ssb_private.h"
817
818 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
819 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
820 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
821 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
822 + u8 address, u16 data);
823
824 static inline
825 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
826 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
827 return ssb_mips_irq(extpci_core->dev) + 2;
828 }
829
830 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
831 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
832 {
833 u32 val;
834
835 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
836 register_pci_controller(&ssb_pcicore_controller);
837 }
838
839 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
840 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
841 {
842 struct ssb_bus *bus = pc->dev->bus;
843 u16 chipid_top;
844 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
845 }
846 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
847
848 +/**************************************************
849 + * Workarounds.
850 + **************************************************/
851 +
852 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
853 +{
854 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
855 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
856 + tmp &= ~0xF000;
857 + tmp |= (pc->dev->core_index << 12);
858 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
859 + }
860 +}
861 +
862 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
863 +{
864 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
865 +}
866 +
867 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
868 +{
869 + const u8 serdes_pll_device = 0x1D;
870 + const u8 serdes_rx_device = 0x1F;
871 + u16 tmp;
872 +
873 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
874 + ssb_pcicore_polarity_workaround(pc));
875 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
876 + if (tmp & 0x4000)
877 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
878 +}
879 +
880 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
881 +{
882 + struct ssb_device *pdev = pc->dev;
883 + struct ssb_bus *bus = pdev->bus;
884 + u32 tmp;
885 +
886 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
887 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
888 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
889 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
890 +
891 + if (pdev->id.revision < 5) {
892 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
893 + tmp &= ~SSB_IMCFGLO_SERTO;
894 + tmp |= 2;
895 + tmp &= ~SSB_IMCFGLO_REQTO;
896 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
897 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
898 + ssb_commit_settings(bus);
899 + } else if (pdev->id.revision >= 11) {
900 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
901 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
902 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
903 + }
904 +}
905 +
906 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
907 +{
908 + u32 tmp;
909 + u8 rev = pc->dev->id.revision;
910 +
911 + if (rev == 0 || rev == 1) {
912 + /* TLP Workaround register. */
913 + tmp = ssb_pcie_read(pc, 0x4);
914 + tmp |= 0x8;
915 + ssb_pcie_write(pc, 0x4, tmp);
916 + }
917 + if (rev == 1) {
918 + /* DLLP Link Control register. */
919 + tmp = ssb_pcie_read(pc, 0x100);
920 + tmp |= 0x40;
921 + ssb_pcie_write(pc, 0x100, tmp);
922 + }
923 +
924 + if (rev == 0) {
925 + const u8 serdes_rx_device = 0x1F;
926 +
927 + ssb_pcie_mdio_write(pc, serdes_rx_device,
928 + 2 /* Timer */, 0x8128);
929 + ssb_pcie_mdio_write(pc, serdes_rx_device,
930 + 6 /* CDR */, 0x0100);
931 + ssb_pcie_mdio_write(pc, serdes_rx_device,
932 + 7 /* CDR BW */, 0x1466);
933 + } else if (rev == 3 || rev == 4 || rev == 5) {
934 + /* TODO: DLLP Power Management Threshold */
935 + ssb_pcicore_serdes_workaround(pc);
936 + /* TODO: ASPM */
937 + } else if (rev == 7) {
938 + /* TODO: No PLL down */
939 + }
940 +
941 + if (rev >= 6) {
942 + /* Miscellaneous Configuration Fixup */
943 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
944 + if (!(tmp & 0x8000))
945 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
946 + tmp | 0x8000);
947 + }
948 +}
949
950 /**************************************************
951 * Generic and Clientmode operation code.
952 **************************************************/
953
954 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
955 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
956 {
957 + struct ssb_device *pdev = pc->dev;
958 + struct ssb_bus *bus = pdev->bus;
959 +
960 + if (bus->bustype == SSB_BUSTYPE_PCI)
961 + ssb_pcicore_fix_sprom_core_index(pc);
962 +
963 /* Disable PCI interrupts. */
964 - ssb_write32(pc->dev, SSB_INTVEC, 0);
965 + ssb_write32(pdev, SSB_INTVEC, 0);
966 +
967 + /* Additional PCIe always once-executed workarounds */
968 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
969 + ssb_pcicore_serdes_workaround(pc);
970 + /* TODO: ASPM */
971 + /* TODO: Clock Request Update */
972 + }
973 }
974
975 -void ssb_pcicore_init(struct ssb_pcicore *pc)
976 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
977 {
978 struct ssb_device *dev = pc->dev;
979 - struct ssb_bus *bus;
980
981 if (!dev)
982 return;
983 - bus = dev->bus;
984 if (!ssb_device_is_enabled(dev))
985 ssb_device_enable(dev, 0);
986
987 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
988 pcicore_write32(pc, 0x134, data);
989 }
990
991 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
992 - u8 address, u16 data)
993 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
994 +{
995 + const u16 mdio_control = 0x128;
996 + const u16 mdio_data = 0x12C;
997 + u32 v;
998 + int i;
999 +
1000 + v = (1 << 30); /* Start of Transaction */
1001 + v |= (1 << 28); /* Write Transaction */
1002 + v |= (1 << 17); /* Turnaround */
1003 + v |= (0x1F << 18);
1004 + v |= (phy << 4);
1005 + pcicore_write32(pc, mdio_data, v);
1006 +
1007 + udelay(10);
1008 + for (i = 0; i < 200; i++) {
1009 + v = pcicore_read32(pc, mdio_control);
1010 + if (v & 0x100 /* Trans complete */)
1011 + break;
1012 + msleep(1);
1013 + }
1014 +}
1015 +
1016 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1017 {
1018 const u16 mdio_control = 0x128;
1019 const u16 mdio_data = 0x12C;
1020 + int max_retries = 10;
1021 + u16 ret = 0;
1022 u32 v;
1023 int i;
1024
1025 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
1026 v |= 0x2; /* MDIO Clock Divisor */
1027 pcicore_write32(pc, mdio_control, v);
1028
1029 + if (pc->dev->id.revision >= 10) {
1030 + max_retries = 200;
1031 + ssb_pcie_mdio_set_phy(pc, device);
1032 + }
1033 +
1034 v = (1 << 30); /* Start of Transaction */
1035 - v |= (1 << 28); /* Write Transaction */
1036 + v |= (1 << 29); /* Read Transaction */
1037 v |= (1 << 17); /* Turnaround */
1038 - v |= (u32)device << 22;
1039 + if (pc->dev->id.revision < 10)
1040 + v |= (u32)device << 22;
1041 v |= (u32)address << 18;
1042 - v |= data;
1043 pcicore_write32(pc, mdio_data, v);
1044 /* Wait for the device to complete the transaction */
1045 udelay(10);
1046 - for (i = 0; i < 10; i++) {
1047 + for (i = 0; i < max_retries; i++) {
1048 v = pcicore_read32(pc, mdio_control);
1049 - if (v & 0x100 /* Trans complete */)
1050 + if (v & 0x100 /* Trans complete */) {
1051 + udelay(10);
1052 + ret = pcicore_read32(pc, mdio_data);
1053 break;
1054 + }
1055 msleep(1);
1056 }
1057 pcicore_write32(pc, mdio_control, 0);
1058 + return ret;
1059 }
1060
1061 -static void ssb_broadcast_value(struct ssb_device *dev,
1062 - u32 address, u32 data)
1063 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1064 + u8 address, u16 data)
1065 {
1066 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1067 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1068 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1069 + const u16 mdio_control = 0x128;
1070 + const u16 mdio_data = 0x12C;
1071 + int max_retries = 10;
1072 + u32 v;
1073 + int i;
1074
1075 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1076 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1077 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1078 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1079 -}
1080 + v = 0x80; /* Enable Preamble Sequence */
1081 + v |= 0x2; /* MDIO Clock Divisor */
1082 + pcicore_write32(pc, mdio_control, v);
1083
1084 -static void ssb_commit_settings(struct ssb_bus *bus)
1085 -{
1086 - struct ssb_device *dev;
1087 + if (pc->dev->id.revision >= 10) {
1088 + max_retries = 200;
1089 + ssb_pcie_mdio_set_phy(pc, device);
1090 + }
1091
1092 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1093 - if (WARN_ON(!dev))
1094 - return;
1095 - /* This forces an update of the cached registers. */
1096 - ssb_broadcast_value(dev, 0xFD8, 0);
1097 + v = (1 << 30); /* Start of Transaction */
1098 + v |= (1 << 28); /* Write Transaction */
1099 + v |= (1 << 17); /* Turnaround */
1100 + if (pc->dev->id.revision < 10)
1101 + v |= (u32)device << 22;
1102 + v |= (u32)address << 18;
1103 + v |= data;
1104 + pcicore_write32(pc, mdio_data, v);
1105 + /* Wait for the device to complete the transaction */
1106 + udelay(10);
1107 + for (i = 0; i < max_retries; i++) {
1108 + v = pcicore_read32(pc, mdio_control);
1109 + if (v & 0x100 /* Trans complete */)
1110 + break;
1111 + msleep(1);
1112 + }
1113 + pcicore_write32(pc, mdio_control, 0);
1114 }
1115
1116 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1117 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1118 if (pc->setup_done)
1119 goto out;
1120 if (pdev->id.coreid == SSB_DEV_PCI) {
1121 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1122 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1123 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1124 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1125 -
1126 - if (pdev->id.revision < 5) {
1127 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1128 - tmp &= ~SSB_IMCFGLO_SERTO;
1129 - tmp |= 2;
1130 - tmp &= ~SSB_IMCFGLO_REQTO;
1131 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1132 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1133 - ssb_commit_settings(bus);
1134 - } else if (pdev->id.revision >= 11) {
1135 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1136 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1137 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1138 - }
1139 + ssb_pcicore_pci_setup_workarounds(pc);
1140 } else {
1141 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1142 - //TODO: Better make defines for all these magic PCIE values.
1143 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1144 - /* TLP Workaround register. */
1145 - tmp = ssb_pcie_read(pc, 0x4);
1146 - tmp |= 0x8;
1147 - ssb_pcie_write(pc, 0x4, tmp);
1148 - }
1149 - if (pdev->id.revision == 0) {
1150 - const u8 serdes_rx_device = 0x1F;
1151 -
1152 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1153 - 2 /* Timer */, 0x8128);
1154 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1155 - 6 /* CDR */, 0x0100);
1156 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1157 - 7 /* CDR BW */, 0x1466);
1158 - } else if (pdev->id.revision == 1) {
1159 - /* DLLP Link Control register. */
1160 - tmp = ssb_pcie_read(pc, 0x100);
1161 - tmp |= 0x40;
1162 - ssb_pcie_write(pc, 0x100, tmp);
1163 - }
1164 + ssb_pcicore_pcie_setup_workarounds(pc);
1165 }
1166 pc->setup_done = 1;
1167 out:
1168 --- a/drivers/ssb/pcihost_wrapper.c
1169 +++ b/drivers/ssb/pcihost_wrapper.c
1170 @@ -6,7 +6,7 @@
1171 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1172 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1173 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1174 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1175 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1176 *
1177 * Licensed under the GNU/GPL. See COPYING for details.
1178 */
1179 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
1180 # define ssb_pcihost_resume NULL
1181 #endif /* CONFIG_PM */
1182
1183 -static int ssb_pcihost_probe(struct pci_dev *dev,
1184 - const struct pci_device_id *id)
1185 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1186 + const struct pci_device_id *id)
1187 {
1188 struct ssb_bus *ssb;
1189 int err = -ENOMEM;
1190 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
1191 pci_set_drvdata(dev, NULL);
1192 }
1193
1194 -int ssb_pcihost_register(struct pci_driver *driver)
1195 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
1196 {
1197 driver->probe = ssb_pcihost_probe;
1198 driver->remove = ssb_pcihost_remove;
1199 --- a/drivers/ssb/scan.c
1200 +++ b/drivers/ssb/scan.c
1201 @@ -2,7 +2,7 @@
1202 * Sonics Silicon Backplane
1203 * Bus scanning
1204 *
1205 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
1206 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
1207 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1208 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1209 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1210 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
1211 #ifdef CONFIG_SSB_PCIHOST
1212 if (bus->bustype == SSB_BUSTYPE_PCI) {
1213 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1214 - bus->host_pci->device == 0x4324)
1215 + ((bus->host_pci->device == 0x4313) ||
1216 + (bus->host_pci->device == 0x431A) ||
1217 + (bus->host_pci->device == 0x4321) ||
1218 + (bus->host_pci->device == 0x4324)))
1219 return 1;
1220 }
1221 #endif /* CONFIG_SSB_PCIHOST */
1222 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1223 } else {
1224 if (bus->bustype == SSB_BUSTYPE_PCI) {
1225 bus->chip_id = pcidev_to_chipid(bus->host_pci);
1226 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1227 - &bus->chip_rev);
1228 + bus->chip_rev = bus->host_pci->revision;
1229 bus->chip_package = 0;
1230 } else {
1231 bus->chip_id = 0x4710;
1232 --- a/drivers/ssb/sprom.c
1233 +++ b/drivers/ssb/sprom.c
1234 @@ -2,7 +2,7 @@
1235 * Sonics Silicon Backplane
1236 * Common SPROM support routines
1237 *
1238 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1239 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1240 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1241 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1242 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1243 @@ -17,7 +17,7 @@
1244 #include <linux/slab.h>
1245
1246
1247 -static const struct ssb_sprom *fallback_sprom;
1248 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1249
1250
1251 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1252 @@ -145,36 +145,43 @@ out:
1253 }
1254
1255 /**
1256 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1257 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1258 + * fallback SPROM if no SPROM is found.
1259 *
1260 - * @sprom: The SPROM data structure to register.
1261 + * @sprom_callback: The callback function.
1262 *
1263 - * With this function the architecture implementation may register a fallback
1264 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1265 - * where no valid SPROM can be found in the shadow registers.
1266 + * With this function the architecture implementation may register a
1267 + * callback handler which fills the SPROM data structure. The fallback is
1268 + * only used for PCI based SSB devices, where no valid SPROM can be found
1269 + * in the shadow registers.
1270 + *
1271 + * This function is useful for weird architectures that have a half-assed
1272 + * SSB device hardwired to their PCI bus.
1273 + *
1274 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1275 + * devices currently don't use this fallback.
1276 + * Architectures must provide the SPROM for native SSB devices anyway, so
1277 + * the fallback also isn't used for native devices.
1278 *
1279 - * This function is useful for weird architectures that have a half-assed SSB device
1280 - * hardwired to their PCI bus.
1281 - *
1282 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1283 - * don't use this fallback.
1284 - * Architectures must provide the SPROM for native SSB devices anyway,
1285 - * so the fallback also isn't used for native devices.
1286 - *
1287 - * This function is available for architecture code, only. So it is not exported.
1288 + * This function is available for architecture code, only. So it is not
1289 + * exported.
1290 */
1291 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1292 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1293 + struct ssb_sprom *out))
1294 {
1295 - if (fallback_sprom)
1296 + if (get_fallback_sprom)
1297 return -EEXIST;
1298 - fallback_sprom = sprom;
1299 + get_fallback_sprom = sprom_callback;
1300
1301 return 0;
1302 }
1303
1304 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1305 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1306 {
1307 - return fallback_sprom;
1308 + if (!get_fallback_sprom)
1309 + return -ENOENT;
1310 +
1311 + return get_fallback_sprom(bus, out);
1312 }
1313
1314 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1315 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1316 /* this routine differs from specs as we do not access SPROM directly
1317 on PCMCIA */
1318 if (bus->bustype == SSB_BUSTYPE_PCI &&
1319 - bus->chipco.dev && /* can be unavailible! */
1320 + bus->chipco.dev && /* can be unavailable! */
1321 bus->chipco.dev->id.revision >= 31)
1322 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1323
1324 --- a/drivers/ssb/ssb_private.h
1325 +++ b/drivers/ssb/ssb_private.h
1326 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1327 const char *buf, size_t count,
1328 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1329 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1330 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1331 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1332 + struct ssb_sprom *out);
1333
1334
1335 /* core.c */
1336 --- a/include/linux/ssb/ssb.h
1337 +++ b/include/linux/ssb/ssb.h
1338 @@ -16,6 +16,12 @@ struct pcmcia_device;
1339 struct ssb_bus;
1340 struct ssb_driver;
1341
1342 +struct ssb_sprom_core_pwr_info {
1343 + u8 itssi_2g, itssi_5g;
1344 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
1345 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
1346 +};
1347 +
1348 struct ssb_sprom {
1349 u8 revision;
1350 u8 il0mac[6]; /* MAC address for 802.11b/g */
1351 @@ -25,8 +31,10 @@ struct ssb_sprom {
1352 u8 et1phyaddr; /* MII address for enet1 */
1353 u8 et0mdcport; /* MDIO for enet0 */
1354 u8 et1mdcport; /* MDIO for enet1 */
1355 - u8 board_rev; /* Board revision number from SPROM. */
1356 + u16 board_rev; /* Board revision number from SPROM. */
1357 u8 country_code; /* Country Code */
1358 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1359 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1360 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1361 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1362 u16 pa0b0;
1363 @@ -80,6 +88,8 @@ struct ssb_sprom {
1364 u16 boardflags2_hi; /* Board flags (bits 48-63) */
1365 /* TODO store board flags in a single u64 */
1366
1367 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
1368 +
1369 /* Antenna gain values for up to 4 antennas
1370 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
1371 * loss in the connectors is bigger than the gain. */
1372 @@ -92,6 +102,15 @@ struct ssb_sprom {
1373 } ghz5; /* 5GHz band */
1374 } antenna_gain;
1375
1376 + struct {
1377 + struct {
1378 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1379 + } ghz2;
1380 + struct {
1381 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1382 + } ghz5;
1383 + } fem;
1384 +
1385 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1386 };
1387
1388 @@ -99,7 +118,7 @@ struct ssb_sprom {
1389 struct ssb_boardinfo {
1390 u16 vendor;
1391 u16 type;
1392 - u16 rev;
1393 + u8 rev;
1394 };
1395
1396
1397 @@ -229,10 +248,9 @@ struct ssb_driver {
1398 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1399
1400 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1401 -static inline int ssb_driver_register(struct ssb_driver *drv)
1402 -{
1403 - return __ssb_driver_register(drv, THIS_MODULE);
1404 -}
1405 +#define ssb_driver_register(drv) \
1406 + __ssb_driver_register(drv, THIS_MODULE)
1407 +
1408 extern void ssb_driver_unregister(struct ssb_driver *drv);
1409
1410
1411 @@ -308,7 +326,7 @@ struct ssb_bus {
1412
1413 /* ID information about the Chip. */
1414 u16 chip_id;
1415 - u16 chip_rev;
1416 + u8 chip_rev;
1417 u16 sprom_offset;
1418 u16 sprom_size; /* number of words in sprom */
1419 u8 chip_package;
1420 @@ -404,7 +422,9 @@ extern bool ssb_is_sprom_available(struc
1421
1422 /* Set a fallback SPROM.
1423 * See kdoc at the function definition for complete documentation. */
1424 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1425 +extern int ssb_arch_register_fallback_sprom(
1426 + int (*sprom_callback)(struct ssb_bus *bus,
1427 + struct ssb_sprom *out));
1428
1429 /* Suspend a SSB bus.
1430 * Call this from the parent bus suspend routine. */
1431 @@ -518,6 +538,7 @@ extern int ssb_bus_may_powerdown(struct
1432 * Otherwise static always-on powercontrol will be used. */
1433 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1434
1435 +extern void ssb_commit_settings(struct ssb_bus *bus);
1436
1437 /* Various helper functions */
1438 extern u32 ssb_admatch_base(u32 adm);
1439 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1440 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1441 @@ -8,7 +8,7 @@
1442 * gpio interface, extbus, and support for serial and parallel flashes.
1443 *
1444 * Copyright 2005, Broadcom Corporation
1445 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1446 + * Copyright 2006, Michael Buesch <m@bues.ch>
1447 *
1448 * Licensed under the GPL version 2. See COPYING for details.
1449 */
1450 @@ -123,6 +123,8 @@
1451 #define SSB_CHIPCO_FLASHDATA 0x0048
1452 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1453 #define SSB_CHIPCO_BCAST_DATA 0x0054
1454 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1455 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1456 #define SSB_CHIPCO_GPIOIN 0x0060
1457 #define SSB_CHIPCO_GPIOOUT 0x0064
1458 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1459 @@ -131,6 +133,9 @@
1460 #define SSB_CHIPCO_GPIOIRQ 0x0074
1461 #define SSB_CHIPCO_WATCHDOG 0x0080
1462 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1463 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1464 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1465 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1466 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1467 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1468 #define SSB_CHIPCO_CLOCK_N 0x0090
1469 @@ -189,8 +194,10 @@
1470 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1471 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1472 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1473 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1474 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1475 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1476 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1477 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1478 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1479 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1480 #define SSB_CHIPCO_UART0_DATA 0x0300
1481 #define SSB_CHIPCO_UART0_IMR 0x0304
1482 --- a/drivers/ssb/b43_pci_bridge.c
1483 +++ b/drivers/ssb/b43_pci_bridge.c
1484 @@ -5,12 +5,13 @@
1485 * because of its small size we include it in the SSB core
1486 * instead of creating a standalone module.
1487 *
1488 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1489 + * Copyright 2007 Michael Buesch <m@bues.ch>
1490 *
1491 * Licensed under the GNU/GPL. See COPYING for details.
1492 */
1493
1494 #include <linux/pci.h>
1495 +#include <linux/module.h>
1496 #include <linux/ssb/ssb.h>
1497
1498 #include "ssb_private.h"
1499 --- a/drivers/ssb/driver_extif.c
1500 +++ b/drivers/ssb/driver_extif.c
1501 @@ -3,7 +3,7 @@
1502 * Broadcom EXTIF core driver
1503 *
1504 * Copyright 2005, Broadcom Corporation
1505 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1506 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1507 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1508 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1509 *
1510 --- a/drivers/ssb/driver_mipscore.c
1511 +++ b/drivers/ssb/driver_mipscore.c
1512 @@ -3,7 +3,7 @@
1513 * Broadcom MIPS core driver
1514 *
1515 * Copyright 2005, Broadcom Corporation
1516 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1517 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1518 *
1519 * Licensed under the GNU/GPL. See COPYING for details.
1520 */
1521 --- a/drivers/ssb/embedded.c
1522 +++ b/drivers/ssb/embedded.c
1523 @@ -3,7 +3,7 @@
1524 * Embedded systems support code
1525 *
1526 * Copyright 2005-2008, Broadcom Corporation
1527 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1528 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1529 *
1530 * Licensed under the GNU/GPL. See COPYING for details.
1531 */
1532 --- a/drivers/ssb/pcmcia.c
1533 +++ b/drivers/ssb/pcmcia.c
1534 @@ -3,7 +3,7 @@
1535 * PCMCIA-Hostbus related functions
1536 *
1537 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1538 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1539 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1540 *
1541 * Licensed under the GNU/GPL. See COPYING for details.
1542 */
1543 --- a/drivers/ssb/sdio.c
1544 +++ b/drivers/ssb/sdio.c
1545 @@ -6,7 +6,7 @@
1546 *
1547 * Based on drivers/ssb/pcmcia.c
1548 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1549 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1550 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1551 *
1552 * Licensed under the GNU/GPL. See COPYING for details.
1553 *
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