package/mac80211/patches/464-ath5k_optimize_tx_desc_setup.patch

   1 --- a/drivers/net/wireless/ath/ath5k/desc.c
   2 +++ b/drivers/net/wireless/ath/ath5k/desc.c
   3 @@ -184,6 +184,7 @@ static int ath5k_hw_setup_4word_tx_desc(
   4  {
   5         struct ath5k_hw_4w_tx_ctl *tx_ctl;
   6         unsigned int frame_len;
   7 +       u32 txctl0 = 0, txctl1 = 0, txctl2 = 0, txctl3 = 0;
   8
   9         tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
  10
  11 @@ -209,7 +210,8 @@ static int ath5k_hw_setup_4word_tx_desc(
  12                 tx_power = AR5K_TUNE_MAX_TXPOWER;
  13
  14         /* Clear descriptor */
  15 -       memset(&desc->ud.ds_tx5212, 0, sizeof(struct ath5k_hw_5212_tx_desc));
  16 +       memset(&desc->ud.ds_tx5212.tx_stat, 0,
  17 +              sizeof(desc->ud.ds_tx5212.tx_stat));
  18
  19         /* Setup control descriptor */
  20
  21 @@ -221,7 +223,7 @@ static int ath5k_hw_setup_4word_tx_desc(
  22         if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
  23                 return -EINVAL;
  24
  25 -       tx_ctl->tx_control_0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
  26 +       txctl0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
  27
  28         /* Verify and set buffer length */
  29
  30 @@ -232,21 +234,17 @@ static int ath5k_hw_setup_4word_tx_desc(
  31         if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
  32                 return -EINVAL;
  33
  34 -       tx_ctl->tx_control_1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
  35 +       txctl1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
  36
  37 -       tx_ctl->tx_control_0 |=
  38 -               AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
  39 -               AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
  40 -       tx_ctl->tx_control_1 |= AR5K_REG_SM(type,
  41 -                                       AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
  42 -       tx_ctl->tx_control_2 = AR5K_REG_SM(tx_tries0,
  43 -                                       AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
  44 -       tx_ctl->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
  45 +       txctl0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
  46 +                 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
  47 +       txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
  48 +       txctl2 = AR5K_REG_SM(tx_tries0, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
  49 +       txctl3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
  50
  51  #define _TX_FLAGS(_c, _flag)                                   \
  52         if (flags & AR5K_TXDESC_##_flag) {                      \
  53 -               tx_ctl->tx_control_##_c |=                      \
  54 -                       AR5K_4W_TX_DESC_CTL##_c##_##_flag;      \
  55 +               txctl##_c |= AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
  56         }
  57
  58         _TX_FLAGS(0, CLRDMASK);
  59 @@ -262,8 +260,8 @@ static int ath5k_hw_setup_4word_tx_desc(
  60          * WEP crap
  61          */
  62         if (key_index != AR5K_TXKEYIX_INVALID) {
  63 -               tx_ctl->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
  64 -               tx_ctl->tx_control_1 |= AR5K_REG_SM(key_index,
  65 +               txctl0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
  66 +               txctl1 |= AR5K_REG_SM(key_index,
  67                                 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
  68         }
  69
  70 @@ -274,12 +272,16 @@ static int ath5k_hw_setup_4word_tx_desc(
  71                 if ((flags & AR5K_TXDESC_RTSENA) &&
  72                                 (flags & AR5K_TXDESC_CTSENA))
  73                         return -EINVAL;
  74 -               tx_ctl->tx_control_2 |= rtscts_duration &
  75 -                               AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
  76 -               tx_ctl->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
  77 +               txctl2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
  78 +               txctl3 |= AR5K_REG_SM(rtscts_rate,
  79                                 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
  80         }
  81
  82 +       tx_ctl->tx_control_0 = txctl0;
  83 +       tx_ctl->tx_control_1 = txctl1;
  84 +       tx_ctl->tx_control_2 = txctl2;
  85 +       tx_ctl->tx_control_3 = txctl3;
  86 +
  87         return 0;
  88  }
  89