target/linux/orion/patches/004-make_window_setup_a_little_more_safe.patch

   1 Currently, Orion window setup uses hardcoded window indexes for each
   2 of the boot/cs0/cs1/cs2/PCIe WA windows.  The static window allocation
   3 used can clash if board support code will ever attempt to configure
   4 both a dev2 and a PCIe WA window, as both of those use CPU mbus window
   5 #7 at present.
   6
   7 This patch keeps track of the last used window, and opens subsequently
   8 requested windows sequentially, starting from 4.  (Windows 0-3 are used
   9 as MEM/IO windows for the PCI/PCIe buses.)
  10
  11 Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
  12 ---
  13  arch/arm/mach-orion5x/addr-map.c |   20 +++++++++++++++-----
  14  1 files changed, 15 insertions(+), 5 deletions(-)
  15
  16 --- a/arch/arm/mach-orion5x/addr-map.c
  17 +++ b/arch/arm/mach-orion5x/addr-map.c
  18 @@ -70,6 +70,7 @@
  19
  20
  21  struct mbus_dram_target_info orion5x_mbus_dram_info;
  22 +static int __initdata win_alloc_count;
  23
  24  static int __init orion5x_cpu_win_can_remap(int win)
  25  {
  26 @@ -87,6 +88,9 @@
  27  static void __init setup_cpu_win(int win, u32 base, u32 size,
  28                                  u8 target, u8 attr, int remap)
  29  {
  30 +       if (win >= 8)
  31 +               panic("setup_cpu_win: trying to allocate window %d\n", win);
  32 +
  33         orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000);
  34         orion5x_write(CPU_WIN_CTRL(win),
  35                 ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1);
  36 @@ -128,6 +132,7 @@
  37                 TARGET_PCIE, ATTR_PCIE_MEM, -1);
  38         setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
  39                 TARGET_PCI, ATTR_PCI_MEM, -1);
  40 +       win_alloc_count = 4;
  41
  42         /*
  43          * Setup MBUS dram target info.
  44 @@ -156,25 +161,30 @@
  45
  46  void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
  47  {
  48 -       setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
  49 +       setup_cpu_win(win_alloc_count++, base, size,
  50 +                     TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
  51  }
  52
  53  void __init orion5x_setup_dev0_win(u32 base, u32 size)
  54  {
  55 -       setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
  56 +       setup_cpu_win(win_alloc_count++, base, size,
  57 +                     TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
  58  }
  59
  60  void __init orion5x_setup_dev1_win(u32 base, u32 size)
  61  {
  62 -       setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
  63 +       setup_cpu_win(win_alloc_count++, base, size,
  64 +                     TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
  65  }
  66
  67  void __init orion5x_setup_dev2_win(u32 base, u32 size)
  68  {
  69 -       setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
  70 +       setup_cpu_win(win_alloc_count++, base, size,
  71 +                     TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
  72  }
  73
  74  void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
  75  {
  76 -       setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
  77 +       setup_cpu_win(win_alloc_count++, base, size,
  78 +                     TARGET_PCIE, ATTR_PCIE_WA, -1);
  79  }