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rootfs_split fixes
[openwrt.git] / package / bcm43xx-mac80211 / src / bcm43xx / bcm43xx_main.c
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
13
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
18
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
23
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
28
29 */
30
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42
43 #include "bcm43xx.h"
44 #include "bcm43xx_main.h"
45 #include "bcm43xx_debugfs.h"
46 #include "bcm43xx_phy.h"
47 #include "bcm43xx_dma.h"
48 #include "bcm43xx_pio.h"
49 #include "bcm43xx_power.h"
50 #include "bcm43xx_sysfs.h"
51 #include "bcm43xx_xmit.h"
52 #include "bcm43xx_sysfs.h"
53 #include "bcm43xx_lo.h"
54 #include "bcm43xx_pcmcia.h"
55
56
57 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
62
63
64 extern char *nvram_get(char *name);
65
66
67 #if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
68 static int modparam_pio;
69 module_param_named(pio, modparam_pio, int, 0444);
70 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
71 #elif defined(CONFIG_BCM43XX_MAC80211_DMA)
72 # define modparam_pio 0
73 #elif defined(CONFIG_BCM43XX_MAC80211_PIO)
74 # define modparam_pio 1
75 #endif
76
77 static int modparam_bad_frames_preempt;
78 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
79 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
80
81 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
82 module_param_named(short_retry, modparam_short_retry, int, 0444);
83 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
84
85 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
86 module_param_named(long_retry, modparam_long_retry, int, 0444);
87 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
88
89 static int modparam_noleds;
90 module_param_named(noleds, modparam_noleds, int, 0444);
91 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
92
93 static char modparam_fwpostfix[16];
94 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
95 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
96
97 static int modparam_mon_keep_bad;
98 module_param_named(mon_keep_bad, modparam_mon_keep_bad, int, 0444);
99 MODULE_PARM_DESC(mon_keep_bad, "Keep bad frames in monitor mode");
100
101 static int modparam_mon_keep_badplcp;
102 module_param_named(mon_keep_badplcp, modparam_mon_keep_bad, int, 0444);
103 MODULE_PARM_DESC(mon_keep_badplcp, "Keep frames with bad PLCP in monitor mode");
104
105
106 static const struct ssb_device_id bcm43xx_ssb_tbl[] = {
107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, SSB_ANY_REV),
108 SSB_DEVTABLE_END
109 };
110 MODULE_DEVICE_TABLE(ssb, bcm43xx_ssb_tbl);
111
112
113 /* Channel and ratetables are shared for all devices.
114 * They can't be const, because ieee80211 puts some precalculated
115 * data in there. This data is the same for all devices, so we don't
116 * get concurrency issues */
117 #define RATETAB_ENT(_rateid, _flags) \
118 { \
119 .rate = BCM43xx_RATE_TO_BASE100KBPS(_rateid), \
120 .val = (_rateid), \
121 .val2 = (_rateid), \
122 .flags = (_flags), \
123 }
124 static struct ieee80211_rate __bcm43xx_ratetable[] = {
125 RATETAB_ENT(BCM43xx_CCK_RATE_1MB, IEEE80211_RATE_CCK),
126 RATETAB_ENT(BCM43xx_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
127 RATETAB_ENT(BCM43xx_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
128 RATETAB_ENT(BCM43xx_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
129 RATETAB_ENT(BCM43xx_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
130 RATETAB_ENT(BCM43xx_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
131 RATETAB_ENT(BCM43xx_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
132 RATETAB_ENT(BCM43xx_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
133 RATETAB_ENT(BCM43xx_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
134 RATETAB_ENT(BCM43xx_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
135 RATETAB_ENT(BCM43xx_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
136 RATETAB_ENT(BCM43xx_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
137 };
138 #define bcm43xx_a_ratetable (__bcm43xx_ratetable + 4)
139 #define bcm43xx_a_ratetable_size 8
140 #define bcm43xx_b_ratetable (__bcm43xx_ratetable + 0)
141 #define bcm43xx_b_ratetable_size 4
142 #define bcm43xx_g_ratetable (__bcm43xx_ratetable + 0)
143 #define bcm43xx_g_ratetable_size 12
144
145 #define CHANTAB_ENT(_chanid, _freq) \
146 { \
147 .chan = (_chanid), \
148 .freq = (_freq), \
149 .val = (_chanid), \
150 .flag = IEEE80211_CHAN_W_SCAN | \
151 IEEE80211_CHAN_W_ACTIVE_SCAN | \
152 IEEE80211_CHAN_W_IBSS, \
153 .power_level = 0xFF, \
154 .antenna_max = 0xFF, \
155 }
156 static struct ieee80211_channel bcm43xx_bg_chantable[] = {
157 CHANTAB_ENT(1, 2412),
158 CHANTAB_ENT(2, 2417),
159 CHANTAB_ENT(3, 2422),
160 CHANTAB_ENT(4, 2427),
161 CHANTAB_ENT(5, 2432),
162 CHANTAB_ENT(6, 2437),
163 CHANTAB_ENT(7, 2442),
164 CHANTAB_ENT(8, 2447),
165 CHANTAB_ENT(9, 2452),
166 CHANTAB_ENT(10, 2457),
167 CHANTAB_ENT(11, 2462),
168 CHANTAB_ENT(12, 2467),
169 CHANTAB_ENT(13, 2472),
170 CHANTAB_ENT(14, 2484),
171 };
172 #define bcm43xx_bg_chantable_size ARRAY_SIZE(bcm43xx_bg_chantable)
173 static struct ieee80211_channel bcm43xx_a_chantable[] = {
174 CHANTAB_ENT(36, 5180),
175 CHANTAB_ENT(40, 5200),
176 CHANTAB_ENT(44, 5220),
177 CHANTAB_ENT(48, 5240),
178 CHANTAB_ENT(52, 5260),
179 CHANTAB_ENT(56, 5280),
180 CHANTAB_ENT(60, 5300),
181 CHANTAB_ENT(64, 5320),
182 CHANTAB_ENT(149, 5745),
183 CHANTAB_ENT(153, 5765),
184 CHANTAB_ENT(157, 5785),
185 CHANTAB_ENT(161, 5805),
186 CHANTAB_ENT(165, 5825),
187 };
188 #define bcm43xx_a_chantable_size ARRAY_SIZE(bcm43xx_a_chantable)
189
190
191 static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev);
192 static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev);
193 static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev);
194 static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev);
195
196
197 static void bcm43xx_ram_write(struct bcm43xx_wldev *dev, u16 offset, u32 val)
198 {
199 u32 status;
200
201 assert(offset % 4 == 0);
202
203 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
204 if (status & BCM43xx_SBF_XFER_REG_BYTESWAP)
205 val = swab32(val);
206
207 bcm43xx_write32(dev, BCM43xx_MMIO_RAM_CONTROL, offset);
208 mmiowb();
209 bcm43xx_write32(dev, BCM43xx_MMIO_RAM_DATA, val);
210 }
211
212 static inline
213 void bcm43xx_shm_control_word(struct bcm43xx_wldev *dev,
214 u16 routing, u16 offset)
215 {
216 u32 control;
217
218 /* "offset" is the WORD offset. */
219
220 control = routing;
221 control <<= 16;
222 control |= offset;
223 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_CONTROL, control);
224 }
225
226 u32 bcm43xx_shm_read32(struct bcm43xx_wldev *dev,
227 u16 routing, u16 offset)
228 {
229 u32 ret;
230
231 if (routing == BCM43xx_SHM_SHARED) {
232 assert((offset & 0x0001) == 0);
233 if (offset & 0x0003) {
234 /* Unaligned access */
235 bcm43xx_shm_control_word(dev, routing, offset >> 2);
236 ret = bcm43xx_read16(dev,
237 BCM43xx_MMIO_SHM_DATA_UNALIGNED);
238 ret <<= 16;
239 bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
240 ret |= bcm43xx_read16(dev,
241 BCM43xx_MMIO_SHM_DATA);
242
243 return ret;
244 }
245 offset >>= 2;
246 }
247 bcm43xx_shm_control_word(dev, routing, offset);
248 ret = bcm43xx_read32(dev, BCM43xx_MMIO_SHM_DATA);
249
250 return ret;
251 }
252
253 u16 bcm43xx_shm_read16(struct bcm43xx_wldev *dev,
254 u16 routing, u16 offset)
255 {
256 u16 ret;
257
258 if (routing == BCM43xx_SHM_SHARED) {
259 assert((offset & 0x0001) == 0);
260 if (offset & 0x0003) {
261 /* Unaligned access */
262 bcm43xx_shm_control_word(dev, routing, offset >> 2);
263 ret = bcm43xx_read16(dev,
264 BCM43xx_MMIO_SHM_DATA_UNALIGNED);
265
266 return ret;
267 }
268 offset >>= 2;
269 }
270 bcm43xx_shm_control_word(dev, routing, offset);
271 ret = bcm43xx_read16(dev, BCM43xx_MMIO_SHM_DATA);
272
273 return ret;
274 }
275
276 void bcm43xx_shm_write32(struct bcm43xx_wldev *dev,
277 u16 routing, u16 offset,
278 u32 value)
279 {
280 if (routing == BCM43xx_SHM_SHARED) {
281 assert((offset & 0x0001) == 0);
282 if (offset & 0x0003) {
283 /* Unaligned access */
284 bcm43xx_shm_control_word(dev, routing, offset >> 2);
285 mmiowb();
286 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
287 (value >> 16) & 0xffff);
288 mmiowb();
289 bcm43xx_shm_control_word(dev, routing, (offset >> 2) + 1);
290 mmiowb();
291 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA,
292 value & 0xffff);
293 return;
294 }
295 offset >>= 2;
296 }
297 bcm43xx_shm_control_word(dev, routing, offset);
298 mmiowb();
299 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, value);
300 }
301
302 void bcm43xx_shm_write16(struct bcm43xx_wldev *dev,
303 u16 routing, u16 offset,
304 u16 value)
305 {
306 if (routing == BCM43xx_SHM_SHARED) {
307 assert((offset & 0x0001) == 0);
308 if (offset & 0x0003) {
309 /* Unaligned access */
310 bcm43xx_shm_control_word(dev, routing, offset >> 2);
311 mmiowb();
312 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
313 value);
314 return;
315 }
316 offset >>= 2;
317 }
318 bcm43xx_shm_control_word(dev, routing, offset);
319 mmiowb();
320 bcm43xx_write16(dev, BCM43xx_MMIO_SHM_DATA, value);
321 }
322
323 /* Read HostFlags */
324 u32 bcm43xx_hf_read(struct bcm43xx_wldev *dev)
325 {
326 u32 ret;
327
328 ret = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
329 BCM43xx_SHM_SH_HOSTFHI);
330 ret <<= 16;
331 ret |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
332 BCM43xx_SHM_SH_HOSTFLO);
333
334 return ret;
335 }
336
337 /* Write HostFlags */
338 void bcm43xx_hf_write(struct bcm43xx_wldev *dev, u32 value)
339 {
340 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
341 BCM43xx_SHM_SH_HOSTFLO,
342 (value & 0x0000FFFF));
343 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
344 BCM43xx_SHM_SH_HOSTFHI,
345 ((value & 0xFFFF0000) >> 16));
346 }
347
348 void bcm43xx_tsf_read(struct bcm43xx_wldev *dev, u64 *tsf)
349 {
350 /* We need to be careful. As we read the TSF from multiple
351 * registers, we should take care of register overflows.
352 * In theory, the whole tsf read process should be atomic.
353 * We try to be atomic here, by restaring the read process,
354 * if any of the high registers changed (overflew).
355 */
356 if (dev->dev->id.revision >= 3) {
357 u32 low, high, high2;
358
359 do {
360 high = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
361 low = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
362 high2 = bcm43xx_read32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
363 } while (unlikely(high != high2));
364
365 *tsf = high;
366 *tsf <<= 32;
367 *tsf |= low;
368 } else {
369 u64 tmp;
370 u16 v0, v1, v2, v3;
371 u16 test1, test2, test3;
372
373 do {
374 v3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
375 v2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
376 v1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
377 v0 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_0);
378
379 test3 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_3);
380 test2 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_2);
381 test1 = bcm43xx_read16(dev, BCM43xx_MMIO_TSF_1);
382 } while (v3 != test3 || v2 != test2 || v1 != test1);
383
384 *tsf = v3;
385 *tsf <<= 48;
386 tmp = v2;
387 tmp <<= 32;
388 *tsf |= tmp;
389 tmp = v1;
390 tmp <<= 16;
391 *tsf |= tmp;
392 *tsf |= v0;
393 }
394 }
395
396 static void bcm43xx_time_lock(struct bcm43xx_wldev *dev)
397 {
398 u32 status;
399
400 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
401 status |= BCM43xx_SBF_TIME_UPDATE;
402 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
403 mmiowb();
404 }
405
406 static void bcm43xx_time_unlock(struct bcm43xx_wldev *dev)
407 {
408 u32 status;
409
410 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
411 status &= ~BCM43xx_SBF_TIME_UPDATE;
412 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
413 }
414
415 static void bcm43xx_tsf_write_locked(struct bcm43xx_wldev *dev, u64 tsf)
416 {
417 /* Be careful with the in-progress timer.
418 * First zero out the low register, so we have a full
419 * register-overflow duration to complete the operation.
420 */
421 if (dev->dev->id.revision >= 3) {
422 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
423 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
424
425 bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
426 mmiowb();
427 bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
428 mmiowb();
429 bcm43xx_write32(dev, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
430 } else {
431 u16 v0 = (tsf & 0x000000000000FFFFULL);
432 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
433 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
434 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
435
436 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, 0);
437 mmiowb();
438 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_3, v3);
439 mmiowb();
440 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_2, v2);
441 mmiowb();
442 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_1, v1);
443 mmiowb();
444 bcm43xx_write16(dev, BCM43xx_MMIO_TSF_0, v0);
445 }
446 }
447
448 void bcm43xx_tsf_write(struct bcm43xx_wldev *dev, u64 tsf)
449 {
450 bcm43xx_time_lock(dev);
451 bcm43xx_tsf_write_locked(dev, tsf);
452 bcm43xx_time_unlock(dev);
453 }
454
455 static
456 void bcm43xx_macfilter_set(struct bcm43xx_wldev *dev,
457 u16 offset,
458 const u8 *mac)
459 {
460 static const u8 zero_addr[ETH_ALEN] = { 0 };
461 u16 data;
462
463 if (!mac)
464 mac = zero_addr;
465
466 offset |= 0x0020;
467 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
468
469 data = mac[0];
470 data |= mac[1] << 8;
471 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
472 data = mac[2];
473 data |= mac[3] << 8;
474 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
475 data = mac[4];
476 data |= mac[5] << 8;
477 bcm43xx_write16(dev, BCM43xx_MMIO_MACFILTER_DATA, data);
478 }
479
480 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_wldev *dev)
481 {
482 static const u8 zero_addr[ETH_ALEN] = { 0 };
483 const u8 *mac;
484 const u8 *bssid;
485 u8 mac_bssid[ETH_ALEN * 2];
486 int i;
487 u32 tmp;
488
489 bssid = dev->wl->bssid;
490 if (!bssid)
491 bssid = zero_addr;
492 mac = dev->wl->mac_addr;
493 if (!mac)
494 mac = zero_addr;
495
496 bcm43xx_macfilter_set(dev, BCM43xx_MACFILTER_BSSID, bssid);
497
498 memcpy(mac_bssid, mac, ETH_ALEN);
499 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
500
501 /* Write our MAC address and BSSID to template ram */
502 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
503 tmp = (u32)(mac_bssid[i + 0]);
504 tmp |= (u32)(mac_bssid[i + 1]) << 8;
505 tmp |= (u32)(mac_bssid[i + 2]) << 16;
506 tmp |= (u32)(mac_bssid[i + 3]) << 24;
507 bcm43xx_ram_write(dev, 0x20 + i, tmp);
508 }
509 }
510
511 static void bcm43xx_upload_card_macaddress(struct bcm43xx_wldev *dev,
512 const u8 *mac_addr)
513 {
514 dev->wl->mac_addr = mac_addr;
515 bcm43xx_write_mac_bssid_templates(dev);
516 bcm43xx_macfilter_set(dev, BCM43xx_MACFILTER_SELF, mac_addr);
517 }
518
519 static void bcm43xx_set_slot_time(struct bcm43xx_wldev *dev, u16 slot_time)
520 {
521 /* slot_time is in usec. */
522 if (dev->phy.type != BCM43xx_PHYTYPE_G)
523 return;
524 bcm43xx_write16(dev, 0x684, 510 + slot_time);
525 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0010, slot_time);
526 }
527
528 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_wldev *dev)
529 {
530 bcm43xx_set_slot_time(dev, 9);
531 dev->short_slot = 1;
532 }
533
534 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_wldev *dev)
535 {
536 bcm43xx_set_slot_time(dev, 20);
537 dev->short_slot = 0;
538 }
539
540 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
541 * Returns the _previously_ enabled IRQ mask.
542 */
543 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_wldev *dev, u32 mask)
544 {
545 u32 old_mask;
546
547 old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
548 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
549
550 return old_mask;
551 }
552
553 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
554 * Returns the _previously_ enabled IRQ mask.
555 */
556 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_wldev *dev, u32 mask)
557 {
558 u32 old_mask;
559
560 old_mask = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
561 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
562
563 return old_mask;
564 }
565
566 /* Synchronize IRQ top- and bottom-half.
567 * IRQs must be masked before calling this.
568 * This must not be called with the irq_lock held.
569 */
570 static void bcm43xx_synchronize_irq(struct bcm43xx_wldev *dev)
571 {
572 synchronize_irq(dev->dev->irq);
573 tasklet_kill(&dev->isr_tasklet);
574 }
575
576 /* DummyTransmission function, as documented on
577 * http://bcm-specs.sipsolutions.net/DummyTransmission
578 */
579 void bcm43xx_dummy_transmission(struct bcm43xx_wldev *dev)
580 {
581 struct bcm43xx_phy *phy = &dev->phy;
582 unsigned int i, max_loop;
583 u16 value;
584 u32 buffer[5] = {
585 0x00000000,
586 0x00D40000,
587 0x00000000,
588 0x01000000,
589 0x00000000,
590 };
591
592 switch (phy->type) {
593 case BCM43xx_PHYTYPE_A:
594 max_loop = 0x1E;
595 buffer[0] = 0x000201CC;
596 break;
597 case BCM43xx_PHYTYPE_B:
598 case BCM43xx_PHYTYPE_G:
599 max_loop = 0xFA;
600 buffer[0] = 0x000B846E;
601 break;
602 default:
603 assert(0);
604 return;
605 }
606
607 for (i = 0; i < 5; i++)
608 bcm43xx_ram_write(dev, i * 4, buffer[i]);
609
610 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
611
612 bcm43xx_write16(dev, 0x0568, 0x0000);
613 bcm43xx_write16(dev, 0x07C0, 0x0000);
614 value = ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0);
615 bcm43xx_write16(dev, 0x050C, value);
616 bcm43xx_write16(dev, 0x0508, 0x0000);
617 bcm43xx_write16(dev, 0x050A, 0x0000);
618 bcm43xx_write16(dev, 0x054C, 0x0000);
619 bcm43xx_write16(dev, 0x056A, 0x0014);
620 bcm43xx_write16(dev, 0x0568, 0x0826);
621 bcm43xx_write16(dev, 0x0500, 0x0000);
622 bcm43xx_write16(dev, 0x0502, 0x0030);
623
624 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
625 bcm43xx_radio_write16(dev, 0x0051, 0x0017);
626 for (i = 0x00; i < max_loop; i++) {
627 value = bcm43xx_read16(dev, 0x050E);
628 if (value & 0x0080)
629 break;
630 udelay(10);
631 }
632 for (i = 0x00; i < 0x0A; i++) {
633 value = bcm43xx_read16(dev, 0x050E);
634 if (value & 0x0400)
635 break;
636 udelay(10);
637 }
638 for (i = 0x00; i < 0x0A; i++) {
639 value = bcm43xx_read16(dev, 0x0690);
640 if (!(value & 0x0100))
641 break;
642 udelay(10);
643 }
644 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
645 bcm43xx_radio_write16(dev, 0x0051, 0x0037);
646 }
647
648 static void key_write(struct bcm43xx_wldev *dev,
649 u8 index, u8 algorithm, const u8 *key)
650 {
651 unsigned int i;
652 u32 offset;
653 u16 value;
654 u16 kidx;
655
656 /* Key index/algo block */
657 kidx = bcm43xx_kidx_to_fw(dev, index);
658 value = ((kidx << 4) | algorithm);
659 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
660 BCM43xx_SHM_SH_KEYIDXBLOCK +
661 (kidx * 2), value);
662
663 /* Write the key to the Key Table Pointer offset */
664 offset = dev->ktp + (index * BCM43xx_SEC_KEYSIZE);
665 for (i = 0; i < BCM43xx_SEC_KEYSIZE; i += 2) {
666 value = key[i];
667 value |= (u16)(key[i + 1]) << 8;
668 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
669 offset + i, value);
670 }
671 }
672
673 static void keymac_write(struct bcm43xx_wldev *dev,
674 u8 index, const u8 *addr)
675 {
676 u32 addrtmp[2];
677
678 assert(index >= 4 + 4);
679 memcpy(dev->key[index].address, addr, 6);
680 /* We have two default TX keys and two default RX keys.
681 * Physical mac 0 is mapped to physical key 8.
682 * So we must adjust the index here.
683 */
684 index -= 8;
685
686 addrtmp[0] = addr[0];
687 addrtmp[0] |= ((u32)(addr[1]) << 8);
688 addrtmp[0] |= ((u32)(addr[2]) << 16);
689 addrtmp[0] |= ((u32)(addr[3]) << 24);
690 addrtmp[1] = addr[4];
691 addrtmp[1] |= ((u32)(addr[5]) << 8);
692
693 if (dev->dev->id.revision >= 5) {
694 /* Receive match transmitter address mechanism */
695 bcm43xx_shm_write32(dev, BCM43xx_SHM_RCMTA,
696 (index * 2) + 0, addrtmp[0]);
697 bcm43xx_shm_write16(dev, BCM43xx_SHM_RCMTA,
698 (index * 2) + 1, addrtmp[1]);
699 } else {
700 /* RXE (Receive Engine) and
701 * PSM (Programmable State Machine) mechanism
702 */
703 if (index < 8) {
704 /* TODO write to RCM 16, 19, 22 and 25 */
705 TODO();
706 } else {
707 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
708 BCM43xx_SHM_SH_PSM + (index * 6) + 0,
709 addrtmp[0]);
710 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
711 BCM43xx_SHM_SH_PSM + (index * 6) + 4,
712 addrtmp[1]);
713 }
714 }
715 }
716
717 static void do_key_write(struct bcm43xx_wldev *dev,
718 u8 index, u8 algorithm,
719 const u8 *key, size_t key_len,
720 const u8 *mac_addr)
721 {
722 u8 buf[BCM43xx_SEC_KEYSIZE];
723
724 assert(index < dev->max_nr_keys);
725 assert(key_len <= BCM43xx_SEC_KEYSIZE);
726
727 memset(buf, 0, sizeof(buf));
728 if (index >= 8)
729 keymac_write(dev, index, buf); /* First zero out mac. */
730 memcpy(buf, key, key_len);
731 key_write(dev, index, algorithm, buf);
732 if (index >= 8)
733 keymac_write(dev, index, mac_addr);
734
735 dev->key[index].algorithm = algorithm;
736 }
737
738 static int bcm43xx_key_write(struct bcm43xx_wldev *dev,
739 int index, u8 algorithm,
740 const u8 *key, size_t key_len,
741 const u8 *mac_addr,
742 struct ieee80211_key_conf *keyconf)
743 {
744 int i;
745 int sta_keys_start;
746
747 if (key_len > BCM43xx_SEC_KEYSIZE)
748 return -EINVAL;
749 if (index < 0) {
750 /* Per station key with associated MAC address.
751 * Look if it already exists, if yes update, otherwise
752 * allocate a new key.
753 */
754 if (bcm43xx_new_kidx_api(dev))
755 sta_keys_start = 4;
756 else
757 sta_keys_start = 8;
758 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
759 if (compare_ether_addr(dev->key[i].address, mac_addr) == 0) {
760 /* found existing */
761 index = i;
762 break;
763 }
764 }
765 if (index < 0) {
766 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
767 if (!dev->key[i].enabled) {
768 /* found empty */
769 index = i;
770 break;
771 }
772 }
773 }
774 if (index < 0) {
775 dprintk(KERN_ERR PFX "Out of hw key memory\n");
776 return -ENOBUFS;
777 }
778 } else
779 assert(index <= 3);
780
781 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
782 if ((index <= 3) && !bcm43xx_new_kidx_api(dev)) {
783 /* Default RX key */
784 assert(mac_addr == NULL);
785 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
786 }
787 keyconf->hw_key_idx = index;
788
789 return 0;
790 }
791
792 static void bcm43xx_clear_keys(struct bcm43xx_wldev *dev)
793 {
794 static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
795 unsigned int i;
796
797 BUILD_BUG_ON(BCM43xx_SEC_KEYSIZE < ETH_ALEN);
798 for (i = 0; i < dev->max_nr_keys; i++) {
799 do_key_write(dev, i, BCM43xx_SEC_ALGO_NONE,
800 zero, BCM43xx_SEC_KEYSIZE,
801 zero);
802 dev->key[i].enabled = 0;
803 }
804 }
805
806 /* Turn the Analog ON/OFF */
807 static void bcm43xx_switch_analog(struct bcm43xx_wldev *dev, int on)
808 {
809 bcm43xx_write16(dev, BCM43xx_MMIO_PHY0, on ? 0 : 0xF4);
810 }
811
812 void bcm43xx_wireless_core_reset(struct bcm43xx_wldev *dev, u32 flags)
813 {
814 u32 tmslow;
815 u32 macctl;
816
817 flags |= BCM43xx_TMSLOW_PHYCLKEN;
818 flags |= BCM43xx_TMSLOW_PHYRESET;
819 ssb_device_enable(dev->dev, flags);
820 msleep(2); /* Wait for the PLL to turn on. */
821
822 /* Now take the PHY out of Reset again */
823 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
824 tmslow |= SSB_TMSLOW_FGC;
825 tmslow &= ~BCM43xx_TMSLOW_PHYRESET;
826 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
827 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
828 msleep(1);
829 tmslow &= ~SSB_TMSLOW_FGC;
830 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
831 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
832 msleep(1);
833
834 /* Turn Analog ON */
835 bcm43xx_switch_analog(dev, 1);
836
837 macctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
838 macctl &= ~BCM43xx_MACCTL_GMODE;
839 if (flags & BCM43xx_TMSLOW_GMODE)
840 macctl |= BCM43xx_MACCTL_GMODE;
841 macctl |= BCM43xx_MACCTL_IHR_ENABLED;
842 bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, macctl);
843 }
844
845 static void handle_irq_transmit_status(struct bcm43xx_wldev *dev)
846 {
847 u32 v0, v1;
848 u16 tmp;
849 struct bcm43xx_txstatus stat;
850
851 while (1) {
852 v0 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
853 if (!(v0 & 0x00000001))
854 break;
855 v1 = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
856
857 stat.cookie = (v0 >> 16);
858 stat.seq = (v1 & 0x0000FFFF);
859 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
860 tmp = (v0 & 0x0000FFFF);
861 stat.frame_count = ((tmp & 0xF000) >> 12);
862 stat.rts_count = ((tmp & 0x0F00) >> 8);
863 stat.supp_reason = ((tmp & 0x001C) >> 2);
864 stat.pm_indicated = !!(tmp & 0x0080);
865 stat.intermediate = !!(tmp & 0x0040);
866 stat.for_ampdu = !!(tmp & 0x0020);
867 stat.acked = !!(tmp & 0x0002);
868
869 bcm43xx_handle_txstatus(dev, &stat);
870 }
871 }
872
873 static void drain_txstatus_queue(struct bcm43xx_wldev *dev)
874 {
875 u32 dummy;
876
877 if (dev->dev->id.revision < 5)
878 return;
879 /* Read all entries from the microcode TXstatus FIFO
880 * and throw them away.
881 */
882 while (1) {
883 dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_0);
884 if (!(dummy & 0x00000001))
885 break;
886 dummy = bcm43xx_read32(dev, BCM43xx_MMIO_XMITSTAT_1);
887 }
888 }
889
890 static u32 bcm43xx_jssi_read(struct bcm43xx_wldev *dev)
891 {
892 u32 val = 0;
893
894 val = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x08A);
895 val <<= 16;
896 val |= bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x088);
897
898 return val;
899 }
900
901 static void bcm43xx_jssi_write(struct bcm43xx_wldev *dev, u32 jssi)
902 {
903 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x088,
904 (jssi & 0x0000FFFF));
905 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x08A,
906 (jssi & 0xFFFF0000) >> 16);
907 }
908
909 static void bcm43xx_generate_noise_sample(struct bcm43xx_wldev *dev)
910 {
911 bcm43xx_jssi_write(dev, 0x7F7F7F7F);
912 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
913 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
914 | (1 << 4));
915 assert(dev->noisecalc.channel_at_start == dev->phy.channel);
916 }
917
918 static void bcm43xx_calculate_link_quality(struct bcm43xx_wldev *dev)
919 {
920 /* Top half of Link Quality calculation. */
921
922 if (dev->noisecalc.calculation_running)
923 return;
924 dev->noisecalc.channel_at_start = dev->phy.channel;
925 dev->noisecalc.calculation_running = 1;
926 dev->noisecalc.nr_samples = 0;
927
928 bcm43xx_generate_noise_sample(dev);
929 }
930
931 static void handle_irq_noise(struct bcm43xx_wldev *dev)
932 {
933 struct bcm43xx_phy *phy = &dev->phy;
934 u16 tmp;
935 u8 noise[4];
936 u8 i, j;
937 s32 average;
938
939 /* Bottom half of Link Quality calculation. */
940
941 assert(dev->noisecalc.calculation_running);
942 if (dev->noisecalc.channel_at_start != phy->channel)
943 goto drop_calculation;
944 *((u32 *)noise) = cpu_to_le32(bcm43xx_jssi_read(dev));
945 if (noise[0] == 0x7F || noise[1] == 0x7F ||
946 noise[2] == 0x7F || noise[3] == 0x7F)
947 goto generate_new;
948
949 /* Get the noise samples. */
950 assert(dev->noisecalc.nr_samples < 8);
951 i = dev->noisecalc.nr_samples;
952 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
953 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
954 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
955 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
956 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
957 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
958 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
959 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
960 dev->noisecalc.nr_samples++;
961 if (dev->noisecalc.nr_samples == 8) {
962 /* Calculate the Link Quality by the noise samples. */
963 average = 0;
964 for (i = 0; i < 8; i++) {
965 for (j = 0; j < 4; j++)
966 average += dev->noisecalc.samples[i][j];
967 }
968 average /= (8 * 4);
969 average *= 125;
970 average += 64;
971 average /= 128;
972 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x40C);
973 tmp = (tmp / 128) & 0x1F;
974 if (tmp >= 8)
975 average += 2;
976 else
977 average -= 25;
978 if (tmp == 8)
979 average -= 72;
980 else
981 average -= 48;
982
983 dev->stats.link_noise = average;
984 drop_calculation:
985 dev->noisecalc.calculation_running = 0;
986 return;
987 }
988 generate_new:
989 bcm43xx_generate_noise_sample(dev);
990 }
991
992 static void handle_irq_tbtt_indication(struct bcm43xx_wldev *dev)
993 {
994 if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
995 ///TODO: PS TBTT
996 } else {
997 if (1/*FIXME: the last PSpoll frame was sent successfully */)
998 bcm43xx_power_saving_ctl_bits(dev, -1, -1);
999 }
1000 dev->reg124_set_0x4 = 0;
1001 if (bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1002 dev->reg124_set_0x4 = 1;
1003 }
1004
1005 static void handle_irq_atim_end(struct bcm43xx_wldev *dev)
1006 {
1007 if (!dev->reg124_set_0x4 /*FIXME rename this variable*/)
1008 return;
1009 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
1010 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD)
1011 | 0x4);
1012 }
1013
1014 static void handle_irq_pmq(struct bcm43xx_wldev *dev)
1015 {
1016 u32 tmp;
1017
1018 //TODO: AP mode.
1019
1020 while (1) {
1021 tmp = bcm43xx_read32(dev, BCM43xx_MMIO_PS_STATUS);
1022 if (!(tmp & 0x00000008))
1023 break;
1024 }
1025 /* 16bit write is odd, but correct. */
1026 bcm43xx_write16(dev, BCM43xx_MMIO_PS_STATUS, 0x0002);
1027 }
1028
1029 static void bcm43xx_write_template_common(struct bcm43xx_wldev *dev,
1030 const u8* data, u16 size,
1031 u16 ram_offset,
1032 u16 shm_size_offset, u8 rate)
1033 {
1034 u32 i, tmp;
1035 struct bcm43xx_plcp_hdr4 plcp;
1036
1037 plcp.data = 0;
1038 bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1039 bcm43xx_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1040 ram_offset += sizeof(u32);
1041 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1042 * So leave the first two bytes of the next write blank.
1043 */
1044 tmp = (u32)(data[0]) << 16;
1045 tmp |= (u32)(data[1]) << 24;
1046 bcm43xx_ram_write(dev, ram_offset, tmp);
1047 ram_offset += sizeof(u32);
1048 for (i = 2; i < size; i += sizeof(u32)) {
1049 tmp = (u32)(data[i + 0]);
1050 if (i + 1 < size)
1051 tmp |= (u32)(data[i + 1]) << 8;
1052 if (i + 2 < size)
1053 tmp |= (u32)(data[i + 2]) << 16;
1054 if (i + 3 < size)
1055 tmp |= (u32)(data[i + 3]) << 24;
1056 bcm43xx_ram_write(dev, ram_offset + i - 2, tmp);
1057 }
1058 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_size_offset,
1059 size + sizeof(struct bcm43xx_plcp_hdr6));
1060 }
1061
1062 static void bcm43xx_write_beacon_template(struct bcm43xx_wldev *dev,
1063 u16 ram_offset,
1064 u16 shm_size_offset, u8 rate)
1065 {
1066 int len;
1067 const u8 *data;
1068
1069 assert(dev->cached_beacon);
1070 len = min((size_t)dev->cached_beacon->len,
1071 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
1072 data = (const u8 *)(dev->cached_beacon->data);
1073 bcm43xx_write_template_common(dev, data,
1074 len, ram_offset,
1075 shm_size_offset, rate);
1076 }
1077
1078 static void bcm43xx_write_probe_resp_plcp(struct bcm43xx_wldev *dev,
1079 u16 shm_offset, u16 size, u8 rate)
1080 {
1081 struct bcm43xx_plcp_hdr4 plcp;
1082 u32 tmp;
1083 __le16 dur;
1084
1085 plcp.data = 0;
1086 bcm43xx_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1087 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1088 size,
1089 BCM43xx_RATE_TO_BASE100KBPS(rate));
1090 /* Write PLCP in two parts and timing for packet transfer */
1091 tmp = le32_to_cpu(plcp.data);
1092 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset,
1093 tmp & 0xFFFF);
1094 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 2,
1095 tmp >> 16);
1096 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, shm_offset + 6,
1097 le16_to_cpu(dur));
1098 }
1099
1100 /* Instead of using custom probe response template, this function
1101 * just patches custom beacon template by:
1102 * 1) Changing packet type
1103 * 2) Patching duration field
1104 * 3) Stripping TIM
1105 */
1106 static u8 * bcm43xx_generate_probe_resp(struct bcm43xx_wldev *dev,
1107 u16* dest_size, u8 rate)
1108 {
1109 const u8 *src_data;
1110 u8 *dest_data;
1111 u16 src_size, elem_size, src_pos, dest_pos;
1112 __le16 dur;
1113 struct ieee80211_hdr *hdr;
1114
1115 assert(dev->cached_beacon);
1116 src_size = dev->cached_beacon->len;
1117 src_data = (const u8*)dev->cached_beacon->data;
1118
1119 if (unlikely(src_size < 0x24)) {
1120 dprintk(KERN_ERR PFX "bcm43xx_generate_probe_resp: "
1121 "invalid beacon\n");
1122 return NULL;
1123 }
1124
1125 dest_data = kmalloc(src_size, GFP_ATOMIC);
1126 if (unlikely(!dest_data))
1127 return NULL;
1128
1129 /* 0x24 is offset of first variable-len Information-Element
1130 * in beacon frame.
1131 */
1132 memcpy(dest_data, src_data, 0x24);
1133 src_pos = dest_pos = 0x24;
1134 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1135 elem_size = src_data[src_pos + 1] + 2;
1136 if (src_data[src_pos] != 0x05) { /* TIM */
1137 memcpy(dest_data + dest_pos, src_data + src_pos,
1138 elem_size);
1139 dest_pos += elem_size;
1140 }
1141 }
1142 *dest_size = dest_pos;
1143 hdr = (struct ieee80211_hdr *)dest_data;
1144
1145 /* Set the frame control. */
1146 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1147 IEEE80211_STYPE_PROBE_RESP);
1148 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1149 *dest_size,
1150 BCM43xx_RATE_TO_BASE100KBPS(rate));
1151 hdr->duration_id = dur;
1152
1153 return dest_data;
1154 }
1155
1156 static void bcm43xx_write_probe_resp_template(struct bcm43xx_wldev *dev,
1157 u16 ram_offset,
1158 u16 shm_size_offset, u8 rate)
1159 {
1160 u8* probe_resp_data;
1161 u16 size;
1162
1163 assert(dev->cached_beacon);
1164 size = dev->cached_beacon->len;
1165 probe_resp_data = bcm43xx_generate_probe_resp(dev, &size, rate);
1166 if (unlikely(!probe_resp_data))
1167 return;
1168
1169 /* Looks like PLCP headers plus packet timings are stored for
1170 * all possible basic rates
1171 */
1172 bcm43xx_write_probe_resp_plcp(dev, 0x31A, size,
1173 BCM43xx_CCK_RATE_1MB);
1174 bcm43xx_write_probe_resp_plcp(dev, 0x32C, size,
1175 BCM43xx_CCK_RATE_2MB);
1176 bcm43xx_write_probe_resp_plcp(dev, 0x33E, size,
1177 BCM43xx_CCK_RATE_5MB);
1178 bcm43xx_write_probe_resp_plcp(dev, 0x350, size,
1179 BCM43xx_CCK_RATE_11MB);
1180
1181 size = min((size_t)size,
1182 0x200 - sizeof(struct bcm43xx_plcp_hdr6));
1183 bcm43xx_write_template_common(dev, probe_resp_data,
1184 size, ram_offset,
1185 shm_size_offset, rate);
1186 kfree(probe_resp_data);
1187 }
1188
1189 static int bcm43xx_refresh_cached_beacon(struct bcm43xx_wldev *dev,
1190 struct sk_buff *beacon)
1191 {
1192 if (dev->cached_beacon)
1193 kfree_skb(dev->cached_beacon);
1194 dev->cached_beacon = beacon;
1195
1196 return 0;
1197 }
1198
1199 static void bcm43xx_update_templates(struct bcm43xx_wldev *dev)
1200 {
1201 u32 status;
1202
1203 assert(dev->cached_beacon);
1204
1205 bcm43xx_write_beacon_template(dev, 0x68, 0x18,
1206 BCM43xx_CCK_RATE_1MB);
1207 bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
1208 BCM43xx_CCK_RATE_1MB);
1209 bcm43xx_write_probe_resp_template(dev, 0x268, 0x4A,
1210 BCM43xx_CCK_RATE_11MB);
1211
1212 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
1213 status |= 0x03;
1214 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1215 }
1216
1217 static void bcm43xx_refresh_templates(struct bcm43xx_wldev *dev,
1218 struct sk_buff *beacon)
1219 {
1220 int err;
1221
1222 err = bcm43xx_refresh_cached_beacon(dev, beacon);
1223 if (unlikely(err))
1224 return;
1225 bcm43xx_update_templates(dev);
1226 }
1227
1228 static void bcm43xx_set_ssid(struct bcm43xx_wldev *dev,
1229 const u8 *ssid, u8 ssid_len)
1230 {
1231 u32 tmp;
1232 u16 i, len;
1233
1234 len = min((u16)ssid_len, (u16)0x100);
1235 for (i = 0; i < len; i += sizeof(u32)) {
1236 tmp = (u32)(ssid[i + 0]);
1237 if (i + 1 < len)
1238 tmp |= (u32)(ssid[i + 1]) << 8;
1239 if (i + 2 < len)
1240 tmp |= (u32)(ssid[i + 2]) << 16;
1241 if (i + 3 < len)
1242 tmp |= (u32)(ssid[i + 3]) << 24;
1243 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED,
1244 0x380 + i, tmp);
1245 }
1246 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
1247 0x48, len);
1248 }
1249
1250 static void bcm43xx_set_beacon_int(struct bcm43xx_wldev *dev, u16 beacon_int)
1251 {
1252 bcm43xx_time_lock(dev);
1253 if (dev->dev->id.revision >= 3) {
1254 bcm43xx_write32(dev, 0x188, (beacon_int << 16));
1255 } else {
1256 bcm43xx_write16(dev, 0x606, (beacon_int >> 6));
1257 bcm43xx_write16(dev, 0x610, beacon_int);
1258 }
1259 bcm43xx_time_unlock(dev);
1260 }
1261
1262 static void handle_irq_beacon(struct bcm43xx_wldev *dev)
1263 {
1264 u32 status;
1265
1266 if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1267 return;
1268
1269 dev->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1270 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS2_BITFIELD);
1271
1272 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1273 /* ACK beacon IRQ. */
1274 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
1275 BCM43xx_IRQ_BEACON);
1276 dev->irq_savedstate |= BCM43xx_IRQ_BEACON;
1277 if (dev->cached_beacon)
1278 kfree_skb(dev->cached_beacon);
1279 dev->cached_beacon = NULL;
1280 return;
1281 }
1282 if (!(status & 0x1)) {
1283 bcm43xx_write_beacon_template(dev, 0x68, 0x18,
1284 BCM43xx_CCK_RATE_1MB);
1285 status |= 0x1;
1286 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
1287 status);
1288 }
1289 if (!(status & 0x2)) {
1290 bcm43xx_write_beacon_template(dev, 0x468, 0x1A,
1291 BCM43xx_CCK_RATE_1MB);
1292 status |= 0x2;
1293 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS2_BITFIELD,
1294 status);
1295 }
1296 }
1297
1298 static void handle_irq_ucode_debug(struct bcm43xx_wldev *dev)
1299 {
1300 //TODO
1301 }
1302
1303 /* Interrupt handler bottom-half */
1304 static void bcm43xx_interrupt_tasklet(struct bcm43xx_wldev *dev)
1305 {
1306 u32 reason;
1307 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1308 u32 merged_dma_reason = 0;
1309 int i, activity = 0;
1310 unsigned long flags;
1311
1312 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1313
1314 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
1315 assert(dev->started);
1316
1317 reason = dev->irq_reason;
1318 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1319 dma_reason[i] = dev->dma_reason[i];
1320 merged_dma_reason |= dma_reason[i];
1321 }
1322
1323 if (unlikely(reason & BCM43xx_IRQ_MAC_TXERR))
1324 printkl(KERN_ERR PFX "MAC transmission error\n");
1325
1326 if (unlikely(reason & BCM43xx_IRQ_PHY_TXERR))
1327 printkl(KERN_ERR PFX "PHY transmission error\n");
1328
1329 if (unlikely(merged_dma_reason & (BCM43xx_DMAIRQ_FATALMASK |
1330 BCM43xx_DMAIRQ_NONFATALMASK))) {
1331 if (merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK) {
1332 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1333 "0x%08X, 0x%08X, 0x%08X, "
1334 "0x%08X, 0x%08X, 0x%08X\n",
1335 dma_reason[0], dma_reason[1],
1336 dma_reason[2], dma_reason[3],
1337 dma_reason[4], dma_reason[5]);
1338 bcm43xx_controller_restart(dev, "DMA error");
1339 mmiowb();
1340 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1341 return;
1342 }
1343 if (merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK) {
1344 printkl(KERN_ERR PFX "DMA error: "
1345 "0x%08X, 0x%08X, 0x%08X, "
1346 "0x%08X, 0x%08X, 0x%08X\n",
1347 dma_reason[0], dma_reason[1],
1348 dma_reason[2], dma_reason[3],
1349 dma_reason[4], dma_reason[5]);
1350 }
1351 }
1352
1353 if (unlikely(reason & BCM43xx_IRQ_UCODE_DEBUG))
1354 handle_irq_ucode_debug(dev);
1355 if (reason & BCM43xx_IRQ_TBTT_INDI)
1356 handle_irq_tbtt_indication(dev);
1357 if (reason & BCM43xx_IRQ_ATIM_END)
1358 handle_irq_atim_end(dev);
1359 if (reason & BCM43xx_IRQ_BEACON)
1360 handle_irq_beacon(dev);
1361 if (reason & BCM43xx_IRQ_PMQ)
1362 handle_irq_pmq(dev);
1363 if (reason & BCM43xx_IRQ_TXFIFO_FLUSH_OK)
1364 ;/*TODO*/
1365 if (reason & BCM43xx_IRQ_NOISESAMPLE_OK)
1366 handle_irq_noise(dev);
1367
1368 /* Check the DMA reason registers for received data. */
1369 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1370 if (bcm43xx_using_pio(dev))
1371 bcm43xx_pio_rx(dev->pio.queue0);
1372 else
1373 bcm43xx_dma_rx(dev->dma.rx_ring0);
1374 /* We intentionally don't set "activity" to 1, here. */
1375 }
1376 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1377 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1378 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1379 if (bcm43xx_using_pio(dev))
1380 bcm43xx_pio_rx(dev->pio.queue3);
1381 else
1382 bcm43xx_dma_rx(dev->dma.rx_ring3);
1383 activity = 1;
1384 }
1385 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1386 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1387
1388 if (reason & BCM43xx_IRQ_TX_OK) {
1389 handle_irq_transmit_status(dev);
1390 activity = 1;
1391 //TODO: In AP mode, this also causes sending of powersave responses.
1392 }
1393
1394 if (!modparam_noleds)
1395 bcm43xx_leds_update(dev, activity);
1396 bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
1397 mmiowb();
1398 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1399 }
1400
1401 static void pio_irq_workaround(struct bcm43xx_wldev *dev,
1402 u16 base, int queueidx)
1403 {
1404 u16 rxctl;
1405
1406 rxctl = bcm43xx_read16(dev, base + BCM43xx_PIO_RXCTL);
1407 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1408 dev->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1409 else
1410 dev->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1411 }
1412
1413 static void bcm43xx_interrupt_ack(struct bcm43xx_wldev *dev, u32 reason)
1414 {
1415 if (bcm43xx_using_pio(dev) &&
1416 (dev->dev->id.revision < 3) &&
1417 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1418 /* Apply a PIO specific workaround to the dma_reasons */
1419 pio_irq_workaround(dev, BCM43xx_MMIO_PIO1_BASE, 0);
1420 pio_irq_workaround(dev, BCM43xx_MMIO_PIO2_BASE, 1);
1421 pio_irq_workaround(dev, BCM43xx_MMIO_PIO3_BASE, 2);
1422 pio_irq_workaround(dev, BCM43xx_MMIO_PIO4_BASE, 3);
1423 }
1424
1425 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1426
1427 bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_REASON,
1428 dev->dma_reason[0]);
1429 bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_REASON,
1430 dev->dma_reason[1]);
1431 bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_REASON,
1432 dev->dma_reason[2]);
1433 bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_REASON,
1434 dev->dma_reason[3]);
1435 bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_REASON,
1436 dev->dma_reason[4]);
1437 bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_REASON,
1438 dev->dma_reason[5]);
1439 }
1440
1441 /* Interrupt handler top-half */
1442 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id)
1443 {
1444 irqreturn_t ret = IRQ_HANDLED;
1445 struct bcm43xx_wldev *dev = dev_id;
1446 u32 reason;
1447
1448 if (!dev)
1449 return IRQ_NONE;
1450
1451 spin_lock(&dev->wl->irq_lock);
1452
1453 reason = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
1454 if (reason == 0xffffffff) {
1455 /* irq not for us (shared irq) */
1456 ret = IRQ_NONE;
1457 goto out;
1458 }
1459 reason &= bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK);
1460 if (!reason)
1461 goto out;
1462
1463 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
1464 assert(dev->started);
1465
1466 dev->dma_reason[0] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA0_REASON)
1467 & 0x0001DC00;
1468 dev->dma_reason[1] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA1_REASON)
1469 & 0x0000DC00;
1470 dev->dma_reason[2] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA2_REASON)
1471 & 0x0000DC00;
1472 dev->dma_reason[3] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA3_REASON)
1473 & 0x0001DC00;
1474 dev->dma_reason[4] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA4_REASON)
1475 & 0x0000DC00;
1476 dev->dma_reason[5] = bcm43xx_read32(dev, BCM43xx_MMIO_DMA5_REASON)
1477 & 0x0000DC00;
1478
1479 bcm43xx_interrupt_ack(dev, reason);
1480 /* disable all IRQs. They are enabled again in the bottom half. */
1481 dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
1482 /* save the reason code and call our bottom half. */
1483 dev->irq_reason = reason;
1484 tasklet_schedule(&dev->isr_tasklet);
1485 out:
1486 mmiowb();
1487 spin_unlock(&dev->wl->irq_lock);
1488
1489 return ret;
1490 }
1491
1492 static void bcm43xx_release_firmware(struct bcm43xx_wldev *dev)
1493 {
1494 release_firmware(dev->fw.ucode);
1495 dev->fw.ucode = NULL;
1496 release_firmware(dev->fw.pcm);
1497 dev->fw.pcm = NULL;
1498 release_firmware(dev->fw.initvals0);
1499 dev->fw.initvals0 = NULL;
1500 release_firmware(dev->fw.initvals1);
1501 dev->fw.initvals1 = NULL;
1502 }
1503
1504 static int bcm43xx_request_firmware(struct bcm43xx_wldev *dev)
1505 {
1506 u8 rev = dev->dev->id.revision;
1507 int err = 0;
1508 int nr;
1509 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1510
1511 if (!dev->fw.ucode) {
1512 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1513 (rev >= 5 ? 5 : rev),
1514 modparam_fwpostfix);
1515 err = request_firmware(&dev->fw.ucode, buf, dev->dev->dev);
1516 if (err) {
1517 printk(KERN_ERR PFX
1518 "Error: Microcode \"%s\" not available or load failed.\n",
1519 buf);
1520 goto error;
1521 }
1522 }
1523
1524 if (!dev->fw.pcm) {
1525 snprintf(buf, ARRAY_SIZE(buf),
1526 "bcm43xx_pcm%d%s.fw",
1527 (rev < 5 ? 4 : 5),
1528 modparam_fwpostfix);
1529 err = request_firmware(&dev->fw.pcm, buf, dev->dev->dev);
1530 if (err) {
1531 printk(KERN_ERR PFX
1532 "Error: PCM \"%s\" not available or load failed.\n",
1533 buf);
1534 goto error;
1535 }
1536 }
1537
1538 if (!dev->fw.initvals0) {
1539 if (rev == 2 || rev == 4) {
1540 switch (dev->phy.type) {
1541 case BCM43xx_PHYTYPE_A:
1542 nr = 3;
1543 break;
1544 case BCM43xx_PHYTYPE_B:
1545 case BCM43xx_PHYTYPE_G:
1546 nr = 1;
1547 break;
1548 default:
1549 goto err_noinitval;
1550 }
1551
1552 } else if (rev >= 5) {
1553 switch (dev->phy.type) {
1554 case BCM43xx_PHYTYPE_A:
1555 nr = 7;
1556 break;
1557 case BCM43xx_PHYTYPE_B:
1558 case BCM43xx_PHYTYPE_G:
1559 nr = 5;
1560 break;
1561 default:
1562 goto err_noinitval;
1563 }
1564 } else
1565 goto err_noinitval;
1566 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1567 nr, modparam_fwpostfix);
1568
1569 err = request_firmware(&dev->fw.initvals0, buf, dev->dev->dev);
1570 if (err) {
1571 printk(KERN_ERR PFX
1572 "Error: InitVals \"%s\" not available or load failed.\n",
1573 buf);
1574 goto error;
1575 }
1576 if (dev->fw.initvals0->size % sizeof(struct bcm43xx_initval)) {
1577 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1578 goto error;
1579 }
1580 }
1581
1582 if (!dev->fw.initvals1) {
1583 if (rev >= 5) {
1584 u32 sbtmstatehigh;
1585
1586 switch (dev->phy.type) {
1587 case BCM43xx_PHYTYPE_A:
1588 sbtmstatehigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1589 if (sbtmstatehigh & 0x00010000)
1590 nr = 9;
1591 else
1592 nr = 10;
1593 break;
1594 case BCM43xx_PHYTYPE_B:
1595 case BCM43xx_PHYTYPE_G:
1596 nr = 6;
1597 break;
1598 default:
1599 goto err_noinitval;
1600 }
1601 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1602 nr, modparam_fwpostfix);
1603
1604 err = request_firmware(&dev->fw.initvals1, buf, dev->dev->dev);
1605 if (err) {
1606 printk(KERN_ERR PFX
1607 "Error: InitVals \"%s\" not available or load failed.\n",
1608 buf);
1609 goto error;
1610 }
1611 if (dev->fw.initvals1->size % sizeof(struct bcm43xx_initval)) {
1612 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1613 goto error;
1614 }
1615 }
1616 }
1617
1618 out:
1619 return err;
1620 error:
1621 bcm43xx_release_firmware(dev);
1622 goto out;
1623 err_noinitval:
1624 printk(KERN_ERR PFX "Error: No InitVals available!\n");
1625 err = -ENOENT;
1626 goto error;
1627 }
1628
1629 static int bcm43xx_upload_microcode(struct bcm43xx_wldev *dev)
1630 {
1631 const __be32 *data;
1632 unsigned int i, len;
1633 u16 fwrev, fwpatch, fwdate, fwtime;
1634 u32 tmp;
1635 int err = 0;
1636
1637 /* Upload Microcode. */
1638 data = (__be32 *)(dev->fw.ucode->data);
1639 len = dev->fw.ucode->size / sizeof(__be32);
1640 bcm43xx_shm_control_word(dev,
1641 BCM43xx_SHM_UCODE | BCM43xx_SHM_AUTOINC_W,
1642 0x0000);
1643 for (i = 0; i < len; i++) {
1644 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
1645 be32_to_cpu(data[i]));
1646 udelay(10);
1647 }
1648
1649 /* Upload PCM data. */
1650 data = (__be32 *)(dev->fw.pcm->data);
1651 len = dev->fw.pcm->size / sizeof(__be32);
1652 bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EA);
1653 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA, 0x00004000);
1654 /* No need for autoinc bit in SHM_HW */
1655 bcm43xx_shm_control_word(dev, BCM43xx_SHM_HW, 0x01EB);
1656 for (i = 0; i < len; i++) {
1657 bcm43xx_write32(dev, BCM43xx_MMIO_SHM_DATA,
1658 be32_to_cpu(data[i]));
1659 udelay(10);
1660 }
1661
1662 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_ALL);
1663 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
1664
1665 /* Wait for the microcode to load and respond */
1666 i = 0;
1667 while (1) {
1668 tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
1669 if (tmp == BCM43xx_IRQ_MAC_SUSPENDED)
1670 break;
1671 i++;
1672 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
1673 printk(KERN_ERR PFX "Microcode not responding\n");
1674 err = -ENODEV;
1675 goto out;
1676 }
1677 udelay(10);
1678 }
1679 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
1680
1681 /* Get and check the revisions. */
1682 fwrev = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1683 BCM43xx_SHM_SH_UCODEREV);
1684 fwpatch = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1685 BCM43xx_SHM_SH_UCODEPATCH);
1686 fwdate = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1687 BCM43xx_SHM_SH_UCODEDATE);
1688 fwtime = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1689 BCM43xx_SHM_SH_UCODETIME);
1690
1691 if (fwrev <= 0x128) {
1692 printk(KERN_ERR PFX "YOUR FIRMWARE IS TOO OLD. Firmware from "
1693 "binary drivers older than version 4.x is unsupported. "
1694 "You must upgrade your firmware files.\n");
1695 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, 0);
1696 err = -EOPNOTSUPP;
1697 goto out;
1698 }
1699 printk(KERN_DEBUG PFX "Loading firmware version %u.%u "
1700 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1701 fwrev, fwpatch,
1702 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1703 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1704
1705 dev->fw.rev = fwrev;
1706 dev->fw.patch = fwpatch;
1707
1708 out:
1709 return err;
1710 }
1711
1712 static int bcm43xx_write_initvals(struct bcm43xx_wldev *dev,
1713 const struct bcm43xx_initval *data,
1714 const unsigned int len)
1715 {
1716 u16 offset, size;
1717 u32 value;
1718 unsigned int i;
1719
1720 for (i = 0; i < len; i++) {
1721 offset = be16_to_cpu(data[i].offset);
1722 size = be16_to_cpu(data[i].size);
1723 value = be32_to_cpu(data[i].value);
1724
1725 if (unlikely(offset >= 0x1000))
1726 goto err_format;
1727 if (size == 2) {
1728 if (unlikely(value & 0xFFFF0000))
1729 goto err_format;
1730 bcm43xx_write16(dev, offset, (u16)value);
1731 } else if (size == 4) {
1732 bcm43xx_write32(dev, offset, value);
1733 } else
1734 goto err_format;
1735 }
1736
1737 return 0;
1738
1739 err_format:
1740 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
1741 "Please fix your bcm43xx firmware files.\n");
1742 return -EPROTO;
1743 }
1744
1745 static int bcm43xx_upload_initvals(struct bcm43xx_wldev *dev)
1746 {
1747 int err;
1748
1749 err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals0->data,
1750 dev->fw.initvals0->size / sizeof(struct bcm43xx_initval));
1751 if (err)
1752 goto out;
1753 if (dev->fw.initvals1) {
1754 err = bcm43xx_write_initvals(dev, (struct bcm43xx_initval *)dev->fw.initvals1->data,
1755 dev->fw.initvals1->size / sizeof(struct bcm43xx_initval));
1756 if (err)
1757 goto out;
1758 }
1759 out:
1760 return err;
1761 }
1762
1763 /* Initialize the GPIOs
1764 * http://bcm-specs.sipsolutions.net/GPIO
1765 */
1766 static int bcm43xx_gpio_init(struct bcm43xx_wldev *dev)
1767 {
1768 struct ssb_bus *bus = dev->dev->bus;
1769 struct ssb_device *gpiodev, *pcidev = NULL;
1770 u32 mask, set;
1771
1772 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
1773 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
1774 & 0xFFFF3FFF);
1775
1776 bcm43xx_leds_switch_all(dev, 0);
1777 bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
1778 bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
1779 | 0x000F);
1780
1781 mask = 0x0000001F;
1782 set = 0x0000000F;
1783 if (dev->dev->bus->chip_id == 0x4301) {
1784 mask |= 0x0060;
1785 set |= 0x0060;
1786 }
1787 if (0 /* FIXME: conditional unknown */) {
1788 bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
1789 bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
1790 | 0x0100);
1791 mask |= 0x0180;
1792 set |= 0x0180;
1793 }
1794 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) {
1795 bcm43xx_write16(dev, BCM43xx_MMIO_GPIO_MASK,
1796 bcm43xx_read16(dev, BCM43xx_MMIO_GPIO_MASK)
1797 | 0x0200);
1798 mask |= 0x0200;
1799 set |= 0x0200;
1800 }
1801 if (dev->dev->id.revision >= 2)
1802 mask |= 0x0010; /* FIXME: This is redundant. */
1803
1804 #ifdef CONFIG_SSB_DRIVER_PCICORE
1805 pcidev = bus->pcicore.dev;
1806 #endif
1807 gpiodev = bus->chipco.dev ? : pcidev;
1808 if (!gpiodev)
1809 return 0;
1810 ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL,
1811 (ssb_read32(gpiodev, BCM43xx_GPIO_CONTROL)
1812 & mask) | set);
1813
1814 return 0;
1815 }
1816
1817 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1818 static void bcm43xx_gpio_cleanup(struct bcm43xx_wldev *dev)
1819 {
1820 struct ssb_bus *bus = dev->dev->bus;
1821 struct ssb_device *gpiodev, *pcidev = NULL;
1822
1823 #ifdef CONFIG_SSB_DRIVER_PCICORE
1824 pcidev = bus->pcicore.dev;
1825 #endif
1826 gpiodev = bus->chipco.dev ? : pcidev;
1827 if (!gpiodev)
1828 return;
1829 ssb_write32(gpiodev, BCM43xx_GPIO_CONTROL, 0);
1830 }
1831
1832 /* http://bcm-specs.sipsolutions.net/EnableMac */
1833 void bcm43xx_mac_enable(struct bcm43xx_wldev *dev)
1834 {
1835 dev->mac_suspended--;
1836 assert(dev->mac_suspended >= 0);
1837 if (dev->mac_suspended == 0) {
1838 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
1839 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
1840 | BCM43xx_SBF_MAC_ENABLED);
1841 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON,
1842 BCM43xx_IRQ_MAC_SUSPENDED);
1843 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1844 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
1845 bcm43xx_power_saving_ctl_bits(dev, -1, -1);
1846 }
1847 }
1848
1849 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1850 void bcm43xx_mac_suspend(struct bcm43xx_wldev *dev)
1851 {
1852 int i;
1853 u32 tmp;
1854
1855 assert(dev->mac_suspended >= 0);
1856 if (dev->mac_suspended == 0) {
1857 bcm43xx_power_saving_ctl_bits(dev, -1, 1);
1858 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
1859 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
1860 & ~BCM43xx_SBF_MAC_ENABLED);
1861 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
1862 for (i = 10000; i; i--) {
1863 tmp = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
1864 if (tmp & BCM43xx_IRQ_MAC_SUSPENDED)
1865 goto out;
1866 udelay(1);
1867 }
1868 printkl(KERN_ERR PFX "MAC suspend failed\n");
1869 }
1870 out:
1871 dev->mac_suspended++;
1872 }
1873
1874 static void bcm43xx_adjust_opmode(struct bcm43xx_wldev *dev)
1875 {
1876 struct bcm43xx_wl *wl = dev->wl;
1877 u32 ctl;
1878 u16 cfp_pretbtt;
1879
1880 ctl = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
1881 /* Reset status to STA infrastructure mode. */
1882 ctl &= ~BCM43xx_MACCTL_AP;
1883 ctl &= ~BCM43xx_MACCTL_KEEP_CTL;
1884 ctl &= ~BCM43xx_MACCTL_KEEP_BADPLCP;
1885 ctl &= ~BCM43xx_MACCTL_KEEP_BAD;
1886 ctl &= ~BCM43xx_MACCTL_PROMISC;
1887 ctl |= BCM43xx_MACCTL_INFRA;
1888
1889 if (wl->operating) {
1890 switch (wl->if_type) {
1891 case IEEE80211_IF_TYPE_AP:
1892 ctl |= BCM43xx_MACCTL_AP;
1893 break;
1894 case IEEE80211_IF_TYPE_IBSS:
1895 ctl &= ~BCM43xx_MACCTL_INFRA;
1896 break;
1897 case IEEE80211_IF_TYPE_STA:
1898 case IEEE80211_IF_TYPE_MNTR:
1899 case IEEE80211_IF_TYPE_WDS:
1900 break;
1901 default:
1902 assert(0);
1903 }
1904 }
1905 if (wl->monitor) {
1906 ctl |= BCM43xx_MACCTL_KEEP_CTL;
1907 if (modparam_mon_keep_bad)
1908 ctl |= BCM43xx_MACCTL_KEEP_BAD;
1909 if (modparam_mon_keep_badplcp)
1910 ctl |= BCM43xx_MACCTL_KEEP_BADPLCP;
1911 }
1912 if (wl->promisc)
1913 ctl |= BCM43xx_MACCTL_PROMISC;
1914
1915 bcm43xx_write32(dev, BCM43xx_MMIO_MACCTL, ctl);
1916
1917 cfp_pretbtt = 2;
1918 if ((ctl & BCM43xx_MACCTL_INFRA) &&
1919 !(ctl & BCM43xx_MACCTL_AP)) {
1920 if (dev->dev->bus->chip_id == 0x4306 &&
1921 dev->dev->bus->chip_rev == 3)
1922 cfp_pretbtt = 100;
1923 else
1924 cfp_pretbtt = 50;
1925 }
1926 bcm43xx_write16(dev, 0x612, cfp_pretbtt);
1927 }
1928
1929 static void bcm43xx_rate_memory_write(struct bcm43xx_wldev *dev,
1930 u16 rate,
1931 int is_ofdm)
1932 {
1933 u16 offset;
1934
1935 if (is_ofdm) {
1936 offset = 0x480;
1937 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
1938 } else {
1939 offset = 0x4C0;
1940 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
1941 }
1942 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, offset + 0x20,
1943 bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, offset));
1944 }
1945
1946 static void bcm43xx_rate_memory_init(struct bcm43xx_wldev *dev)
1947 {
1948 switch (dev->phy.type) {
1949 case BCM43xx_PHYTYPE_A:
1950 case BCM43xx_PHYTYPE_G:
1951 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_6MB, 1);
1952 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_12MB, 1);
1953 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_18MB, 1);
1954 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_24MB, 1);
1955 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_36MB, 1);
1956 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_48MB, 1);
1957 bcm43xx_rate_memory_write(dev, BCM43xx_OFDM_RATE_54MB, 1);
1958 if (dev->phy.type == BCM43xx_PHYTYPE_A)
1959 break;
1960 /* fallthrough */
1961 case BCM43xx_PHYTYPE_B:
1962 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_1MB, 0);
1963 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_2MB, 0);
1964 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_5MB, 0);
1965 bcm43xx_rate_memory_write(dev, BCM43xx_CCK_RATE_11MB, 0);
1966 break;
1967 default:
1968 assert(0);
1969 }
1970 }
1971
1972 /* Set the TX-Antenna for management frames sent by firmware. */
1973 static void bcm43xx_mgmtframe_txantenna(struct bcm43xx_wldev *dev,
1974 int antenna)
1975 {
1976 u16 ant = 0;
1977 u16 tmp;
1978
1979 switch (antenna) {
1980 case BCM43xx_ANTENNA0:
1981 ant |= BCM43xx_TX4_PHY_ANT0;
1982 break;
1983 case BCM43xx_ANTENNA1:
1984 ant |= BCM43xx_TX4_PHY_ANT1;
1985 break;
1986 case BCM43xx_ANTENNA_AUTO:
1987 ant |= BCM43xx_TX4_PHY_ANTLAST;
1988 break;
1989 default:
1990 assert(0);
1991 }
1992
1993 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
1994
1995 /* For Beacons */
1996 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
1997 BCM43xx_SHM_SH_BEACPHYCTL);
1998 tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
1999 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
2000 BCM43xx_SHM_SH_BEACPHYCTL, tmp);
2001 /* For ACK/CTS */
2002 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2003 BCM43xx_SHM_SH_ACKCTSPHYCTL);
2004 tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
2005 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
2006 BCM43xx_SHM_SH_ACKCTSPHYCTL, tmp);
2007 /* For Probe Resposes */
2008 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2009 BCM43xx_SHM_SH_PRPHYCTL);
2010 tmp = (tmp & ~BCM43xx_TX4_PHY_ANT) | ant;
2011 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
2012 BCM43xx_SHM_SH_PRPHYCTL, tmp);
2013 }
2014
2015 /* This is the opposite of bcm43xx_chip_init() */
2016 static void bcm43xx_chip_exit(struct bcm43xx_wldev *dev)
2017 {
2018 bcm43xx_radio_turn_off(dev);
2019 if (!modparam_noleds)
2020 bcm43xx_leds_exit(dev);
2021 bcm43xx_gpio_cleanup(dev);
2022 /* firmware is released later */
2023 }
2024
2025 /* Initialize the chip
2026 * http://bcm-specs.sipsolutions.net/ChipInit
2027 */
2028 static int bcm43xx_chip_init(struct bcm43xx_wldev *dev)
2029 {
2030 struct bcm43xx_phy *phy = &dev->phy;
2031 int err, tmp;
2032 u32 value32;
2033 u16 value16;
2034
2035 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
2036 BCM43xx_SBF_CORE_READY
2037 | BCM43xx_SBF_400);
2038
2039 err = bcm43xx_request_firmware(dev);
2040 if (err)
2041 goto out;
2042 err = bcm43xx_upload_microcode(dev);
2043 if (err)
2044 goto out; /* firmware is released later */
2045
2046 err = bcm43xx_gpio_init(dev);
2047 if (err)
2048 goto out; /* firmware is released later */
2049 err = bcm43xx_upload_initvals(dev);
2050 if (err)
2051 goto err_gpio_cleanup;
2052 bcm43xx_radio_turn_on(dev);
2053 dev->radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
2054 dprintk(KERN_INFO PFX "Radio %s by hardware\n",
2055 (dev->radio_hw_enable == 0) ? "disabled" : "enabled");
2056
2057 bcm43xx_write16(dev, 0x03E6, 0x0000);
2058 err = bcm43xx_phy_init(dev);
2059 if (err)
2060 goto err_radio_off;
2061
2062 /* Select initial Interference Mitigation. */
2063 tmp = phy->interfmode;
2064 phy->interfmode = BCM43xx_INTERFMODE_NONE;
2065 bcm43xx_radio_set_interference_mitigation(dev, tmp);
2066
2067 bcm43xx_set_rx_antenna(dev, BCM43xx_ANTENNA_DEFAULT);
2068 bcm43xx_mgmtframe_txantenna(dev, BCM43xx_ANTENNA_DEFAULT);
2069
2070 if (phy->type == BCM43xx_PHYTYPE_B) {
2071 value16 = bcm43xx_read16(dev, 0x005E);
2072 value16 |= 0x0004;
2073 bcm43xx_write16(dev, 0x005E, value16);
2074 }
2075 bcm43xx_write32(dev, 0x0100, 0x01000000);
2076 if (dev->dev->id.revision < 5)
2077 bcm43xx_write32(dev, 0x010C, 0x01000000);
2078
2079 value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2080 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2081 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2082 value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2083 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2084 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2085
2086 value32 = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2087 value32 |= 0x100000;
2088 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2089
2090 if (bcm43xx_using_pio(dev)) {
2091 bcm43xx_write32(dev, 0x0210, 0x00000100);
2092 bcm43xx_write32(dev, 0x0230, 0x00000100);
2093 bcm43xx_write32(dev, 0x0250, 0x00000100);
2094 bcm43xx_write32(dev, 0x0270, 0x00000100);
2095 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2096 }
2097
2098 /* Probe Response Timeout value */
2099 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2100 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2101
2102 /* Initially set the wireless operation mode. */
2103 bcm43xx_adjust_opmode(dev);
2104
2105 if (dev->dev->id.revision < 3) {
2106 bcm43xx_write16(dev, 0x060E, 0x0000);
2107 bcm43xx_write16(dev, 0x0610, 0x8000);
2108 bcm43xx_write16(dev, 0x0604, 0x0000);
2109 bcm43xx_write16(dev, 0x0606, 0x0200);
2110 } else {
2111 bcm43xx_write32(dev, 0x0188, 0x80000000);
2112 bcm43xx_write32(dev, 0x018C, 0x02000000);
2113 }
2114 bcm43xx_write32(dev, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2115 bcm43xx_write32(dev, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2116 bcm43xx_write32(dev, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2117 bcm43xx_write32(dev, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2118 bcm43xx_write32(dev, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2119 bcm43xx_write32(dev, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2120 bcm43xx_write32(dev, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2121
2122 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2123 value32 |= 0x00100000;
2124 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2125
2126 bcm43xx_write16(dev, BCM43xx_MMIO_POWERUP_DELAY,
2127 dev->dev->bus->chipco.fast_pwrup_delay);
2128
2129 assert(err == 0);
2130 dprintk(KERN_INFO PFX "Chip initialized\n");
2131 out:
2132 return err;
2133
2134 err_radio_off:
2135 bcm43xx_radio_turn_off(dev);
2136 err_gpio_cleanup:
2137 bcm43xx_gpio_cleanup(dev);
2138 goto out;
2139 }
2140
2141 static void bcm43xx_periodic_every120sec(struct bcm43xx_wldev *dev)
2142 {
2143 struct bcm43xx_phy *phy = &dev->phy;
2144
2145 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
2146 return;
2147
2148 bcm43xx_mac_suspend(dev);
2149 bcm43xx_lo_g_measure(dev);
2150 bcm43xx_mac_enable(dev);
2151 }
2152
2153 static void bcm43xx_periodic_every60sec(struct bcm43xx_wldev *dev)
2154 {
2155 bcm43xx_lo_g_ctl_mark_all_unused(dev);
2156 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
2157 bcm43xx_mac_suspend(dev);
2158 bcm43xx_calc_nrssi_slope(dev);
2159 bcm43xx_mac_enable(dev);
2160 }
2161 }
2162
2163 static void bcm43xx_periodic_every30sec(struct bcm43xx_wldev *dev)
2164 {
2165 /* Update device statistics. */
2166 bcm43xx_calculate_link_quality(dev);
2167 }
2168
2169 static void bcm43xx_periodic_every15sec(struct bcm43xx_wldev *dev)
2170 {
2171 struct bcm43xx_phy *phy = &dev->phy;
2172
2173 if (phy->type == BCM43xx_PHYTYPE_G) {
2174 //TODO: update_aci_moving_average
2175 if (phy->aci_enable && phy->aci_wlan_automatic) {
2176 bcm43xx_mac_suspend(dev);
2177 if (!phy->aci_enable && 1 /*TODO: not scanning? */) {
2178 if (0 /*TODO: bunch of conditions*/) {
2179 bcm43xx_radio_set_interference_mitigation(dev,
2180 BCM43xx_INTERFMODE_MANUALWLAN);
2181 }
2182 } else if (1/*TODO*/) {
2183 /*
2184 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(dev))) {
2185 bcm43xx_radio_set_interference_mitigation(dev,
2186 BCM43xx_INTERFMODE_NONE);
2187 }
2188 */
2189 }
2190 bcm43xx_mac_enable(dev);
2191 } else if (phy->interfmode == BCM43xx_INTERFMODE_NONWLAN &&
2192 phy->rev == 1) {
2193 //TODO: implement rev1 workaround
2194 }
2195 }
2196 bcm43xx_phy_xmitpower(dev); //FIXME: unless scanning?
2197 //TODO for APHY (temperature?)
2198 }
2199
2200 static void bcm43xx_periodic_every1sec(struct bcm43xx_wldev *dev)
2201 {
2202 int radio_hw_enable;
2203
2204 /* check if radio hardware enabled status changed */
2205 radio_hw_enable = bcm43xx_is_hw_radio_enabled(dev);
2206 if (unlikely(dev->radio_hw_enable != radio_hw_enable)) {
2207 dev->radio_hw_enable = radio_hw_enable;
2208 dprintk(KERN_INFO PFX "Radio hardware status changed to %s\n",
2209 (radio_hw_enable == 0) ? "disabled" : "enabled");
2210 bcm43xx_leds_update(dev, 0);
2211 }
2212 }
2213
2214 static void do_periodic_work(struct bcm43xx_wldev *dev)
2215 {
2216 unsigned int state;
2217
2218 state = dev->periodic_state;
2219 if (state % 120 == 0)
2220 bcm43xx_periodic_every120sec(dev);
2221 if (state % 60 == 0)
2222 bcm43xx_periodic_every60sec(dev);
2223 if (state % 30 == 0)
2224 bcm43xx_periodic_every30sec(dev);
2225 if (state % 15 == 0)
2226 bcm43xx_periodic_every15sec(dev);
2227 bcm43xx_periodic_every1sec(dev);
2228 }
2229
2230 /* Estimate a "Badness" value based on the periodic work
2231 * state-machine state. "Badness" is worse (bigger), if the
2232 * periodic work will take longer.
2233 */
2234 static int estimate_periodic_work_badness(unsigned int state)
2235 {
2236 int badness = 0;
2237
2238 if (state % 120 == 0) /* every 120 sec */
2239 badness += 10;
2240 if (state % 60 == 0) /* every 60 sec */
2241 badness += 5;
2242 if (state % 30 == 0) /* every 30 sec */
2243 badness += 1;
2244 if (state % 15 == 0) /* every 15 sec */
2245 badness += 1;
2246
2247 #define BADNESS_LIMIT 4
2248 return badness;
2249 }
2250
2251 static void bcm43xx_periodic_work_handler(struct work_struct *work)
2252 {
2253 struct bcm43xx_wldev *dev =
2254 container_of(work, struct bcm43xx_wldev, periodic_work.work);
2255 unsigned long flags, delay;
2256 u32 savedirqs = 0;
2257 int badness;
2258
2259 mutex_lock(&dev->wl->mutex);
2260
2261 if (unlikely(bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED))
2262 goto out;
2263 if (unlikely(!dev->started))
2264 goto out;
2265 if (bcm43xx_debug(dev, BCM43xx_DBG_PWORK_STOP))
2266 goto out_requeue;
2267
2268 badness = estimate_periodic_work_badness(dev->periodic_state);
2269 if (badness > BADNESS_LIMIT) {
2270 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2271 /* Suspend TX as we don't want to transmit packets while
2272 * we recalibrate the hardware. */
2273 bcm43xx_tx_suspend(dev);
2274 savedirqs = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
2275 /* Periodic work will take a long time, so we want it to
2276 * be preemtible and release the spinlock. */
2277 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2278 bcm43xx_synchronize_irq(dev);
2279
2280 do_periodic_work(dev);
2281
2282 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2283 bcm43xx_interrupt_enable(dev, savedirqs);
2284 bcm43xx_tx_resume(dev);
2285 mmiowb();
2286 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2287 } else {
2288 /* Take the global driver lock. This will lock any operation. */
2289 spin_lock_irqsave(&dev->wl->irq_lock, flags);
2290
2291 do_periodic_work(dev);
2292
2293 mmiowb();
2294 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
2295 }
2296 dev->periodic_state++;
2297 out_requeue:
2298 if (bcm43xx_debug(dev, BCM43xx_DBG_PWORK_FAST))
2299 delay = msecs_to_jiffies(50);
2300 else
2301 delay = round_jiffies(HZ);
2302 queue_delayed_work(dev->wl->hw->workqueue,
2303 &dev->periodic_work, delay);
2304 out:
2305 mutex_unlock(&dev->wl->mutex);
2306 }
2307
2308 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_wldev *dev)
2309 {
2310 cancel_rearming_delayed_work(&dev->periodic_work);
2311 }
2312
2313 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_wldev *dev)
2314 {
2315 struct delayed_work *work = &dev->periodic_work;
2316
2317 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
2318 dev->periodic_state = 0;
2319 INIT_DELAYED_WORK(work, bcm43xx_periodic_work_handler);
2320 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2321 }
2322
2323 /* Validate access to the chip (SHM) */
2324 static int bcm43xx_validate_chipaccess(struct bcm43xx_wldev *dev)
2325 {
2326 u32 value;
2327 u32 shm_backup;
2328
2329 shm_backup = bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0);
2330 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0xAA5555AA);
2331 if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0xAA5555AA)
2332 goto error;
2333 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, 0x55AAAA55);
2334 if (bcm43xx_shm_read32(dev, BCM43xx_SHM_SHARED, 0) != 0x55AAAA55)
2335 goto error;
2336 bcm43xx_shm_write32(dev, BCM43xx_SHM_SHARED, 0, shm_backup);
2337
2338 value = bcm43xx_read32(dev, BCM43xx_MMIO_MACCTL);
2339 if ((value | BCM43xx_MACCTL_GMODE) !=
2340 (BCM43xx_MACCTL_GMODE | BCM43xx_MACCTL_IHR_ENABLED))
2341 goto error;
2342
2343 value = bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_REASON);
2344 if (value)
2345 goto error;
2346
2347 return 0;
2348 error:
2349 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2350 return -ENODEV;
2351 }
2352
2353 static void bcm43xx_security_init(struct bcm43xx_wldev *dev)
2354 {
2355 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2356 assert(dev->max_nr_keys <= ARRAY_SIZE(dev->key));
2357 dev->ktp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED,
2358 BCM43xx_SHM_SH_KTP);
2359 /* KTP is a word address, but we address SHM bytewise.
2360 * So multiply by two.
2361 */
2362 dev->ktp *= 2;
2363 if (dev->dev->id.revision >= 5) {
2364 /* Number of RCMTA address slots */
2365 bcm43xx_write16(dev, BCM43xx_MMIO_RCMTA_COUNT,
2366 dev->max_nr_keys - 8);
2367 }
2368 bcm43xx_clear_keys(dev);
2369 }
2370
2371 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
2372 {
2373 struct bcm43xx_wl *wl = (struct bcm43xx_wl *)rng->priv;
2374 unsigned long flags;
2375
2376 /* Don't take wl->mutex here, as it could deadlock with
2377 * hwrng internal locking. It's not needed to take
2378 * wl->mutex here, anyway. */
2379
2380 spin_lock_irqsave(&wl->irq_lock, flags);
2381 *data = bcm43xx_read16(wl->current_dev, BCM43xx_MMIO_RNG);
2382 spin_unlock_irqrestore(&wl->irq_lock, flags);
2383
2384 return (sizeof(u16));
2385 }
2386
2387 static void bcm43xx_rng_exit(struct bcm43xx_wl *wl)
2388 {
2389 if (wl->rng_initialized)
2390 hwrng_unregister(&wl->rng);
2391 }
2392
2393 static int bcm43xx_rng_init(struct bcm43xx_wl *wl)
2394 {
2395 int err;
2396
2397 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2398 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2399 wl->rng.name = wl->rng_name;
2400 wl->rng.data_read = bcm43xx_rng_read;
2401 wl->rng.priv = (unsigned long)wl;
2402 wl->rng_initialized = 1;
2403 err = hwrng_register(&wl->rng);
2404 if (err) {
2405 wl->rng_initialized = 0;
2406 printk(KERN_ERR PFX "Failed to register the random "
2407 "number generator (%d)\n", err);
2408 }
2409
2410 return err;
2411 }
2412
2413 static int bcm43xx_tx(struct ieee80211_hw *hw,
2414 struct sk_buff *skb,
2415 struct ieee80211_tx_control *ctl)
2416 {
2417 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2418 struct bcm43xx_wldev *dev = wl->current_dev;
2419 int err = -ENODEV;
2420 unsigned long flags;
2421
2422 /* DMA-TX is done without a global lock. */
2423 if (unlikely(!dev))
2424 goto out;
2425 assert(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED);
2426 assert(dev->started);
2427 if (bcm43xx_using_pio(dev)) {
2428 spin_lock_irqsave(&wl->irq_lock, flags);
2429 err = bcm43xx_pio_tx(dev, skb, ctl);
2430 spin_unlock_irqrestore(&wl->irq_lock, flags);
2431 } else
2432 err = bcm43xx_dma_tx(dev, skb, ctl);
2433 out:
2434 if (unlikely(err))
2435 return NETDEV_TX_BUSY;
2436 return NETDEV_TX_OK;
2437 }
2438
2439 static int bcm43xx_conf_tx(struct ieee80211_hw *hw,
2440 int queue,
2441 const struct ieee80211_tx_queue_params *params)
2442 {
2443 return 0;
2444 }
2445
2446 static int bcm43xx_get_tx_stats(struct ieee80211_hw *hw,
2447 struct ieee80211_tx_queue_stats *stats)
2448 {
2449 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2450 struct bcm43xx_wldev *dev = wl->current_dev;
2451 unsigned long flags;
2452 int err = -ENODEV;
2453
2454 if (!dev)
2455 goto out;
2456 spin_lock_irqsave(&wl->irq_lock, flags);
2457 if (likely(bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)) {
2458 if (bcm43xx_using_pio(dev))
2459 bcm43xx_pio_get_tx_stats(dev, stats);
2460 else
2461 bcm43xx_dma_get_tx_stats(dev, stats);
2462 err = 0;
2463 }
2464 spin_unlock_irqrestore(&wl->irq_lock, flags);
2465 out:
2466 return err;
2467 }
2468
2469 static int bcm43xx_get_stats(struct ieee80211_hw *hw,
2470 struct ieee80211_low_level_stats *stats)
2471 {
2472 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2473 unsigned long flags;
2474
2475 spin_lock_irqsave(&wl->irq_lock, flags);
2476 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2477 spin_unlock_irqrestore(&wl->irq_lock, flags);
2478
2479 return 0;
2480 }
2481
2482 static int bcm43xx_dev_reset(struct ieee80211_hw *hw)
2483 {
2484 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2485 struct bcm43xx_wldev *dev = wl->current_dev;
2486 unsigned long flags;
2487
2488 if (!dev)
2489 return -ENODEV;
2490 spin_lock_irqsave(&wl->irq_lock, flags);
2491 bcm43xx_controller_restart(dev, "Reset by ieee80211 subsystem");
2492 spin_unlock_irqrestore(&wl->irq_lock, flags);
2493
2494 return 0;
2495 }
2496
2497 static const char * phymode_to_string(unsigned int phymode)
2498 {
2499 switch (phymode) {
2500 case BCM43xx_PHYMODE_A:
2501 return "A";
2502 case BCM43xx_PHYMODE_B:
2503 return "B";
2504 case BCM43xx_PHYMODE_G:
2505 return "G";
2506 default:
2507 assert(0);
2508 }
2509 return "";
2510 }
2511
2512 static int find_wldev_for_phymode(struct bcm43xx_wl *wl,
2513 unsigned int phymode,
2514 struct bcm43xx_wldev **dev,
2515 int *gmode)
2516 {
2517 struct bcm43xx_wldev *d;
2518
2519 list_for_each_entry(d, &wl->devlist, list) {
2520 if (d->phy.possible_phymodes & phymode) {
2521 /* Ok, this device supports the PHY-mode.
2522 * Now figure out how the gmode bit has to be
2523 * set to support it. */
2524 if (phymode == BCM43xx_PHYMODE_A)
2525 *gmode = 0;
2526 else
2527 *gmode = 1;
2528 *dev = d;
2529
2530 return 0;
2531 }
2532 }
2533
2534 return -ESRCH;
2535 }
2536
2537 static void bcm43xx_put_phy_into_reset(struct bcm43xx_wldev *dev)
2538 {
2539 struct ssb_device *sdev = dev->dev;
2540 u32 tmslow;
2541
2542 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2543 tmslow &= ~BCM43xx_TMSLOW_GMODE;
2544 tmslow |= BCM43xx_TMSLOW_PHYRESET;
2545 tmslow |= SSB_TMSLOW_FGC;
2546 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2547 msleep(1);
2548
2549 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2550 tmslow &= ~SSB_TMSLOW_FGC;
2551 tmslow |= BCM43xx_TMSLOW_PHYRESET;
2552 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2553 msleep(1);
2554 }
2555
2556 static int bcm43xx_switch_phymode(struct bcm43xx_wl *wl,
2557 unsigned int new_mode)
2558 {
2559 struct bcm43xx_wldev *up_dev;
2560 struct bcm43xx_wldev *down_dev;
2561 int err;
2562 int gmode = -1;
2563 int old_was_started = 0;
2564 int old_was_inited = 0;
2565
2566 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2567 if (err) {
2568 printk(KERN_INFO PFX "Could not find a device for %s-PHY mode\n",
2569 phymode_to_string(new_mode));
2570 return err;
2571 }
2572 assert(gmode == 0 || gmode == 1);
2573 if ((up_dev == wl->current_dev) &&
2574 (wl->current_dev->phy.gmode == gmode)) {
2575 /* This device is already running. */
2576 return 0;
2577 }
2578 dprintk(KERN_INFO PFX "Reconfiguring PHYmode to %s-PHY\n",
2579 phymode_to_string(new_mode));
2580 down_dev = wl->current_dev;
2581
2582 /* Shutdown the currently running core. */
2583 if (down_dev->started) {
2584 old_was_started = 1;
2585 bcm43xx_wireless_core_stop(down_dev);
2586 }
2587 if (bcm43xx_status(down_dev) == BCM43xx_STAT_INITIALIZED) {
2588 old_was_inited = 1;
2589 bcm43xx_wireless_core_exit(down_dev);
2590 }
2591
2592 if (down_dev != up_dev) {
2593 /* We switch to a different core, so we put PHY into
2594 * RESET on the old core. */
2595 bcm43xx_put_phy_into_reset(down_dev);
2596 }
2597
2598 /* Now start the new core. */
2599 up_dev->phy.gmode = gmode;
2600 if (old_was_inited) {
2601 err = bcm43xx_wireless_core_init(up_dev);
2602 if (err) {
2603 printk(KERN_INFO PFX "Fatal: Could not initialize device for "
2604 "new selected %s-PHY mode\n",
2605 phymode_to_string(new_mode));
2606 return err;
2607 }
2608 }
2609 if (old_was_started) {
2610 assert(old_was_inited);
2611 err = bcm43xx_wireless_core_start(up_dev);
2612 if (err) {
2613 printk(KERN_INFO PFX "Fatal: Coult not start device for "
2614 "new selected %s-PHY mode\n",
2615 phymode_to_string(new_mode));
2616 bcm43xx_wireless_core_exit(up_dev);
2617 return err;
2618 }
2619 }
2620
2621 wl->current_dev = up_dev;
2622
2623 return 0;
2624 }
2625
2626 static int bcm43xx_antenna_from_ieee80211(u8 antenna)
2627 {
2628 switch (antenna) {
2629 case 0: /* default/diversity */
2630 return BCM43xx_ANTENNA_DEFAULT;
2631 case 1: /* Antenna 0 */
2632 return BCM43xx_ANTENNA0;
2633 case 2: /* Antenna 1 */
2634 return BCM43xx_ANTENNA1;
2635 default:
2636 return BCM43xx_ANTENNA_DEFAULT;
2637 }
2638 }
2639
2640 static int bcm43xx_dev_config(struct ieee80211_hw *hw,
2641 struct ieee80211_conf *conf)
2642 {
2643 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2644 struct bcm43xx_wldev *dev;
2645 struct bcm43xx_phy *phy;
2646 unsigned long flags;
2647 unsigned int new_phymode = 0xFFFF;
2648 int antenna_tx;
2649 int antenna_rx;
2650 int err = 0;
2651 u32 savedirqs;
2652
2653 antenna_tx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_tx);
2654 antenna_rx = bcm43xx_antenna_from_ieee80211(conf->antenna_sel_rx);
2655
2656 mutex_lock(&wl->mutex);
2657
2658 /* Switch the PHY mode (if necessary). */
2659 switch (conf->phymode) {
2660 case MODE_IEEE80211A:
2661 new_phymode = BCM43xx_PHYMODE_A;
2662 break;
2663 case MODE_IEEE80211B:
2664 new_phymode = BCM43xx_PHYMODE_B;
2665 break;
2666 case MODE_IEEE80211G:
2667 new_phymode = BCM43xx_PHYMODE_G;
2668 break;
2669 default:
2670 assert(0);
2671 }
2672 err = bcm43xx_switch_phymode(wl, new_phymode);
2673 if (err)
2674 goto out_unlock_mutex;
2675 dev = wl->current_dev;
2676 phy = &dev->phy;
2677
2678 /* Disable IRQs while reconfiguring the device.
2679 * This makes it possible to drop the spinlock throughout
2680 * the reconfiguration process. */
2681 spin_lock_irqsave(&wl->irq_lock, flags);
2682 if ((bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) ||
2683 !dev->started) {
2684 spin_unlock_irqrestore(&wl->irq_lock, flags);
2685 goto out_unlock_mutex;
2686 }
2687 savedirqs = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
2688 spin_unlock_irqrestore(&wl->irq_lock, flags);
2689 bcm43xx_synchronize_irq(dev);
2690
2691 /* Switch to the requested channel.
2692 * The firmware takes care of races with the TX handler. */
2693 if (conf->channel_val != phy->channel)
2694 bcm43xx_radio_selectchannel(dev, conf->channel_val, 0);
2695
2696 /* Enable/Disable ShortSlot timing. */
2697 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) != dev->short_slot) {
2698 assert(phy->type == BCM43xx_PHYTYPE_G);
2699 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2700 bcm43xx_short_slot_timing_enable(dev);
2701 else
2702 bcm43xx_short_slot_timing_disable(dev);
2703 }
2704
2705 /* Adjust the desired TX power level. */
2706 if (conf->power_level != 0) {
2707 if (conf->power_level != phy->power_level) {
2708 phy->power_level = conf->power_level;
2709 bcm43xx_phy_xmitpower(dev);
2710 }
2711 }
2712
2713 /* Hide/Show the SSID (AP mode only). */
2714 if (conf->flags & IEEE80211_CONF_SSID_HIDDEN) {
2715 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
2716 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
2717 | BCM43xx_SBF_NO_SSID_BCAST);
2718 } else {
2719 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD,
2720 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD)
2721 & ~BCM43xx_SBF_NO_SSID_BCAST);
2722 }
2723
2724 /* Antennas for RX and management frame TX. */
2725 bcm43xx_mgmtframe_txantenna(dev, antenna_tx);
2726 bcm43xx_set_rx_antenna(dev, antenna_rx);
2727
2728 /* Update templates for AP mode. */
2729 if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP))
2730 bcm43xx_set_beacon_int(dev, conf->beacon_int);
2731
2732
2733 spin_lock_irqsave(&wl->irq_lock, flags);
2734 bcm43xx_interrupt_enable(dev, savedirqs);
2735 mmiowb();
2736 spin_unlock_irqrestore(&wl->irq_lock, flags);
2737 out_unlock_mutex:
2738 mutex_unlock(&wl->mutex);
2739
2740 return err;
2741 }
2742
2743 static int bcm43xx_dev_set_key(struct ieee80211_hw *hw,
2744 set_key_cmd cmd,
2745 u8 *addr,
2746 struct ieee80211_key_conf *key,
2747 int aid)
2748 {
2749 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2750 struct bcm43xx_wldev *dev = wl->current_dev;
2751 unsigned long flags;
2752 u8 algorithm;
2753 u8 index;
2754 int err = -EINVAL;
2755
2756 if (!dev)
2757 return -ENODEV;
2758 switch (key->alg) {
2759 case ALG_NONE:
2760 case ALG_NULL:
2761 algorithm = BCM43xx_SEC_ALGO_NONE;
2762 break;
2763 case ALG_WEP:
2764 if (key->keylen == 5)
2765 algorithm = BCM43xx_SEC_ALGO_WEP40;
2766 else
2767 algorithm = BCM43xx_SEC_ALGO_WEP104;
2768 break;
2769 case ALG_TKIP:
2770 algorithm = BCM43xx_SEC_ALGO_TKIP;
2771 break;
2772 case ALG_CCMP:
2773 algorithm = BCM43xx_SEC_ALGO_AES;
2774 break;
2775 default:
2776 assert(0);
2777 goto out;
2778 }
2779
2780 index = (u8)(key->keyidx);
2781 if (index > 3)
2782 goto out;
2783
2784 mutex_lock(&wl->mutex);
2785 spin_lock_irqsave(&wl->irq_lock, flags);
2786
2787 if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED) {
2788 err = -ENODEV;
2789 goto out_unlock;
2790 }
2791
2792 switch (cmd) {
2793 case SET_KEY:
2794 key->flags &= ~IEEE80211_KEY_FORCE_SW_ENCRYPT;
2795
2796 if (algorithm == BCM43xx_SEC_ALGO_TKIP) {
2797 /* FIXME: No TKIP hardware encryption for now. */
2798 key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
2799 }
2800
2801 if (is_broadcast_ether_addr(addr)) {
2802 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2803 err = bcm43xx_key_write(dev, index, algorithm,
2804 key->key, key->keylen,
2805 NULL, key);
2806 } else {
2807 err = bcm43xx_key_write(dev, -1, algorithm,
2808 key->key, key->keylen,
2809 addr, key);
2810 }
2811 if (err) {
2812 key->flags |= IEEE80211_KEY_FORCE_SW_ENCRYPT;
2813 goto out_unlock;
2814 }
2815 dev->key[key->hw_key_idx].enabled = 1;
2816
2817 if (algorithm == BCM43xx_SEC_ALGO_WEP40 ||
2818 algorithm == BCM43xx_SEC_ALGO_WEP104) {
2819 bcm43xx_hf_write(dev,
2820 bcm43xx_hf_read(dev) |
2821 BCM43xx_HF_USEDEFKEYS);
2822 } else {
2823 bcm43xx_hf_write(dev,
2824 bcm43xx_hf_read(dev) &
2825 ~BCM43xx_HF_USEDEFKEYS);
2826 }
2827 break;
2828 case DISABLE_KEY: {
2829 static const u8 zero[BCM43xx_SEC_KEYSIZE] = { 0 };
2830
2831 algorithm = BCM43xx_SEC_ALGO_NONE;
2832 if (is_broadcast_ether_addr(addr)) {
2833 err = bcm43xx_key_write(dev, index, algorithm,
2834 zero, BCM43xx_SEC_KEYSIZE,
2835 NULL, key);
2836 } else {
2837 err = bcm43xx_key_write(dev, -1, algorithm,
2838 zero, BCM43xx_SEC_KEYSIZE,
2839 addr, key);
2840 }
2841 dev->key[key->hw_key_idx].enabled = 0;
2842 break;
2843 }
2844 case REMOVE_ALL_KEYS:
2845 bcm43xx_clear_keys(dev);
2846 err = 0;
2847 break;
2848 default:
2849 assert(0);
2850 }
2851 out_unlock:
2852 spin_unlock_irqrestore(&wl->irq_lock, flags);
2853 mutex_unlock(&wl->mutex);
2854 out:
2855 if (!err) {
2856 dprintk(KERN_DEBUG PFX "Using %s based encryption for keyidx: %d, "
2857 "mac: " MAC_FMT "\n",
2858 (key->flags & IEEE80211_KEY_FORCE_SW_ENCRYPT) ?
2859 "software" : "hardware",
2860 key->keyidx, MAC_ARG(addr));
2861 }
2862 return err;
2863 }
2864
2865 static void bcm43xx_set_multicast_list(struct ieee80211_hw *hw,
2866 unsigned short netflags,
2867 int mc_count)
2868 {
2869 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2870 struct bcm43xx_wldev *dev = wl->current_dev;
2871 unsigned long flags;
2872
2873 if (!dev)
2874 return;
2875 spin_lock_irqsave(&wl->irq_lock, flags);
2876 if (wl->promisc != !!(netflags & IFF_PROMISC)) {
2877 wl->promisc = !!(netflags & IFF_PROMISC);
2878 if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED)
2879 bcm43xx_adjust_opmode(dev);
2880 }
2881 spin_unlock_irqrestore(&wl->irq_lock, flags);
2882 }
2883
2884 static int bcm43xx_config_interface(struct ieee80211_hw *hw,
2885 int if_id,
2886 struct ieee80211_if_conf *conf)
2887 {
2888 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
2889 struct bcm43xx_wldev *dev = wl->current_dev;
2890 unsigned long flags;
2891
2892 if (!dev)
2893 return -ENODEV;
2894 mutex_lock(&wl->mutex);
2895 spin_lock_irqsave(&wl->irq_lock, flags);
2896 if (conf->type != IEEE80211_IF_TYPE_MNTR) {
2897 assert(wl->if_id == if_id);
2898 wl->bssid = conf->bssid;
2899 if (bcm43xx_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2900 assert(conf->type == IEEE80211_IF_TYPE_AP);
2901 bcm43xx_set_ssid(dev, conf->ssid, conf->ssid_len);
2902 if (conf->beacon)
2903 bcm43xx_refresh_templates(dev, conf->beacon);
2904 }
2905 bcm43xx_write_mac_bssid_templates(dev);
2906 }
2907 spin_unlock_irqrestore(&wl->irq_lock, flags);
2908 mutex_unlock(&wl->mutex);
2909
2910 return 0;
2911 }
2912
2913 /* Locking: wl->mutex */
2914 static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev *dev)
2915 {
2916 struct bcm43xx_wl *wl = dev->wl;
2917 unsigned long flags;
2918
2919 if (!dev->started)
2920 return;
2921 dev->started = 0;
2922
2923 mutex_unlock(&wl->mutex);
2924 /* Must unlock as it would otherwise deadlock. No races here. */
2925 bcm43xx_periodic_tasks_delete(dev);
2926 flush_workqueue(dev->wl->hw->workqueue);
2927 mutex_lock(&wl->mutex);
2928
2929 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2930
2931 /* Disable and sync interrupts. */
2932 spin_lock_irqsave(&wl->irq_lock, flags);
2933 dev->irq_savedstate = bcm43xx_interrupt_disable(dev, BCM43xx_IRQ_ALL);
2934 bcm43xx_read32(dev, BCM43xx_MMIO_GEN_IRQ_MASK); /* flush */
2935 spin_unlock_irqrestore(&wl->irq_lock, flags);
2936 bcm43xx_synchronize_irq(dev);
2937
2938 bcm43xx_mac_suspend(dev);
2939 free_irq(dev->dev->irq, dev);
2940 dprintk(KERN_INFO PFX "Wireless interface stopped\n");
2941 }
2942
2943 /* Locking: wl->mutex */
2944 static int bcm43xx_wireless_core_start(struct bcm43xx_wldev *dev)
2945 {
2946 struct bcm43xx_wl *wl = dev->wl;
2947 int err;
2948
2949 assert(!dev->started);
2950
2951 drain_txstatus_queue(dev);
2952 err = request_irq(dev->dev->irq, bcm43xx_interrupt_handler,
2953 IRQF_SHARED, KBUILD_MODNAME, dev);
2954 if (err) {
2955 printk(KERN_ERR PFX "Cannot request IRQ-%d\n",
2956 dev->dev->irq);
2957 goto out;
2958 }
2959 dev->started = 1;
2960 bcm43xx_interrupt_enable(dev, dev->irq_savedstate);
2961 bcm43xx_mac_enable(dev);
2962
2963 ieee80211_start_queues(wl->hw);
2964 bcm43xx_periodic_tasks_setup(dev);
2965 dprintk(KERN_INFO PFX "Wireless interface started\n");
2966 out:
2967 return err;
2968 }
2969
2970 /* Get PHY and RADIO versioning numbers */
2971 static int bcm43xx_phy_versioning(struct bcm43xx_wldev *dev)
2972 {
2973 struct bcm43xx_phy *phy = &dev->phy;
2974 u32 tmp;
2975 u8 analog_type;
2976 u8 phy_type;
2977 u8 phy_rev;
2978 u16 radio_manuf;
2979 u16 radio_ver;
2980 u16 radio_rev;
2981 int unsupported = 0;
2982
2983 /* Get PHY versioning */
2984 tmp = bcm43xx_read16(dev, BCM43xx_MMIO_PHY_VER);
2985 analog_type = (tmp & BCM43xx_PHYVER_ANALOG) >> BCM43xx_PHYVER_ANALOG_SHIFT;
2986 phy_type = (tmp & BCM43xx_PHYVER_TYPE) >> BCM43xx_PHYVER_TYPE_SHIFT;
2987 phy_rev = (tmp & BCM43xx_PHYVER_VERSION);
2988 switch (phy_type) {
2989 case BCM43xx_PHYTYPE_A:
2990 if (phy_rev >= 4)
2991 unsupported = 1;
2992 break;
2993 case BCM43xx_PHYTYPE_B:
2994 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
2995 unsupported = 1;
2996 break;
2997 case BCM43xx_PHYTYPE_G:
2998 if (phy_rev > 8)
2999 unsupported = 1;
3000 break;
3001 default:
3002 unsupported = 1;
3003 };
3004 if (unsupported) {
3005 printk(KERN_ERR PFX "FOUND UNSUPPORTED PHY "
3006 "(Analog %u, Type %u, Revision %u)\n",
3007 analog_type, phy_type, phy_rev);
3008 return -EOPNOTSUPP;
3009 }
3010 dprintk(KERN_INFO PFX "Found PHY: Analog %u, Type %u, Revision %u\n",
3011 analog_type, phy_type, phy_rev);
3012
3013
3014 /* Get RADIO versioning */
3015 if (dev->dev->bus->chip_id == 0x4317) {
3016 if (dev->dev->bus->chip_rev == 0)
3017 tmp = 0x3205017F;
3018 else if (dev->dev->bus->chip_rev == 1)
3019 tmp = 0x4205017F;
3020 else
3021 tmp = 0x5205017F;
3022 } else {
3023 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL,
3024 BCM43xx_RADIOCTL_ID);
3025 tmp = bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_HIGH);
3026 tmp <<= 16;
3027 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL,
3028 BCM43xx_RADIOCTL_ID);
3029 tmp |= bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_LOW);
3030 }
3031 radio_manuf = (tmp & 0x00000FFF);
3032 radio_ver = (tmp & 0x0FFFF000) >> 12;
3033 radio_rev = (tmp & 0xF0000000) >> 28;
3034 switch (phy_type) {
3035 case BCM43xx_PHYTYPE_A:
3036 if (radio_ver != 0x2060)
3037 unsupported = 1;
3038 if (radio_rev != 1)
3039 unsupported = 1;
3040 if (radio_manuf != 0x17F)
3041 unsupported = 1;
3042 break;
3043 case BCM43xx_PHYTYPE_B:
3044 if ((radio_ver & 0xFFF0) != 0x2050)
3045 unsupported = 1;
3046 break;
3047 case BCM43xx_PHYTYPE_G:
3048 if (radio_ver != 0x2050)
3049 unsupported = 1;
3050 break;
3051 default:
3052 assert(0);
3053 }
3054 if (unsupported) {
3055 printk(KERN_ERR PFX "FOUND UNSUPPORTED RADIO "
3056 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3057 radio_manuf, radio_ver, radio_rev);
3058 return -EOPNOTSUPP;
3059 }
3060 dprintk(KERN_INFO PFX "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3061 radio_manuf, radio_ver, radio_rev);
3062
3063
3064 phy->radio_manuf = radio_manuf;
3065 phy->radio_ver = radio_ver;
3066 phy->radio_rev = radio_rev;
3067
3068 phy->analog = analog_type;
3069 phy->type = phy_type;
3070 phy->rev = phy_rev;
3071
3072 return 0;
3073 }
3074
3075 static void setup_struct_phy_for_init(struct bcm43xx_wldev *dev,
3076 struct bcm43xx_phy *phy)
3077 {
3078 struct bcm43xx_txpower_lo_control *lo;
3079 int i;
3080
3081 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3082 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3083
3084 /* Flags */
3085 phy->locked = 0;
3086
3087 phy->aci_enable = 0;
3088 phy->aci_wlan_automatic = 0;
3089 phy->aci_hw_rssi = 0;
3090
3091 lo = phy->lo_control;
3092 if (lo) {
3093 memset(lo, 0, sizeof(*(phy->lo_control)));
3094 lo->rebuild = 1;
3095 lo->tx_bias = 0xFF;
3096 }
3097 phy->max_lb_gain = 0;
3098 phy->trsw_rx_gain = 0;
3099 phy->txpwr_offset = 0;
3100
3101 /* NRSSI */
3102 phy->nrssislope = 0;
3103 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3104 phy->nrssi[i] = -1000;
3105 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3106 phy->nrssi_lt[i] = i;
3107
3108 phy->lofcal = 0xFFFF;
3109 phy->initval = 0xFFFF;
3110
3111 spin_lock_init(&phy->lock);
3112 phy->interfmode = BCM43xx_INTERFMODE_NONE;
3113 phy->channel = 0xFF;
3114 }
3115
3116 static void setup_struct_wldev_for_init(struct bcm43xx_wldev *dev)
3117 {
3118 /* Flags */
3119 dev->reg124_set_0x4 = 0;
3120
3121 /* Stats */
3122 memset(&dev->stats, 0, sizeof(dev->stats));
3123
3124 setup_struct_phy_for_init(dev, &dev->phy);
3125
3126 /* IRQ related flags */
3127 dev->irq_reason = 0;
3128 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3129 dev->irq_savedstate = BCM43xx_IRQ_MASKTEMPLATE;
3130
3131 dev->mac_suspended = 1;
3132
3133 /* Noise calculation context */
3134 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3135 }
3136
3137 static void bcm43xx_bluetooth_coext_enable(struct bcm43xx_wldev *dev)
3138 {
3139 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3140 u32 hf;
3141
3142 if (!(sprom->r1.boardflags_lo & BCM43xx_BFL_BTCOEXIST))
3143 return;
3144 if (dev->phy.type != BCM43xx_PHYTYPE_B && !dev->phy.gmode)
3145 return;
3146
3147 hf = bcm43xx_hf_read(dev);
3148 if (sprom->r1.boardflags_lo & BCM43xx_BFL_BTCMOD)
3149 hf |= BCM43xx_HF_BTCOEXALT;
3150 else
3151 hf |= BCM43xx_HF_BTCOEX;
3152 bcm43xx_hf_write(dev, hf);
3153 //TODO
3154 }
3155
3156 static void bcm43xx_bluetooth_coext_disable(struct bcm43xx_wldev *dev)
3157 {//TODO
3158 }
3159
3160 static void bcm43xx_imcfglo_timeouts_workaround(struct bcm43xx_wldev *dev)
3161 {
3162 #ifdef CONFIG_SSB_DRIVER_PCICORE
3163 struct ssb_bus *bus = dev->dev->bus;
3164 u32 tmp;
3165
3166 if (bus->pcicore.dev &&
3167 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3168 bus->pcicore.dev->id.revision <= 5) {
3169 /* IMCFGLO timeouts workaround. */
3170 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3171 tmp &= ~SSB_IMCFGLO_REQTO;
3172 tmp &= ~SSB_IMCFGLO_SERTO;
3173 switch (bus->bustype) {
3174 case SSB_BUSTYPE_PCI:
3175 case SSB_BUSTYPE_PCMCIA:
3176 tmp |= 0x32;
3177 break;
3178 case SSB_BUSTYPE_SSB:
3179 tmp |= 0x53;
3180 break;
3181 }
3182 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3183 }
3184 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3185 }
3186
3187 /* Shutdown a wireless core */
3188 static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev *dev)
3189 {
3190 struct bcm43xx_phy *phy = &dev->phy;
3191
3192 if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
3193 return;
3194
3195 bcm43xx_rng_exit(dev->wl);
3196 bcm43xx_pio_free(dev);
3197 bcm43xx_dma_free(dev);
3198 bcm43xx_chip_exit(dev);
3199 bcm43xx_radio_turn_off(dev);
3200 bcm43xx_switch_analog(dev, 0);
3201 if (phy->dyn_tssi_tbl)
3202 kfree(phy->tssi2dbm);
3203 kfree(phy->lo_control);
3204 phy->lo_control = NULL;
3205 ssb_device_disable(dev->dev, 0);
3206 ssb_bus_may_powerdown(dev->dev->bus);
3207 bcm43xx_set_status(dev, BCM43xx_STAT_UNINIT);
3208 }
3209
3210 /* Initialize a wireless core */
3211 static int bcm43xx_wireless_core_init(struct bcm43xx_wldev *dev)
3212 {
3213 struct bcm43xx_wl *wl = dev->wl;
3214 struct ssb_bus *bus = dev->dev->bus;
3215 struct ssb_sprom *sprom = &bus->sprom;
3216 struct bcm43xx_phy *phy = &dev->phy;
3217 int err;
3218 u32 hf, tmp;
3219
3220 assert(bcm43xx_status(dev) == BCM43xx_STAT_UNINIT);
3221 bcm43xx_set_status(dev, BCM43xx_STAT_INITIALIZING);
3222
3223 err = ssb_bus_powerup(bus, 0);
3224 if (err)
3225 goto out;
3226 if (!ssb_device_is_enabled(dev->dev)) {
3227 tmp = phy->gmode ? BCM43xx_TMSLOW_GMODE : 0;
3228 bcm43xx_wireless_core_reset(dev, tmp);
3229 }
3230
3231 if ((phy->type == BCM43xx_PHYTYPE_B) || (phy->type == BCM43xx_PHYTYPE_G)) {
3232 phy->lo_control = kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3233 if (!phy->lo_control) {
3234 err = -ENOMEM;
3235 goto err_busdown;
3236 }
3237 }
3238 setup_struct_wldev_for_init(dev);
3239
3240 err = bcm43xx_phy_init_tssi2dbm_table(dev);
3241 if (err)
3242 goto err_kfree_lo_control;
3243
3244 /* Enable IRQ routing to this device. */
3245 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3246
3247 bcm43xx_imcfglo_timeouts_workaround(dev);
3248 bcm43xx_bluetooth_coext_disable(dev);
3249 bcm43xx_phy_early_init(dev);
3250 err = bcm43xx_chip_init(dev);
3251 if (err)
3252 goto err_kfree_tssitbl;
3253 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
3254 BCM43xx_SHM_SH_WLCOREREV,
3255 dev->dev->id.revision);
3256 hf = bcm43xx_hf_read(dev);
3257 if (phy->type == BCM43xx_PHYTYPE_G) {
3258 hf |= BCM43xx_HF_SYMW;
3259 if (phy->rev == 1)
3260 hf |= BCM43xx_HF_GDCW;
3261 if (sprom->r1.boardflags_lo & BCM43xx_BFL_PACTRL)
3262 hf |= BCM43xx_HF_OFDMPABOOST;
3263 } else if (phy->type == BCM43xx_PHYTYPE_B) {
3264 hf |= BCM43xx_HF_SYMW;
3265 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3266 hf &= ~BCM43xx_HF_GDCW;
3267 }
3268 bcm43xx_hf_write(dev, hf);
3269
3270 /* Short/Long Retry Limit.
3271 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3272 * the chip-internal counter.
3273 */
3274 tmp = limit_value(modparam_short_retry, 0, 0xF);
3275 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3276 BCM43xx_SHM_SC_SRLIMIT, tmp);
3277 tmp = limit_value(modparam_long_retry, 0, 0xF);
3278 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3279 BCM43xx_SHM_SC_LRLIMIT, tmp);
3280
3281 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
3282 BCM43xx_SHM_SH_SFFBLIM, 3);
3283 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
3284 BCM43xx_SHM_SH_LFFBLIM, 2);
3285
3286 bcm43xx_rate_memory_init(dev);
3287
3288 /* Minimum Contention Window */
3289 if (phy->type == BCM43xx_PHYTYPE_B) {
3290 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3291 BCM43xx_SHM_SC_MINCONT, 0x1F);
3292 } else {
3293 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3294 BCM43xx_SHM_SC_MINCONT, 0xF);
3295 }
3296 /* Maximum Contention Window */
3297 bcm43xx_shm_write16(dev, BCM43xx_SHM_SCRATCH,
3298 BCM43xx_SHM_SC_MAXCONT, 0x3FF);
3299
3300 do {
3301 if (bcm43xx_using_pio(dev)) {
3302 err = bcm43xx_pio_init(dev);
3303 } else {
3304 err = bcm43xx_dma_init(dev);
3305 if (!err)
3306 bcm43xx_qos_init(dev);
3307 }
3308 } while (err == -EAGAIN);
3309 if (err)
3310 goto err_chip_exit;
3311
3312 //FIXME
3313 #if 1
3314 bcm43xx_write16(dev, 0x0612, 0x0050);
3315 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
3316 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
3317 #endif
3318
3319 bcm43xx_bluetooth_coext_enable(dev);
3320
3321 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3322 wl->bssid = NULL;
3323 bcm43xx_upload_card_macaddress(dev, NULL);
3324 bcm43xx_security_init(dev);
3325 bcm43xx_rng_init(wl);
3326
3327 bcm43xx_set_status(dev, BCM43xx_STAT_INITIALIZED);
3328
3329 out:
3330 return err;
3331
3332 err_chip_exit:
3333 bcm43xx_chip_exit(dev);
3334 err_kfree_tssitbl:
3335 if (phy->dyn_tssi_tbl)
3336 kfree(phy->tssi2dbm);
3337 err_kfree_lo_control:
3338 kfree(phy->lo_control);
3339 phy->lo_control = NULL;
3340 err_busdown:
3341 ssb_bus_may_powerdown(bus);
3342 bcm43xx_set_status(dev, BCM43xx_STAT_UNINIT);
3343 return err;
3344 }
3345
3346 static int bcm43xx_add_interface(struct ieee80211_hw *hw,
3347 struct ieee80211_if_init_conf *conf)
3348 {
3349 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
3350 struct bcm43xx_wldev *dev;
3351 unsigned long flags;
3352 int err = -EOPNOTSUPP;
3353 int did_init = 0;
3354
3355 mutex_lock(&wl->mutex);
3356 if ((conf->type != IEEE80211_IF_TYPE_MNTR) &&
3357 wl->operating)
3358 goto out_mutex_unlock;
3359
3360 dprintk(KERN_INFO PFX "Adding Interface type %d\n", conf->type);
3361
3362 dev = wl->current_dev;
3363 if (bcm43xx_status(dev) == BCM43xx_STAT_UNINIT) {
3364 err = bcm43xx_wireless_core_init(dev);
3365 if (err)
3366 goto out_mutex_unlock;
3367 did_init = 1;
3368 }
3369 if (!dev->started) {
3370 err = bcm43xx_wireless_core_start(dev);
3371 if (err) {
3372 if (did_init)
3373 bcm43xx_wireless_core_exit(dev);
3374 goto out_mutex_unlock;
3375 }
3376 }
3377
3378 spin_lock_irqsave(&wl->irq_lock, flags);
3379 switch (conf->type) {
3380 case IEEE80211_IF_TYPE_MNTR:
3381 wl->monitor++;
3382 break;
3383 default:
3384 wl->operating = 1;
3385 wl->if_id = conf->if_id;
3386 wl->if_type = conf->type;
3387 bcm43xx_upload_card_macaddress(dev, conf->mac_addr);
3388 }
3389 bcm43xx_adjust_opmode(dev);
3390 spin_unlock_irqrestore(&wl->irq_lock, flags);
3391
3392 err = 0;
3393 out_mutex_unlock:
3394 mutex_unlock(&wl->mutex);
3395
3396 return err;
3397 }
3398
3399 static void bcm43xx_remove_interface(struct ieee80211_hw *hw,
3400 struct ieee80211_if_init_conf *conf)
3401 {
3402 struct bcm43xx_wl *wl = hw_to_bcm43xx_wl(hw);
3403 struct bcm43xx_wldev *dev;
3404 unsigned long flags;
3405
3406 dprintk(KERN_INFO PFX "Removing Interface type %d\n", conf->type);
3407
3408 mutex_lock(&wl->mutex);
3409 if (conf->type == IEEE80211_IF_TYPE_MNTR) {
3410 wl->monitor--;
3411 assert(wl->monitor >= 0);
3412 } else {
3413 assert(wl->operating);
3414 wl->operating = 0;
3415 }
3416
3417 dev = wl->current_dev;
3418 if (!wl->operating && wl->monitor == 0) {
3419 /* No interface left. */
3420 if (dev->started)
3421 bcm43xx_wireless_core_stop(dev);
3422 bcm43xx_wireless_core_exit(dev);
3423 } else {
3424 /* Just monitor interfaces left. */
3425 spin_lock_irqsave(&wl->irq_lock, flags);
3426 bcm43xx_adjust_opmode(dev);
3427 if (!wl->operating)
3428 bcm43xx_upload_card_macaddress(dev, NULL);
3429 spin_unlock_irqrestore(&wl->irq_lock, flags);
3430 }
3431 mutex_unlock(&wl->mutex);
3432 }
3433
3434
3435 static const struct ieee80211_ops bcm43xx_hw_ops = {
3436 .tx = bcm43xx_tx,
3437 .conf_tx = bcm43xx_conf_tx,
3438 .add_interface = bcm43xx_add_interface,
3439 .remove_interface = bcm43xx_remove_interface,
3440 .reset = bcm43xx_dev_reset,
3441 .config = bcm43xx_dev_config,
3442 .config_interface = bcm43xx_config_interface,
3443 .set_multicast_list = bcm43xx_set_multicast_list,
3444 .set_key = bcm43xx_dev_set_key,
3445 .get_stats = bcm43xx_get_stats,
3446 .get_tx_stats = bcm43xx_get_tx_stats,
3447 };
3448
3449 /* Hard-reset the chip. Do not call this directly.
3450 * Use bcm43xx_controller_restart()
3451 */
3452 static void bcm43xx_chip_reset(struct work_struct *work)
3453 {
3454 struct bcm43xx_wldev *dev =
3455 container_of(work, struct bcm43xx_wldev, restart_work);
3456 struct bcm43xx_wl *wl = dev->wl;
3457 int err;
3458 int was_started = 0;
3459 int was_inited = 0;
3460
3461 mutex_lock(&wl->mutex);
3462
3463 /* Bring the device down... */
3464 if (dev->started) {
3465 was_started = 1;
3466 bcm43xx_wireless_core_stop(dev);
3467 }
3468 if (bcm43xx_status(dev) == BCM43xx_STAT_INITIALIZED) {
3469 was_inited = 1;
3470 bcm43xx_wireless_core_exit(dev);
3471 }
3472
3473 /* ...and up again. */
3474 if (was_inited) {
3475 err = bcm43xx_wireless_core_init(dev);
3476 if (err)
3477 goto out;
3478 }
3479 if (was_started) {
3480 assert(was_inited);
3481 err = bcm43xx_wireless_core_start(dev);
3482 if (err) {
3483 bcm43xx_wireless_core_exit(dev);
3484 goto out;
3485 }
3486 }
3487 out:
3488 mutex_unlock(&wl->mutex);
3489 if (err)
3490 printk(KERN_ERR PFX "Controller restart FAILED\n");
3491 else
3492 printk(KERN_INFO PFX "Controller restarted\n");
3493 }
3494
3495 static int bcm43xx_setup_modes(struct bcm43xx_wldev *dev,
3496 int have_aphy,
3497 int have_bphy,
3498 int have_gphy)
3499 {
3500 struct ieee80211_hw *hw = dev->wl->hw;
3501 struct ieee80211_hw_mode *mode;
3502 struct bcm43xx_phy *phy = &dev->phy;
3503 int cnt = 0;
3504 int err;
3505
3506 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3507 have_aphy = 0;
3508
3509 phy->possible_phymodes = 0;
3510 for ( ; 1; cnt++) {
3511 if (have_aphy) {
3512 assert(cnt < BCM43xx_MAX_PHYHWMODES);
3513 mode = &phy->hwmodes[cnt];
3514
3515 mode->mode = MODE_IEEE80211A;
3516 mode->num_channels = bcm43xx_a_chantable_size;
3517 mode->channels = bcm43xx_a_chantable;
3518 mode->num_rates = bcm43xx_a_ratetable_size;
3519 mode->rates = bcm43xx_a_ratetable;
3520 err = ieee80211_register_hwmode(hw, mode);
3521 if (err)
3522 return err;
3523
3524 phy->possible_phymodes |= BCM43xx_PHYMODE_A;
3525 have_aphy = 0;
3526 continue;
3527 }
3528 if (have_bphy) {
3529 assert(cnt < BCM43xx_MAX_PHYHWMODES);
3530 mode = &phy->hwmodes[cnt];
3531
3532 mode->mode = MODE_IEEE80211B;
3533 mode->num_channels = bcm43xx_bg_chantable_size;
3534 mode->channels = bcm43xx_bg_chantable;
3535 mode->num_rates = bcm43xx_b_ratetable_size;
3536 mode->rates = bcm43xx_b_ratetable;
3537 err = ieee80211_register_hwmode(hw, mode);
3538 if (err)
3539 return err;
3540
3541 phy->possible_phymodes |= BCM43xx_PHYMODE_B;
3542 have_bphy = 0;
3543 continue;
3544 }
3545 if (have_gphy) {
3546 assert(cnt < BCM43xx_MAX_PHYHWMODES);
3547 mode = &phy->hwmodes[cnt];
3548
3549 mode->mode = MODE_IEEE80211G;
3550 mode->num_channels = bcm43xx_bg_chantable_size;
3551 mode->channels = bcm43xx_bg_chantable;
3552 mode->num_rates = bcm43xx_g_ratetable_size;
3553 mode->rates = bcm43xx_g_ratetable;
3554 err = ieee80211_register_hwmode(hw, mode);
3555 if (err)
3556 return err;
3557
3558 phy->possible_phymodes |= BCM43xx_PHYMODE_G;
3559 have_gphy = 0;
3560 continue;
3561 }
3562 break;
3563 }
3564
3565 return 0;
3566 }
3567
3568 static void bcm43xx_wireless_core_detach(struct bcm43xx_wldev *dev)
3569 {
3570 /* We release firmware that late to not be required to re-request
3571 * is all the time when we reinit the core. */
3572 bcm43xx_release_firmware(dev);
3573 }
3574
3575 static int bcm43xx_wireless_core_attach(struct bcm43xx_wldev *dev)
3576 {
3577 struct bcm43xx_wl *wl = dev->wl;
3578 struct ssb_bus *bus = dev->dev->bus;
3579 struct pci_dev *pdev = bus->host_pci;
3580 int err;
3581 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3582 u32 tmp;
3583
3584 /* Do NOT do any device initialization here.
3585 * Do it in wireless_core_init() instead.
3586 * This function is for gathering basic information about the HW, only.
3587 * Also some structs may be set up here. But most likely you want to have
3588 * that in core_init(), too.
3589 */
3590
3591 /* Get the PHY type. */
3592 if (dev->dev->id.revision >= 5) {
3593 u32 tmshigh;
3594
3595 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3596 have_aphy = !!(tmshigh & BCM43xx_TMSHIGH_APHY);
3597 have_gphy = !!(tmshigh & BCM43xx_TMSHIGH_GPHY);
3598 if (!have_aphy && !have_gphy)
3599 have_bphy = 1;
3600 } else if (dev->dev->id.revision == 4) {
3601 have_gphy = 1;
3602 have_aphy = 1;
3603 } else
3604 have_bphy = 1;
3605
3606 /* Initialize LEDs structs. */
3607 err = bcm43xx_leds_init(dev);
3608 if (err)
3609 goto out;
3610
3611 dev->phy.gmode = (have_gphy || have_bphy);
3612 tmp = dev->phy.gmode ? BCM43xx_TMSLOW_GMODE : 0;
3613 bcm43xx_wireless_core_reset(dev, tmp);
3614
3615 err = bcm43xx_phy_versioning(dev);
3616 if (err)
3617 goto err_leds_exit;
3618 /* Check if this device supports multiband. */
3619 if (!pdev ||
3620 (pdev->device != 0x4312 &&
3621 pdev->device != 0x4319 &&
3622 pdev->device != 0x4324)) {
3623 /* No multiband support. */
3624 have_aphy = 0;
3625 have_bphy = 0;
3626 have_gphy = 0;
3627 switch (dev->phy.type) {
3628 case BCM43xx_PHYTYPE_A:
3629 have_aphy = 1;
3630 break;
3631 case BCM43xx_PHYTYPE_B:
3632 have_bphy = 1;
3633 break;
3634 case BCM43xx_PHYTYPE_G:
3635 have_gphy = 1;
3636 break;
3637 default:
3638 assert(0);
3639 }
3640 }
3641 dev->phy.gmode = (have_gphy || have_bphy);
3642 tmp = dev->phy.gmode ? BCM43xx_TMSLOW_GMODE : 0;
3643 bcm43xx_wireless_core_reset(dev, tmp);
3644
3645 err = bcm43xx_validate_chipaccess(dev);
3646 if (err)
3647 goto err_leds_exit;
3648 err = bcm43xx_setup_modes(dev, have_aphy,
3649 have_bphy, have_gphy);
3650 if (err)
3651 goto err_leds_exit;
3652
3653 /* Now set some default "current_dev" */
3654 if (!wl->current_dev)
3655 wl->current_dev = dev;
3656 INIT_WORK(&dev->restart_work, bcm43xx_chip_reset);
3657
3658 bcm43xx_radio_turn_off(dev);
3659 bcm43xx_switch_analog(dev, 0);
3660 ssb_device_disable(dev->dev, 0);
3661 ssb_bus_may_powerdown(bus);
3662
3663 out:
3664 return err;
3665
3666 err_leds_exit:
3667 bcm43xx_leds_exit(dev);
3668 return err;
3669 }
3670
3671 static void bcm43xx_one_core_detach(struct ssb_device *dev)
3672 {
3673 struct bcm43xx_wldev *wldev;
3674 struct bcm43xx_wl *wl;
3675
3676 wldev = ssb_get_drvdata(dev);
3677 wl = wldev->wl;
3678 bcm43xx_debugfs_remove_device(wldev);
3679 bcm43xx_wireless_core_detach(wldev);
3680 list_del(&wldev->list);
3681 wl->nr_devs--;
3682 ssb_set_drvdata(dev, NULL);
3683 kfree(wldev);
3684 }
3685
3686 static int bcm43xx_one_core_attach(struct ssb_device *dev,
3687 struct bcm43xx_wl *wl)
3688 {
3689 struct bcm43xx_wldev *wldev;
3690 struct pci_dev *pdev;
3691 int err = -ENOMEM;
3692
3693 if (!list_empty(&wl->devlist)) {
3694 /* We are not the first core on this chip. */
3695 pdev = dev->bus->host_pci;
3696 /* Only special chips support more than one wireless
3697 * core, although some of the other chips have more than
3698 * one wireless core as well. Check for this and
3699 * bail out early.
3700 */
3701 if (!pdev ||
3702 ((pdev->device != 0x4321) &&
3703 (pdev->device != 0x4313) &&
3704 (pdev->device != 0x431A))) {
3705 dprintk(KERN_INFO PFX "Ignoring unconnected 802.11 core\n");
3706 return -ENODEV;
3707 }
3708 }
3709
3710 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3711 if (!wldev)
3712 goto out;
3713
3714 wldev->dev = dev;
3715 wldev->wl = wl;
3716 bcm43xx_set_status(wldev, BCM43xx_STAT_UNINIT);
3717 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3718 tasklet_init(&wldev->isr_tasklet,
3719 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3720 (unsigned long)wldev);
3721 if (modparam_pio)
3722 wldev->__using_pio = 1;
3723 INIT_LIST_HEAD(&wldev->list);
3724
3725 err = bcm43xx_wireless_core_attach(wldev);
3726 if (err)
3727 goto err_kfree_wldev;
3728
3729 list_add(&wldev->list, &wl->devlist);
3730 wl->nr_devs++;
3731 ssb_set_drvdata(dev, wldev);
3732 bcm43xx_debugfs_add_device(wldev);
3733
3734 out:
3735 return err;
3736
3737 err_kfree_wldev:
3738 kfree(wldev);
3739 return err;
3740 }
3741
3742 static void bcm43xx_sprom_fixup(struct ssb_bus *bus)
3743 {
3744 /* boardflags workarounds */
3745 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3746 bus->chip_id == 0x4301 &&
3747 bus->boardinfo.rev == 0x74)
3748 bus->sprom.r1.boardflags_lo |= BCM43xx_BFL_BTCOEXIST;
3749 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3750 bus->boardinfo.type == 0x4E &&
3751 bus->boardinfo.rev > 0x40)
3752 bus->sprom.r1.boardflags_lo |= BCM43xx_BFL_PACTRL;
3753
3754 /* Convert Antennagain values to Q5.2 */
3755 bus->sprom.r1.antenna_gain_a <<= 2;
3756 bus->sprom.r1.antenna_gain_bg <<= 2;
3757 }
3758
3759 static void bcm43xx_wireless_exit(struct ssb_device *dev,
3760 struct bcm43xx_wl *wl)
3761 {
3762 struct ieee80211_hw *hw = wl->hw;
3763
3764 ssb_set_devtypedata(dev, NULL);
3765 ieee80211_free_hw(hw);
3766 }
3767
3768 static int bcm43xx_wireless_init(struct ssb_device *dev)
3769 {
3770 struct ssb_sprom *sprom = &dev->bus->sprom;
3771 struct ieee80211_hw *hw;
3772 struct bcm43xx_wl *wl;
3773 int err = -ENOMEM;
3774
3775 bcm43xx_sprom_fixup(dev->bus);
3776
3777 hw = ieee80211_alloc_hw(sizeof(*wl), &bcm43xx_hw_ops);
3778 if (!hw) {
3779 printk(KERN_ERR PFX "Could not allocate ieee80211 device\n");
3780 goto out;
3781 }
3782
3783 /* fill hw info */
3784 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3785 IEEE80211_HW_MONITOR_DURING_OPER |
3786 IEEE80211_HW_DEVICE_HIDES_WEP |
3787 IEEE80211_HW_WEP_INCLUDE_IV;
3788 hw->max_signal = 100;
3789 hw->max_rssi = -110;
3790 hw->max_noise = -110;
3791 hw->queues = 1; /* FIXME: hardware has more queues */
3792 SET_IEEE80211_DEV(hw, dev->dev);
3793 if (is_valid_ether_addr(sprom->r1.et1mac))
3794 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.et1mac);
3795 else
3796 SET_IEEE80211_PERM_ADDR(hw, sprom->r1.il0mac);
3797
3798 /* Get and initialize struct bcm43xx_wl */
3799 wl = hw_to_bcm43xx_wl(hw);
3800 memset(wl, 0, sizeof(*wl));
3801 wl->hw = hw;
3802 spin_lock_init(&wl->irq_lock);
3803 spin_lock_init(&wl->leds_lock);
3804 mutex_init(&wl->mutex);
3805 INIT_LIST_HEAD(&wl->devlist);
3806
3807 ssb_set_devtypedata(dev, wl);
3808 printk(KERN_INFO PFX "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3809 err = 0;
3810 out:
3811 return err;
3812 }
3813
3814 static int bcm43xx_probe(struct ssb_device *dev,
3815 const struct ssb_device_id *id)
3816 {
3817 struct bcm43xx_wl *wl;
3818 int err;
3819 int first = 0;
3820
3821 wl = ssb_get_devtypedata(dev);
3822 if (!wl) {
3823 /* Probing the first core. Must setup common struct bcm43xx_wl */
3824 first = 1;
3825 err = bcm43xx_wireless_init(dev);
3826 if (err)
3827 goto out;
3828 wl = ssb_get_devtypedata(dev);
3829 assert(wl);
3830 }
3831 err = bcm43xx_one_core_attach(dev, wl);
3832 if (err)
3833 goto err_wireless_exit;
3834
3835 if (first) {
3836 err = ieee80211_register_hw(wl->hw);
3837 if (err)
3838 goto err_one_core_detach;
3839 }
3840
3841 out:
3842 return err;
3843
3844 err_one_core_detach:
3845 bcm43xx_one_core_detach(dev);
3846 err_wireless_exit:
3847 if (first)
3848 bcm43xx_wireless_exit(dev, wl);
3849 return err;
3850 }
3851
3852 static void bcm43xx_remove(struct ssb_device *dev)
3853 {
3854 struct bcm43xx_wl *wl = ssb_get_devtypedata(dev);
3855 struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
3856
3857 assert(wl);
3858 if (wl->current_dev == wldev)
3859 ieee80211_unregister_hw(wl->hw);
3860
3861 bcm43xx_one_core_detach(dev);
3862
3863 if (list_empty(&wl->devlist)) {
3864 /* Last core on the chip unregistered.
3865 * We can destroy common struct bcm43xx_wl.
3866 */
3867 bcm43xx_wireless_exit(dev, wl);
3868 }
3869 }
3870
3871 /* Hard-reset the chip.
3872 * This can be called from interrupt or process context.
3873 * dev->irq_lock must be locked.
3874 */
3875 void bcm43xx_controller_restart(struct bcm43xx_wldev *dev, const char *reason)
3876 {
3877 if (bcm43xx_status(dev) != BCM43xx_STAT_INITIALIZED)
3878 return;
3879 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
3880 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3881 }
3882
3883 #ifdef CONFIG_PM
3884
3885 static int bcm43xx_suspend(struct ssb_device *dev, pm_message_t state)
3886 {
3887 struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
3888 struct bcm43xx_wl *wl = wldev->wl;
3889
3890 dprintk(KERN_INFO PFX "Suspending...\n");
3891
3892 mutex_lock(&wl->mutex);
3893 wldev->was_started = !!wldev->started;
3894 wldev->was_initialized = (bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED);
3895 if (wldev->started)
3896 bcm43xx_wireless_core_stop(wldev);
3897 if (bcm43xx_status(wldev) == BCM43xx_STAT_INITIALIZED)
3898 bcm43xx_wireless_core_exit(wldev);
3899
3900 mutex_unlock(&wl->mutex);
3901
3902 dprintk(KERN_INFO PFX "Device suspended.\n");
3903
3904 return 0;
3905 }
3906
3907 static int bcm43xx_resume(struct ssb_device *dev)
3908 {
3909 struct bcm43xx_wldev *wldev = ssb_get_drvdata(dev);
3910 int err = 0;
3911
3912 dprintk(KERN_INFO PFX "Resuming...\n");
3913
3914 if (wldev->was_initialized) {
3915 err = bcm43xx_wireless_core_init(wldev);
3916 if (err) {
3917 printk(KERN_ERR PFX "Resume failed at core init\n");
3918 goto out;
3919 }
3920 }
3921 if (wldev->was_started) {
3922 assert(wldev->was_initialized);
3923 err = bcm43xx_wireless_core_start(wldev);
3924 if (err) {
3925 printk(KERN_ERR PFX "Resume failed at core start\n");
3926 goto out;
3927 }
3928 }
3929
3930 dprintk(KERN_INFO PFX "Device resumed.\n");
3931 out:
3932 return err;
3933 }
3934
3935 #else /* CONFIG_PM */
3936 # define bcm43xx_suspend NULL
3937 # define bcm43xx_resume NULL
3938 #endif /* CONFIG_PM */
3939
3940 static struct ssb_driver bcm43xx_ssb_driver = {
3941 .name = KBUILD_MODNAME,
3942 .id_table = bcm43xx_ssb_tbl,
3943 .probe = bcm43xx_probe,
3944 .remove = bcm43xx_remove,
3945 .suspend = bcm43xx_suspend,
3946 .resume = bcm43xx_resume,
3947 };
3948
3949 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3950 /* The PCI frontend stub */
3951 static const struct pci_device_id bcm43xx_pci_tbl[] = {
3952 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4307) },
3953 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4311) },
3954 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
3955 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
3956 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
3957 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
3958 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
3959 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
3960 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
3961 { 0 },
3962 };
3963 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
3964
3965 static struct pci_driver bcm43xx_pci_driver = {
3966 .name = "bcm43xx-pci",
3967 .id_table = bcm43xx_pci_tbl,
3968 };
3969 #endif /* CONFIG_BCM43XX_MAC80211_PCI */
3970
3971 static int __init bcm43xx_init(void)
3972 {
3973 int err;
3974
3975 bcm43xx_debugfs_init();
3976 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3977 err = ssb_pcihost_register(&bcm43xx_pci_driver);
3978 if (err)
3979 goto err_dfs_exit;
3980 #endif
3981 err = bcm43xx_pcmcia_init();
3982 if (err)
3983 goto err_pci_exit;
3984 err = ssb_driver_register(&bcm43xx_ssb_driver);
3985 if (err)
3986 goto err_pcmcia_exit;
3987
3988 return err;
3989
3990 err_pcmcia_exit:
3991 bcm43xx_pcmcia_exit();
3992 err_pci_exit:
3993 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3994 ssb_pcihost_unregister(&bcm43xx_pci_driver);
3995 #endif
3996 err_dfs_exit:
3997 bcm43xx_debugfs_exit();
3998 return err;
3999 }
4000
4001 static void __exit bcm43xx_exit(void)
4002 {
4003 ssb_driver_unregister(&bcm43xx_ssb_driver);
4004 bcm43xx_pcmcia_exit();
4005 #ifdef CONFIG_BCM43XX_MAC80211_PCI
4006 ssb_pcihost_unregister(&bcm43xx_pci_driver);
4007 #endif
4008 bcm43xx_debugfs_exit();
4009 }
4010
4011 module_init(bcm43xx_init)
4012 module_exit(bcm43xx_exit)
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