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[openwrt.git] / package / bcm43xx-mac80211 / src / bcm43xx / bcm43xx_phy.c
1 /*
2
3 Broadcom BCM43xx wireless driver
4
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Copyright (c) 2005, 2006 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; see the file COPYING. If not, write to
23 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
24 Boston, MA 02110-1301, USA.
25
26 */
27
28 #include <linux/delay.h>
29 #include <linux/types.h>
30
31 #include "bcm43xx.h"
32 #include "bcm43xx_phy.h"
33 #include "bcm43xx_main.h"
34 #include "bcm43xx_tables.h"
35 #include "bcm43xx_power.h"
36 #include "bcm43xx_lo.h"
37
38
39 static const s8 bcm43xx_tssi2dbm_b_table[] = {
40 0x4D, 0x4C, 0x4B, 0x4A,
41 0x4A, 0x49, 0x48, 0x47,
42 0x47, 0x46, 0x45, 0x45,
43 0x44, 0x43, 0x42, 0x42,
44 0x41, 0x40, 0x3F, 0x3E,
45 0x3D, 0x3C, 0x3B, 0x3A,
46 0x39, 0x38, 0x37, 0x36,
47 0x35, 0x34, 0x32, 0x31,
48 0x30, 0x2F, 0x2D, 0x2C,
49 0x2B, 0x29, 0x28, 0x26,
50 0x25, 0x23, 0x21, 0x1F,
51 0x1D, 0x1A, 0x17, 0x14,
52 0x10, 0x0C, 0x06, 0x00,
53 -7, -7, -7, -7,
54 -7, -7, -7, -7,
55 -7, -7, -7, -7,
56 };
57
58 static const s8 bcm43xx_tssi2dbm_g_table[] = {
59 77, 77, 77, 76,
60 76, 76, 75, 75,
61 74, 74, 73, 73,
62 73, 72, 72, 71,
63 71, 70, 70, 69,
64 68, 68, 67, 67,
65 66, 65, 65, 64,
66 63, 63, 62, 61,
67 60, 59, 58, 57,
68 56, 55, 54, 53,
69 52, 50, 49, 47,
70 45, 43, 40, 37,
71 33, 28, 22, 14,
72 5, -7, -20, -20,
73 -20, -20, -20, -20,
74 -20, -20, -20, -20,
75 };
76
77 const u8 bcm43xx_radio_channel_codes_bg[] = {
78 12, 17, 22, 27,
79 32, 37, 42, 47,
80 52, 57, 62, 67,
81 72, 84,
82 };
83
84
85 static void bcm43xx_phy_initg(struct bcm43xx_wldev *dev);
86
87 /* Reverse the bits of a 4bit value.
88 * Example: 1101 is flipped 1011
89 */
90 static u16 flip_4bit(u16 value)
91 {
92 u16 flipped = 0x0000;
93
94 assert((value & ~0x000F) == 0x0000);
95
96 flipped |= (value & 0x0001) << 3;
97 flipped |= (value & 0x0002) << 1;
98 flipped |= (value & 0x0004) >> 1;
99 flipped |= (value & 0x0008) >> 3;
100
101 return flipped;
102 }
103
104 static void generate_rfatt_list(struct bcm43xx_wldev *dev,
105 struct bcm43xx_rfatt_list *list)
106 {
107 struct bcm43xx_phy *phy = &dev->phy;
108
109 /* APHY.rev < 5 || GPHY.rev < 6 */
110 static const struct bcm43xx_rfatt rfatt_0[] = {
111 { .att = 3, .with_padmix = 0, },
112 { .att = 1, .with_padmix = 0, },
113 { .att = 5, .with_padmix = 0, },
114 { .att = 7, .with_padmix = 0, },
115 { .att = 9, .with_padmix = 0, },
116 { .att = 2, .with_padmix = 0, },
117 { .att = 0, .with_padmix = 0, },
118 { .att = 4, .with_padmix = 0, },
119 { .att = 6, .with_padmix = 0, },
120 { .att = 8, .with_padmix = 0, },
121 { .att = 1, .with_padmix = 1, },
122 { .att = 2, .with_padmix = 1, },
123 { .att = 3, .with_padmix = 1, },
124 { .att = 4, .with_padmix = 1, },
125 };
126 /* Radio.rev == 8 && Radio.version == 0x2050 */
127 static const struct bcm43xx_rfatt rfatt_1[] = {
128 { .att = 2, .with_padmix = 1, },
129 { .att = 4, .with_padmix = 1, },
130 { .att = 6, .with_padmix = 1, },
131 { .att = 8, .with_padmix = 1, },
132 { .att = 10, .with_padmix = 1, },
133 { .att = 12, .with_padmix = 1, },
134 { .att = 14, .with_padmix = 1, },
135 };
136 /* Otherwise */
137 static const struct bcm43xx_rfatt rfatt_2[] = {
138 { .att = 0, .with_padmix = 1, },
139 { .att = 2, .with_padmix = 1, },
140 { .att = 4, .with_padmix = 1, },
141 { .att = 6, .with_padmix = 1, },
142 { .att = 8, .with_padmix = 1, },
143 { .att = 9, .with_padmix = 1, },
144 { .att = 9, .with_padmix = 1, },
145 };
146
147 if ((phy->type == BCM43xx_PHYTYPE_A && phy->rev < 5) ||
148 (phy->type == BCM43xx_PHYTYPE_G && phy->rev < 6)) {
149 /* Software pctl */
150 list->list = rfatt_0;
151 list->len = ARRAY_SIZE(rfatt_0);
152 list->min_val = 0;
153 list->max_val = 9;
154 return;
155 }
156 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
157 /* Hardware pctl */
158 list->list = rfatt_1;
159 list->len = ARRAY_SIZE(rfatt_1);
160 list->min_val = 2;
161 list->max_val = 14;
162 return;
163 }
164 /* Hardware pctl */
165 list->list = rfatt_2;
166 list->len = ARRAY_SIZE(rfatt_2);
167 list->min_val = 0;
168 list->max_val = 9;
169 }
170
171 static void generate_bbatt_list(struct bcm43xx_wldev *dev,
172 struct bcm43xx_bbatt_list *list)
173 {
174 static const struct bcm43xx_bbatt bbatt_0[] = {
175 { .att = 0, },
176 { .att = 1, },
177 { .att = 2, },
178 { .att = 3, },
179 { .att = 4, },
180 { .att = 5, },
181 { .att = 6, },
182 { .att = 7, },
183 { .att = 8, },
184 };
185
186 list->list = bbatt_0;
187 list->len = ARRAY_SIZE(bbatt_0);
188 list->min_val = 0;
189 list->max_val = 8;
190 }
191
192 static void bcm43xx_shm_clear_tssi(struct bcm43xx_wldev *dev)
193 {
194 struct bcm43xx_phy *phy = &dev->phy;
195
196 switch (phy->type) {
197 case BCM43xx_PHYTYPE_A:
198 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0068, 0x7F7F);
199 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x006a, 0x7F7F);
200 break;
201 case BCM43xx_PHYTYPE_B:
202 case BCM43xx_PHYTYPE_G:
203 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0058, 0x7F7F);
204 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x005a, 0x7F7F);
205 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0070, 0x7F7F);
206 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, 0x0072, 0x7F7F);
207 break;
208 }
209 }
210
211 void bcm43xx_raw_phy_lock(struct bcm43xx_wldev *dev)
212 {
213 struct bcm43xx_phy *phy = &dev->phy;
214
215 assert(irqs_disabled());
216 if (bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD) == 0) {
217 phy->locked = 0;
218 return;
219 }
220 if (dev->dev->id.revision < 3) {
221 bcm43xx_mac_suspend(dev);
222 spin_lock(&phy->lock);
223 } else {
224 if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
225 bcm43xx_power_saving_ctl_bits(dev, -1, 1);
226 }
227 phy->locked = 1;
228 }
229
230 void bcm43xx_raw_phy_unlock(struct bcm43xx_wldev *dev)
231 {
232 struct bcm43xx_phy *phy = &dev->phy;
233
234 assert(irqs_disabled());
235 if (dev->dev->id.revision < 3) {
236 if (phy->locked) {
237 spin_unlock(&phy->lock);
238 bcm43xx_mac_enable(dev);
239 }
240 } else {
241 if (!bcm43xx_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
242 bcm43xx_power_saving_ctl_bits(dev, -1, -1);
243 }
244 phy->locked = 0;
245 }
246
247 /* Different PHYs require different register routing flags.
248 * This adjusts (and does sanity checks on) the routing flags.
249 */
250 static inline u16 adjust_phyreg_for_phytype(struct bcm43xx_phy *phy,
251 u16 offset)
252 {
253 if (phy->type == BCM43xx_PHYTYPE_A) {
254 /* OFDM registers are base-registers for the A-PHY. */
255 offset &= ~BCM43xx_PHYROUTE_OFDM_GPHY;
256 }
257 if (offset & BCM43xx_PHYROUTE_EXT_GPHY) {
258 /* Ext-G registers are only available on G-PHYs */
259 if (phy->type != BCM43xx_PHYTYPE_G) {
260 dprintk(KERN_ERR PFX "EXT-G PHY access at "
261 "0x%04X on %u type PHY\n",
262 offset, phy->type);
263 }
264 }
265
266 return offset;
267 }
268
269 u16 bcm43xx_phy_read(struct bcm43xx_wldev *dev, u16 offset)
270 {
271 struct bcm43xx_phy *phy = &dev->phy;
272
273 offset = adjust_phyreg_for_phytype(phy, offset);
274 bcm43xx_write16(dev, BCM43xx_MMIO_PHY_CONTROL, offset);
275 return bcm43xx_read16(dev, BCM43xx_MMIO_PHY_DATA);
276 }
277
278 void bcm43xx_phy_write(struct bcm43xx_wldev *dev, u16 offset, u16 val)
279 {
280 struct bcm43xx_phy *phy = &dev->phy;
281
282 offset = adjust_phyreg_for_phytype(phy, offset);
283 bcm43xx_write16(dev, BCM43xx_MMIO_PHY_CONTROL, offset);
284 mmiowb();
285 bcm43xx_write16(dev, BCM43xx_MMIO_PHY_DATA, val);
286 }
287
288 static void bcm43xx_radio_set_txpower_a(struct bcm43xx_wldev *dev, u16 txpower);
289
290 /* Adjust the transmission power output (G-PHY) */
291 void bcm43xx_set_txpower_g(struct bcm43xx_wldev *dev,
292 const struct bcm43xx_bbatt *bbatt,
293 const struct bcm43xx_rfatt *rfatt,
294 u8 tx_control)
295 {
296 struct bcm43xx_phy *phy = &dev->phy;
297 struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
298 u16 bb, rf;
299 u16 tx_bias, tx_magn;
300
301 bb = bbatt->att;
302 rf = rfatt->att;
303 tx_bias = lo->tx_bias;
304 tx_magn = lo->tx_magn;
305 if (unlikely(tx_bias == 0xFF))
306 tx_bias = 0;
307
308 /* Save the values for later */
309 phy->tx_control = tx_control;
310 memcpy(&phy->rfatt, rfatt, sizeof(*rfatt));
311 memcpy(&phy->bbatt, bbatt, sizeof(*bbatt));
312
313 if (bcm43xx_debug(dev, BCM43xx_DBG_XMITPOWER)) {
314 dprintk(KERN_DEBUG PFX "Tuning TX-power to bbatt(%u), "
315 "rfatt(%u), tx_control(0x%02X), "
316 "tx_bias(0x%02X), tx_magn(0x%02X)\n",
317 bb, rf, tx_control, tx_bias, tx_magn);
318 }
319
320 bcm43xx_phy_set_baseband_attenuation(dev, bb);
321 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED, BCM43xx_SHM_SH_RFATT, rf);
322 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
323 bcm43xx_radio_write16(dev, 0x43,
324 (rf & 0x000F) | (tx_control & 0x0070));
325 } else {
326 bcm43xx_radio_write16(dev, 0x43,
327 (bcm43xx_radio_read16(dev, 0x43)
328 & 0xFFF0) | (rf & 0x000F));
329 bcm43xx_radio_write16(dev, 0x52,
330 (bcm43xx_radio_read16(dev, 0x52)
331 & ~0x0070) | (tx_control & 0x0070));
332 }
333 if (has_tx_magnification(phy)) {
334 bcm43xx_radio_write16(dev, 0x52, tx_magn | tx_bias);
335 } else {
336 bcm43xx_radio_write16(dev, 0x52,
337 (bcm43xx_radio_read16(dev, 0x52)
338 & 0xFFF0) | (tx_bias & 0x000F));
339 }
340 if (phy->type == BCM43xx_PHYTYPE_G)
341 bcm43xx_lo_g_adjust(dev);
342 }
343
344 static void default_baseband_attenuation(struct bcm43xx_wldev *dev,
345 struct bcm43xx_bbatt *bb)
346 {
347 struct bcm43xx_phy *phy = &dev->phy;
348
349 if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
350 bb->att = 0;
351 else
352 bb->att = 2;
353 }
354
355 static void default_radio_attenuation(struct bcm43xx_wldev *dev,
356 struct bcm43xx_rfatt *rf)
357 {
358 struct ssb_bus *bus = dev->dev->bus;
359 struct bcm43xx_phy *phy = &dev->phy;
360
361 rf->with_padmix = 0;
362
363 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
364 bus->boardinfo.type == SSB_BOARD_BCM4309G) {
365 if (bus->boardinfo.rev < 0x43) {
366 rf->att = 2;
367 return;
368 } else if (bus->boardinfo.rev < 0x51) {
369 rf->att = 3;
370 return;
371 }
372 }
373
374 if (phy->type == BCM43xx_PHYTYPE_A) {
375 rf->att = 0x60;
376 return;
377 }
378
379 switch (phy->radio_ver) {
380 case 0x2053:
381 switch (phy->radio_rev) {
382 case 1:
383 rf->att = 6;
384 return;
385 }
386 break;
387 case 0x2050:
388 switch (phy->radio_rev) {
389 case 0:
390 rf->att = 5;
391 return;
392 case 1:
393 if (phy->type == BCM43xx_PHYTYPE_G) {
394 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
395 bus->boardinfo.type == SSB_BOARD_BCM4309G &&
396 bus->boardinfo.rev >= 30)
397 rf->att = 3;
398 else if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
399 bus->boardinfo.type == SSB_BOARD_BU4306)
400 rf->att = 3;
401 else
402 rf->att = 1;
403 } else {
404 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
405 bus->boardinfo.type == SSB_BOARD_BCM4309G &&
406 bus->boardinfo.rev >= 30)
407 rf->att = 7;
408 else
409 rf->att = 6;
410 }
411 return;
412 case 2:
413 if (phy->type == BCM43xx_PHYTYPE_G) {
414 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
415 bus->boardinfo.type == SSB_BOARD_BCM4309G &&
416 bus->boardinfo.rev >= 30)
417 rf->att = 3;
418 else if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
419 bus->boardinfo.type == SSB_BOARD_BU4306)
420 rf->att = 5;
421 else if (bus->chip_id == 0x4320)
422 rf->att = 4;
423 else
424 rf->att = 3;
425 } else
426 rf->att = 6;
427 return;
428 case 3:
429 rf->att = 5;
430 return;
431 case 4:
432 case 5:
433 rf->att = 1;
434 return;
435 case 6:
436 case 7:
437 rf->att = 5;
438 return;
439 case 8:
440 rf->att = 0xA;
441 rf->with_padmix = 1;
442 return;
443 case 9:
444 default:
445 rf->att = 5;
446 return;
447 }
448 }
449 rf->att = 5;
450 }
451
452 static u16 default_tx_control(struct bcm43xx_wldev *dev)
453 {
454 struct bcm43xx_phy *phy = &dev->phy;
455
456 if (phy->radio_ver != 0x2050)
457 return 0;
458 if (phy->radio_rev == 1)
459 return BCM43xx_TXCTL_PA2DB | BCM43xx_TXCTL_TXMIX;
460 if (phy->radio_rev < 6)
461 return BCM43xx_TXCTL_PA2DB;
462 if (phy->radio_rev == 8)
463 return BCM43xx_TXCTL_TXMIX;
464 return 0;
465 }
466
467 /* This func is called "PHY calibrate" in the specs... */
468 void bcm43xx_phy_early_init(struct bcm43xx_wldev *dev)
469 {
470 struct bcm43xx_phy *phy = &dev->phy;
471 struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
472
473 default_baseband_attenuation(dev, &phy->bbatt);
474 default_radio_attenuation(dev, &phy->rfatt);
475 phy->tx_control = (default_tx_control(dev) << 4);
476
477 bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD); /* Dummy read. */
478 if (phy->type == BCM43xx_PHYTYPE_B ||
479 phy->type == BCM43xx_PHYTYPE_G) {
480 generate_rfatt_list(dev, &lo->rfatt_list);
481 generate_bbatt_list(dev, &lo->bbatt_list);
482 }
483 if (phy->type == BCM43xx_PHYTYPE_G && phy->rev == 1) {
484 /* Workaround: Temporarly disable gmode through the early init
485 * phase, as the gmode stuff is not needed for phy rev 1 */
486 phy->gmode = 0;
487 bcm43xx_wireless_core_reset(dev, 0);
488 bcm43xx_phy_initg(dev);
489 phy->gmode = 1;
490 bcm43xx_wireless_core_reset(dev, BCM43xx_TMSLOW_GMODE);
491 }
492 }
493
494 /* GPHY_TSSI_Power_Lookup_Table_Init */
495 static void bcm43xx_gphy_tssi_power_lt_init(struct bcm43xx_wldev *dev)
496 {
497 struct bcm43xx_phy *phy = &dev->phy;
498 int i;
499 u16 value;
500
501 for (i = 0; i < 32; i++)
502 bcm43xx_ofdmtab_write16(dev, 0x3C20, i, phy->tssi2dbm[i]);
503 for (i = 32; i < 64; i++)
504 bcm43xx_ofdmtab_write16(dev, 0x3C00, i - 32, phy->tssi2dbm[i]);
505 for (i = 0; i < 64; i += 2) {
506 value = (u16)phy->tssi2dbm[i];
507 value |= ((u16)phy->tssi2dbm[i + 1]) << 8;
508 bcm43xx_phy_write(dev, 0x380 + (i / 2), value);
509 }
510 }
511
512 /* GPHY_Gain_Lookup_Table_Init */
513 static void bcm43xx_gphy_gain_lt_init(struct bcm43xx_wldev *dev)
514 {
515 struct bcm43xx_phy *phy = &dev->phy;
516 struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
517 u16 nr_written = 0;
518 u16 tmp;
519 u8 rf, bb;
520
521 if (!lo->lo_measured) {
522 bcm43xx_phy_write(dev, 0x3FF, 0);
523 return;
524 }
525
526 for (rf = 0; rf < lo->rfatt_list.len; rf++) {
527 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
528 if (nr_written >= 0x40)
529 return;
530 tmp = lo->bbatt_list.list[bb].att;
531 tmp <<= 8;
532 if (phy->radio_rev == 8)
533 tmp |= 0x50;
534 else
535 tmp |= 0x40;
536 tmp |= lo->rfatt_list.list[rf].att;
537 bcm43xx_phy_write(dev, 0x3C0 + nr_written,
538 tmp);
539 nr_written++;
540 }
541 }
542 }
543
544 /* GPHY_DC_Lookup_Table */
545 void bcm43xx_gphy_dc_lt_init(struct bcm43xx_wldev *dev)
546 {
547 struct bcm43xx_phy *phy = &dev->phy;
548 struct bcm43xx_txpower_lo_control *lo = phy->lo_control;
549 struct bcm43xx_loctl *loctl0;
550 struct bcm43xx_loctl *loctl1;
551 int i;
552 int rf_offset, bb_offset;
553 u16 tmp;
554
555 for (i = 0;
556 i < lo->rfatt_list.len + lo->bbatt_list.len;
557 i += 2) {
558 rf_offset = i / lo->rfatt_list.len;
559 bb_offset = i % lo->rfatt_list.len;
560
561 loctl0 = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
562 &lo->bbatt_list.list[bb_offset]);
563 if (i + 1 < lo->rfatt_list.len * lo->bbatt_list.len) {
564 rf_offset = (i + 1) / lo->rfatt_list.len;
565 bb_offset = (i + 1) % lo->rfatt_list.len;
566
567 loctl1 = bcm43xx_get_lo_g_ctl(dev, &lo->rfatt_list.list[rf_offset],
568 &lo->bbatt_list.list[bb_offset]);
569 } else
570 loctl1 = loctl0;
571
572 tmp = ((u16)loctl0->q & 0xF);
573 tmp |= ((u16)loctl0->i & 0xF) << 4;
574 tmp |= ((u16)loctl1->q & 0xF) << 8;
575 tmp |= ((u16)loctl1->i & 0xF) << 12;//FIXME?
576 bcm43xx_phy_write(dev, 0x3A0 + (i / 2),
577 tmp);
578 }
579 }
580
581 static void hardware_pctl_init_aphy(struct bcm43xx_wldev *dev)
582 {
583 //TODO
584 }
585
586 static void hardware_pctl_init_gphy(struct bcm43xx_wldev *dev)
587 {
588 struct bcm43xx_phy *phy = &dev->phy;
589
590 bcm43xx_phy_write(dev, 0x0036,
591 (bcm43xx_phy_read(dev, 0x0036) & 0xFFC0)
592 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
593 bcm43xx_phy_write(dev, 0x0478,
594 (bcm43xx_phy_read(dev, 0x0478) & 0xFF00)
595 | (phy->tgt_idle_tssi - phy->cur_idle_tssi));
596 bcm43xx_gphy_tssi_power_lt_init(dev);
597 bcm43xx_gphy_gain_lt_init(dev);
598 bcm43xx_phy_write(dev, 0x0060,
599 bcm43xx_phy_read(dev, 0x0060) & 0xFFBF);
600 bcm43xx_phy_write(dev, 0x0014, 0x0000);
601
602 assert(phy->rev >= 6);
603 bcm43xx_phy_write(dev, 0x0478,
604 bcm43xx_phy_read(dev, 0x0478)
605 | 0x0800);
606 bcm43xx_phy_write(dev, 0x0478,
607 bcm43xx_phy_read(dev, 0x0478)
608 & 0xFEFF);
609 bcm43xx_phy_write(dev, 0x0801,
610 bcm43xx_phy_read(dev, 0x0801)
611 & 0xFFBF);
612
613 bcm43xx_gphy_dc_lt_init(dev);
614 }
615
616 /* HardwarePowerControl for A and G PHY.
617 * This does nothing, if the card does not have HW PCTL
618 */
619 static void bcm43xx_hardware_pctl_init(struct bcm43xx_wldev *dev)
620 {
621 struct bcm43xx_phy *phy = &dev->phy;
622
623 if (!has_hardware_pctl(phy))
624 return;
625 if (phy->type == BCM43xx_PHYTYPE_A) {
626 hardware_pctl_init_aphy(dev);
627 return;
628 }
629 if (phy->type == BCM43xx_PHYTYPE_G) {
630 hardware_pctl_init_gphy(dev);
631 return;
632 }
633 assert(0);
634 }
635
636 static void bcm43xx_hardware_pctl_early_init(struct bcm43xx_wldev *dev)
637 {
638 struct bcm43xx_phy *phy = &dev->phy;
639
640 if (!has_hardware_pctl(phy)) {
641 bcm43xx_phy_write(dev, 0x047A, 0xC111);
642 return;
643 }
644
645 bcm43xx_phy_write(dev, 0x0036,
646 bcm43xx_phy_read(dev, 0x0036) & 0xFEFF);
647 bcm43xx_phy_write(dev, 0x002F, 0x0202);
648 bcm43xx_phy_write(dev, 0x047C,
649 bcm43xx_phy_read(dev, 0x047C) | 0x0002);
650 bcm43xx_phy_write(dev, 0x047A,
651 bcm43xx_phy_read(dev, 0x047A) | 0xF000);
652 if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
653 bcm43xx_phy_write(dev, 0x047A,
654 (bcm43xx_phy_read(dev, 0x047A)
655 & 0xFF0F) | 0x0010);
656 bcm43xx_phy_write(dev, 0x005D,
657 bcm43xx_phy_read(dev, 0x005D)
658 | 0x8000);
659 bcm43xx_phy_write(dev, 0x004E,
660 (bcm43xx_phy_read(dev, 0x004E)
661 & 0xFFC0) | 0x0010);
662 bcm43xx_phy_write(dev, 0x002E, 0xC07F);
663 bcm43xx_phy_write(dev, 0x0036,
664 bcm43xx_phy_read(dev, 0x0036)
665 | 0x0400);
666 } else {
667 bcm43xx_phy_write(dev, 0x0036,
668 bcm43xx_phy_read(dev, 0x0036)
669 | 0x0200);
670 bcm43xx_phy_write(dev, 0x0036,
671 bcm43xx_phy_read(dev, 0x0036)
672 | 0x0400);
673 bcm43xx_phy_write(dev, 0x005D,
674 bcm43xx_phy_read(dev, 0x005D)
675 & 0x7FFF);
676 bcm43xx_phy_write(dev, 0x004F,
677 bcm43xx_phy_read(dev, 0x004F)
678 & 0xFFFE);
679 bcm43xx_phy_write(dev, 0x004E,
680 (bcm43xx_phy_read(dev, 0x004E)
681 & 0xFFC0) | 0x0010);
682 bcm43xx_phy_write(dev, 0x002E, 0xC07F);
683 bcm43xx_phy_write(dev, 0x047A,
684 (bcm43xx_phy_read(dev, 0x047A)
685 & 0xFF0F) | 0x0010);
686 }
687 }
688
689 /* Intialize B/G PHY power control
690 * as described in http://bcm-specs.sipsolutions.net/InitPowerControl
691 */
692 static void bcm43xx_phy_init_pctl(struct bcm43xx_wldev *dev)
693 {
694 struct ssb_bus *bus = dev->dev->bus;
695 struct bcm43xx_phy *phy = &dev->phy;
696 struct bcm43xx_rfatt old_rfatt;
697 struct bcm43xx_bbatt old_bbatt;
698 u8 old_tx_control = 0;
699
700 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
701 (bus->boardinfo.type == SSB_BOARD_BU4306))
702 return;
703
704 bcm43xx_phy_write(dev, 0x0028, 0x8018);
705
706 /* This does something with the Analog... */
707 bcm43xx_write16(dev, BCM43xx_MMIO_PHY0,
708 bcm43xx_read16(dev, BCM43xx_MMIO_PHY0)
709 & 0xFFDF);
710
711 if (phy->type == BCM43xx_PHYTYPE_G && !phy->gmode)
712 return;
713 bcm43xx_hardware_pctl_early_init(dev);
714 if (phy->cur_idle_tssi == 0) {
715 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
716 bcm43xx_radio_write16(dev, 0x0076,
717 (bcm43xx_radio_read16(dev, 0x0076)
718 & 0x00F7) | 0x0084);
719 } else {
720 struct bcm43xx_rfatt rfatt;
721 struct bcm43xx_bbatt bbatt;
722
723 memcpy(&old_rfatt, &phy->rfatt, sizeof(old_rfatt));
724 memcpy(&old_bbatt, &phy->bbatt, sizeof(old_bbatt));
725 old_tx_control = phy->tx_control;
726
727 bbatt.att = 11;
728 if (phy->radio_rev == 8) {
729 rfatt.att = 15;
730 rfatt.with_padmix = 1;
731 } else {
732 rfatt.att = 9;
733 rfatt.with_padmix = 0;
734 }
735 bcm43xx_set_txpower_g(dev, &bbatt, &rfatt, 0);
736 }
737 bcm43xx_dummy_transmission(dev);
738 phy->cur_idle_tssi = bcm43xx_phy_read(dev, BCM43xx_PHY_ITSSI);
739 if (BCM43xx_DEBUG) {
740 /* Current-Idle-TSSI sanity check. */
741 if (abs(phy->cur_idle_tssi - phy->tgt_idle_tssi) >= 20) {
742 dprintk(KERN_ERR PFX "!WARNING! Idle-TSSI phy->cur_idle_tssi "
743 "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
744 "adjustment.\n", phy->cur_idle_tssi, phy->tgt_idle_tssi);
745 phy->cur_idle_tssi = 0;
746 }
747 }
748 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
749 bcm43xx_radio_write16(dev, 0x0076,
750 bcm43xx_radio_read16(dev, 0x0076)
751 & 0xFF7B);
752 } else {
753 bcm43xx_set_txpower_g(dev, &old_bbatt,
754 &old_rfatt, old_tx_control);
755 }
756 }
757 bcm43xx_hardware_pctl_init(dev);
758 bcm43xx_shm_clear_tssi(dev);
759 }
760
761 static void bcm43xx_phy_agcsetup(struct bcm43xx_wldev *dev)
762 {
763 struct bcm43xx_phy *phy = &dev->phy;
764 u16 offset = 0x0000;
765
766 if (phy->rev == 1)
767 offset = 0x4C00;
768
769 bcm43xx_ofdmtab_write16(dev, offset, 0, 0x00FE);
770 bcm43xx_ofdmtab_write16(dev, offset, 1, 0x000D);
771 bcm43xx_ofdmtab_write16(dev, offset, 2, 0x0013);
772 bcm43xx_ofdmtab_write16(dev, offset, 3, 0x0019);
773
774 if (phy->rev == 1) {
775 bcm43xx_ofdmtab_write16(dev, 0x1800, 0, 0x2710);
776 bcm43xx_ofdmtab_write16(dev, 0x1801, 0, 0x9B83);
777 bcm43xx_ofdmtab_write16(dev, 0x1802, 0, 0x9B83);
778 bcm43xx_ofdmtab_write16(dev, 0x1803, 0, 0x0F8D);
779 bcm43xx_phy_write(dev, 0x0455, 0x0004);
780 }
781
782 bcm43xx_phy_write(dev, 0x04A5,
783 (bcm43xx_phy_read(dev, 0x04A5)
784 & 0x00FF) | 0x5700);
785 bcm43xx_phy_write(dev, 0x041A,
786 (bcm43xx_phy_read(dev, 0x041A)
787 & 0xFF80) | 0x000F);
788 bcm43xx_phy_write(dev, 0x041A,
789 (bcm43xx_phy_read(dev, 0x041A)
790 & 0xC07F) | 0x2B80);
791 bcm43xx_phy_write(dev, 0x048C,
792 (bcm43xx_phy_read(dev, 0x048C)
793 & 0xF0FF) | 0x0300);
794
795 bcm43xx_radio_write16(dev, 0x007A,
796 bcm43xx_radio_read16(dev, 0x007A)
797 | 0x0008);
798
799 bcm43xx_phy_write(dev, 0x04A0,
800 (bcm43xx_phy_read(dev, 0x04A0)
801 & 0xFFF0) | 0x0008);
802 bcm43xx_phy_write(dev, 0x04A1,
803 (bcm43xx_phy_read(dev, 0x04A1)
804 & 0xF0FF) | 0x0600);
805 bcm43xx_phy_write(dev, 0x04A2,
806 (bcm43xx_phy_read(dev, 0x04A2)
807 & 0xF0FF) | 0x0700);
808 bcm43xx_phy_write(dev, 0x04A0,
809 (bcm43xx_phy_read(dev, 0x04A0)
810 & 0xF0FF) | 0x0100);
811
812 if (phy->rev == 1) {
813 bcm43xx_phy_write(dev, 0x04A2,
814 (bcm43xx_phy_read(dev, 0x04A2)
815 & 0xFFF0) | 0x0007);
816 }
817
818 bcm43xx_phy_write(dev, 0x0488,
819 (bcm43xx_phy_read(dev, 0x0488)
820 & 0xFF00) | 0x001C);
821 bcm43xx_phy_write(dev, 0x0488,
822 (bcm43xx_phy_read(dev, 0x0488)
823 & 0xC0FF) | 0x0200);
824 bcm43xx_phy_write(dev, 0x0496,
825 (bcm43xx_phy_read(dev, 0x0496)
826 & 0xFF00) | 0x001C);
827 bcm43xx_phy_write(dev, 0x0489,
828 (bcm43xx_phy_read(dev, 0x0489)
829 & 0xFF00) | 0x0020);
830 bcm43xx_phy_write(dev, 0x0489,
831 (bcm43xx_phy_read(dev, 0x0489)
832 & 0xC0FF) | 0x0200);
833 bcm43xx_phy_write(dev, 0x0482,
834 (bcm43xx_phy_read(dev, 0x0482)
835 & 0xFF00) | 0x002E);
836 bcm43xx_phy_write(dev, 0x0496,
837 (bcm43xx_phy_read(dev, 0x0496)
838 & 0x00FF) | 0x1A00);
839 bcm43xx_phy_write(dev, 0x0481,
840 (bcm43xx_phy_read(dev, 0x0481)
841 & 0xFF00) | 0x0028);
842 bcm43xx_phy_write(dev, 0x0481,
843 (bcm43xx_phy_read(dev, 0x0481)
844 & 0x00FF) | 0x2C00);
845
846 if (phy->rev == 1) {
847 bcm43xx_phy_write(dev, 0x0430, 0x092B);
848 bcm43xx_phy_write(dev, 0x041B,
849 (bcm43xx_phy_read(dev, 0x041B)
850 & 0xFFE1) | 0x0002);
851 } else {
852 bcm43xx_phy_write(dev, 0x041B,
853 bcm43xx_phy_read(dev, 0x041B)
854 & 0xFFE1);
855 bcm43xx_phy_write(dev, 0x041F, 0x287A);
856 bcm43xx_phy_write(dev, 0x0420,
857 (bcm43xx_phy_read(dev, 0x0420)
858 & 0xFFF0) | 0x0004);
859 }
860
861 if (phy->rev >= 6) {
862 bcm43xx_phy_write(dev, 0x0422, 0x287A);
863 bcm43xx_phy_write(dev, 0x0420,
864 (bcm43xx_phy_read(dev, 0x0420)
865 & 0x0FFF) | 0x3000);
866 }
867
868 bcm43xx_phy_write(dev, 0x04A8,
869 (bcm43xx_phy_read(dev, 0x04A8)
870 & 0x8080) | 0x7874);
871 bcm43xx_phy_write(dev, 0x048E, 0x1C00);
872
873 offset = 0x0800;
874 if (phy->rev == 1) {
875 offset = 0x5400;
876 bcm43xx_phy_write(dev, 0x04AB,
877 (bcm43xx_phy_read(dev, 0x04AB)
878 & 0xF0FF) | 0x0600);
879 bcm43xx_phy_write(dev, 0x048B, 0x005E);
880 bcm43xx_phy_write(dev, 0x048C,
881 (bcm43xx_phy_read(dev, 0x048C)
882 & 0xFF00) | 0x001E);
883 bcm43xx_phy_write(dev, 0x048D, 0x0002);
884 }
885 bcm43xx_ofdmtab_write16(dev, offset, 0, 0x00);
886 bcm43xx_ofdmtab_write16(dev, offset, 1, 0x07);
887 bcm43xx_ofdmtab_write16(dev, offset, 2, 0x10);
888 bcm43xx_ofdmtab_write16(dev, offset, 3, 0x1C);
889
890 if (phy->rev >= 6) {
891 bcm43xx_phy_write(dev, 0x0426,
892 bcm43xx_phy_read(dev, 0x0426)
893 & 0xFFFC);
894 bcm43xx_phy_write(dev, 0x0426,
895 bcm43xx_phy_read(dev, 0x0426)
896 & 0xEFFF);
897 }
898 }
899
900 static void bcm43xx_phy_setupg(struct bcm43xx_wldev *dev)
901 {
902 struct ssb_bus *bus = dev->dev->bus;
903 struct bcm43xx_phy *phy = &dev->phy;
904 u16 i;
905
906 assert(phy->type == BCM43xx_PHYTYPE_G);
907 if (phy->rev == 1) {
908 bcm43xx_phy_write(dev, 0x0406, 0x4F19);
909 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
910 (bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & 0xFC3F) | 0x0340);
911 bcm43xx_phy_write(dev, 0x042C, 0x005A);
912 bcm43xx_phy_write(dev, 0x0427, 0x001A);
913
914 for (i = 0; i < BCM43xx_TAB_FINEFREQG_SIZE; i++)
915 bcm43xx_ofdmtab_write16(dev, 0x5800, i, bcm43xx_tab_finefreqg[i]);
916 for (i = 0; i < BCM43xx_TAB_NOISEG1_SIZE; i++)
917 bcm43xx_ofdmtab_write16(dev, 0x1800, i, bcm43xx_tab_noiseg1[i]);
918 for (i = 0; i < BCM43xx_TAB_ROTOR_SIZE; i++)
919 bcm43xx_ofdmtab_write16(dev, 0x2000, i, bcm43xx_tab_rotor[i]);
920 } else {
921 /* nrssi values are signed 6-bit values. Not sure why we write 0x7654 here... */
922 bcm43xx_nrssi_hw_write(dev, 0xBA98, (s16)0x7654);
923
924 if (phy->rev == 2) {
925 bcm43xx_phy_write(dev, 0x04C0, 0x1861);
926 bcm43xx_phy_write(dev, 0x04C1, 0x0271);
927 } else if (phy->rev > 2) {
928 bcm43xx_phy_write(dev, 0x04C0, 0x0098);
929 bcm43xx_phy_write(dev, 0x04C1, 0x0070);
930 bcm43xx_phy_write(dev, 0x04C9, 0x0080);
931 }
932 bcm43xx_phy_write(dev, 0x042B, bcm43xx_phy_read(dev, 0x042B) | 0x800);
933
934 for (i = 0; i < 64; i++)
935 bcm43xx_ofdmtab_write16(dev, 0x4000, i, i);
936 for (i = 0; i < BCM43xx_TAB_NOISEG2_SIZE; i++)
937 bcm43xx_ofdmtab_write16(dev, 0x1800, i, bcm43xx_tab_noiseg2[i]);
938 }
939
940 if (phy->rev <= 2)
941 for (i = 0; i < BCM43xx_TAB_NOISESCALEG_SIZE; i++)
942 bcm43xx_ofdmtab_write16(dev, 0x1400, i, bcm43xx_tab_noisescaleg1[i]);
943 else if ((phy->rev >= 7) && (bcm43xx_phy_read(dev, 0x0449) & 0x0200))
944 for (i = 0; i < BCM43xx_TAB_NOISESCALEG_SIZE; i++)
945 bcm43xx_ofdmtab_write16(dev, 0x1400, i, bcm43xx_tab_noisescaleg3[i]);
946 else
947 for (i = 0; i < BCM43xx_TAB_NOISESCALEG_SIZE; i++)
948 bcm43xx_ofdmtab_write16(dev, 0x1400, i, bcm43xx_tab_noisescaleg2[i]);
949
950 if (phy->rev == 2)
951 for (i = 0; i < BCM43xx_TAB_SIGMASQR_SIZE; i++)
952 bcm43xx_ofdmtab_write16(dev, 0x5000, i, bcm43xx_tab_sigmasqr1[i]);
953 else if ((phy->rev > 2) && (phy->rev <= 8))
954 for (i = 0; i < BCM43xx_TAB_SIGMASQR_SIZE; i++)
955 bcm43xx_ofdmtab_write16(dev, 0x5000, i, bcm43xx_tab_sigmasqr2[i]);
956
957 if (phy->rev == 1) {
958 for (i = 0; i < BCM43xx_TAB_RETARD_SIZE; i++)
959 bcm43xx_ofdmtab_write32(dev, 0x2400, i, bcm43xx_tab_retard[i]);
960 for (i = 4; i < 20; i++)
961 bcm43xx_ofdmtab_write16(dev, 0x5400, i, 0x0020);
962 bcm43xx_phy_agcsetup(dev);
963
964 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
965 (bus->boardinfo.type == SSB_BOARD_BU4306) &&
966 (bus->boardinfo.rev == 0x17))
967 return;
968
969 bcm43xx_ofdmtab_write16(dev, 0x5001, 0, 0x0002);
970 bcm43xx_ofdmtab_write16(dev, 0x5002, 0, 0x0001);
971 } else {
972 for (i = 0; i < 0x20; i++)
973 bcm43xx_ofdmtab_write16(dev, 0x1000, i, 0x0820);
974 bcm43xx_phy_agcsetup(dev);
975 bcm43xx_phy_read(dev, 0x0400); /* dummy read */
976 bcm43xx_phy_write(dev, 0x0403, 0x1000);
977 bcm43xx_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
978 bcm43xx_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
979
980 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
981 (bus->boardinfo.type == SSB_BOARD_BU4306) &&
982 (bus->boardinfo.rev == 0x17))
983 return;
984
985 bcm43xx_ofdmtab_write16(dev, 0x0401, 0, 0x0002);
986 bcm43xx_ofdmtab_write16(dev, 0x0402, 0, 0x0001);
987 }
988 }
989
990 /* Initialize the noisescaletable for APHY */
991 static void bcm43xx_phy_init_noisescaletbl(struct bcm43xx_wldev *dev)
992 {
993 struct bcm43xx_phy *phy = &dev->phy;
994 int i;
995
996 for (i = 0; i < 12; i++) {
997 if (phy->rev == 2)
998 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x6767);
999 else
1000 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x2323);
1001 }
1002 if (phy->rev == 2)
1003 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x6700);
1004 else
1005 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x2300);
1006 for (i = 0; i < 11; i++) {
1007 if (phy->rev == 2)
1008 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x6767);
1009 else
1010 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x2323);
1011 }
1012 if (phy->rev == 2)
1013 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x0067);
1014 else
1015 bcm43xx_ofdmtab_write16(dev, 0x1400, i, 0x0023);
1016 }
1017
1018 static void bcm43xx_phy_setupa(struct bcm43xx_wldev *dev)
1019 {
1020 struct bcm43xx_phy *phy = &dev->phy;
1021 u16 i;
1022
1023 assert(phy->type == BCM43xx_PHYTYPE_A);
1024 switch (phy->rev) {
1025 case 2:
1026 bcm43xx_phy_write(dev, 0x008E, 0x3800);
1027 bcm43xx_phy_write(dev, 0x0035, 0x03FF);
1028 bcm43xx_phy_write(dev, 0x0036, 0x0400);
1029
1030 bcm43xx_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1031
1032 bcm43xx_phy_write(dev, 0x001C, 0x0FF9);
1033 bcm43xx_phy_write(dev, 0x0020, bcm43xx_phy_read(dev, 0x0020) & 0xFF0F);
1034 bcm43xx_ofdmtab_write16(dev, 0x3C0C, 0, 0x07BF);
1035 bcm43xx_radio_write16(dev, 0x0002, 0x07BF);
1036
1037 bcm43xx_phy_write(dev, 0x0024, 0x4680);
1038 bcm43xx_phy_write(dev, 0x0020, 0x0003);
1039 bcm43xx_phy_write(dev, 0x001D, 0x0F40);
1040 bcm43xx_phy_write(dev, 0x001F, 0x1C00);
1041
1042 bcm43xx_phy_write(dev, 0x002A,
1043 (bcm43xx_phy_read(dev, 0x002A)
1044 & 0x00FF) | 0x0400);
1045 bcm43xx_phy_write(dev, 0x002B,
1046 bcm43xx_phy_read(dev, 0x002B)
1047 & 0xFBFF);
1048 bcm43xx_phy_write(dev, 0x008E, 0x58C1);
1049
1050 bcm43xx_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1051 bcm43xx_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1052 bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1053 bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1054 bcm43xx_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1055
1056 bcm43xx_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1057 bcm43xx_ofdmtab_write16(dev, 0x0000, 1, 0x0013);
1058 bcm43xx_ofdmtab_write16(dev, 0x0000, 2, 0x0013);
1059 bcm43xx_ofdmtab_write16(dev, 0x0000, 3, 0x0013);
1060 bcm43xx_ofdmtab_write16(dev, 0x0000, 4, 0x0015);
1061 bcm43xx_ofdmtab_write16(dev, 0x0000, 5, 0x0015);
1062 bcm43xx_ofdmtab_write16(dev, 0x0000, 6, 0x0019);
1063
1064 bcm43xx_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1065 bcm43xx_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1066 bcm43xx_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1067
1068 for (i = 0; i < 16; i++)
1069 bcm43xx_ofdmtab_write16(dev, 0x4000, i, (0x8 + i) & 0x000F);
1070
1071 bcm43xx_ofdmtab_write16(dev, 0x3003, 0, 0x1044);
1072 bcm43xx_ofdmtab_write16(dev, 0x3004, 0, 0x7201);
1073 bcm43xx_ofdmtab_write16(dev, 0x3006, 0, 0x0040);
1074 bcm43xx_ofdmtab_write16(dev, 0x3001, 0, (bcm43xx_ofdmtab_read16(dev, 0x3001, 0) & 0x0010) | 0x0008);
1075
1076 for (i = 0; i < BCM43xx_TAB_FINEFREQA_SIZE; i++)
1077 bcm43xx_ofdmtab_write16(dev, 0x5800, i, bcm43xx_tab_finefreqa[i]);
1078 for (i = 0; i < BCM43xx_TAB_NOISEA2_SIZE; i++)
1079 bcm43xx_ofdmtab_write16(dev, 0x1800, i, bcm43xx_tab_noisea2[i]);
1080 for (i = 0; i < BCM43xx_TAB_ROTOR_SIZE; i++)
1081 bcm43xx_ofdmtab_write32(dev, 0x2000, i, bcm43xx_tab_rotor[i]);
1082 bcm43xx_phy_init_noisescaletbl(dev);
1083 for (i = 0; i < BCM43xx_TAB_RETARD_SIZE; i++)
1084 bcm43xx_ofdmtab_write32(dev, 0x2400, i, bcm43xx_tab_retard[i]);
1085 break;
1086 case 3:
1087 for (i = 0; i < 64; i++)
1088 bcm43xx_ofdmtab_write16(dev, 0x4000, i, i);
1089
1090 bcm43xx_ofdmtab_write16(dev, 0x3807, 0, 0x0051);
1091
1092 bcm43xx_phy_write(dev, 0x001C, 0x0FF9);
1093 bcm43xx_phy_write(dev, 0x0020,
1094 bcm43xx_phy_read(dev, 0x0020) & 0xFF0F);
1095 bcm43xx_radio_write16(dev, 0x0002, 0x07BF);
1096
1097 bcm43xx_phy_write(dev, 0x0024, 0x4680);
1098 bcm43xx_phy_write(dev, 0x0020, 0x0003);
1099 bcm43xx_phy_write(dev, 0x001D, 0x0F40);
1100 bcm43xx_phy_write(dev, 0x001F, 0x1C00);
1101 bcm43xx_phy_write(dev, 0x002A,
1102 (bcm43xx_phy_read(dev, 0x002A)
1103 & 0x00FF) | 0x0400);
1104
1105 bcm43xx_ofdmtab_write16(dev, 0x3000, 1,
1106 (bcm43xx_ofdmtab_read16(dev, 0x3000, 1)
1107 & 0x0010) | 0x0008);
1108 for (i = 0; i < BCM43xx_TAB_NOISEA3_SIZE; i++) {
1109 bcm43xx_ofdmtab_write16(dev, 0x1800, i,
1110 bcm43xx_tab_noisea3[i]);
1111 }
1112 bcm43xx_phy_init_noisescaletbl(dev);
1113 for (i = 0; i < BCM43xx_TAB_SIGMASQR_SIZE; i++) {
1114 bcm43xx_ofdmtab_write16(dev, 0x5000, i,
1115 bcm43xx_tab_sigmasqr1[i]);
1116 }
1117
1118 bcm43xx_phy_write(dev, 0x0003, 0x1808);
1119
1120 bcm43xx_ofdmtab_write16(dev, 0x0803, 0, 0x000F);
1121 bcm43xx_ofdmtab_write16(dev, 0x0804, 0, 0x001F);
1122 bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x002A);
1123 bcm43xx_ofdmtab_write16(dev, 0x0805, 0, 0x0030);
1124 bcm43xx_ofdmtab_write16(dev, 0x0807, 0, 0x003A);
1125
1126 bcm43xx_ofdmtab_write16(dev, 0x0000, 0, 0x0013);
1127 bcm43xx_ofdmtab_write16(dev, 0x0001, 0, 0x0013);
1128 bcm43xx_ofdmtab_write16(dev, 0x0002, 0, 0x0013);
1129 bcm43xx_ofdmtab_write16(dev, 0x0003, 0, 0x0013);
1130 bcm43xx_ofdmtab_write16(dev, 0x0004, 0, 0x0015);
1131 bcm43xx_ofdmtab_write16(dev, 0x0005, 0, 0x0015);
1132 bcm43xx_ofdmtab_write16(dev, 0x0006, 0, 0x0019);
1133
1134 bcm43xx_ofdmtab_write16(dev, 0x0404, 0, 0x0003);
1135 bcm43xx_ofdmtab_write16(dev, 0x0405, 0, 0x0003);
1136 bcm43xx_ofdmtab_write16(dev, 0x0406, 0, 0x0007);
1137
1138 bcm43xx_ofdmtab_write16(dev, 0x3C02, 0, 0x000F);
1139 bcm43xx_ofdmtab_write16(dev, 0x3C03, 0, 0x0014);
1140 break;
1141 default:
1142 assert(0);
1143 }
1144 }
1145
1146 /* Initialize APHY. This is also called for the GPHY in some cases. */
1147 static void bcm43xx_phy_inita(struct bcm43xx_wldev *dev)
1148 {
1149 struct ssb_bus *bus = dev->dev->bus;
1150 struct bcm43xx_phy *phy = &dev->phy;
1151 u16 tval;
1152
1153 might_sleep();
1154
1155 if (phy->type == BCM43xx_PHYTYPE_A) {
1156 bcm43xx_phy_setupa(dev);
1157 } else {
1158 bcm43xx_phy_setupg(dev);
1159 if (phy->gmode &&
1160 (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL))
1161 bcm43xx_phy_write(dev, 0x046E, 0x03CF);
1162 return;
1163 }
1164
1165 bcm43xx_phy_write(dev, BCM43xx_PHY_A_CRS,
1166 (bcm43xx_phy_read(dev, BCM43xx_PHY_A_CRS) & 0xF83C) | 0x0340);
1167 bcm43xx_phy_write(dev, 0x0034, 0x0001);
1168
1169 TODO();//TODO: RSSI AGC
1170 bcm43xx_phy_write(dev, BCM43xx_PHY_A_CRS,
1171 bcm43xx_phy_read(dev, BCM43xx_PHY_A_CRS) | (1 << 14));
1172 bcm43xx_radio_init2060(dev);
1173
1174 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1175 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
1176 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
1177 if (phy->lofcal == 0xFFFF) {
1178 TODO();//TODO: LOF Cal
1179 bcm43xx_radio_set_tx_iq(dev);
1180 } else
1181 bcm43xx_radio_write16(dev, 0x001E, phy->lofcal);
1182 }
1183
1184 bcm43xx_phy_write(dev, 0x007A, 0xF111);
1185
1186 if (phy->cur_idle_tssi == 0) {
1187 bcm43xx_radio_write16(dev, 0x0019, 0x0000);
1188 bcm43xx_radio_write16(dev, 0x0017, 0x0020);
1189
1190 tval = bcm43xx_ofdmtab_read16(dev, 0x3001, 0);
1191 if (phy->rev == 1) {
1192 bcm43xx_ofdmtab_write16(dev, 0x3001, 0,
1193 (bcm43xx_ofdmtab_read16(dev, 0x3001, 0) & 0xFF87)
1194 | 0x0058);
1195 } else {
1196 bcm43xx_ofdmtab_write16(dev, 0x3001, 0,
1197 (bcm43xx_ofdmtab_read16(dev, 0x3001, 0) & 0xFFC3)
1198 | 0x002C);
1199 }
1200 bcm43xx_dummy_transmission(dev);
1201 phy->cur_idle_tssi = bcm43xx_phy_read(dev, BCM43xx_PHY_A_PCTL);
1202 bcm43xx_ofdmtab_write16(dev, 0x3001, 0, tval);
1203
1204 bcm43xx_radio_set_txpower_a(dev, 0x0018);
1205 }
1206 bcm43xx_shm_clear_tssi(dev);
1207 }
1208
1209 static void bcm43xx_phy_initb2(struct bcm43xx_wldev *dev)
1210 {
1211 struct bcm43xx_phy *phy = &dev->phy;
1212 u16 offset, val;
1213
1214 bcm43xx_write16(dev, 0x03EC, 0x3F22);
1215 bcm43xx_phy_write(dev, 0x0020, 0x301C);
1216 bcm43xx_phy_write(dev, 0x0026, 0x0000);
1217 bcm43xx_phy_write(dev, 0x0030, 0x00C6);
1218 bcm43xx_phy_write(dev, 0x0088, 0x3E00);
1219 val = 0x3C3D;
1220 for (offset = 0x0089; offset < 0x00A7; offset++) {
1221 bcm43xx_phy_write(dev, offset, val);
1222 val -= 0x0202;
1223 }
1224 bcm43xx_phy_write(dev, 0x03E4, 0x3000);
1225 if (phy->channel == 0xFF)
1226 bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_BG, 0);
1227 else
1228 bcm43xx_radio_selectchannel(dev, phy->channel, 0);
1229 if (phy->radio_ver != 0x2050) {
1230 bcm43xx_radio_write16(dev, 0x0075, 0x0080);
1231 bcm43xx_radio_write16(dev, 0x0079, 0x0081);
1232 }
1233 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1234 bcm43xx_radio_write16(dev, 0x0050, 0x0023);
1235 if (phy->radio_ver == 0x2050) {
1236 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1237 bcm43xx_radio_write16(dev, 0x005A, 0x0070);
1238 bcm43xx_radio_write16(dev, 0x005B, 0x007B);
1239 bcm43xx_radio_write16(dev, 0x005C, 0x00B0);
1240 bcm43xx_radio_write16(dev, 0x007A, 0x000F);
1241 bcm43xx_phy_write(dev, 0x0038, 0x0677);
1242 bcm43xx_radio_init2050(dev);
1243 }
1244 bcm43xx_phy_write(dev, 0x0014, 0x0080);
1245 bcm43xx_phy_write(dev, 0x0032, 0x00CA);
1246 bcm43xx_phy_write(dev, 0x0032, 0x00CC);
1247 bcm43xx_phy_write(dev, 0x0035, 0x07C2);
1248 bcm43xx_lo_b_measure(dev);
1249 bcm43xx_phy_write(dev, 0x0026, 0xCC00);
1250 if (phy->radio_ver != 0x2050)
1251 bcm43xx_phy_write(dev, 0x0026, 0xCE00);
1252 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT, 0x1000);
1253 bcm43xx_phy_write(dev, 0x002A, 0x88A3);
1254 if (phy->radio_ver != 0x2050)
1255 bcm43xx_phy_write(dev, 0x002A, 0x88C2);
1256 bcm43xx_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1257 bcm43xx_phy_init_pctl(dev);
1258 }
1259
1260 static void bcm43xx_phy_initb4(struct bcm43xx_wldev *dev)
1261 {
1262 struct bcm43xx_phy *phy = &dev->phy;
1263 u16 offset, val;
1264
1265 bcm43xx_write16(dev, 0x03EC, 0x3F22);
1266 bcm43xx_phy_write(dev, 0x0020, 0x301C);
1267 bcm43xx_phy_write(dev, 0x0026, 0x0000);
1268 bcm43xx_phy_write(dev, 0x0030, 0x00C6);
1269 bcm43xx_phy_write(dev, 0x0088, 0x3E00);
1270 val = 0x3C3D;
1271 for (offset = 0x0089; offset < 0x00A7; offset++) {
1272 bcm43xx_phy_write(dev, offset, val);
1273 val -= 0x0202;
1274 }
1275 bcm43xx_phy_write(dev, 0x03E4, 0x3000);
1276 if (phy->channel == 0xFF)
1277 bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_BG, 0);
1278 else
1279 bcm43xx_radio_selectchannel(dev, phy->channel, 0);
1280 if (phy->radio_ver != 0x2050) {
1281 bcm43xx_radio_write16(dev, 0x0075, 0x0080);
1282 bcm43xx_radio_write16(dev, 0x0079, 0x0081);
1283 }
1284 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1285 bcm43xx_radio_write16(dev, 0x0050, 0x0023);
1286 if (phy->radio_ver == 0x2050) {
1287 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1288 bcm43xx_radio_write16(dev, 0x005A, 0x0070);
1289 bcm43xx_radio_write16(dev, 0x005B, 0x007B);
1290 bcm43xx_radio_write16(dev, 0x005C, 0x00B0);
1291 bcm43xx_radio_write16(dev, 0x007A, 0x000F);
1292 bcm43xx_phy_write(dev, 0x0038, 0x0677);
1293 bcm43xx_radio_init2050(dev);
1294 }
1295 bcm43xx_phy_write(dev, 0x0014, 0x0080);
1296 bcm43xx_phy_write(dev, 0x0032, 0x00CA);
1297 if (phy->radio_ver == 0x2050)
1298 bcm43xx_phy_write(dev, 0x0032, 0x00E0);
1299 bcm43xx_phy_write(dev, 0x0035, 0x07C2);
1300
1301 bcm43xx_lo_b_measure(dev);
1302
1303 bcm43xx_phy_write(dev, 0x0026, 0xCC00);
1304 if (phy->radio_ver == 0x2050)
1305 bcm43xx_phy_write(dev, 0x0026, 0xCE00);
1306 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT, 0x1100);
1307 bcm43xx_phy_write(dev, 0x002A, 0x88A3);
1308 if (phy->radio_ver == 0x2050)
1309 bcm43xx_phy_write(dev, 0x002A, 0x88C2);
1310 bcm43xx_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1311 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
1312 bcm43xx_calc_nrssi_slope(dev);
1313 bcm43xx_calc_nrssi_threshold(dev);
1314 }
1315 bcm43xx_phy_init_pctl(dev);
1316 }
1317
1318 static void bcm43xx_phy_initb5(struct bcm43xx_wldev *dev)
1319 {
1320 struct ssb_bus *bus = dev->dev->bus;
1321 struct bcm43xx_phy *phy = &dev->phy;
1322 u16 offset, value;
1323 u8 old_channel;
1324
1325 if (phy->analog == 1) {
1326 bcm43xx_radio_write16(dev, 0x007A,
1327 bcm43xx_radio_read16(dev, 0x007A)
1328 | 0x0050);
1329 }
1330 if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1331 (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1332 value = 0x2120;
1333 for (offset = 0x00A8 ; offset < 0x00C7; offset++) {
1334 bcm43xx_phy_write(dev, offset, value);
1335 value += 0x202;
1336 }
1337 }
1338 bcm43xx_phy_write(dev, 0x0035,
1339 (bcm43xx_phy_read(dev, 0x0035) & 0xF0FF)
1340 | 0x0700);
1341 if (phy->radio_ver == 0x2050)
1342 bcm43xx_phy_write(dev, 0x0038, 0x0667);
1343
1344 if (phy->gmode || phy->rev >= 2) {
1345 if (phy->radio_ver == 0x2050) {
1346 bcm43xx_radio_write16(dev, 0x007A,
1347 bcm43xx_radio_read16(dev, 0x007A)
1348 | 0x0020);
1349 bcm43xx_radio_write16(dev, 0x0051,
1350 bcm43xx_radio_read16(dev, 0x0051)
1351 | 0x0004);
1352 }
1353 bcm43xx_write16(dev, BCM43xx_MMIO_PHY_RADIO, 0x0000);
1354
1355 bcm43xx_phy_write(dev, 0x0802, bcm43xx_phy_read(dev, 0x0802) | 0x0100);
1356 bcm43xx_phy_write(dev, 0x042B, bcm43xx_phy_read(dev, 0x042B) | 0x2000);
1357
1358 bcm43xx_phy_write(dev, 0x001C, 0x186A);
1359
1360 bcm43xx_phy_write(dev, 0x0013, (bcm43xx_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1361 bcm43xx_phy_write(dev, 0x0035, (bcm43xx_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1362 bcm43xx_phy_write(dev, 0x005D, (bcm43xx_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1363 }
1364
1365 if (dev->bad_frames_preempt) {
1366 bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
1367 bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD) | (1 << 11));
1368 }
1369
1370 if (phy->analog == 1) {
1371 bcm43xx_phy_write(dev, 0x0026, 0xCE00);
1372 bcm43xx_phy_write(dev, 0x0021, 0x3763);
1373 bcm43xx_phy_write(dev, 0x0022, 0x1BC3);
1374 bcm43xx_phy_write(dev, 0x0023, 0x06F9);
1375 bcm43xx_phy_write(dev, 0x0024, 0x037E);
1376 } else
1377 bcm43xx_phy_write(dev, 0x0026, 0xCC00);
1378 bcm43xx_phy_write(dev, 0x0030, 0x00C6);
1379 bcm43xx_write16(dev, 0x03EC, 0x3F22);
1380
1381 if (phy->analog == 1)
1382 bcm43xx_phy_write(dev, 0x0020, 0x3E1C);
1383 else
1384 bcm43xx_phy_write(dev, 0x0020, 0x301C);
1385
1386 if (phy->analog == 0)
1387 bcm43xx_write16(dev, 0x03E4, 0x3000);
1388
1389 old_channel = phy->channel;
1390 /* Force to channel 7, even if not supported. */
1391 bcm43xx_radio_selectchannel(dev, 7, 0);
1392
1393 if (phy->radio_ver != 0x2050) {
1394 bcm43xx_radio_write16(dev, 0x0075, 0x0080);
1395 bcm43xx_radio_write16(dev, 0x0079, 0x0081);
1396 }
1397
1398 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1399 bcm43xx_radio_write16(dev, 0x0050, 0x0023);
1400
1401 if (phy->radio_ver == 0x2050) {
1402 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1403 bcm43xx_radio_write16(dev, 0x005A, 0x0070);
1404 }
1405
1406 bcm43xx_radio_write16(dev, 0x005B, 0x007B);
1407 bcm43xx_radio_write16(dev, 0x005C, 0x00B0);
1408
1409 bcm43xx_radio_write16(dev, 0x007A, bcm43xx_radio_read16(dev, 0x007A) | 0x0007);
1410
1411 bcm43xx_radio_selectchannel(dev, old_channel, 0);
1412
1413 bcm43xx_phy_write(dev, 0x0014, 0x0080);
1414 bcm43xx_phy_write(dev, 0x0032, 0x00CA);
1415 bcm43xx_phy_write(dev, 0x002A, 0x88A3);
1416
1417 bcm43xx_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1418
1419 if (phy->radio_ver == 0x2050)
1420 bcm43xx_radio_write16(dev, 0x005D, 0x000D);
1421
1422 bcm43xx_write16(dev, 0x03E4, (bcm43xx_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1423 }
1424
1425 static void bcm43xx_phy_initb6(struct bcm43xx_wldev *dev)
1426 {
1427 struct bcm43xx_phy *phy = &dev->phy;
1428 u16 offset, val;
1429 u8 old_channel;
1430
1431 bcm43xx_phy_write(dev, 0x003E, 0x817A);
1432 bcm43xx_radio_write16(dev, 0x007A,
1433 (bcm43xx_radio_read16(dev, 0x007A) | 0x0058));
1434 if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1435 bcm43xx_radio_write16(dev, 0x51, 0x37);
1436 bcm43xx_radio_write16(dev, 0x52, 0x70);
1437 bcm43xx_radio_write16(dev, 0x53, 0xB3);
1438 bcm43xx_radio_write16(dev, 0x54, 0x9B);
1439 bcm43xx_radio_write16(dev, 0x5A, 0x88);
1440 bcm43xx_radio_write16(dev, 0x5B, 0x88);
1441 bcm43xx_radio_write16(dev, 0x5D, 0x88);
1442 bcm43xx_radio_write16(dev, 0x5E, 0x88);
1443 bcm43xx_radio_write16(dev, 0x7D, 0x88);
1444 bcm43xx_hf_write(dev, bcm43xx_hf_read(dev)
1445 | BCM43xx_HF_TSSIRPSMW);
1446 }
1447 assert(phy->radio_rev != 6 && phy->radio_rev != 7); /* We had code for these revs here...*/
1448 if (phy->radio_rev == 8) {
1449 bcm43xx_radio_write16(dev, 0x51, 0);
1450 bcm43xx_radio_write16(dev, 0x52, 0x40);
1451 bcm43xx_radio_write16(dev, 0x53, 0xB7);
1452 bcm43xx_radio_write16(dev, 0x54, 0x98);
1453 bcm43xx_radio_write16(dev, 0x5A, 0x88);
1454 bcm43xx_radio_write16(dev, 0x5B, 0x6B);
1455 bcm43xx_radio_write16(dev, 0x5C, 0x0F);
1456 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_ALTIQ) {
1457 bcm43xx_radio_write16(dev, 0x5D, 0xFA);
1458 bcm43xx_radio_write16(dev, 0x5E, 0xD8);
1459 } else {
1460 bcm43xx_radio_write16(dev, 0x5D, 0xF5);
1461 bcm43xx_radio_write16(dev, 0x5E, 0xB8);
1462 }
1463 bcm43xx_radio_write16(dev, 0x0073, 0x0003);
1464 bcm43xx_radio_write16(dev, 0x007D, 0x00A8);
1465 bcm43xx_radio_write16(dev, 0x007C, 0x0001);
1466 bcm43xx_radio_write16(dev, 0x007E, 0x0008);
1467 }
1468 val = 0x1E1F;
1469 for (offset = 0x0088; offset < 0x0098; offset++) {
1470 bcm43xx_phy_write(dev, offset, val);
1471 val -= 0x0202;
1472 }
1473 val = 0x3E3F;
1474 for (offset = 0x0098; offset < 0x00A8; offset++) {
1475 bcm43xx_phy_write(dev, offset, val);
1476 val -= 0x0202;
1477 }
1478 val = 0x2120;
1479 for (offset = 0x00A8; offset < 0x00C8; offset++) {
1480 bcm43xx_phy_write(dev, offset, (val & 0x3F3F));
1481 val += 0x0202;
1482 }
1483 if (phy->type == BCM43xx_PHYTYPE_G) {
1484 bcm43xx_radio_write16(dev, 0x007A,
1485 bcm43xx_radio_read16(dev, 0x007A) | 0x0020);
1486 bcm43xx_radio_write16(dev, 0x0051,
1487 bcm43xx_radio_read16(dev, 0x0051) | 0x0004);
1488 bcm43xx_phy_write(dev, 0x0802,
1489 bcm43xx_phy_read(dev, 0x0802) | 0x0100);
1490 bcm43xx_phy_write(dev, 0x042B,
1491 bcm43xx_phy_read(dev, 0x042B) | 0x2000);
1492 bcm43xx_phy_write(dev, 0x5B, 0);
1493 bcm43xx_phy_write(dev, 0x5C, 0);
1494 }
1495
1496 old_channel = phy->channel;
1497 if (old_channel >= 8)
1498 bcm43xx_radio_selectchannel(dev, 1, 0);
1499 else
1500 bcm43xx_radio_selectchannel(dev, 13, 0);
1501
1502 bcm43xx_radio_write16(dev, 0x0050, 0x0020);
1503 bcm43xx_radio_write16(dev, 0x0050, 0x0023);
1504 udelay(40);
1505 if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1506 bcm43xx_radio_write16(dev, 0x7C,
1507 (bcm43xx_radio_read16(dev, 0x7C)
1508 | 0x0002));
1509 bcm43xx_radio_write16(dev, 0x50, 0x20);
1510 }
1511 if (phy->radio_rev <= 2) {
1512 bcm43xx_radio_write16(dev, 0x7C, 0x20);
1513 bcm43xx_radio_write16(dev, 0x5A, 0x70);
1514 bcm43xx_radio_write16(dev, 0x5B, 0x7B);
1515 bcm43xx_radio_write16(dev, 0x5C, 0xB0);
1516 }
1517 bcm43xx_radio_write16(dev, 0x007A,
1518 (bcm43xx_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1519
1520 bcm43xx_radio_selectchannel(dev, old_channel, 0);
1521
1522 bcm43xx_phy_write(dev, 0x0014, 0x0200);
1523 if (phy->radio_rev >= 6)
1524 bcm43xx_phy_write(dev, 0x2A, 0x88C2);
1525 else
1526 bcm43xx_phy_write(dev, 0x2A, 0x8AC0);
1527 bcm43xx_phy_write(dev, 0x0038, 0x0668);
1528 bcm43xx_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
1529 if (phy->radio_rev <= 5) {
1530 bcm43xx_phy_write(dev, 0x5D,
1531 (bcm43xx_phy_read(dev, 0x5D)
1532 & 0xFF80) | 0x0003);
1533 }
1534 if (phy->radio_rev <= 2)
1535 bcm43xx_radio_write16(dev, 0x005D, 0x000D);
1536
1537 if (phy->analog == 4) {
1538 bcm43xx_write16(dev, 0x3E4, 9);
1539 bcm43xx_phy_write(dev, 0x61,
1540 bcm43xx_phy_read(dev, 0x61)
1541 & 0x0FFF);
1542 } else {
1543 bcm43xx_phy_write(dev, 0x0002,
1544 (bcm43xx_phy_read(dev, 0x0002) & 0xFFC0)
1545 | 0x0004);
1546 }
1547 if (phy->type == BCM43xx_PHYTYPE_B) {
1548 bcm43xx_write16(dev, 0x03E6, 0x8140);
1549 bcm43xx_phy_write(dev, 0x0016, 0x0410);
1550 bcm43xx_phy_write(dev, 0x0017, 0x0820);
1551 bcm43xx_phy_write(dev, 0x0062, 0x0007);
1552 bcm43xx_radio_init2050(dev);
1553 bcm43xx_lo_g_measure(dev);
1554 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI) {
1555 bcm43xx_calc_nrssi_slope(dev);
1556 bcm43xx_calc_nrssi_threshold(dev);
1557 }
1558 bcm43xx_phy_init_pctl(dev);
1559 } else if (phy->type == BCM43xx_PHYTYPE_G)
1560 bcm43xx_write16(dev, 0x03E6, 0x0);
1561 }
1562
1563 static void bcm43xx_calc_loopback_gain(struct bcm43xx_wldev *dev)
1564 {
1565 struct bcm43xx_phy *phy = &dev->phy;
1566 u16 backup_phy[16] = {0};
1567 u16 backup_radio[3];
1568 u16 backup_bband;
1569 u16 i, j, loop_i_max;
1570 u16 trsw_rx;
1571 u16 loop1_outer_done, loop1_inner_done;
1572
1573 backup_phy[0] = bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0);
1574 backup_phy[1] = bcm43xx_phy_read(dev, BCM43xx_PHY_CCKBBANDCFG);
1575 backup_phy[2] = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER);
1576 backup_phy[3] = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL);
1577 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1578 backup_phy[4] = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER);
1579 backup_phy[5] = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL);
1580 }
1581 backup_phy[6] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x5A));
1582 backup_phy[7] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x59));
1583 backup_phy[8] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x58));
1584 backup_phy[9] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x0A));
1585 backup_phy[10] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x03));
1586 backup_phy[11] = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_MASK);
1587 backup_phy[12] = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_CTL);
1588 backup_phy[13] = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2B));
1589 backup_phy[14] = bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL);
1590 backup_phy[15] = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
1591 backup_bband = phy->bbatt.att;
1592 backup_radio[0] = bcm43xx_radio_read16(dev, 0x52);
1593 backup_radio[1] = bcm43xx_radio_read16(dev, 0x43);
1594 backup_radio[2] = bcm43xx_radio_read16(dev, 0x7A);
1595
1596 bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
1597 bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0) & 0x3FFF);
1598 bcm43xx_phy_write(dev, BCM43xx_PHY_CCKBBANDCFG,
1599 bcm43xx_phy_read(dev, BCM43xx_PHY_CCKBBANDCFG) | 0x8000);
1600 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
1601 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0002);
1602 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1603 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) & 0xFFFD);
1604 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
1605 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0001);
1606 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1607 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) & 0xFFFE);
1608 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1609 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
1610 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER) | 0x0001);
1611 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
1612 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL) & 0xFFFE);
1613 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
1614 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER) | 0x0002);
1615 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
1616 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL) & 0xFFFD);
1617 }
1618 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
1619 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x000C);
1620 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1621 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) | 0x000C);
1622 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
1623 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0030);
1624 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1625 (bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
1626 & 0xFFCF) | 0x10);
1627
1628 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), 0x0780);
1629 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), 0xC810);
1630 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0x000D);
1631
1632 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x0A),
1633 bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x0A)) | 0x2000);
1634 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1635 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
1636 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER) | 0x0004);
1637 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
1638 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL) & 0xFFFB);
1639 }
1640 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x03),
1641 (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x03))
1642 & 0xFF9F) | 0x40);
1643
1644 if (phy->radio_rev == 8) {
1645 bcm43xx_radio_write16(dev, 0x43, 0x000F);
1646 } else {
1647 bcm43xx_radio_write16(dev, 0x52, 0);
1648 bcm43xx_radio_write16(dev, 0x43,
1649 (bcm43xx_radio_read16(dev, 0x43)
1650 & 0xFFF0) | 0x9);
1651 }
1652 bcm43xx_phy_set_baseband_attenuation(dev, 11);
1653
1654 if (phy->rev >= 3)
1655 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0xC020);
1656 else
1657 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8020);
1658 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, 0);
1659
1660 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B),
1661 (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2B))
1662 & 0xFFC0) | 0x01);
1663 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B),
1664 (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x2B))
1665 & 0xC0FF) | 0x800);
1666
1667 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
1668 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER) | 0x0100);
1669 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1670 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL) & 0xCFFF);
1671
1672 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_EXTLNA) {
1673 if (phy->rev >= 7) {
1674 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
1675 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER)
1676 | 0x0800);
1677 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1678 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
1679 | 0x8000);
1680 }
1681 }
1682 bcm43xx_radio_write16(dev, 0x7A,
1683 bcm43xx_radio_read16(dev, 0x7A)
1684 & 0x00F7);
1685
1686 j = 0;
1687 loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1688 for (i = 0; i < loop_i_max; i++) {
1689 for (j = 0; j < 16; j++) {
1690 bcm43xx_radio_write16(dev, 0x43, i);
1691 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1692 (bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
1693 & 0xF0FF) | (j << 8));
1694 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
1695 (bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
1696 & 0x0FFF) | 0xA000);
1697 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
1698 bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
1699 | 0xF000);
1700 udelay(20);
1701 if (bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE) >= 0xDFC)
1702 goto exit_loop1;
1703 }
1704 }
1705 exit_loop1:
1706 loop1_outer_done = i;
1707 loop1_inner_done = j;
1708 if (j >= 8) {
1709 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1710 bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
1711 | 0x30);
1712 trsw_rx = 0x1B;
1713 for (j = j - 8; j < 16; j++) {
1714 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
1715 (bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL)
1716 & 0xF0FF) | (j << 8));
1717 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
1718 (bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
1719 & 0x0FFF) | 0xA000);
1720 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL,
1721 bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL)
1722 | 0xF000);
1723 udelay(20);
1724 trsw_rx -= 3;
1725 if (bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE) >= 0xDFC)
1726 goto exit_loop2;
1727 }
1728 } else
1729 trsw_rx = 0x18;
1730 exit_loop2:
1731
1732 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
1733 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, backup_phy[4]);
1734 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, backup_phy[5]);
1735 }
1736 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), backup_phy[6]);
1737 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), backup_phy[7]);
1738 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), backup_phy[8]);
1739 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x0A), backup_phy[9]);
1740 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x03), backup_phy[10]);
1741 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, backup_phy[11]);
1742 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, backup_phy[12]);
1743 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), backup_phy[13]);
1744 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, backup_phy[14]);
1745
1746 bcm43xx_phy_set_baseband_attenuation(dev, backup_bband);
1747
1748 bcm43xx_radio_write16(dev, 0x52, backup_radio[0]);
1749 bcm43xx_radio_write16(dev, 0x43, backup_radio[1]);
1750 bcm43xx_radio_write16(dev, 0x7A, backup_radio[2]);
1751
1752 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, backup_phy[2] | 0x0003);
1753 udelay(10);
1754 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, backup_phy[2]);
1755 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, backup_phy[3]);
1756 bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0, backup_phy[0]);
1757 bcm43xx_phy_write(dev, BCM43xx_PHY_CCKBBANDCFG, backup_phy[1]);
1758
1759 phy->max_lb_gain = ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1760 phy->trsw_rx_gain = trsw_rx * 2;
1761 }
1762
1763 static void bcm43xx_phy_initg(struct bcm43xx_wldev *dev)
1764 {
1765 struct bcm43xx_phy *phy = &dev->phy;
1766 u16 tmp;
1767
1768 if (phy->rev == 1)
1769 bcm43xx_phy_initb5(dev);
1770 else
1771 bcm43xx_phy_initb6(dev);
1772
1773 if (phy->rev >= 2 || phy->gmode)
1774 bcm43xx_phy_inita(dev);
1775
1776 if (phy->rev >= 2) {
1777 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, 0);
1778 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, 0);
1779 }
1780 if (phy->rev == 2) {
1781 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0);
1782 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xC0);
1783 }
1784 if (phy->rev > 5) {
1785 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, 0x400);
1786 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xC0);
1787 }
1788 if (phy->gmode || phy->rev >= 2) {
1789 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_VERSION_OFDM);
1790 tmp &= BCM43xx_PHYVER_VERSION;
1791 if (tmp == 3 || tmp == 5) {
1792 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xC2), 0x1816);
1793 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xC3), 0x8006);
1794 }
1795 if (tmp == 5) {
1796 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xCC),
1797 (bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM(0xCC))
1798 & 0x00FF) | 0x1F00);
1799 }
1800 }
1801 if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
1802 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0x7E), 0x78);
1803 if (phy->radio_rev == 8) {
1804 bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x01),
1805 bcm43xx_phy_read(dev, BCM43xx_PHY_EXTG(0x01))
1806 | 0x80);
1807 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0x3E),
1808 bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM(0x3E))
1809 | 0x4);
1810 }
1811 if (has_loopback_gain(phy))
1812 bcm43xx_calc_loopback_gain(dev);
1813
1814 if (phy->radio_rev != 8) {
1815 if (phy->initval == 0xFFFF)
1816 phy->initval = bcm43xx_radio_init2050(dev);
1817 else
1818 bcm43xx_radio_write16(dev, 0x0078, phy->initval);
1819 }
1820 if (phy->lo_control->tx_bias == 0xFF) {
1821 bcm43xx_lo_g_measure(dev);
1822 } else {
1823 if (has_tx_magnification(phy)) {
1824 bcm43xx_radio_write16(dev, 0x52,
1825 (bcm43xx_radio_read16(dev, 0x52) & 0xFF00) |
1826 phy->lo_control->tx_bias |
1827 phy->lo_control->tx_magn);
1828 } else {
1829 bcm43xx_radio_write16(dev, 0x52,
1830 (bcm43xx_radio_read16(dev, 0x52) & 0xFFF0) |
1831 phy->lo_control->tx_bias);
1832 }
1833 if (phy->rev >= 6) {
1834 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x36),
1835 (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x36))
1836 & 0x0FFF) | (phy->lo_control->tx_bias << 12));
1837 }
1838 if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL)
1839 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x8075);
1840 else
1841 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2E), 0x807F);
1842 if (phy->rev < 2)
1843 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x101);
1844 else
1845 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2F), 0x202);
1846 }
1847 if (phy->gmode || phy->rev >= 2) {
1848 bcm43xx_lo_g_adjust(dev);
1849 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8078);
1850 }
1851
1852 if (!(dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI)) {
1853 /* The specs state to update the NRSSI LT with
1854 * the value 0x7FFFFFFF here. I think that is some weird
1855 * compiler optimization in the original driver.
1856 * Essentially, what we do here is resetting all NRSSI LT
1857 * entries to -32 (see the limit_value() in nrssi_hw_update())
1858 */
1859 bcm43xx_nrssi_hw_update(dev, 0xFFFF);//FIXME?
1860 bcm43xx_calc_nrssi_threshold(dev);
1861 } else if (phy->gmode || phy->rev >= 2) {
1862 if (phy->nrssi[0] == -1000) {
1863 assert(phy->nrssi[1] == -1000);
1864 bcm43xx_calc_nrssi_slope(dev);
1865 } else
1866 bcm43xx_calc_nrssi_threshold(dev);
1867 }
1868 if (phy->radio_rev == 8)
1869 bcm43xx_phy_write(dev, BCM43xx_PHY_EXTG(0x05), 0x3230);
1870 bcm43xx_phy_init_pctl(dev);
1871 /* FIXME: The spec says in the following if, the 0 should be replaced
1872 'if OFDM may not be used in the current locale'
1873 but OFDM is legal everywhere */
1874 if ((dev->dev->bus->chip_id == 0x4306 && dev->dev->bus->chip_package == 2) || 0) {
1875 bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
1876 bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0)
1877 & 0xBFFF);
1878 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM(0xC3),
1879 bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM(0xC3))
1880 & 0x7FFF);
1881 }
1882 }
1883
1884 /* Set the baseband attenuation value on chip. */
1885 void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_wldev *dev,
1886 u16 baseband_attenuation)
1887 {
1888 struct bcm43xx_phy *phy = &dev->phy;
1889
1890 if (phy->analog == 0) {
1891 bcm43xx_write16(dev, BCM43xx_MMIO_PHY0,
1892 (bcm43xx_read16(dev, BCM43xx_MMIO_PHY0)
1893 & 0xFFF0) | baseband_attenuation);
1894 } else if (phy->analog == 1) {
1895 bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL,
1896 (bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL)
1897 & 0xFFC3) | (baseband_attenuation << 2));
1898 } else {
1899 bcm43xx_phy_write(dev, BCM43xx_PHY_DACCTL,
1900 (bcm43xx_phy_read(dev, BCM43xx_PHY_DACCTL)
1901 & 0xFF87) | (baseband_attenuation << 3));
1902 }
1903 }
1904
1905 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
1906 * This function converts a TSSI value to dBm in Q5.2
1907 */
1908 static s8 bcm43xx_phy_estimate_power_out(struct bcm43xx_wldev *dev, s8 tssi)
1909 {
1910 struct bcm43xx_phy *phy = &dev->phy;
1911 s8 dbm = 0;
1912 s32 tmp;
1913
1914 tmp = (phy->tgt_idle_tssi - phy->cur_idle_tssi + tssi);
1915
1916 switch (phy->type) {
1917 case BCM43xx_PHYTYPE_A:
1918 tmp += 0x80;
1919 tmp = limit_value(tmp, 0x00, 0xFF);
1920 dbm = phy->tssi2dbm[tmp];
1921 TODO(); //TODO: There's a FIXME on the specs
1922 break;
1923 case BCM43xx_PHYTYPE_B:
1924 case BCM43xx_PHYTYPE_G:
1925 tmp = limit_value(tmp, 0x00, 0x3F);
1926 dbm = phy->tssi2dbm[tmp];
1927 break;
1928 default:
1929 assert(0);
1930 }
1931
1932 return dbm;
1933 }
1934
1935 void bcm43xx_put_attenuation_into_ranges(struct bcm43xx_wldev *dev,
1936 int *_bbatt, int *_rfatt)
1937 {
1938 int rfatt = *_rfatt;
1939 int bbatt = *_bbatt;
1940 struct bcm43xx_txpower_lo_control *lo = dev->phy.lo_control;
1941
1942 /* Get baseband and radio attenuation values into their permitted ranges.
1943 * Radio attenuation affects power level 4 times as much as baseband. */
1944
1945 /* Range constants */
1946 const int rf_min = lo->rfatt_list.min_val;
1947 const int rf_max = lo->rfatt_list.max_val;
1948 const int bb_min = lo->bbatt_list.min_val;
1949 const int bb_max = lo->bbatt_list.max_val;
1950
1951 while (1) {
1952 if (rfatt > rf_max &&
1953 bbatt > bb_max - 4)
1954 break; /* Can not get it into ranges */
1955 if (rfatt < rf_min &&
1956 bbatt < bb_min + 4)
1957 break; /* Can not get it into ranges */
1958 if (bbatt > bb_max &&
1959 rfatt > rf_max - 1)
1960 break; /* Can not get it into ranges */
1961 if (bbatt < bb_min &&
1962 rfatt < rf_min + 1)
1963 break; /* Can not get it into ranges */
1964
1965 if (bbatt > bb_max) {
1966 bbatt -= 4;
1967 rfatt += 1;
1968 continue;
1969 }
1970 if (bbatt < bb_min) {
1971 bbatt += 4;
1972 rfatt -= 1;
1973 continue;
1974 }
1975 if (rfatt > rf_max) {
1976 rfatt -= 1;
1977 bbatt += 4;
1978 continue;
1979 }
1980 if (rfatt < rf_min) {
1981 rfatt += 1;
1982 bbatt -= 4;
1983 continue;
1984 }
1985 break;
1986 }
1987
1988 *_rfatt = limit_value(rfatt, rf_min, rf_max);
1989 *_bbatt = limit_value(bbatt, bb_min, bb_max);
1990 }
1991
1992 /* http://bcm-specs.sipsolutions.net/RecalculateTransmissionPower */
1993 void bcm43xx_phy_xmitpower(struct bcm43xx_wldev *dev)
1994 {
1995 struct ssb_bus *bus = dev->dev->bus;
1996 struct bcm43xx_phy *phy = &dev->phy;
1997
1998 if (phy->cur_idle_tssi == 0)
1999 return;
2000 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
2001 (bus->boardinfo.type == SSB_BOARD_BU4306))
2002 return;
2003 #ifdef CONFIG_BCM43XX_MAC80211_DEBUG
2004 if (phy->manual_txpower_control)
2005 return;
2006 #endif
2007
2008 switch (phy->type) {
2009 case BCM43xx_PHYTYPE_A: {
2010
2011 TODO(); //TODO: Nothing for A PHYs yet :-/
2012
2013 break;
2014 }
2015 case BCM43xx_PHYTYPE_B:
2016 case BCM43xx_PHYTYPE_G: {
2017 u16 tmp;
2018 s8 v0, v1, v2, v3;
2019 s8 average;
2020 int max_pwr;
2021 int desired_pwr, estimated_pwr, pwr_adjust;
2022 int rfatt_delta, bbatt_delta;
2023 int rfatt, bbatt;
2024 u8 tx_control;
2025 unsigned long phylock_flags;
2026
2027 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x0058);
2028 v0 = (s8)(tmp & 0x00FF);
2029 v1 = (s8)((tmp & 0xFF00) >> 8);
2030 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x005A);
2031 v2 = (s8)(tmp & 0x00FF);
2032 v3 = (s8)((tmp & 0xFF00) >> 8);
2033 tmp = 0;
2034
2035 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F) {
2036 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x0070);
2037 v0 = (s8)(tmp & 0x00FF);
2038 v1 = (s8)((tmp & 0xFF00) >> 8);
2039 tmp = bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x0072);
2040 v2 = (s8)(tmp & 0x00FF);
2041 v3 = (s8)((tmp & 0xFF00) >> 8);
2042 if (v0 == 0x7F || v1 == 0x7F || v2 == 0x7F || v3 == 0x7F)
2043 return;
2044 v0 = (v0 + 0x20) & 0x3F;
2045 v1 = (v1 + 0x20) & 0x3F;
2046 v2 = (v2 + 0x20) & 0x3F;
2047 v3 = (v3 + 0x20) & 0x3F;
2048 tmp = 1;
2049 }
2050 bcm43xx_shm_clear_tssi(dev);
2051
2052 average = (v0 + v1 + v2 + v3 + 2) / 4;
2053
2054 if (tmp && (bcm43xx_shm_read16(dev, BCM43xx_SHM_SHARED, 0x005E) & 0x8))
2055 average -= 13;
2056
2057 estimated_pwr = bcm43xx_phy_estimate_power_out(dev, average);
2058
2059 max_pwr = dev->dev->bus->sprom.r1.maxpwr_bg;
2060 if ((dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) &&
2061 (phy->type == BCM43xx_PHYTYPE_G))
2062 max_pwr -= 0x3;
2063 if (unlikely(max_pwr <= 0)) {
2064 printk(KERN_ERR PFX "Invalid max-TX-power value in SPROM.\n");
2065 max_pwr = 60; /* fake it */
2066 dev->dev->bus->sprom.r1.maxpwr_bg = max_pwr;
2067 }
2068
2069 /*TODO:
2070 max_pwr = min(REG - dev->dev->bus->sprom.antennagain_bgphy - 0x6, max_pwr)
2071 where REG is the max power as per the regulatory domain
2072 */
2073
2074 desired_pwr = phy->power_level;
2075 /* Convert the desired_pwr to Q5.2 and limit it. */
2076 desired_pwr = limit_value((desired_pwr << 2), 0, max_pwr);
2077 if (bcm43xx_debug(dev, BCM43xx_DBG_XMITPOWER)) {
2078 dprintk(KERN_DEBUG PFX
2079 "Current TX power output: " Q52_FMT " dBm, "
2080 "Desired TX power output: " Q52_FMT " dBm\n",
2081 Q52_ARG(estimated_pwr), Q52_ARG(desired_pwr));
2082 }
2083
2084 pwr_adjust = desired_pwr - estimated_pwr;
2085 rfatt_delta = -((pwr_adjust + 7) >> 3);
2086 bbatt_delta = (-(pwr_adjust >> 1)) - (4 * rfatt_delta);
2087 if ((rfatt_delta == 0) && (bbatt_delta == 0)) {
2088 bcm43xx_lo_g_ctl_mark_cur_used(dev);
2089 return;
2090 }
2091
2092 /* Calculate the new attenuation values. */
2093 bbatt = phy->bbatt.att;
2094 bbatt += bbatt_delta;
2095 rfatt = phy->rfatt.att;
2096 rfatt += rfatt_delta;
2097
2098 bcm43xx_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2099 tx_control = phy->tx_control;
2100 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2101 if (rfatt <= 1) {
2102 if (tx_control == 0) {
2103 tx_control = BCM43xx_TXCTL_PA2DB | BCM43xx_TXCTL_TXMIX;
2104 rfatt += 2;
2105 bbatt += 2;
2106 } else if (dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_PACTRL) {
2107 bbatt += 4 * (rfatt - 2);
2108 rfatt = 2;
2109 }
2110 } else if (rfatt > 4 && tx_control) {
2111 tx_control = 0;
2112 if (bbatt < 3) {
2113 rfatt -= 3;
2114 bbatt += 2;
2115 } else {
2116 rfatt -= 2;
2117 bbatt -= 2;
2118 }
2119 }
2120 }
2121 phy->tx_control = tx_control;
2122 bcm43xx_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2123
2124 bcm43xx_phy_lock(dev, phylock_flags);
2125 bcm43xx_radio_lock(dev);
2126 bcm43xx_set_txpower_g(dev, &phy->bbatt, &phy->rfatt, phy->tx_control);
2127 bcm43xx_lo_g_ctl_mark_cur_used(dev);
2128 bcm43xx_radio_unlock(dev);
2129 bcm43xx_phy_unlock(dev, phylock_flags);
2130 break;
2131 }
2132 default:
2133 assert(0);
2134 }
2135 }
2136
2137 static inline
2138 s32 bcm43xx_tssi2dbm_ad(s32 num, s32 den)
2139 {
2140 if (num < 0)
2141 return num/den;
2142 else
2143 return (num+den/2)/den;
2144 }
2145
2146 static inline
2147 s8 bcm43xx_tssi2dbm_entry(s8 entry [], u8 index, s16 pab0, s16 pab1, s16 pab2)
2148 {
2149 s32 m1, m2, f = 256, q, delta;
2150 s8 i = 0;
2151
2152 m1 = bcm43xx_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2153 m2 = max(bcm43xx_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2154 do {
2155 if (i > 15)
2156 return -EINVAL;
2157 q = bcm43xx_tssi2dbm_ad(f * 4096 -
2158 bcm43xx_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2159 delta = abs(q - f);
2160 f = q;
2161 i++;
2162 } while (delta >= 2);
2163 entry[index] = limit_value(bcm43xx_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2164 return 0;
2165 }
2166
2167 /* http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table */
2168 int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_wldev *dev)
2169 {
2170 struct bcm43xx_phy *phy = &dev->phy;
2171 s16 pab0, pab1, pab2;
2172 u8 idx;
2173 s8 *dyn_tssi2dbm;
2174
2175 if (phy->type == BCM43xx_PHYTYPE_A) {
2176 pab0 = (s16)(dev->dev->bus->sprom.r1.pa1b0);
2177 pab1 = (s16)(dev->dev->bus->sprom.r1.pa1b1);
2178 pab2 = (s16)(dev->dev->bus->sprom.r1.pa1b2);
2179 } else {
2180 pab0 = (s16)(dev->dev->bus->sprom.r1.pa0b0);
2181 pab1 = (s16)(dev->dev->bus->sprom.r1.pa0b1);
2182 pab2 = (s16)(dev->dev->bus->sprom.r1.pa0b2);
2183 }
2184
2185 if ((dev->dev->bus->chip_id == 0x4301) && (phy->radio_ver != 0x2050)) {
2186 phy->tgt_idle_tssi = 0x34;
2187 phy->tssi2dbm = bcm43xx_tssi2dbm_b_table;
2188 return 0;
2189 }
2190
2191 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2192 pab0 != -1 && pab1 != -1 && pab2 != -1) {
2193 /* The pabX values are set in SPROM. Use them. */
2194 if (phy->type == BCM43xx_PHYTYPE_A) {
2195 if ((s8)dev->dev->bus->sprom.r1.itssi_a != 0 &&
2196 (s8)dev->dev->bus->sprom.r1.itssi_a != -1)
2197 phy->tgt_idle_tssi = (s8)(dev->dev->bus->sprom.r1.itssi_a);
2198 else
2199 phy->tgt_idle_tssi = 62;
2200 } else {
2201 if ((s8)dev->dev->bus->sprom.r1.itssi_bg != 0 &&
2202 (s8)dev->dev->bus->sprom.r1.itssi_bg != -1)
2203 phy->tgt_idle_tssi = (s8)(dev->dev->bus->sprom.r1.itssi_bg);
2204 else
2205 phy->tgt_idle_tssi = 62;
2206 }
2207 dyn_tssi2dbm = kmalloc(64, GFP_KERNEL);
2208 if (dyn_tssi2dbm == NULL) {
2209 printk(KERN_ERR PFX "Could not allocate memory"
2210 "for tssi2dbm table\n");
2211 return -ENOMEM;
2212 }
2213 for (idx = 0; idx < 64; idx++)
2214 if (bcm43xx_tssi2dbm_entry(dyn_tssi2dbm, idx, pab0, pab1, pab2)) {
2215 phy->tssi2dbm = NULL;
2216 printk(KERN_ERR PFX "Could not generate "
2217 "tssi2dBm table\n");
2218 kfree(dyn_tssi2dbm);
2219 return -ENODEV;
2220 }
2221 phy->tssi2dbm = dyn_tssi2dbm;
2222 phy->dyn_tssi_tbl = 1;
2223 } else {
2224 /* pabX values not set in SPROM. */
2225 switch (phy->type) {
2226 case BCM43xx_PHYTYPE_A:
2227 /* APHY needs a generated table. */
2228 phy->tssi2dbm = NULL;
2229 printk(KERN_ERR PFX "Could not generate tssi2dBm "
2230 "table (wrong SPROM info)!\n");
2231 return -ENODEV;
2232 case BCM43xx_PHYTYPE_B:
2233 phy->tgt_idle_tssi = 0x34;
2234 phy->tssi2dbm = bcm43xx_tssi2dbm_b_table;
2235 break;
2236 case BCM43xx_PHYTYPE_G:
2237 phy->tgt_idle_tssi = 0x34;
2238 phy->tssi2dbm = bcm43xx_tssi2dbm_g_table;
2239 break;
2240 }
2241 }
2242
2243 return 0;
2244 }
2245
2246 int bcm43xx_phy_init(struct bcm43xx_wldev *dev)
2247 {
2248 struct bcm43xx_phy *phy = &dev->phy;
2249 int err = -ENODEV;
2250
2251 switch (phy->type) {
2252 case BCM43xx_PHYTYPE_A:
2253 if (phy->rev == 2 || phy->rev == 3) {
2254 bcm43xx_phy_inita(dev);
2255 err = 0;
2256 }
2257 break;
2258 case BCM43xx_PHYTYPE_B:
2259 switch (phy->rev) {
2260 case 2:
2261 bcm43xx_phy_initb2(dev);
2262 err = 0;
2263 break;
2264 case 4:
2265 bcm43xx_phy_initb4(dev);
2266 err = 0;
2267 break;
2268 case 5:
2269 bcm43xx_phy_initb5(dev);
2270 err = 0;
2271 break;
2272 case 6:
2273 bcm43xx_phy_initb6(dev);
2274 err = 0;
2275 break;
2276 }
2277 break;
2278 case BCM43xx_PHYTYPE_G:
2279 bcm43xx_phy_initg(dev);
2280 err = 0;
2281 break;
2282 }
2283 if (err)
2284 printk(KERN_WARNING PFX "Unknown PHYTYPE found!\n");
2285
2286 return err;
2287 }
2288
2289 void bcm43xx_set_rx_antenna(struct bcm43xx_wldev *dev, int antenna)
2290 {
2291 struct bcm43xx_phy *phy = &dev->phy;
2292 u32 hf;
2293 u16 tmp;
2294 int autodiv = 0;
2295
2296 if (antenna == BCM43xx_ANTENNA_AUTO0 ||
2297 antenna == BCM43xx_ANTENNA_AUTO1)
2298 autodiv = 1;
2299
2300 hf = bcm43xx_hf_read(dev);
2301 hf &= ~BCM43xx_HF_ANTDIVHELP;
2302 bcm43xx_hf_write(dev, hf);
2303
2304 switch (phy->type) {
2305 case BCM43xx_PHYTYPE_A:
2306 case BCM43xx_PHYTYPE_G:
2307 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_BBANDCFG);
2308 tmp &= ~BCM43xx_PHY_BBANDCFG_RXANT;
2309 tmp |= (autodiv ? BCM43xx_ANTENNA_AUTO0 : antenna)
2310 << BCM43xx_PHY_BBANDCFG_RXANT_SHIFT;
2311 bcm43xx_phy_write(dev, BCM43xx_PHY_BBANDCFG, tmp);
2312
2313 if (autodiv) {
2314 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ANTDWELL);
2315 if (antenna == BCM43xx_ANTENNA_AUTO0)
2316 tmp &= ~BCM43xx_PHY_ANTDWELL_AUTODIV1;
2317 else
2318 tmp |= BCM43xx_PHY_ANTDWELL_AUTODIV1;
2319 bcm43xx_phy_write(dev, BCM43xx_PHY_ANTDWELL, tmp);
2320 }
2321 if (phy->type == BCM43xx_PHYTYPE_G) {
2322 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ANTWRSETT);
2323 if (autodiv)
2324 tmp |= BCM43xx_PHY_ANTWRSETT_ARXDIV;
2325 else
2326 tmp &= ~BCM43xx_PHY_ANTWRSETT_ARXDIV;
2327 bcm43xx_phy_write(dev, BCM43xx_PHY_ANTWRSETT, tmp);
2328 if (phy->rev >= 2) {
2329 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM61);
2330 tmp |= BCM43xx_PHY_OFDM61_10;
2331 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM61, tmp);
2332
2333 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_DIVSRCHGAINBACK);
2334 tmp = (tmp & 0xFF00) | 0x15;
2335 bcm43xx_phy_write(dev, BCM43xx_PHY_DIVSRCHGAINBACK, tmp);
2336
2337 if (phy->rev == 2) {
2338 bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, 8);
2339 } else {
2340 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ADIVRELATED);
2341 tmp = (tmp & 0xFF00) | 8;
2342 bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, tmp);
2343 }
2344 }
2345 if (phy->rev >= 6)
2346 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM9B, 0xDC);
2347 } else {
2348 if (phy->rev < 3) {
2349 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ANTDWELL);
2350 tmp = (tmp & 0xFF00) | 0x24;
2351 bcm43xx_phy_write(dev, BCM43xx_PHY_ANTDWELL, tmp);
2352 } else {
2353 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_OFDM61);
2354 tmp |= 0x10;
2355 bcm43xx_phy_write(dev, BCM43xx_PHY_OFDM61, tmp);
2356 if (phy->analog == 3) {
2357 bcm43xx_phy_write(dev, BCM43xx_PHY_CLIPPWRDOWNT, 0x1D);
2358 bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, 8);
2359 } else {
2360 bcm43xx_phy_write(dev, BCM43xx_PHY_CLIPPWRDOWNT, 0x3A);
2361 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_ADIVRELATED);
2362 tmp = (tmp & 0xFF00) | 8;
2363 bcm43xx_phy_write(dev, BCM43xx_PHY_ADIVRELATED, tmp);
2364 }
2365 }
2366 }
2367 break;
2368 case BCM43xx_PHYTYPE_B:
2369 tmp = bcm43xx_phy_read(dev, BCM43xx_PHY_CCKBBANDCFG);
2370 tmp &= ~BCM43xx_PHY_BBANDCFG_RXANT;
2371 tmp |= (autodiv ? BCM43xx_ANTENNA_AUTO0 : antenna)
2372 << BCM43xx_PHY_BBANDCFG_RXANT_SHIFT;
2373 bcm43xx_phy_write(dev, BCM43xx_PHY_CCKBBANDCFG, tmp);
2374 break;
2375 default:
2376 assert(0);
2377 }
2378
2379 hf |= BCM43xx_HF_ANTDIVHELP;
2380 bcm43xx_hf_write(dev, hf);
2381 }
2382
2383 /* Get the freq, as it has to be written to the device. */
2384 static inline
2385 u16 channel2freq_bg(u8 channel)
2386 {
2387 assert(channel >= 1 && channel <= 14);
2388
2389 return bcm43xx_radio_channel_codes_bg[channel - 1];
2390 }
2391
2392 /* Get the freq, as it has to be written to the device. */
2393 static inline
2394 u16 channel2freq_a(u8 channel)
2395 {
2396 assert(channel <= 200);
2397
2398 return (5000 + 5 * channel);
2399 }
2400
2401 void bcm43xx_radio_lock(struct bcm43xx_wldev *dev)
2402 {
2403 u32 status;
2404
2405 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2406 status |= BCM43xx_SBF_RADIOREG_LOCK;
2407 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
2408 mmiowb();
2409 udelay(10);
2410 }
2411
2412 void bcm43xx_radio_unlock(struct bcm43xx_wldev *dev)
2413 {
2414 u32 status;
2415
2416 bcm43xx_read16(dev, BCM43xx_MMIO_PHY_VER); /* dummy read */
2417 status = bcm43xx_read32(dev, BCM43xx_MMIO_STATUS_BITFIELD);
2418 status &= ~BCM43xx_SBF_RADIOREG_LOCK;
2419 bcm43xx_write32(dev, BCM43xx_MMIO_STATUS_BITFIELD, status);
2420 mmiowb();
2421 }
2422
2423 u16 bcm43xx_radio_read16(struct bcm43xx_wldev *dev, u16 offset)
2424 {
2425 struct bcm43xx_phy *phy = &dev->phy;
2426
2427 switch (phy->type) {
2428 case BCM43xx_PHYTYPE_A:
2429 offset |= 0x0040;
2430 break;
2431 case BCM43xx_PHYTYPE_B:
2432 if (phy->radio_ver == 0x2053) {
2433 if (offset < 0x70)
2434 offset += 0x80;
2435 else if (offset < 0x80)
2436 offset += 0x70;
2437 } else if (phy->radio_ver == 0x2050) {
2438 offset |= 0x80;
2439 } else
2440 assert(0);
2441 break;
2442 case BCM43xx_PHYTYPE_G:
2443 offset |= 0x80;
2444 break;
2445 }
2446
2447 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL, offset);
2448 return bcm43xx_read16(dev, BCM43xx_MMIO_RADIO_DATA_LOW);
2449 }
2450
2451 void bcm43xx_radio_write16(struct bcm43xx_wldev *dev, u16 offset, u16 val)
2452 {
2453 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_CONTROL, offset);
2454 mmiowb();
2455 bcm43xx_write16(dev, BCM43xx_MMIO_RADIO_DATA_LOW, val);
2456 }
2457
2458 static void bcm43xx_set_all_gains(struct bcm43xx_wldev *dev,
2459 s16 first, s16 second, s16 third)
2460 {
2461 struct bcm43xx_phy *phy = &dev->phy;
2462 u16 i;
2463 u16 start = 0x08, end = 0x18;
2464 u16 tmp;
2465 u16 table;
2466
2467 if (phy->rev <= 1) {
2468 start = 0x10;
2469 end = 0x20;
2470 }
2471
2472 table = BCM43xx_OFDMTAB_GAINX;
2473 if (phy->rev <= 1)
2474 table = BCM43xx_OFDMTAB_GAINX_R1;
2475 for (i = 0; i < 4; i++)
2476 bcm43xx_ofdmtab_write16(dev, table, i, first);
2477
2478 for (i = start; i < end; i++)
2479 bcm43xx_ofdmtab_write16(dev, table, i, second);
2480
2481 if (third != -1) {
2482 tmp = ((u16)third << 14) | ((u16)third << 6);
2483 bcm43xx_phy_write(dev, 0x04A0,
2484 (bcm43xx_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
2485 bcm43xx_phy_write(dev, 0x04A1,
2486 (bcm43xx_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
2487 bcm43xx_phy_write(dev, 0x04A2,
2488 (bcm43xx_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
2489 }
2490 bcm43xx_dummy_transmission(dev);
2491 }
2492
2493 static void bcm43xx_set_original_gains(struct bcm43xx_wldev *dev)
2494 {
2495 struct bcm43xx_phy *phy = &dev->phy;
2496 u16 i, tmp;
2497 u16 table;
2498 u16 start = 0x0008, end = 0x0018;
2499
2500 if (phy->rev <= 1) {
2501 start = 0x0010;
2502 end = 0x0020;
2503 }
2504
2505 table = BCM43xx_OFDMTAB_GAINX;
2506 if (phy->rev <= 1)
2507 table = BCM43xx_OFDMTAB_GAINX_R1;
2508 for (i = 0; i < 4; i++) {
2509 tmp = (i & 0xFFFC);
2510 tmp |= (i & 0x0001) << 1;
2511 tmp |= (i & 0x0002) >> 1;
2512
2513 bcm43xx_ofdmtab_write16(dev, table, i, tmp);
2514 }
2515
2516 for (i = start; i < end; i++)
2517 bcm43xx_ofdmtab_write16(dev, table, i, i - start);
2518
2519 bcm43xx_phy_write(dev, 0x04A0,
2520 (bcm43xx_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
2521 bcm43xx_phy_write(dev, 0x04A1,
2522 (bcm43xx_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
2523 bcm43xx_phy_write(dev, 0x04A2,
2524 (bcm43xx_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
2525 bcm43xx_dummy_transmission(dev);
2526 }
2527
2528 /* Synthetic PU workaround */
2529 static void bcm43xx_synth_pu_workaround(struct bcm43xx_wldev *dev, u8 channel)
2530 {
2531 struct bcm43xx_phy *phy = &dev->phy;
2532
2533 might_sleep();
2534
2535 if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
2536 /* We do not need the workaround. */
2537 return;
2538 }
2539
2540 if (channel <= 10) {
2541 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
2542 channel2freq_bg(channel + 4));
2543 } else {
2544 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
2545 channel2freq_bg(1));
2546 }
2547 msleep(1);
2548 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
2549 channel2freq_bg(channel));
2550 }
2551
2552 u8 bcm43xx_radio_aci_detect(struct bcm43xx_wldev *dev, u8 channel)
2553 {
2554 struct bcm43xx_phy *phy = &dev->phy;
2555 u8 ret = 0;
2556 u16 saved, rssi, temp;
2557 int i, j = 0;
2558
2559 saved = bcm43xx_phy_read(dev, 0x0403);
2560 bcm43xx_radio_selectchannel(dev, channel, 0);
2561 bcm43xx_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2562 if (phy->aci_hw_rssi)
2563 rssi = bcm43xx_phy_read(dev, 0x048A) & 0x3F;
2564 else
2565 rssi = saved & 0x3F;
2566 /* clamp temp to signed 5bit */
2567 if (rssi > 32)
2568 rssi -= 64;
2569 for (i = 0;i < 100; i++) {
2570 temp = (bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x3F;
2571 if (temp > 32)
2572 temp -= 64;
2573 if (temp < rssi)
2574 j++;
2575 if (j >= 20)
2576 ret = 1;
2577 }
2578 bcm43xx_phy_write(dev, 0x0403, saved);
2579
2580 return ret;
2581 }
2582
2583 u8 bcm43xx_radio_aci_scan(struct bcm43xx_wldev *dev)
2584 {
2585 struct bcm43xx_phy *phy = &dev->phy;
2586 u8 ret[13];
2587 unsigned int channel = phy->channel;
2588 unsigned int i, j, start, end;
2589 unsigned long phylock_flags;
2590
2591 if (!((phy->type == BCM43xx_PHYTYPE_G) && (phy->rev > 0)))
2592 return 0;
2593
2594 bcm43xx_phy_lock(dev, phylock_flags);
2595 bcm43xx_radio_lock(dev);
2596 bcm43xx_phy_write(dev, 0x0802,
2597 bcm43xx_phy_read(dev, 0x0802) & 0xFFFC);
2598 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
2599 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & 0x7FFF);
2600 bcm43xx_set_all_gains(dev, 3, 8, 1);
2601
2602 start = (channel - 5 > 0) ? channel - 5 : 1;
2603 end = (channel + 5 < 14) ? channel + 5 : 13;
2604
2605 for (i = start; i <= end; i++) {
2606 if (abs(channel - i) > 2)
2607 ret[i-1] = bcm43xx_radio_aci_detect(dev, i);
2608 }
2609 bcm43xx_radio_selectchannel(dev, channel, 0);
2610 bcm43xx_phy_write(dev, 0x0802,
2611 (bcm43xx_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2612 bcm43xx_phy_write(dev, 0x0403,
2613 bcm43xx_phy_read(dev, 0x0403) & 0xFFF8);
2614 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
2615 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x8000);
2616 bcm43xx_set_original_gains(dev);
2617 for (i = 0; i < 13; i++) {
2618 if (!ret[i])
2619 continue;
2620 end = (i + 5 < 13) ? i + 5 : 13;
2621 for (j = i; j < end; j++)
2622 ret[j] = 1;
2623 }
2624 bcm43xx_radio_unlock(dev);
2625 bcm43xx_phy_unlock(dev, phylock_flags);
2626
2627 return ret[channel - 1];
2628 }
2629
2630 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2631 void bcm43xx_nrssi_hw_write(struct bcm43xx_wldev *dev, u16 offset, s16 val)
2632 {
2633 bcm43xx_phy_write(dev, BCM43xx_PHY_NRSSILT_CTRL, offset);
2634 mmiowb();
2635 bcm43xx_phy_write(dev, BCM43xx_PHY_NRSSILT_DATA, (u16)val);
2636 }
2637
2638 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2639 s16 bcm43xx_nrssi_hw_read(struct bcm43xx_wldev *dev, u16 offset)
2640 {
2641 u16 val;
2642
2643 bcm43xx_phy_write(dev, BCM43xx_PHY_NRSSILT_CTRL, offset);
2644 val = bcm43xx_phy_read(dev, BCM43xx_PHY_NRSSILT_DATA);
2645
2646 return (s16)val;
2647 }
2648
2649 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2650 void bcm43xx_nrssi_hw_update(struct bcm43xx_wldev *dev, u16 val)
2651 {
2652 u16 i;
2653 s16 tmp;
2654
2655 for (i = 0; i < 64; i++) {
2656 tmp = bcm43xx_nrssi_hw_read(dev, i);
2657 tmp -= val;
2658 tmp = limit_value(tmp, -32, 31);
2659 bcm43xx_nrssi_hw_write(dev, i, tmp);
2660 }
2661 }
2662
2663 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
2664 void bcm43xx_nrssi_mem_update(struct bcm43xx_wldev *dev)
2665 {
2666 struct bcm43xx_phy *phy = &dev->phy;
2667 s16 i, delta;
2668 s32 tmp;
2669
2670 delta = 0x1F - phy->nrssi[0];
2671 for (i = 0; i < 64; i++) {
2672 tmp = (i - delta) * phy->nrssislope;
2673 tmp /= 0x10000;
2674 tmp += 0x3A;
2675 tmp = limit_value(tmp, 0, 0x3F);
2676 phy->nrssi_lt[i] = tmp;
2677 }
2678 }
2679
2680 static void bcm43xx_calc_nrssi_offset(struct bcm43xx_wldev *dev)
2681 {
2682 struct bcm43xx_phy *phy = &dev->phy;
2683 u16 backup[20] = { 0 };
2684 s16 v47F;
2685 u16 i;
2686 u16 saved = 0xFFFF;
2687
2688 backup[0] = bcm43xx_phy_read(dev, 0x0001);
2689 backup[1] = bcm43xx_phy_read(dev, 0x0811);
2690 backup[2] = bcm43xx_phy_read(dev, 0x0812);
2691 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2692 backup[3] = bcm43xx_phy_read(dev, 0x0814);
2693 backup[4] = bcm43xx_phy_read(dev, 0x0815);
2694 }
2695 backup[5] = bcm43xx_phy_read(dev, 0x005A);
2696 backup[6] = bcm43xx_phy_read(dev, 0x0059);
2697 backup[7] = bcm43xx_phy_read(dev, 0x0058);
2698 backup[8] = bcm43xx_phy_read(dev, 0x000A);
2699 backup[9] = bcm43xx_phy_read(dev, 0x0003);
2700 backup[10] = bcm43xx_radio_read16(dev, 0x007A);
2701 backup[11] = bcm43xx_radio_read16(dev, 0x0043);
2702
2703 bcm43xx_phy_write(dev, 0x0429,
2704 bcm43xx_phy_read(dev, 0x0429) & 0x7FFF);
2705 bcm43xx_phy_write(dev, 0x0001,
2706 (bcm43xx_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
2707 bcm43xx_phy_write(dev, 0x0811,
2708 bcm43xx_phy_read(dev, 0x0811) | 0x000C);
2709 bcm43xx_phy_write(dev, 0x0812,
2710 (bcm43xx_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
2711 bcm43xx_phy_write(dev, 0x0802,
2712 bcm43xx_phy_read(dev, 0x0802) & ~(0x1 | 0x2));
2713 if (phy->rev >= 6) {
2714 backup[12] = bcm43xx_phy_read(dev, 0x002E);
2715 backup[13] = bcm43xx_phy_read(dev, 0x002F);
2716 backup[14] = bcm43xx_phy_read(dev, 0x080F);
2717 backup[15] = bcm43xx_phy_read(dev, 0x0810);
2718 backup[16] = bcm43xx_phy_read(dev, 0x0801);
2719 backup[17] = bcm43xx_phy_read(dev, 0x0060);
2720 backup[18] = bcm43xx_phy_read(dev, 0x0014);
2721 backup[19] = bcm43xx_phy_read(dev, 0x0478);
2722
2723 bcm43xx_phy_write(dev, 0x002E, 0);
2724 bcm43xx_phy_write(dev, 0x002F, 0);
2725 bcm43xx_phy_write(dev, 0x080F, 0);
2726 bcm43xx_phy_write(dev, 0x0810, 0);
2727 bcm43xx_phy_write(dev, 0x0478,
2728 bcm43xx_phy_read(dev, 0x0478) | 0x0100);
2729 bcm43xx_phy_write(dev, 0x0801,
2730 bcm43xx_phy_read(dev, 0x0801) | 0x0040);
2731 bcm43xx_phy_write(dev, 0x0060,
2732 bcm43xx_phy_read(dev, 0x0060) | 0x0040);
2733 bcm43xx_phy_write(dev, 0x0014,
2734 bcm43xx_phy_read(dev, 0x0014) | 0x0200);
2735 }
2736 bcm43xx_radio_write16(dev, 0x007A,
2737 bcm43xx_radio_read16(dev, 0x007A) | 0x0070);
2738 bcm43xx_radio_write16(dev, 0x007A,
2739 bcm43xx_radio_read16(dev, 0x007A) | 0x0080);
2740 udelay(30);
2741
2742 v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
2743 if (v47F >= 0x20)
2744 v47F -= 0x40;
2745 if (v47F == 31) {
2746 for (i = 7; i >= 4; i--) {
2747 bcm43xx_radio_write16(dev, 0x007B, i);
2748 udelay(20);
2749 v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
2750 if (v47F >= 0x20)
2751 v47F -= 0x40;
2752 if (v47F < 31 && saved == 0xFFFF)
2753 saved = i;
2754 }
2755 if (saved == 0xFFFF)
2756 saved = 4;
2757 } else {
2758 bcm43xx_radio_write16(dev, 0x007A,
2759 bcm43xx_radio_read16(dev, 0x007A) & 0x007F);
2760 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2761 bcm43xx_phy_write(dev, 0x0814,
2762 bcm43xx_phy_read(dev, 0x0814) | 0x0001);
2763 bcm43xx_phy_write(dev, 0x0815,
2764 bcm43xx_phy_read(dev, 0x0815) & 0xFFFE);
2765 }
2766 bcm43xx_phy_write(dev, 0x0811,
2767 bcm43xx_phy_read(dev, 0x0811) | 0x000C);
2768 bcm43xx_phy_write(dev, 0x0812,
2769 bcm43xx_phy_read(dev, 0x0812) | 0x000C);
2770 bcm43xx_phy_write(dev, 0x0811,
2771 bcm43xx_phy_read(dev, 0x0811) | 0x0030);
2772 bcm43xx_phy_write(dev, 0x0812,
2773 bcm43xx_phy_read(dev, 0x0812) | 0x0030);
2774 bcm43xx_phy_write(dev, 0x005A, 0x0480);
2775 bcm43xx_phy_write(dev, 0x0059, 0x0810);
2776 bcm43xx_phy_write(dev, 0x0058, 0x000D);
2777 if (phy->rev == 0) {
2778 bcm43xx_phy_write(dev, 0x0003, 0x0122);
2779 } else {
2780 bcm43xx_phy_write(dev, 0x000A,
2781 bcm43xx_phy_read(dev, 0x000A)
2782 | 0x2000);
2783 }
2784 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2785 bcm43xx_phy_write(dev, 0x0814,
2786 bcm43xx_phy_read(dev, 0x0814) | 0x0004);
2787 bcm43xx_phy_write(dev, 0x0815,
2788 bcm43xx_phy_read(dev, 0x0815) & 0xFFFB);
2789 }
2790 bcm43xx_phy_write(dev, 0x0003,
2791 (bcm43xx_phy_read(dev, 0x0003) & 0xFF9F)
2792 | 0x0040);
2793 bcm43xx_radio_write16(dev, 0x007A,
2794 bcm43xx_radio_read16(dev, 0x007A) | 0x000F);
2795 bcm43xx_set_all_gains(dev, 3, 0, 1);
2796 bcm43xx_radio_write16(dev, 0x0043,
2797 (bcm43xx_radio_read16(dev, 0x0043)
2798 & 0x00F0) | 0x000F);
2799 udelay(30);
2800 v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
2801 if (v47F >= 0x20)
2802 v47F -= 0x40;
2803 if (v47F == -32) {
2804 for (i = 0; i < 4; i++) {
2805 bcm43xx_radio_write16(dev, 0x007B, i);
2806 udelay(20);
2807 v47F = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
2808 if (v47F >= 0x20)
2809 v47F -= 0x40;
2810 if (v47F > -31 && saved == 0xFFFF)
2811 saved = i;
2812 }
2813 if (saved == 0xFFFF)
2814 saved = 3;
2815 } else
2816 saved = 0;
2817 }
2818 bcm43xx_radio_write16(dev, 0x007B, saved);
2819
2820 if (phy->rev >= 6) {
2821 bcm43xx_phy_write(dev, 0x002E, backup[12]);
2822 bcm43xx_phy_write(dev, 0x002F, backup[13]);
2823 bcm43xx_phy_write(dev, 0x080F, backup[14]);
2824 bcm43xx_phy_write(dev, 0x0810, backup[15]);
2825 }
2826 if (phy->rev != 1) { /* Not in specs, but needed to prevent PPC machine check */
2827 bcm43xx_phy_write(dev, 0x0814, backup[3]);
2828 bcm43xx_phy_write(dev, 0x0815, backup[4]);
2829 }
2830 bcm43xx_phy_write(dev, 0x005A, backup[5]);
2831 bcm43xx_phy_write(dev, 0x0059, backup[6]);
2832 bcm43xx_phy_write(dev, 0x0058, backup[7]);
2833 bcm43xx_phy_write(dev, 0x000A, backup[8]);
2834 bcm43xx_phy_write(dev, 0x0003, backup[9]);
2835 bcm43xx_radio_write16(dev, 0x0043, backup[11]);
2836 bcm43xx_radio_write16(dev, 0x007A, backup[10]);
2837 bcm43xx_phy_write(dev, 0x0802,
2838 bcm43xx_phy_read(dev, 0x0802) | 0x1 | 0x2);
2839 bcm43xx_phy_write(dev, 0x0429,
2840 bcm43xx_phy_read(dev, 0x0429) | 0x8000);
2841 bcm43xx_set_original_gains(dev);
2842 if (phy->rev >= 6) {
2843 bcm43xx_phy_write(dev, 0x0801, backup[16]);
2844 bcm43xx_phy_write(dev, 0x0060, backup[17]);
2845 bcm43xx_phy_write(dev, 0x0014, backup[18]);
2846 bcm43xx_phy_write(dev, 0x0478, backup[19]);
2847 }
2848 bcm43xx_phy_write(dev, 0x0001, backup[0]);
2849 bcm43xx_phy_write(dev, 0x0812, backup[2]);
2850 bcm43xx_phy_write(dev, 0x0811, backup[1]);
2851 }
2852
2853 void bcm43xx_calc_nrssi_slope(struct bcm43xx_wldev *dev)
2854 {
2855 struct bcm43xx_phy *phy = &dev->phy;
2856 u16 backup[18] = { 0 };
2857 u16 tmp;
2858 s16 nrssi0, nrssi1;
2859
2860 switch (phy->type) {
2861 case BCM43xx_PHYTYPE_B:
2862 backup[0] = bcm43xx_radio_read16(dev, 0x007A);
2863 backup[1] = bcm43xx_radio_read16(dev, 0x0052);
2864 backup[2] = bcm43xx_radio_read16(dev, 0x0043);
2865 backup[3] = bcm43xx_phy_read(dev, 0x0030);
2866 backup[4] = bcm43xx_phy_read(dev, 0x0026);
2867 backup[5] = bcm43xx_phy_read(dev, 0x0015);
2868 backup[6] = bcm43xx_phy_read(dev, 0x002A);
2869 backup[7] = bcm43xx_phy_read(dev, 0x0020);
2870 backup[8] = bcm43xx_phy_read(dev, 0x005A);
2871 backup[9] = bcm43xx_phy_read(dev, 0x0059);
2872 backup[10] = bcm43xx_phy_read(dev, 0x0058);
2873 backup[11] = bcm43xx_read16(dev, 0x03E2);
2874 backup[12] = bcm43xx_read16(dev, 0x03E6);
2875 backup[13] = bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT);
2876
2877 tmp = bcm43xx_radio_read16(dev, 0x007A);
2878 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
2879 bcm43xx_radio_write16(dev, 0x007A, tmp);
2880 bcm43xx_phy_write(dev, 0x0030, 0x00FF);
2881 bcm43xx_write16(dev, 0x03EC, 0x7F7F);
2882 bcm43xx_phy_write(dev, 0x0026, 0x0000);
2883 bcm43xx_phy_write(dev, 0x0015,
2884 bcm43xx_phy_read(dev, 0x0015) | 0x0020);
2885 bcm43xx_phy_write(dev, 0x002A, 0x08A3);
2886 bcm43xx_radio_write16(dev, 0x007A,
2887 bcm43xx_radio_read16(dev, 0x007A) | 0x0080);
2888
2889 nrssi0 = (s16)bcm43xx_phy_read(dev, 0x0027);
2890 bcm43xx_radio_write16(dev, 0x007A,
2891 bcm43xx_radio_read16(dev, 0x007A) & 0x007F);
2892 if (phy->rev >= 2) {
2893 bcm43xx_write16(dev, 0x03E6, 0x0040);
2894 } else if (phy->rev == 0) {
2895 bcm43xx_write16(dev, 0x03E6, 0x0122);
2896 } else {
2897 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
2898 bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT) & 0x2000);
2899 }
2900 bcm43xx_phy_write(dev, 0x0020, 0x3F3F);
2901 bcm43xx_phy_write(dev, 0x0015, 0xF330);
2902 bcm43xx_radio_write16(dev, 0x005A, 0x0060);
2903 bcm43xx_radio_write16(dev, 0x0043,
2904 bcm43xx_radio_read16(dev, 0x0043) & 0x00F0);
2905 bcm43xx_phy_write(dev, 0x005A, 0x0480);
2906 bcm43xx_phy_write(dev, 0x0059, 0x0810);
2907 bcm43xx_phy_write(dev, 0x0058, 0x000D);
2908 udelay(20);
2909
2910 nrssi1 = (s16)bcm43xx_phy_read(dev, 0x0027);
2911 bcm43xx_phy_write(dev, 0x0030, backup[3]);
2912 bcm43xx_radio_write16(dev, 0x007A, backup[0]);
2913 bcm43xx_write16(dev, 0x03E2, backup[11]);
2914 bcm43xx_phy_write(dev, 0x0026, backup[4]);
2915 bcm43xx_phy_write(dev, 0x0015, backup[5]);
2916 bcm43xx_phy_write(dev, 0x002A, backup[6]);
2917 bcm43xx_synth_pu_workaround(dev, phy->channel);
2918 if (phy->rev != 0)
2919 bcm43xx_write16(dev, 0x03F4, backup[13]);
2920
2921 bcm43xx_phy_write(dev, 0x0020, backup[7]);
2922 bcm43xx_phy_write(dev, 0x005A, backup[8]);
2923 bcm43xx_phy_write(dev, 0x0059, backup[9]);
2924 bcm43xx_phy_write(dev, 0x0058, backup[10]);
2925 bcm43xx_radio_write16(dev, 0x0052, backup[1]);
2926 bcm43xx_radio_write16(dev, 0x0043, backup[2]);
2927
2928 if (nrssi0 == nrssi1)
2929 phy->nrssislope = 0x00010000;
2930 else
2931 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
2932
2933 if (nrssi0 <= -4) {
2934 phy->nrssi[0] = nrssi0;
2935 phy->nrssi[1] = nrssi1;
2936 }
2937 break;
2938 case BCM43xx_PHYTYPE_G:
2939 if (phy->radio_rev >= 9)
2940 return;
2941 if (phy->radio_rev == 8)
2942 bcm43xx_calc_nrssi_offset(dev);
2943
2944 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
2945 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & 0x7FFF);
2946 bcm43xx_phy_write(dev, 0x0802,
2947 bcm43xx_phy_read(dev, 0x0802) & 0xFFFC);
2948 backup[7] = bcm43xx_read16(dev, 0x03E2);
2949 bcm43xx_write16(dev, 0x03E2,
2950 bcm43xx_read16(dev, 0x03E2) | 0x8000);
2951 backup[0] = bcm43xx_radio_read16(dev, 0x007A);
2952 backup[1] = bcm43xx_radio_read16(dev, 0x0052);
2953 backup[2] = bcm43xx_radio_read16(dev, 0x0043);
2954 backup[3] = bcm43xx_phy_read(dev, 0x0015);
2955 backup[4] = bcm43xx_phy_read(dev, 0x005A);
2956 backup[5] = bcm43xx_phy_read(dev, 0x0059);
2957 backup[6] = bcm43xx_phy_read(dev, 0x0058);
2958 backup[8] = bcm43xx_read16(dev, 0x03E6);
2959 backup[9] = bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT);
2960 if (phy->rev >= 3) {
2961 backup[10] = bcm43xx_phy_read(dev, 0x002E);
2962 backup[11] = bcm43xx_phy_read(dev, 0x002F);
2963 backup[12] = bcm43xx_phy_read(dev, 0x080F);
2964 backup[13] = bcm43xx_phy_read(dev, BCM43xx_PHY_G_LO_CONTROL);
2965 backup[14] = bcm43xx_phy_read(dev, 0x0801);
2966 backup[15] = bcm43xx_phy_read(dev, 0x0060);
2967 backup[16] = bcm43xx_phy_read(dev, 0x0014);
2968 backup[17] = bcm43xx_phy_read(dev, 0x0478);
2969 bcm43xx_phy_write(dev, 0x002E, 0);
2970 bcm43xx_phy_write(dev, BCM43xx_PHY_G_LO_CONTROL, 0);
2971 switch (phy->rev) {
2972 case 4: case 6: case 7:
2973 bcm43xx_phy_write(dev, 0x0478,
2974 bcm43xx_phy_read(dev, 0x0478)
2975 | 0x0100);
2976 bcm43xx_phy_write(dev, 0x0801,
2977 bcm43xx_phy_read(dev, 0x0801)
2978 | 0x0040);
2979 break;
2980 case 3: case 5:
2981 bcm43xx_phy_write(dev, 0x0801,
2982 bcm43xx_phy_read(dev, 0x0801)
2983 & 0xFFBF);
2984 break;
2985 }
2986 bcm43xx_phy_write(dev, 0x0060,
2987 bcm43xx_phy_read(dev, 0x0060)
2988 | 0x0040);
2989 bcm43xx_phy_write(dev, 0x0014,
2990 bcm43xx_phy_read(dev, 0x0014)
2991 | 0x0200);
2992 }
2993 bcm43xx_radio_write16(dev, 0x007A,
2994 bcm43xx_radio_read16(dev, 0x007A) | 0x0070);
2995 bcm43xx_set_all_gains(dev, 0, 8, 0);
2996 bcm43xx_radio_write16(dev, 0x007A,
2997 bcm43xx_radio_read16(dev, 0x007A) & 0x00F7);
2998 if (phy->rev >= 2) {
2999 bcm43xx_phy_write(dev, 0x0811,
3000 (bcm43xx_phy_read(dev, 0x0811) & 0xFFCF) | 0x0030);
3001 bcm43xx_phy_write(dev, 0x0812,
3002 (bcm43xx_phy_read(dev, 0x0812) & 0xFFCF) | 0x0010);
3003 }
3004 bcm43xx_radio_write16(dev, 0x007A,
3005 bcm43xx_radio_read16(dev, 0x007A) | 0x0080);
3006 udelay(20);
3007
3008 nrssi0 = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
3009 if (nrssi0 >= 0x0020)
3010 nrssi0 -= 0x0040;
3011
3012 bcm43xx_radio_write16(dev, 0x007A,
3013 bcm43xx_radio_read16(dev, 0x007A) & 0x007F);
3014 if (phy->rev >= 2) {
3015 bcm43xx_phy_write(dev, 0x0003,
3016 (bcm43xx_phy_read(dev, 0x0003)
3017 & 0xFF9F) | 0x0040);
3018 }
3019
3020 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
3021 bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT)
3022 | 0x2000);
3023 bcm43xx_radio_write16(dev, 0x007A,
3024 bcm43xx_radio_read16(dev, 0x007A) | 0x000F);
3025 bcm43xx_phy_write(dev, 0x0015, 0xF330);
3026 if (phy->rev >= 2) {
3027 bcm43xx_phy_write(dev, 0x0812,
3028 (bcm43xx_phy_read(dev, 0x0812) & 0xFFCF) | 0x0020);
3029 bcm43xx_phy_write(dev, 0x0811,
3030 (bcm43xx_phy_read(dev, 0x0811) & 0xFFCF) | 0x0020);
3031 }
3032
3033 bcm43xx_set_all_gains(dev, 3, 0, 1);
3034 if (phy->radio_rev == 8) {
3035 bcm43xx_radio_write16(dev, 0x0043, 0x001F);
3036 } else {
3037 tmp = bcm43xx_radio_read16(dev, 0x0052) & 0xFF0F;
3038 bcm43xx_radio_write16(dev, 0x0052, tmp | 0x0060);
3039 tmp = bcm43xx_radio_read16(dev, 0x0043) & 0xFFF0;
3040 bcm43xx_radio_write16(dev, 0x0043, tmp | 0x0009);
3041 }
3042 bcm43xx_phy_write(dev, 0x005A, 0x0480);
3043 bcm43xx_phy_write(dev, 0x0059, 0x0810);
3044 bcm43xx_phy_write(dev, 0x0058, 0x000D);
3045 udelay(20);
3046 nrssi1 = (s16)((bcm43xx_phy_read(dev, 0x047F) >> 8) & 0x003F);
3047 if (nrssi1 >= 0x0020)
3048 nrssi1 -= 0x0040;
3049 if (nrssi0 == nrssi1)
3050 phy->nrssislope = 0x00010000;
3051 else
3052 phy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
3053 if (nrssi0 >= -4) {
3054 phy->nrssi[0] = nrssi1;
3055 phy->nrssi[1] = nrssi0;
3056 }
3057 if (phy->rev >= 3) {
3058 bcm43xx_phy_write(dev, 0x002E, backup[10]);
3059 bcm43xx_phy_write(dev, 0x002F, backup[11]);
3060 bcm43xx_phy_write(dev, 0x080F, backup[12]);
3061 bcm43xx_phy_write(dev, BCM43xx_PHY_G_LO_CONTROL, backup[13]);
3062 }
3063 if (phy->rev >= 2) {
3064 bcm43xx_phy_write(dev, 0x0812,
3065 bcm43xx_phy_read(dev, 0x0812) & 0xFFCF);
3066 bcm43xx_phy_write(dev, 0x0811,
3067 bcm43xx_phy_read(dev, 0x0811) & 0xFFCF);
3068 }
3069
3070 bcm43xx_radio_write16(dev, 0x007A, backup[0]);
3071 bcm43xx_radio_write16(dev, 0x0052, backup[1]);
3072 bcm43xx_radio_write16(dev, 0x0043, backup[2]);
3073 bcm43xx_write16(dev, 0x03E2, backup[7]);
3074 bcm43xx_write16(dev, 0x03E6, backup[8]);
3075 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT, backup[9]);
3076 bcm43xx_phy_write(dev, 0x0015, backup[3]);
3077 bcm43xx_phy_write(dev, 0x005A, backup[4]);
3078 bcm43xx_phy_write(dev, 0x0059, backup[5]);
3079 bcm43xx_phy_write(dev, 0x0058, backup[6]);
3080 bcm43xx_synth_pu_workaround(dev, phy->channel);
3081 bcm43xx_phy_write(dev, 0x0802,
3082 bcm43xx_phy_read(dev, 0x0802) | (0x0001 | 0x0002));
3083 bcm43xx_set_original_gains(dev);
3084 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
3085 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x8000);
3086 if (phy->rev >= 3) {
3087 bcm43xx_phy_write(dev, 0x0801, backup[14]);
3088 bcm43xx_phy_write(dev, 0x0060, backup[15]);
3089 bcm43xx_phy_write(dev, 0x0014, backup[16]);
3090 bcm43xx_phy_write(dev, 0x0478, backup[17]);
3091 }
3092 bcm43xx_nrssi_mem_update(dev);
3093 bcm43xx_calc_nrssi_threshold(dev);
3094 break;
3095 default:
3096 assert(0);
3097 }
3098 }
3099
3100 void bcm43xx_calc_nrssi_threshold(struct bcm43xx_wldev *dev)
3101 {
3102 struct bcm43xx_phy *phy = &dev->phy;
3103 s32 threshold;
3104 s32 a, b;
3105 s16 tmp16;
3106 u16 tmp_u16;
3107
3108 switch (phy->type) {
3109 case BCM43xx_PHYTYPE_B: {
3110 if (phy->radio_ver != 0x2050)
3111 return;
3112 if (!(dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI))
3113 return;
3114
3115 if (phy->radio_rev >= 6) {
3116 threshold = (phy->nrssi[1] - phy->nrssi[0]) * 32;
3117 threshold += 20 * (phy->nrssi[0] + 1);
3118 threshold /= 40;
3119 } else
3120 threshold = phy->nrssi[1] - 5;
3121
3122 threshold = limit_value(threshold, 0, 0x3E);
3123 bcm43xx_phy_read(dev, 0x0020); /* dummy read */
3124 bcm43xx_phy_write(dev, 0x0020, (((u16)threshold) << 8) | 0x001C);
3125
3126 if (phy->radio_rev >= 6) {
3127 bcm43xx_phy_write(dev, 0x0087, 0x0E0D);
3128 bcm43xx_phy_write(dev, 0x0086, 0x0C0B);
3129 bcm43xx_phy_write(dev, 0x0085, 0x0A09);
3130 bcm43xx_phy_write(dev, 0x0084, 0x0808);
3131 bcm43xx_phy_write(dev, 0x0083, 0x0808);
3132 bcm43xx_phy_write(dev, 0x0082, 0x0604);
3133 bcm43xx_phy_write(dev, 0x0081, 0x0302);
3134 bcm43xx_phy_write(dev, 0x0080, 0x0100);
3135 }
3136 break;
3137 }
3138 case BCM43xx_PHYTYPE_G:
3139 if (!phy->gmode ||
3140 !(dev->dev->bus->sprom.r1.boardflags_lo & BCM43xx_BFL_RSSI)) {
3141 tmp16 = bcm43xx_nrssi_hw_read(dev, 0x20);
3142 if (tmp16 >= 0x20)
3143 tmp16 -= 0x40;
3144 if (tmp16 < 3) {
3145 bcm43xx_phy_write(dev, 0x048A,
3146 (bcm43xx_phy_read(dev, 0x048A)
3147 & 0xF000) | 0x09EB);
3148 } else {
3149 bcm43xx_phy_write(dev, 0x048A,
3150 (bcm43xx_phy_read(dev, 0x048A)
3151 & 0xF000) | 0x0AED);
3152 }
3153 } else {
3154 if (phy->interfmode == BCM43xx_INTERFMODE_NONWLAN) {
3155 a = 0xE;
3156 b = 0xA;
3157 } else if (!phy->aci_wlan_automatic && phy->aci_enable) {
3158 a = 0x13;
3159 b = 0x12;
3160 } else {
3161 a = 0xE;
3162 b = 0x11;
3163 }
3164
3165 a = a * (phy->nrssi[1] - phy->nrssi[0]);
3166 a += (phy->nrssi[0] << 6);
3167 if (a < 32)
3168 a += 31;
3169 else
3170 a += 32;
3171 a = a >> 6;
3172 a = limit_value(a, -31, 31);
3173
3174 b = b * (phy->nrssi[1] - phy->nrssi[0]);
3175 b += (phy->nrssi[0] << 6);
3176 if (b < 32)
3177 b += 31;
3178 else
3179 b += 32;
3180 b = b >> 6;
3181 b = limit_value(b, -31, 31);
3182
3183 tmp_u16 = bcm43xx_phy_read(dev, 0x048A) & 0xF000;
3184 tmp_u16 |= ((u32)b & 0x0000003F);
3185 tmp_u16 |= (((u32)a & 0x0000003F) << 6);
3186 bcm43xx_phy_write(dev, 0x048A, tmp_u16);
3187 }
3188 break;
3189 default:
3190 assert(0);
3191 }
3192 }
3193
3194 /* Stack implementation to save/restore values from the
3195 * interference mitigation code.
3196 * It is save to restore values in random order.
3197 */
3198 static void _stack_save(u32 *_stackptr, size_t *stackidx,
3199 u8 id, u16 offset, u16 value)
3200 {
3201 u32 *stackptr = &(_stackptr[*stackidx]);
3202
3203 assert((offset & 0xF000) == 0x0000);
3204 assert((id & 0xF0) == 0x00);
3205 *stackptr = offset;
3206 *stackptr |= ((u32)id) << 12;
3207 *stackptr |= ((u32)value) << 16;
3208 (*stackidx)++;
3209 assert(*stackidx < BCM43xx_INTERFSTACK_SIZE);
3210 }
3211
3212 static u16 _stack_restore(u32 *stackptr,
3213 u8 id, u16 offset)
3214 {
3215 size_t i;
3216
3217 assert((offset & 0xF000) == 0x0000);
3218 assert((id & 0xF0) == 0x00);
3219 for (i = 0; i < BCM43xx_INTERFSTACK_SIZE; i++, stackptr++) {
3220 if ((*stackptr & 0x00000FFF) != offset)
3221 continue;
3222 if (((*stackptr & 0x0000F000) >> 12) != id)
3223 continue;
3224 return ((*stackptr & 0xFFFF0000) >> 16);
3225 }
3226 assert(0);
3227
3228 return 0;
3229 }
3230
3231 #define phy_stacksave(offset) \
3232 do { \
3233 _stack_save(stack, &stackidx, 0x1, (offset), \
3234 bcm43xx_phy_read(dev, (offset))); \
3235 } while (0)
3236 #define phy_stackrestore(offset) \
3237 do { \
3238 bcm43xx_phy_write(dev, (offset), \
3239 _stack_restore(stack, 0x1, \
3240 (offset))); \
3241 } while (0)
3242 #define radio_stacksave(offset) \
3243 do { \
3244 _stack_save(stack, &stackidx, 0x2, (offset), \
3245 bcm43xx_radio_read16(dev, (offset))); \
3246 } while (0)
3247 #define radio_stackrestore(offset) \
3248 do { \
3249 bcm43xx_radio_write16(dev, (offset), \
3250 _stack_restore(stack, 0x2, \
3251 (offset))); \
3252 } while (0)
3253 #define ofdmtab_stacksave(table, offset) \
3254 do { \
3255 _stack_save(stack, &stackidx, 0x3, (offset)|(table), \
3256 bcm43xx_ofdmtab_read16(dev, (table), (offset))); \
3257 } while (0)
3258 #define ofdmtab_stackrestore(table, offset) \
3259 do { \
3260 bcm43xx_ofdmtab_write16(dev, (table), (offset), \
3261 _stack_restore(stack, 0x3, \
3262 (offset)|(table))); \
3263 } while (0)
3264
3265 static void
3266 bcm43xx_radio_interference_mitigation_enable(struct bcm43xx_wldev *dev,
3267 int mode)
3268 {
3269 struct bcm43xx_phy *phy = &dev->phy;
3270 u16 tmp, flipped;
3271 size_t stackidx = 0;
3272 u32 *stack = phy->interfstack;
3273
3274 switch (mode) {
3275 case BCM43xx_INTERFMODE_NONWLAN:
3276 if (phy->rev != 1) {
3277 bcm43xx_phy_write(dev, 0x042B,
3278 bcm43xx_phy_read(dev, 0x042B) | 0x0800);
3279 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
3280 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) & ~0x4000);
3281 break;
3282 }
3283 radio_stacksave(0x0078);
3284 tmp = (bcm43xx_radio_read16(dev, 0x0078) & 0x001E);
3285 flipped = flip_4bit(tmp);
3286 if (flipped < 10 && flipped >= 8)
3287 flipped = 7;
3288 else if (flipped >= 10)
3289 flipped -= 3;
3290 flipped = flip_4bit(flipped);
3291 flipped = (flipped << 1) | 0x0020;
3292 bcm43xx_radio_write16(dev, 0x0078, flipped);
3293
3294 bcm43xx_calc_nrssi_threshold(dev);
3295
3296 phy_stacksave(0x0406);
3297 bcm43xx_phy_write(dev, 0x0406, 0x7E28);
3298
3299 bcm43xx_phy_write(dev, 0x042B,
3300 bcm43xx_phy_read(dev, 0x042B) | 0x0800);
3301 bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
3302 bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD) | 0x1000);
3303
3304 phy_stacksave(0x04A0);
3305 bcm43xx_phy_write(dev, 0x04A0,
3306 (bcm43xx_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
3307 phy_stacksave(0x04A1);
3308 bcm43xx_phy_write(dev, 0x04A1,
3309 (bcm43xx_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
3310 phy_stacksave(0x04A2);
3311 bcm43xx_phy_write(dev, 0x04A2,
3312 (bcm43xx_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
3313 phy_stacksave(0x04A8);
3314 bcm43xx_phy_write(dev, 0x04A8,
3315 (bcm43xx_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
3316 phy_stacksave(0x04AB);
3317 bcm43xx_phy_write(dev, 0x04AB,
3318 (bcm43xx_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
3319
3320 phy_stacksave(0x04A7);
3321 bcm43xx_phy_write(dev, 0x04A7, 0x0002);
3322 phy_stacksave(0x04A3);
3323 bcm43xx_phy_write(dev, 0x04A3, 0x287A);
3324 phy_stacksave(0x04A9);
3325 bcm43xx_phy_write(dev, 0x04A9, 0x2027);
3326 phy_stacksave(0x0493);
3327 bcm43xx_phy_write(dev, 0x0493, 0x32F5);
3328 phy_stacksave(0x04AA);
3329 bcm43xx_phy_write(dev, 0x04AA, 0x2027);
3330 phy_stacksave(0x04AC);
3331 bcm43xx_phy_write(dev, 0x04AC, 0x32F5);
3332 break;
3333 case BCM43xx_INTERFMODE_MANUALWLAN:
3334 if (bcm43xx_phy_read(dev, 0x0033) & 0x0800)
3335 break;
3336
3337 phy->aci_enable = 1;
3338
3339 phy_stacksave(BCM43xx_PHY_RADIO_BITFIELD);
3340 phy_stacksave(BCM43xx_PHY_G_CRS);
3341 if (phy->rev < 2) {
3342 phy_stacksave(0x0406);
3343 } else {
3344 phy_stacksave(0x04C0);
3345 phy_stacksave(0x04C1);
3346 }
3347 phy_stacksave(0x0033);
3348 phy_stacksave(0x04A7);
3349 phy_stacksave(0x04A3);
3350 phy_stacksave(0x04A9);
3351 phy_stacksave(0x04AA);
3352 phy_stacksave(0x04AC);
3353 phy_stacksave(0x0493);
3354 phy_stacksave(0x04A1);
3355 phy_stacksave(0x04A0);
3356 phy_stacksave(0x04A2);
3357 phy_stacksave(0x048A);
3358 phy_stacksave(0x04A8);
3359 phy_stacksave(0x04AB);
3360 if (phy->rev == 2) {
3361 phy_stacksave(0x04AD);
3362 phy_stacksave(0x04AE);
3363 } else if (phy->rev >= 3) {
3364 phy_stacksave(0x04AD);
3365 phy_stacksave(0x0415);
3366 phy_stacksave(0x0416);
3367 phy_stacksave(0x0417);
3368 ofdmtab_stacksave(0x1A00, 0x2);
3369 ofdmtab_stacksave(0x1A00, 0x3);
3370 }
3371 phy_stacksave(0x042B);
3372 phy_stacksave(0x048C);
3373
3374 bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
3375 bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD)
3376 & ~0x1000);
3377 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
3378 (bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS)
3379 & 0xFFFC) | 0x0002);
3380
3381 bcm43xx_phy_write(dev, 0x0033, 0x0800);
3382 bcm43xx_phy_write(dev, 0x04A3, 0x2027);
3383 bcm43xx_phy_write(dev, 0x04A9, 0x1CA8);
3384 bcm43xx_phy_write(dev, 0x0493, 0x287A);
3385 bcm43xx_phy_write(dev, 0x04AA, 0x1CA8);
3386 bcm43xx_phy_write(dev, 0x04AC, 0x287A);
3387
3388 bcm43xx_phy_write(dev, 0x04A0,
3389 (bcm43xx_phy_read(dev, 0x04A0)
3390 & 0xFFC0) | 0x001A);
3391 bcm43xx_phy_write(dev, 0x04A7, 0x000D);
3392
3393 if (phy->rev < 2) {
3394 bcm43xx_phy_write(dev, 0x0406, 0xFF0D);
3395 } else if (phy->rev == 2) {
3396 bcm43xx_phy_write(dev, 0x04C0, 0xFFFF);
3397 bcm43xx_phy_write(dev, 0x04C1, 0x00A9);
3398 } else {
3399 bcm43xx_phy_write(dev, 0x04C0, 0x00C1);
3400 bcm43xx_phy_write(dev, 0x04C1, 0x0059);
3401 }
3402
3403 bcm43xx_phy_write(dev, 0x04A1,
3404 (bcm43xx_phy_read(dev, 0x04A1)
3405 & 0xC0FF) | 0x1800);
3406 bcm43xx_phy_write(dev, 0x04A1,
3407 (bcm43xx_phy_read(dev, 0x04A1)
3408 & 0xFFC0) | 0x0015);
3409 bcm43xx_phy_write(dev, 0x04A8,
3410 (bcm43xx_phy_read(dev, 0x04A8)
3411 & 0xCFFF) | 0x1000);
3412 bcm43xx_phy_write(dev, 0x04A8,
3413 (bcm43xx_phy_read(dev, 0x04A8)
3414 & 0xF0FF) | 0x0A00);
3415 bcm43xx_phy_write(dev, 0x04AB,
3416 (bcm43xx_phy_read(dev, 0x04AB)
3417 & 0xCFFF) | 0x1000);
3418 bcm43xx_phy_write(dev, 0x04AB,
3419 (bcm43xx_phy_read(dev, 0x04AB)
3420 & 0xF0FF) | 0x0800);
3421 bcm43xx_phy_write(dev, 0x04AB,
3422 (bcm43xx_phy_read(dev, 0x04AB)
3423 & 0xFFCF) | 0x0010);
3424 bcm43xx_phy_write(dev, 0x04AB,
3425 (bcm43xx_phy_read(dev, 0x04AB)
3426 & 0xFFF0) | 0x0005);
3427 bcm43xx_phy_write(dev, 0x04A8,
3428 (bcm43xx_phy_read(dev, 0x04A8)
3429 & 0xFFCF) | 0x0010);
3430 bcm43xx_phy_write(dev, 0x04A8,
3431 (bcm43xx_phy_read(dev, 0x04A8)
3432 & 0xFFF0) | 0x0006);
3433 bcm43xx_phy_write(dev, 0x04A2,
3434 (bcm43xx_phy_read(dev, 0x04A2)
3435 & 0xF0FF) | 0x0800);
3436 bcm43xx_phy_write(dev, 0x04A0,
3437 (bcm43xx_phy_read(dev, 0x04A0)
3438 & 0xF0FF) | 0x0500);
3439 bcm43xx_phy_write(dev, 0x04A2,
3440 (bcm43xx_phy_read(dev, 0x04A2)
3441 & 0xFFF0) | 0x000B);
3442
3443 if (phy->rev >= 3) {
3444 bcm43xx_phy_write(dev, 0x048A,
3445 bcm43xx_phy_read(dev, 0x048A)
3446 & ~0x8000);
3447 bcm43xx_phy_write(dev, 0x0415,
3448 (bcm43xx_phy_read(dev, 0x0415)
3449 & 0x8000) | 0x36D8);
3450 bcm43xx_phy_write(dev, 0x0416,
3451 (bcm43xx_phy_read(dev, 0x0416)
3452 & 0x8000) | 0x36D8);
3453 bcm43xx_phy_write(dev, 0x0417,
3454 (bcm43xx_phy_read(dev, 0x0417)
3455 & 0xFE00) | 0x016D);
3456 } else {
3457 bcm43xx_phy_write(dev, 0x048A,
3458 bcm43xx_phy_read(dev, 0x048A)
3459 | 0x1000);
3460 bcm43xx_phy_write(dev, 0x048A,
3461 (bcm43xx_phy_read(dev, 0x048A)
3462 & 0x9FFF) | 0x2000);
3463 bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) | BCM43xx_HF_ACIW);
3464 }
3465 if (phy->rev >= 2) {
3466 bcm43xx_phy_write(dev, 0x042B,
3467 bcm43xx_phy_read(dev, 0x042B)
3468 | 0x0800);
3469 }
3470 bcm43xx_phy_write(dev, 0x048C,
3471 (bcm43xx_phy_read(dev, 0x048C)
3472 & 0xF0FF) | 0x0200);
3473 if (phy->rev == 2) {
3474 bcm43xx_phy_write(dev, 0x04AE,
3475 (bcm43xx_phy_read(dev, 0x04AE)
3476 & 0xFF00) | 0x007F);
3477 bcm43xx_phy_write(dev, 0x04AD,
3478 (bcm43xx_phy_read(dev, 0x04AD)
3479 & 0x00FF) | 0x1300);
3480 } else if (phy->rev >= 6) {
3481 bcm43xx_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
3482 bcm43xx_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
3483 bcm43xx_phy_write(dev, 0x04AD,
3484 bcm43xx_phy_read(dev, 0x04AD)
3485 & 0x00FF);
3486 }
3487 bcm43xx_calc_nrssi_slope(dev);
3488 break;
3489 default:
3490 assert(0);
3491 }
3492 }
3493
3494 static void
3495 bcm43xx_radio_interference_mitigation_disable(struct bcm43xx_wldev *dev,
3496 int mode)
3497 {
3498 struct bcm43xx_phy *phy = &dev->phy;
3499 u32 *stack = phy->interfstack;
3500
3501 switch (mode) {
3502 case BCM43xx_INTERFMODE_NONWLAN:
3503 if (phy->rev != 1) {
3504 bcm43xx_phy_write(dev, 0x042B,
3505 bcm43xx_phy_read(dev, 0x042B) & ~0x0800);
3506 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
3507 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x4000);
3508 break;
3509 }
3510 radio_stackrestore(0x0078);
3511 bcm43xx_calc_nrssi_threshold(dev);
3512 phy_stackrestore(0x0406);
3513 bcm43xx_phy_write(dev, 0x042B,
3514 bcm43xx_phy_read(dev, 0x042B) & ~0x0800);
3515 if (!dev->bad_frames_preempt) {
3516 bcm43xx_phy_write(dev, BCM43xx_PHY_RADIO_BITFIELD,
3517 bcm43xx_phy_read(dev, BCM43xx_PHY_RADIO_BITFIELD)
3518 & ~(1 << 11));
3519 }
3520 bcm43xx_phy_write(dev, BCM43xx_PHY_G_CRS,
3521 bcm43xx_phy_read(dev, BCM43xx_PHY_G_CRS) | 0x4000);
3522 phy_stackrestore(0x04A0);
3523 phy_stackrestore(0x04A1);
3524 phy_stackrestore(0x04A2);
3525 phy_stackrestore(0x04A8);
3526 phy_stackrestore(0x04AB);
3527 phy_stackrestore(0x04A7);
3528 phy_stackrestore(0x04A3);
3529 phy_stackrestore(0x04A9);
3530 phy_stackrestore(0x0493);
3531 phy_stackrestore(0x04AA);
3532 phy_stackrestore(0x04AC);
3533 break;
3534 case BCM43xx_INTERFMODE_MANUALWLAN:
3535 if (!(bcm43xx_phy_read(dev, 0x0033) & 0x0800))
3536 break;
3537
3538 phy->aci_enable = 0;
3539
3540 phy_stackrestore(BCM43xx_PHY_RADIO_BITFIELD);
3541 phy_stackrestore(BCM43xx_PHY_G_CRS);
3542 phy_stackrestore(0x0033);
3543 phy_stackrestore(0x04A3);
3544 phy_stackrestore(0x04A9);
3545 phy_stackrestore(0x0493);
3546 phy_stackrestore(0x04AA);
3547 phy_stackrestore(0x04AC);
3548 phy_stackrestore(0x04A0);
3549 phy_stackrestore(0x04A7);
3550 if (phy->rev >= 2) {
3551 phy_stackrestore(0x04C0);
3552 phy_stackrestore(0x04C1);
3553 } else
3554 phy_stackrestore(0x0406);
3555 phy_stackrestore(0x04A1);
3556 phy_stackrestore(0x04AB);
3557 phy_stackrestore(0x04A8);
3558 if (phy->rev == 2) {
3559 phy_stackrestore(0x04AD);
3560 phy_stackrestore(0x04AE);
3561 } else if (phy->rev >= 3) {
3562 phy_stackrestore(0x04AD);
3563 phy_stackrestore(0x0415);
3564 phy_stackrestore(0x0416);
3565 phy_stackrestore(0x0417);
3566 ofdmtab_stackrestore(0x1A00, 0x2);
3567 ofdmtab_stackrestore(0x1A00, 0x3);
3568 }
3569 phy_stackrestore(0x04A2);
3570 phy_stackrestore(0x048A);
3571 phy_stackrestore(0x042B);
3572 phy_stackrestore(0x048C);
3573 bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) & ~BCM43xx_HF_ACIW);
3574 bcm43xx_calc_nrssi_slope(dev);
3575 break;
3576 default:
3577 assert(0);
3578 }
3579 }
3580
3581 #undef phy_stacksave
3582 #undef phy_stackrestore
3583 #undef radio_stacksave
3584 #undef radio_stackrestore
3585 #undef ofdmtab_stacksave
3586 #undef ofdmtab_stackrestore
3587
3588 int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_wldev *dev,
3589 int mode)
3590 {
3591 struct bcm43xx_phy *phy = &dev->phy;
3592 int currentmode;
3593
3594 if ((phy->type != BCM43xx_PHYTYPE_G) ||
3595 (phy->rev == 0) ||
3596 (!phy->gmode))
3597 return -ENODEV;
3598
3599 phy->aci_wlan_automatic = 0;
3600 switch (mode) {
3601 case BCM43xx_INTERFMODE_AUTOWLAN:
3602 phy->aci_wlan_automatic = 1;
3603 if (phy->aci_enable)
3604 mode = BCM43xx_INTERFMODE_MANUALWLAN;
3605 else
3606 mode = BCM43xx_INTERFMODE_NONE;
3607 break;
3608 case BCM43xx_INTERFMODE_NONE:
3609 case BCM43xx_INTERFMODE_NONWLAN:
3610 case BCM43xx_INTERFMODE_MANUALWLAN:
3611 break;
3612 default:
3613 return -EINVAL;
3614 }
3615
3616 currentmode = phy->interfmode;
3617 if (currentmode == mode)
3618 return 0;
3619 if (currentmode != BCM43xx_INTERFMODE_NONE)
3620 bcm43xx_radio_interference_mitigation_disable(dev, currentmode);
3621
3622 if (mode == BCM43xx_INTERFMODE_NONE) {
3623 phy->aci_enable = 0;
3624 phy->aci_hw_rssi = 0;
3625 } else
3626 bcm43xx_radio_interference_mitigation_enable(dev, mode);
3627 phy->interfmode = mode;
3628
3629 return 0;
3630 }
3631
3632 static u16 bcm43xx_radio_core_calibration_value(struct bcm43xx_wldev *dev)
3633 {
3634 u16 reg, index, ret;
3635
3636 static const u8 rcc_table[] = {
3637 0x02, 0x03, 0x01, 0x0F,
3638 0x06, 0x07, 0x05, 0x0F,
3639 0x0A, 0x0B, 0x09, 0x0F,
3640 0x0E, 0x0F, 0x0D, 0x0F,
3641 };
3642
3643 reg = bcm43xx_radio_read16(dev, 0x60);
3644 index = (reg & 0x001E) >> 1;
3645 ret = rcc_table[index] << 1;
3646 ret |= (reg & 0x0001);
3647 ret |= 0x0020;
3648
3649 return ret;
3650 }
3651
3652 #define LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0))
3653 static u16 radio2050_rfover_val(struct bcm43xx_wldev *dev,
3654 u16 phy_register,
3655 unsigned int lpd)
3656 {
3657 struct bcm43xx_phy *phy = &dev->phy;
3658 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
3659
3660 if (!phy->gmode)
3661 return 0;
3662
3663 if (has_loopback_gain(phy)) {
3664 int max_lb_gain = phy->max_lb_gain;
3665 u16 extlna;
3666 u16 i;
3667
3668 if (phy->radio_rev == 8)
3669 max_lb_gain += 0x3E;
3670 else
3671 max_lb_gain += 0x26;
3672 if (max_lb_gain >= 0x46) {
3673 extlna = 0x3000;
3674 max_lb_gain -= 0x46;
3675 } else if (max_lb_gain >= 0x3A) {
3676 extlna = 0x1000;
3677 max_lb_gain -= 0x3A;
3678 } else if (max_lb_gain >= 0x2E) {
3679 extlna = 0x2000;
3680 max_lb_gain -= 0x2E;
3681 } else {
3682 extlna = 0;
3683 max_lb_gain -= 0x10;
3684 }
3685
3686 for (i = 0; i < 16; i++) {
3687 max_lb_gain -= (i * 6);
3688 if (max_lb_gain < 6)
3689 break;
3690 }
3691
3692 if ((phy->rev < 7) ||
3693 !(sprom->r1.boardflags_lo & BCM43xx_BFL_EXTLNA)) {
3694 if (phy_register == BCM43xx_PHY_RFOVER) {
3695 return 0x1B3;
3696 } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
3697 extlna |= (i << 8);
3698 switch (lpd) {
3699 case LPD(0, 1, 1):
3700 return 0x0F92;
3701 case LPD(0, 0, 1):
3702 case LPD(1, 0, 1):
3703 return (0x0092 | extlna);
3704 case LPD(1, 0, 0):
3705 return (0x0093 | extlna);
3706 }
3707 assert(0);
3708 }
3709 assert(0);
3710 } else {
3711 if (phy_register == BCM43xx_PHY_RFOVER) {
3712 return 0x9B3;
3713 } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
3714 if (extlna)
3715 extlna |= 0x8000;
3716 extlna |= (i << 8);
3717 switch (lpd) {
3718 case LPD(0, 1, 1):
3719 return 0x8F92;
3720 case LPD(0, 0, 1):
3721 return (0x8092 | extlna);
3722 case LPD(1, 0, 1):
3723 return (0x2092 | extlna);
3724 case LPD(1, 0, 0):
3725 return (0x2093 | extlna);
3726 }
3727 assert(0);
3728 }
3729 assert(0);
3730 }
3731 } else {
3732 if ((phy->rev < 7) ||
3733 !(sprom->r1.boardflags_lo & BCM43xx_BFL_EXTLNA)) {
3734 if (phy_register == BCM43xx_PHY_RFOVER) {
3735 return 0x1B3;
3736 } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
3737 switch (lpd) {
3738 case LPD(0, 1, 1):
3739 return 0x0FB2;
3740 case LPD(0, 0, 1):
3741 return 0x00B2;
3742 case LPD(1, 0, 1):
3743 return 0x30B2;
3744 case LPD(1, 0, 0):
3745 return 0x30B3;
3746 }
3747 assert(0);
3748 }
3749 assert(0);
3750 } else {
3751 if (phy_register == BCM43xx_PHY_RFOVER) {
3752 return 0x9B3;
3753 } else if (phy_register == BCM43xx_PHY_RFOVERVAL) {
3754 switch (lpd) {
3755 case LPD(0, 1, 1):
3756 return 0x8FB2;
3757 case LPD(0, 0, 1):
3758 return 0x80B2;
3759 case LPD(1, 0, 1):
3760 return 0x20B2;
3761 case LPD(1, 0, 0):
3762 return 0x20B3;
3763 }
3764 assert(0);
3765 }
3766 assert(0);
3767 }
3768 }
3769 return 0;
3770 }
3771
3772 struct init2050_saved_values {
3773 /* Core registers */
3774 u16 reg_3EC;
3775 u16 reg_3E6;
3776 u16 reg_3F4;
3777 /* Radio registers */
3778 u16 radio_43;
3779 u16 radio_51;
3780 u16 radio_52;
3781 /* PHY registers */
3782 u16 phy_pgactl;
3783 u16 phy_base_5A;
3784 u16 phy_base_59;
3785 u16 phy_base_58;
3786 u16 phy_base_30;
3787 u16 phy_rfover;
3788 u16 phy_rfoverval;
3789 u16 phy_analogover;
3790 u16 phy_analogoverval;
3791 u16 phy_crs0;
3792 u16 phy_classctl;
3793 u16 phy_lo_mask;
3794 u16 phy_lo_ctl;
3795 u16 phy_syncctl;
3796 };
3797
3798 u16 bcm43xx_radio_init2050(struct bcm43xx_wldev *dev)
3799 {
3800 struct bcm43xx_phy *phy = &dev->phy;
3801 struct init2050_saved_values sav;
3802 u16 rcc;
3803 u16 radio78;
3804 u16 ret;
3805 u16 i, j;
3806 u32 tmp1 = 0, tmp2 = 0;
3807
3808 memset(&sav, 0, sizeof(sav)); /* get rid of "may be used uninitialized..." */
3809
3810 sav.radio_43 = bcm43xx_radio_read16(dev, 0x43);
3811 sav.radio_51 = bcm43xx_radio_read16(dev, 0x51);
3812 sav.radio_52 = bcm43xx_radio_read16(dev, 0x52);
3813 sav.phy_pgactl = bcm43xx_phy_read(dev, BCM43xx_PHY_PGACTL);
3814 sav.phy_base_5A = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x5A));
3815 sav.phy_base_59 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x59));
3816 sav.phy_base_58 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x58));
3817
3818 if (phy->type == BCM43xx_PHYTYPE_B) {
3819 sav.phy_base_30 = bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x30));
3820 sav.reg_3EC = bcm43xx_read16(dev, 0x3EC);
3821
3822 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), 0xFF);
3823 bcm43xx_write16(dev, 0x3EC, 0x3F3F);
3824 } else if (phy->gmode || phy->rev >= 2) {
3825 sav.phy_rfover = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVER);
3826 sav.phy_rfoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_RFOVERVAL);
3827 sav.phy_analogover = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER);
3828 sav.phy_analogoverval = bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL);
3829 sav.phy_crs0 = bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0);
3830 sav.phy_classctl = bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL);
3831
3832 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER,
3833 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVER)
3834 | 0x0003);
3835 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL,
3836 bcm43xx_phy_read(dev, BCM43xx_PHY_ANALOGOVERVAL)
3837 & 0xFFFC);
3838 bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0,
3839 bcm43xx_phy_read(dev, BCM43xx_PHY_CRS0)
3840 & 0x7FFF);
3841 bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL,
3842 bcm43xx_phy_read(dev, BCM43xx_PHY_CLASSCTL)
3843 & 0xFFFC);
3844 if (has_loopback_gain(phy)) {
3845 sav.phy_lo_mask = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_MASK);
3846 sav.phy_lo_ctl = bcm43xx_phy_read(dev, BCM43xx_PHY_LO_CTL);
3847
3848 if (phy->rev >= 3)
3849 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0xC020);
3850 else
3851 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, 0x8020);
3852 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, 0);
3853 }
3854
3855 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3856 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3857 LPD(0, 1, 1)));
3858 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER,
3859 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVER, 0));
3860 }
3861 bcm43xx_write16(dev, 0x3E2, bcm43xx_read16(dev, 0x3E2) | 0x8000);
3862
3863 sav.phy_syncctl = bcm43xx_phy_read(dev, BCM43xx_PHY_SYNCCTL);
3864 bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL,
3865 bcm43xx_phy_read(dev, BCM43xx_PHY_SYNCCTL)
3866 & 0xFF7F);
3867 sav.reg_3E6 = bcm43xx_read16(dev, 0x3E6);
3868 sav.reg_3F4 = bcm43xx_read16(dev, 0x3F4);
3869
3870 if (phy->analog == 0) {
3871 bcm43xx_write16(dev, 0x03E6, 0x0122);
3872 } else {
3873 if (phy->analog >= 2) {
3874 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x03),
3875 (bcm43xx_phy_read(dev, BCM43xx_PHY_BASE(0x03))
3876 & 0xFFBF) | 0x40);
3877 }
3878 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
3879 (bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT) | 0x2000));
3880 }
3881
3882 rcc = bcm43xx_radio_core_calibration_value(dev);
3883
3884 if (phy->type == BCM43xx_PHYTYPE_B)
3885 bcm43xx_radio_write16(dev, 0x78, 0x26);
3886 if (phy->gmode || phy->rev >= 2) {
3887 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3888 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3889 LPD(0, 1, 1)));
3890 }
3891 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xBFAF);
3892 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x2B), 0x1403);
3893 if (phy->gmode || phy->rev >= 2) {
3894 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3895 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3896 LPD(0, 0, 1)));
3897 }
3898 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xBFA0);
3899 bcm43xx_radio_write16(dev, 0x51,
3900 bcm43xx_radio_read16(dev, 0x51)
3901 | 0x0004);
3902 if (phy->radio_rev == 8) {
3903 bcm43xx_radio_write16(dev, 0x43, 0x1F);
3904 } else {
3905 bcm43xx_radio_write16(dev, 0x52, 0);
3906 bcm43xx_radio_write16(dev, 0x43,
3907 (bcm43xx_radio_read16(dev, 0x43)
3908 & 0xFFF0) | 0x0009);
3909 }
3910 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
3911
3912 for (i = 0; i < 16; i++) {
3913 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), 0x0480);
3914 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), 0xC810);
3915 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0x000D);
3916 if (phy->gmode || phy->rev >= 2) {
3917 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3918 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3919 LPD(1, 0, 1)));
3920 }
3921 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
3922 udelay(10);
3923 if (phy->gmode || phy->rev >= 2) {
3924 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3925 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3926 LPD(1, 0, 1)));
3927 }
3928 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xEFB0);
3929 udelay(10);
3930 if (phy->gmode || phy->rev >= 2) {
3931 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3932 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3933 LPD(1, 0, 0)));
3934 }
3935 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xFFF0);
3936 udelay(20);
3937 tmp1 += bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
3938 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
3939 if (phy->gmode || phy->rev >= 2) {
3940 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3941 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3942 LPD(1, 0, 1)));
3943 }
3944 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
3945 }
3946 udelay(10);
3947
3948 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
3949 tmp1++;
3950 tmp1 >>= 9;
3951
3952 for (i = 0; i < 16; i++) {
3953 radio78 = ((flip_4bit(i) << 1) | 0x20);
3954 bcm43xx_radio_write16(dev, 0x78, radio78);
3955 udelay(10);
3956 for (j = 0; j < 16; j++) {
3957 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), 0x0D80);
3958 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), 0xC810);
3959 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0x000D);
3960 if (phy->gmode || phy->rev >= 2) {
3961 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3962 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3963 LPD(1, 0, 1)));
3964 }
3965 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
3966 udelay(10);
3967 if (phy->gmode || phy->rev >= 2) {
3968 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3969 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3970 LPD(1, 0, 1)));
3971 }
3972 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xEFB0);
3973 udelay(10);
3974 if (phy->gmode || phy->rev >= 2) {
3975 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3976 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3977 LPD(1, 0, 0)));
3978 }
3979 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xFFF0);
3980 udelay(10);
3981 tmp2 += bcm43xx_phy_read(dev, BCM43xx_PHY_LO_LEAKAGE);
3982 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), 0);
3983 if (phy->gmode || phy->rev >= 2) {
3984 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL,
3985 radio2050_rfover_val(dev, BCM43xx_PHY_RFOVERVAL,
3986 LPD(1, 0, 1)));
3987 }
3988 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, 0xAFB0);
3989 }
3990 tmp2++;
3991 tmp2 >>= 8;
3992 if (tmp1 < tmp2)
3993 break;
3994 }
3995
3996 /* Restore the registers */
3997 bcm43xx_phy_write(dev, BCM43xx_PHY_PGACTL, sav.phy_pgactl);
3998 bcm43xx_radio_write16(dev, 0x51, sav.radio_51);
3999 bcm43xx_radio_write16(dev, 0x52, sav.radio_52);
4000 bcm43xx_radio_write16(dev, 0x43, sav.radio_43);
4001 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x5A), sav.phy_base_5A);
4002 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x59), sav.phy_base_59);
4003 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x58), sav.phy_base_58);
4004 bcm43xx_write16(dev, 0x3E6, sav.reg_3E6);
4005 if (phy->analog != 0)
4006 bcm43xx_write16(dev, 0x3F4, sav.reg_3F4);
4007 bcm43xx_phy_write(dev, BCM43xx_PHY_SYNCCTL, sav.phy_syncctl);
4008 bcm43xx_synth_pu_workaround(dev, phy->channel);
4009 if (phy->type == BCM43xx_PHYTYPE_B) {
4010 bcm43xx_phy_write(dev, BCM43xx_PHY_BASE(0x30), sav.phy_base_30);
4011 bcm43xx_write16(dev, 0x3EC, sav.reg_3EC);
4012 } else if (phy->gmode) {
4013 bcm43xx_write16(dev, BCM43xx_MMIO_PHY_RADIO,
4014 bcm43xx_read16(dev, BCM43xx_MMIO_PHY_RADIO)
4015 & 0x7FFF);
4016 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVER, sav.phy_rfover);
4017 bcm43xx_phy_write(dev, BCM43xx_PHY_RFOVERVAL, sav.phy_rfoverval);
4018 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVER, sav.phy_analogover);
4019 bcm43xx_phy_write(dev, BCM43xx_PHY_ANALOGOVERVAL, sav.phy_analogoverval);
4020 bcm43xx_phy_write(dev, BCM43xx_PHY_CRS0, sav.phy_crs0);
4021 bcm43xx_phy_write(dev, BCM43xx_PHY_CLASSCTL, sav.phy_classctl);
4022 if (has_loopback_gain(phy)) {
4023 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_MASK, sav.phy_lo_mask);
4024 bcm43xx_phy_write(dev, BCM43xx_PHY_LO_CTL, sav.phy_lo_ctl);
4025 }
4026 }
4027 if (i > 15)
4028 ret = radio78;
4029 else
4030 ret = rcc;
4031
4032 return ret;
4033 }
4034
4035 void bcm43xx_radio_init2060(struct bcm43xx_wldev *dev)
4036 {
4037 int err;
4038
4039 bcm43xx_radio_write16(dev, 0x0004, 0x00C0);
4040 bcm43xx_radio_write16(dev, 0x0005, 0x0008);
4041 bcm43xx_radio_write16(dev, 0x0009, 0x0040);
4042 bcm43xx_radio_write16(dev, 0x0005, 0x00AA);
4043 bcm43xx_radio_write16(dev, 0x0032, 0x008F);
4044 bcm43xx_radio_write16(dev, 0x0006, 0x008F);
4045 bcm43xx_radio_write16(dev, 0x0034, 0x008F);
4046 bcm43xx_radio_write16(dev, 0x002C, 0x0007);
4047 bcm43xx_radio_write16(dev, 0x0082, 0x0080);
4048 bcm43xx_radio_write16(dev, 0x0080, 0x0000);
4049 bcm43xx_radio_write16(dev, 0x003F, 0x00DA);
4050 bcm43xx_radio_write16(dev, 0x0005, bcm43xx_radio_read16(dev, 0x0005) & ~0x0008);
4051 bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0010);
4052 bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0020);
4053 bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0020);
4054 msleep(1); /* delay 400usec */
4055
4056 bcm43xx_radio_write16(dev, 0x0081, (bcm43xx_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
4057 msleep(1); /* delay 400usec */
4058
4059 bcm43xx_radio_write16(dev, 0x0005, (bcm43xx_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
4060 bcm43xx_radio_write16(dev, 0x0085, bcm43xx_radio_read16(dev, 0x0085) & ~0x0010);
4061 bcm43xx_radio_write16(dev, 0x0005, bcm43xx_radio_read16(dev, 0x0005) & ~0x0008);
4062 bcm43xx_radio_write16(dev, 0x0081, bcm43xx_radio_read16(dev, 0x0081) & ~0x0040);
4063 bcm43xx_radio_write16(dev, 0x0081, (bcm43xx_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
4064 bcm43xx_radio_write16(dev, 0x0005, (bcm43xx_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
4065 bcm43xx_phy_write(dev, 0x0063, 0xDDC6);
4066 bcm43xx_phy_write(dev, 0x0069, 0x07BE);
4067 bcm43xx_phy_write(dev, 0x006A, 0x0000);
4068
4069 err = bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_A, 0);
4070 assert(err == 0);
4071
4072 msleep(1);
4073 }
4074
4075 static inline
4076 u16 freq_r3A_value(u16 frequency)
4077 {
4078 u16 value;
4079
4080 if (frequency < 5091)
4081 value = 0x0040;
4082 else if (frequency < 5321)
4083 value = 0x0000;
4084 else if (frequency < 5806)
4085 value = 0x0080;
4086 else
4087 value = 0x0040;
4088
4089 return value;
4090 }
4091
4092 void bcm43xx_radio_set_tx_iq(struct bcm43xx_wldev *dev)
4093 {
4094 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
4095 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
4096 u16 tmp = bcm43xx_radio_read16(dev, 0x001E);
4097 int i, j;
4098
4099 for (i = 0; i < 5; i++) {
4100 for (j = 0; j < 5; j++) {
4101 if (tmp == (data_high[i] << 4 | data_low[j])) {
4102 bcm43xx_phy_write(dev, 0x0069, (i - j) << 8 | 0x00C0);
4103 return;
4104 }
4105 }
4106 }
4107 }
4108
4109 int bcm43xx_radio_selectchannel(struct bcm43xx_wldev *dev,
4110 u8 channel,
4111 int synthetic_pu_workaround)
4112 {
4113 struct bcm43xx_phy *phy = &dev->phy;
4114 u16 r8, tmp;
4115 u16 freq;
4116 u16 channelcookie;
4117
4118 /* First we set the channel radio code to prevent the
4119 * firmware from sending ghost packets.
4120 */
4121 channelcookie = channel;
4122 if (phy->type == BCM43xx_PHYTYPE_A)
4123 channelcookie |= 0x100;
4124 bcm43xx_shm_write16(dev, BCM43xx_SHM_SHARED,
4125 BCM43xx_SHM_SH_CHAN, channelcookie);
4126
4127 if (phy->type == BCM43xx_PHYTYPE_A) {
4128 if (channel > 200)
4129 return -EINVAL;
4130 freq = channel2freq_a(channel);
4131
4132 r8 = bcm43xx_radio_read16(dev, 0x0008);
4133 bcm43xx_write16(dev, 0x03F0, freq);
4134 bcm43xx_radio_write16(dev, 0x0008, r8);
4135
4136 TODO();//TODO: write max channel TX power? to Radio 0x2D
4137 tmp = bcm43xx_radio_read16(dev, 0x002E);
4138 tmp &= 0x0080;
4139 TODO();//TODO: OR tmp with the Power out estimation for this channel?
4140 bcm43xx_radio_write16(dev, 0x002E, tmp);
4141
4142 if (freq >= 4920 && freq <= 5500) {
4143 /*
4144 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
4145 * = (freq * 0.025862069
4146 */
4147 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
4148 }
4149 bcm43xx_radio_write16(dev, 0x0007, (r8 << 4) | r8);
4150 bcm43xx_radio_write16(dev, 0x0020, (r8 << 4) | r8);
4151 bcm43xx_radio_write16(dev, 0x0021, (r8 << 4) | r8);
4152 bcm43xx_radio_write16(dev, 0x0022,
4153 (bcm43xx_radio_read16(dev, 0x0022)
4154 & 0x000F) | (r8 << 4));
4155 bcm43xx_radio_write16(dev, 0x002A, (r8 << 4));
4156 bcm43xx_radio_write16(dev, 0x002B, (r8 << 4));
4157 bcm43xx_radio_write16(dev, 0x0008,
4158 (bcm43xx_radio_read16(dev, 0x0008)
4159 & 0x00F0) | (r8 << 4));
4160 bcm43xx_radio_write16(dev, 0x0029,
4161 (bcm43xx_radio_read16(dev, 0x0029)
4162 & 0xFF0F) | 0x00B0);
4163 bcm43xx_radio_write16(dev, 0x0035, 0x00AA);
4164 bcm43xx_radio_write16(dev, 0x0036, 0x0085);
4165 bcm43xx_radio_write16(dev, 0x003A,
4166 (bcm43xx_radio_read16(dev, 0x003A)
4167 & 0xFF20) | freq_r3A_value(freq));
4168 bcm43xx_radio_write16(dev, 0x003D,
4169 bcm43xx_radio_read16(dev, 0x003D) & 0x00FF);
4170 bcm43xx_radio_write16(dev, 0x0081,
4171 (bcm43xx_radio_read16(dev, 0x0081)
4172 & 0xFF7F) | 0x0080);
4173 bcm43xx_radio_write16(dev, 0x0035,
4174 bcm43xx_radio_read16(dev, 0x0035) & 0xFFEF);
4175 bcm43xx_radio_write16(dev, 0x0035,
4176 (bcm43xx_radio_read16(dev, 0x0035)
4177 & 0xFFEF) | 0x0010);
4178 bcm43xx_radio_set_tx_iq(dev);
4179 TODO(); //TODO: TSSI2dbm workaround
4180 bcm43xx_phy_xmitpower(dev);//FIXME correct?
4181 } else {
4182 if ((channel < 1) || (channel > 14))
4183 return -EINVAL;
4184
4185 if (synthetic_pu_workaround)
4186 bcm43xx_synth_pu_workaround(dev, channel);
4187
4188 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL,
4189 channel2freq_bg(channel));
4190
4191 if (channel == 14) {
4192 if (dev->dev->bus->sprom.r1.country_code == SSB_SPROM1CCODE_JAPAN)
4193 bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) & ~BCM43xx_HF_ACPR);
4194 else
4195 bcm43xx_hf_write(dev, bcm43xx_hf_read(dev) | BCM43xx_HF_ACPR);
4196 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
4197 bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT)
4198 | (1 << 11));
4199 } else {
4200 bcm43xx_write16(dev, BCM43xx_MMIO_CHANNEL_EXT,
4201 bcm43xx_read16(dev, BCM43xx_MMIO_CHANNEL_EXT)
4202 & 0xF7BF);
4203 }
4204 }
4205
4206 phy->channel = channel;
4207 /* Wait for the radio to tune to the channel and stabilize. */
4208 msleep(8);
4209
4210 return 0;
4211 }
4212
4213 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
4214 static u16 bcm43xx_get_txgain_base_band(u16 txpower)
4215 {
4216 u16 ret;
4217
4218 assert(txpower <= 63);
4219
4220 if (txpower >= 54)
4221 ret = 2;
4222 else if (txpower >= 49)
4223 ret = 4;
4224 else if (txpower >= 44)
4225 ret = 5;
4226 else
4227 ret = 6;
4228
4229 return ret;
4230 }
4231
4232 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
4233 static u16 bcm43xx_get_txgain_freq_power_amp(u16 txpower)
4234 {
4235 u16 ret;
4236
4237 assert(txpower <= 63);
4238
4239 if (txpower >= 32)
4240 ret = 0;
4241 else if (txpower >= 25)
4242 ret = 1;
4243 else if (txpower >= 20)
4244 ret = 2;
4245 else if (txpower >= 12)
4246 ret = 3;
4247 else
4248 ret = 4;
4249
4250 return ret;
4251 }
4252
4253 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
4254 static u16 bcm43xx_get_txgain_dac(u16 txpower)
4255 {
4256 u16 ret;
4257
4258 assert(txpower <= 63);
4259
4260 if (txpower >= 54)
4261 ret = txpower - 53;
4262 else if (txpower >= 49)
4263 ret = txpower - 42;
4264 else if (txpower >= 44)
4265 ret = txpower - 37;
4266 else if (txpower >= 32)
4267 ret = txpower - 32;
4268 else if (txpower >= 25)
4269 ret = txpower - 20;
4270 else if (txpower >= 20)
4271 ret = txpower - 13;
4272 else if (txpower >= 12)
4273 ret = txpower - 8;
4274 else
4275 ret = txpower;
4276
4277 return ret;
4278 }
4279
4280 static void bcm43xx_radio_set_txpower_a(struct bcm43xx_wldev *dev, u16 txpower)
4281 {
4282 struct bcm43xx_phy *phy = &dev->phy;
4283 u16 pamp, base, dac, t;
4284
4285 txpower = limit_value(txpower, 0, 63);
4286
4287 pamp = bcm43xx_get_txgain_freq_power_amp(txpower);
4288 pamp <<= 5;
4289 pamp &= 0x00E0;
4290 bcm43xx_phy_write(dev, 0x0019, pamp);
4291
4292 base = bcm43xx_get_txgain_base_band(txpower);
4293 base &= 0x000F;
4294 bcm43xx_phy_write(dev, 0x0017, base | 0x0020);
4295
4296 t = bcm43xx_ofdmtab_read16(dev, 0x3000, 1);
4297 t &= 0x0007;
4298
4299 dac = bcm43xx_get_txgain_dac(txpower);
4300 dac <<= 3;
4301 dac |= t;
4302
4303 bcm43xx_ofdmtab_write16(dev, 0x3000, 1, dac);
4304
4305 phy->txpwr_offset = txpower;
4306
4307 TODO();
4308 //TODO: FuncPlaceholder (Adjust BB loft cancel)
4309 }
4310
4311 void bcm43xx_radio_turn_on(struct bcm43xx_wldev *dev)
4312 {
4313 struct bcm43xx_phy *phy = &dev->phy;
4314 int err;
4315
4316 might_sleep();
4317
4318 if (phy->radio_on)
4319 return;
4320
4321 switch (phy->type) {
4322 case BCM43xx_PHYTYPE_A:
4323 bcm43xx_radio_write16(dev, 0x0004, 0x00C0);
4324 bcm43xx_radio_write16(dev, 0x0005, 0x0008);
4325 bcm43xx_phy_write(dev, 0x0010, bcm43xx_phy_read(dev, 0x0010) & 0xFFF7);
4326 bcm43xx_phy_write(dev, 0x0011, bcm43xx_phy_read(dev, 0x0011) & 0xFFF7);
4327 bcm43xx_radio_init2060(dev);
4328 break;
4329 case BCM43xx_PHYTYPE_B:
4330 case BCM43xx_PHYTYPE_G:
4331 bcm43xx_phy_write(dev, 0x0015, 0x8000);
4332 bcm43xx_phy_write(dev, 0x0015, 0xCC00);
4333 bcm43xx_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
4334 err = bcm43xx_radio_selectchannel(dev, BCM43xx_DEFAULT_CHANNEL_BG, 1);
4335 assert(err == 0);
4336 break;
4337 default:
4338 assert(0);
4339 }
4340 phy->radio_on = 1;
4341 dprintk(KERN_INFO PFX "Radio turned on\n");
4342 }
4343
4344 void bcm43xx_radio_turn_off(struct bcm43xx_wldev *dev)
4345 {
4346 struct bcm43xx_phy *phy = &dev->phy;
4347
4348 if (phy->type == BCM43xx_PHYTYPE_A) {
4349 bcm43xx_radio_write16(dev, 0x0004, 0x00FF);
4350 bcm43xx_radio_write16(dev, 0x0005, 0x00FB);
4351 bcm43xx_phy_write(dev, 0x0010, bcm43xx_phy_read(dev, 0x0010) | 0x0008);
4352 bcm43xx_phy_write(dev, 0x0011, bcm43xx_phy_read(dev, 0x0011) | 0x0008);
4353 }
4354 if (phy->type == BCM43xx_PHYTYPE_G && dev->dev->id.revision >= 5) {
4355 bcm43xx_phy_write(dev, 0x0811, bcm43xx_phy_read(dev, 0x0811) | 0x008C);
4356 bcm43xx_phy_write(dev, 0x0812, bcm43xx_phy_read(dev, 0x0812) & 0xFF73);
4357 } else
4358 bcm43xx_phy_write(dev, 0x0015, 0xAA00);
4359 phy->radio_on = 0;
4360 dprintk(KERN_INFO PFX "Radio turned off\n");
4361 }
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