package/bcm43xx-mac80211/src/bcm43xx/bcm43xx_phy.h

   1 #ifndef BCM43xx_PHY_H_
   2 #define BCM43xx_PHY_H_
   3
   4 #include <linux/types.h>
   5
   6 struct bcm43xx_wldev;
   7
   8
   9 /*** PHY Registers ***/
  10
  11 /* Routing */
  12 #define BCM43xx_PHYROUTE_OFDM_GPHY      0x400
  13 #define BCM43xx_PHYROUTE_EXT_GPHY       0x800
  14
  15 /* Base registers. */
  16 #define BCM43xx_PHY_BASE(reg)   (reg)
  17 /* OFDM (A) registers of a G-PHY */
  18 #define BCM43xx_PHY_OFDM(reg)   ((reg) | BCM43xx_PHYROUTE_OFDM_GPHY)
  19 /* Extended G-PHY registers */
  20 #define BCM43xx_PHY_EXTG(reg)   ((reg) | BCM43xx_PHYROUTE_EXT_GPHY)
  21
  22
  23 /* OFDM (A) PHY Registers */
  24 #define BCM43xx_PHY_VERSION_OFDM        BCM43xx_PHY_OFDM(0x00)  /* Versioning register for A-PHY */
  25 #define BCM43xx_PHY_BBANDCFG            BCM43xx_PHY_OFDM(0x01)  /* Baseband config */
  26 #define  BCM43xx_PHY_BBANDCFG_RXANT     0x180                   /* RX Antenna selection */
  27 #define  BCM43xx_PHY_BBANDCFG_RXANT_SHIFT       7
  28 #define BCM43xx_PHY_PWRDOWN             BCM43xx_PHY_OFDM(0x03)  /* Powerdown */
  29 #define BCM43xx_PHY_CRSTHRES1           BCM43xx_PHY_OFDM(0x06)  /* CRS Threshold 1 */
  30 #define BCM43xx_PHY_LNAHPFCTL           BCM43xx_PHY_OFDM(0x1C)  /* LNA/HPF control */
  31 #define BCM43xx_PHY_ADIVRELATED         BCM43xx_PHY_OFDM(0x27)  /* FIXME rename */
  32 #define BCM43xx_PHY_CRS0                BCM43xx_PHY_OFDM(0x29)
  33 #define BCM43xx_PHY_ANTDWELL            BCM43xx_PHY_OFDM(0x2B)  /* Antenna dwell */
  34 #define  BCM43xx_PHY_ANTDWELL_AUTODIV1  0x0100                  /* Automatic RX diversity start antenna */
  35 #define BCM43xx_PHY_ENCORE              BCM43xx_PHY_OFDM(0x49)  /* "Encore" (RangeMax / BroadRange) */
  36 #define  BCM43xx_PHY_ENCORE_EN          0x0200                  /* Encore enable */
  37 #define BCM43xx_PHY_LMS                 BCM43xx_PHY_OFDM(0x55)
  38 #define BCM43xx_PHY_OFDM61              BCM43xx_PHY_OFDM(0x61)  /* FIXME rename */
  39 #define  BCM43xx_PHY_OFDM61_10          0x0010                  /* FIXME rename */
  40 #define BCM43xx_PHY_IQBAL               BCM43xx_PHY_OFDM(0x69)  /* I/Q balance */
  41 #define BCM43xx_PHY_OTABLECTL           BCM43xx_PHY_OFDM(0x72)  /* OFDM table control (see below) */
  42 #define  BCM43xx_PHY_OTABLEOFF          0x03FF                  /* OFDM table offset (see below) */
  43 #define  BCM43xx_PHY_OTABLENR           0xFC00                  /* OFDM table number (see below) */
  44 #define  BCM43xx_PHY_OTABLENR_SHIFT     10
  45 #define BCM43xx_PHY_OTABLEI             BCM43xx_PHY_OFDM(0x73)  /* OFDM table data I */
  46 #define BCM43xx_PHY_OTABLEQ             BCM43xx_PHY_OFDM(0x74)  /* OFDM table data Q */
  47 #define BCM43xx_PHY_HPWR_TSSICTL        BCM43xx_PHY_OFDM(0x78)  /* Hardware power TSSI control */
  48 #define BCM43xx_PHY_NRSSITHRES          BCM43xx_PHY_OFDM(0x8A)  /* NRSSI threshold */
  49 #define BCM43xx_PHY_ANTWRSETT           BCM43xx_PHY_OFDM(0x8C)  /* Antenna WR settle */
  50 #define  BCM43xx_PHY_ANTWRSETT_ARXDIV   0x2000                  /* Automatic RX diversity enabled */
  51 #define BCM43xx_PHY_CLIPPWRDOWNT        BCM43xx_PHY_OFDM(0x93)  /* Clip powerdown threshold */
  52 #define BCM43xx_PHY_OFDM9B              BCM43xx_PHY_OFDM(0x9B)  /* FIXME rename */
  53 #define BCM43xx_PHY_N1P1GAIN            BCM43xx_PHY_OFDM(0xA0)
  54 #define BCM43xx_PHY_P1P2GAIN            BCM43xx_PHY_OFDM(0xA1)
  55 #define BCM43xx_PHY_N1N2GAIN            BCM43xx_PHY_OFDM(0xA2)
  56 #define BCM43xx_PHY_CLIPTHRES           BCM43xx_PHY_OFDM(0xA3)
  57 #define BCM43xx_PHY_CLIPN1P2THRES       BCM43xx_PHY_OFDM(0xA4)
  58 #define BCM43xx_PHY_DIVSRCHIDX          BCM43xx_PHY_OFDM(0xA8)  /* Divider search gain/index */
  59 #define BCM43xx_PHY_CLIPP2THRES         BCM43xx_PHY_OFDM(0xA9)
  60 #define BCM43xx_PHY_CLIPP3THRES         BCM43xx_PHY_OFDM(0xAA)
  61 #define BCM43xx_PHY_DIVP1P2GAIN         BCM43xx_PHY_OFDM(0xAB)
  62 #define BCM43xx_PHY_DIVSRCHGAINBACK     BCM43xx_PHY_OFDM(0xAD)  /* Divider search gain back */
  63 #define BCM43xx_PHY_DIVSRCHGAINCHNG     BCM43xx_PHY_OFDM(0xAE)  /* Divider search gain change */
  64 #define BCM43xx_PHY_CRSTHRES1_R1        BCM43xx_PHY_OFDM(0xC0)  /* CRS Threshold 1 (rev 1 only) */
  65 #define BCM43xx_PHY_CRSTHRES2_R1        BCM43xx_PHY_OFDM(0xC1)  /* CRS Threshold 2 (rev 1 only) */
  66 #define BCM43xx_PHY_TSSIP_LTBASE        BCM43xx_PHY_OFDM(0x380) /* TSSI power lookup table base */
  67 #define BCM43xx_PHY_DC_LTBASE           BCM43xx_PHY_OFDM(0x3A0) /* DC lookup table base */
  68 #define BCM43xx_PHY_GAIN_LTBASE         BCM43xx_PHY_OFDM(0x3C0) /* Gain lookup table base */
  69
  70 /* CCK (B) PHY Registers */
  71 #define BCM43xx_PHY_VERSION_CCK         BCM43xx_PHY_BASE(0x00)  /* Versioning register for B-PHY */
  72 #define BCM43xx_PHY_CCKBBANDCFG         BCM43xx_PHY_BASE(0x01)  /* Contains antenna 0/1 control bit */
  73 #define BCM43xx_PHY_PGACTL              BCM43xx_PHY_BASE(0x15)  /* PGA control */
  74 #define  BCM43xx_PHY_PGACTL_LPF         0x1000                  /* Low pass filter (?) */
  75 #define  BCM43xx_PHY_PGACTL_LOWBANDW    0x0040                  /* Low bandwidth flag */
  76 #define  BCM43xx_PHY_PGACTL_UNKNOWN     0xEFA0
  77 #define BCM43xx_PHY_FBCTL1              BCM43xx_PHY_BASE(0x18)  /* Frequency bandwidth control 1 */
  78 #define BCM43xx_PHY_ITSSI               BCM43xx_PHY_BASE(0x29)  /* Idle TSSI */
  79 #define BCM43xx_PHY_LO_LEAKAGE          BCM43xx_PHY_BASE(0x2D)  /* Measured LO leakage */
  80 #define BCM43xx_PHY_ENERGY              BCM43xx_PHY_BASE(0x33)  /* Energy */
  81 #define BCM43xx_PHY_SYNCCTL             BCM43xx_PHY_BASE(0x35)
  82 #define BCM43xx_PHY_FBCTL2              BCM43xx_PHY_BASE(0x38)  /* Frequency bandwidth control 2 */
  83 #define BCM43xx_PHY_DACCTL              BCM43xx_PHY_BASE(0x60)  /* DAC control */
  84 #define BCM43xx_PHY_RCCALOVER           BCM43xx_PHY_BASE(0x78)  /* RC calibration override */
  85
  86 /* Extended G-PHY Registers */
  87 #define BCM43xx_PHY_CLASSCTL            BCM43xx_PHY_EXTG(0x02)  /* Classify control */
  88 #define BCM43xx_PHY_GTABCTL             BCM43xx_PHY_EXTG(0x03)  /* G-PHY table control (see below) */
  89 #define  BCM43xx_PHY_GTABOFF            0x03FF                  /* G-PHY table offset (see below) */
  90 #define  BCM43xx_PHY_GTABNR             0xFC00                  /* G-PHY table number (see below) */
  91 #define  BCM43xx_PHY_GTABNR_SHIFT       10
  92 #define BCM43xx_PHY_GTABDATA            BCM43xx_PHY_EXTG(0x04)  /* G-PHY table data */
  93 #define BCM43xx_PHY_LO_MASK             BCM43xx_PHY_EXTG(0x0F)  /* Local Oscillator control mask */
  94 #define BCM43xx_PHY_LO_CTL              BCM43xx_PHY_EXTG(0x10)  /* Local Oscillator control */
  95 #define BCM43xx_PHY_RFOVER              BCM43xx_PHY_EXTG(0x11)  /* RF override */
  96 #define BCM43xx_PHY_RFOVERVAL           BCM43xx_PHY_EXTG(0x12)  /* RF override value */
  97 #define  BCM43xx_PHY_RFOVERVAL_EXTLNA   0x8000
  98 #define  BCM43xx_PHY_RFOVERVAL_LNA      0x7000
  99 #define  BCM43xx_PHY_RFOVERVAL_LNA_SHIFT        12
 100 #define  BCM43xx_PHY_RFOVERVAL_PGA      0x0F00
 101 #define  BCM43xx_PHY_RFOVERVAL_PGA_SHIFT        8
 102 #define  BCM43xx_PHY_RFOVERVAL_UNK      0x0010 /* Unknown, always set. */
 103 #define  BCM43xx_PHY_RFOVERVAL_TRSWRX   0x00E0
 104 #define  BCM43xx_PHY_RFOVERVAL_BW       0x0003 /* Bandwidth flags */
 105 #define   BCM43xx_PHY_RFOVERVAL_BW_LPF  0x0001 /* Low Pass Filter */
 106 #define   BCM43xx_PHY_RFOVERVAL_BW_LBW  0x0002 /* Low Bandwidth (when set), high when unset */
 107 #define BCM43xx_PHY_ANALOGOVER          BCM43xx_PHY_EXTG(0x14)  /* Analog override */
 108 #define BCM43xx_PHY_ANALOGOVERVAL       BCM43xx_PHY_EXTG(0x15)  /* Analog override value */
 109
 110
 111
 112 /*** OFDM table numbers ***/
 113 #define BCM43xx_OFDMTAB(number, offset) (((number) << BCM43xx_PHY_OTABLENR_SHIFT) | (offset))
 114 #define BCM43xx_OFDMTAB_AGC1            BCM43xx_OFDMTAB(0x00, 0)
 115 #define BCM43xx_OFDMTAB_GAIN0           BCM43xx_OFDMTAB(0x00, 0)
 116 #define BCM43xx_OFDMTAB_GAINX           BCM43xx_OFDMTAB(0x01, 0)        //TODO rename
 117 #define BCM43xx_OFDMTAB_GAIN1           BCM43xx_OFDMTAB(0x01, 4)
 118 #define BCM43xx_OFDMTAB_AGC3            BCM43xx_OFDMTAB(0x02, 0)
 119 #define BCM43xx_OFDMTAB_GAIN2           BCM43xx_OFDMTAB(0x02, 3)
 120 #define BCM43xx_OFDMTAB_LNAHPFGAIN1     BCM43xx_OFDMTAB(0x03, 0)
 121 #define BCM43xx_OFDMTAB_WRSSI           BCM43xx_OFDMTAB(0x04, 0)
 122 #define BCM43xx_OFDMTAB_LNAHPFGAIN2     BCM43xx_OFDMTAB(0x04, 0)
 123 #define BCM43xx_OFDMTAB_NOISESCALE      BCM43xx_OFDMTAB(0x05, 0)
 124 #define BCM43xx_OFDMTAB_AGC2            BCM43xx_OFDMTAB(0x06, 0)
 125 #define BCM43xx_OFDMTAB_ROTOR           BCM43xx_OFDMTAB(0x08, 0)
 126 #define BCM43xx_OFDMTAB_ADVRETARD       BCM43xx_OFDMTAB(0x09, 0)
 127 #define BCM43xx_OFDMTAB_DAC             BCM43xx_OFDMTAB(0x0C, 0)
 128 #define BCM43xx_OFDMTAB_DC              BCM43xx_OFDMTAB(0x0E, 7)
 129 #define BCM43xx_OFDMTAB_PWRDYN2         BCM43xx_OFDMTAB(0x0E, 12)
 130 #define BCM43xx_OFDMTAB_LNAGAIN         BCM43xx_OFDMTAB(0x0E, 13)
 131 //TODO
 132 #define BCM43xx_OFDMTAB_LPFGAIN         BCM43xx_OFDMTAB(0x0F, 12)
 133 #define BCM43xx_OFDMTAB_RSSI            BCM43xx_OFDMTAB(0x10, 0)
 134 //TODO
 135 #define BCM43xx_OFDMTAB_AGC1_R1         BCM43xx_OFDMTAB(0x13, 0)
 136 #define BCM43xx_OFDMTAB_GAINX_R1        BCM43xx_OFDMTAB(0x14, 0)        //TODO rename
 137 #define BCM43xx_OFDMTAB_MINSIGSQ        BCM43xx_OFDMTAB(0x14, 1)
 138 #define BCM43xx_OFDMTAB_AGC3_R1         BCM43xx_OFDMTAB(0x15, 0)
 139 #define BCM43xx_OFDMTAB_WRSSI_R1        BCM43xx_OFDMTAB(0x15, 4)
 140 #define BCM43xx_OFDMTAB_TSSI            BCM43xx_OFDMTAB(0x15, 0)
 141 #define BCM43xx_OFDMTAB_DACRFPABB       BCM43xx_OFDMTAB(0x16, 0)
 142 #define BCM43xx_OFDMTAB_DACOFF          BCM43xx_OFDMTAB(0x17, 0)
 143 #define BCM43xx_OFDMTAB_DCBIAS          BCM43xx_OFDMTAB(0x18, 0)
 144
 145 u16 bcm43xx_ofdmtab_read16(struct bcm43xx_wldev *dev, u16 table, u16 offset);
 146 void bcm43xx_ofdmtab_write16(struct bcm43xx_wldev *dev, u16 table,
 147                              u16 offset, u16 value);
 148 u32 bcm43xx_ofdmtab_read32(struct bcm43xx_wldev *dev, u16 table, u16 offset);
 149 void bcm43xx_ofdmtab_write32(struct bcm43xx_wldev *dev, u16 table,
 150                              u16 offset, u32 value);
 151
 152
 153 /*** G-PHY table numbers */
 154 #define BCM43xx_GTAB(number, offset)    (((number) << BCM43xx_PHY_GTABNR_SHIFT) | (offset))
 155 #define BCM43xx_GTAB_NRSSI              BCM43xx_GTAB(0x00, 0)
 156 #define BCM43xx_GTAB_TRFEMW             BCM43xx_GTAB(0x0C, 0x120)
 157 #define BCM43xx_GTAB_ORIGTR             BCM43xx_GTAB(0x2E, 0x298)
 158
 159 u16 bcm43xx_gtab_read(struct bcm43xx_wldev *dev, u16 table, u16 offset);        //TODO implement
 160 void bcm43xx_gtab_write(struct bcm43xx_wldev *dev, u16 table,
 161                         u16 offset, u16 value);                                 //TODO implement
 162
 163
 164
 165 #define BCM43xx_DEFAULT_CHANNEL_A       36
 166 #define BCM43xx_DEFAULT_CHANNEL_BG      6
 167
 168 enum {
 169         BCM43xx_ANTENNA0,       /* Antenna 0 */
 170         BCM43xx_ANTENNA1,       /* Antenna 0 */
 171         BCM43xx_ANTENNA_AUTO1,  /* Automatic, starting with antenna 1 */
 172         BCM43xx_ANTENNA_AUTO0,  /* Automatic, starting with antenna 0 */
 173
 174         BCM43xx_ANTENNA_AUTO    = BCM43xx_ANTENNA_AUTO0,
 175         BCM43xx_ANTENNA_DEFAULT = BCM43xx_ANTENNA_AUTO,
 176 };
 177
 178 enum {
 179         BCM43xx_INTERFMODE_NONE,
 180         BCM43xx_INTERFMODE_NONWLAN,
 181         BCM43xx_INTERFMODE_MANUALWLAN,
 182         BCM43xx_INTERFMODE_AUTOWLAN,
 183 };
 184
 185
 186 /* Masks for the different PHY versioning registers. */
 187 #define BCM43xx_PHYVER_ANALOG           0xF000
 188 #define BCM43xx_PHYVER_ANALOG_SHIFT     12
 189 #define BCM43xx_PHYVER_TYPE             0x0F00
 190 #define BCM43xx_PHYVER_TYPE_SHIFT       8
 191 #define BCM43xx_PHYVER_VERSION          0x00FF
 192
 193
 194 void bcm43xx_raw_phy_lock(struct bcm43xx_wldev *dev);
 195 #define bcm43xx_phy_lock(dev, flags) \
 196         do {                                    \
 197                 local_irq_save(flags);          \
 198                 bcm43xx_raw_phy_lock(dev);      \
 199         } while (0)
 200 void bcm43xx_raw_phy_unlock(struct bcm43xx_wldev *dev);
 201 #define bcm43xx_phy_unlock(dev, flags) \
 202         do {                                    \
 203                 bcm43xx_raw_phy_unlock(dev);    \
 204                 local_irq_restore(flags);       \
 205         } while (0)
 206
 207 u16 bcm43xx_phy_read(struct bcm43xx_wldev *dev, u16 offset);
 208 void bcm43xx_phy_write(struct bcm43xx_wldev *dev, u16 offset, u16 val);
 209
 210 int bcm43xx_phy_init_tssi2dbm_table(struct bcm43xx_wldev *dev);
 211
 212 void bcm43xx_phy_early_init(struct bcm43xx_wldev *dev);
 213 int bcm43xx_phy_init(struct bcm43xx_wldev *dev);
 214
 215 void bcm43xx_set_rx_antenna(struct bcm43xx_wldev *dev, int antenna);
 216
 217 void bcm43xx_phy_xmitpower(struct bcm43xx_wldev *dev);
 218 void bcm43xx_gphy_dc_lt_init(struct bcm43xx_wldev *dev);
 219
 220 /* Returns the boolean whether the board has HardwarePowerControl */
 221 #define has_hardware_pctl(phy) \
 222         (((phy)->type == BCM43xx_PHYTYPE_A && (phy)->rev >= 5) ||       \
 223          ((phy)->type == BCM43xx_PHYTYPE_G && (phy)->rev >= 6))
 224 /* Returns the boolean whether "TX Magnification" is enabled. */
 225 #define has_tx_magnification(phy) \
 226         (((phy)->rev >= 2) &&                   \
 227          ((phy)->radio_ver == 0x2050) &&        \
 228          ((phy)->radio_rev == 8))
 229 /* Card uses the loopback gain stuff */
 230 #define has_loopback_gain(phy) \
 231         (((phy)->rev > 1) || ((phy)->gmode))
 232
 233 /* Radio Attenuation (RF Attenuation) */
 234 struct bcm43xx_rfatt {
 235         u8 att;         /* Attenuation value */
 236         u8 with_padmix; /* Flag, PAD Mixer enabled. */
 237 };
 238 struct bcm43xx_rfatt_list {
 239         /* Attenuation values list */
 240         const struct bcm43xx_rfatt *list;
 241         u8 len;
 242         /* Minimum/Maximum attenuation values */
 243         u8 min_val;
 244         u8 max_val;
 245 };
 246
 247 /* Baseband Attenuation */
 248 struct bcm43xx_bbatt {
 249         u8 att;         /* Attenuation value */
 250 };
 251 struct bcm43xx_bbatt_list {
 252         /* Attenuation values list */
 253         const struct bcm43xx_bbatt *list;
 254         u8 len;
 255         /* Minimum/Maximum attenuation values */
 256         u8 min_val;
 257         u8 max_val;
 258 };
 259
 260 /* tx_control bits. */
 261 #define BCM43xx_TXCTL_PA3DB     0x40 /* PA Gain 3dB */
 262 #define BCM43xx_TXCTL_PA2DB     0x20 /* PA Gain 2dB */
 263 #define BCM43xx_TXCTL_TXMIX     0x10 /* TX Mixer Gain */
 264
 265 /* Write BasebandAttenuation value to the device. */
 266 void bcm43xx_phy_set_baseband_attenuation(struct bcm43xx_wldev *dev,
 267                                           u16 baseband_attenuation);
 268
 269
 270 extern const u8 bcm43xx_radio_channel_codes_bg[];
 271
 272 void bcm43xx_radio_lock(struct bcm43xx_wldev *dev);
 273 void bcm43xx_radio_unlock(struct bcm43xx_wldev *dev);
 274
 275 u16 bcm43xx_radio_read16(struct bcm43xx_wldev *dev, u16 offset);
 276 void bcm43xx_radio_write16(struct bcm43xx_wldev *dev, u16 offset, u16 val);
 277
 278 u16 bcm43xx_radio_init2050(struct bcm43xx_wldev *dev);
 279 void bcm43xx_radio_init2060(struct bcm43xx_wldev *dev);
 280
 281 void bcm43xx_radio_turn_on(struct bcm43xx_wldev *dev);
 282 void bcm43xx_radio_turn_off(struct bcm43xx_wldev *dev);
 283
 284 int bcm43xx_radio_selectchannel(struct bcm43xx_wldev *dev, u8 channel,
 285                                 int synthetic_pu_workaround);
 286
 287 u8 bcm43xx_radio_aci_detect(struct bcm43xx_wldev *dev, u8 channel);
 288 u8 bcm43xx_radio_aci_scan(struct bcm43xx_wldev *dev);
 289
 290 int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_wldev *dev, int mode);
 291
 292 void bcm43xx_calc_nrssi_slope(struct bcm43xx_wldev *dev);
 293 void bcm43xx_calc_nrssi_threshold(struct bcm43xx_wldev *dev);
 294 s16 bcm43xx_nrssi_hw_read(struct bcm43xx_wldev *dev, u16 offset);
 295 void bcm43xx_nrssi_hw_write(struct bcm43xx_wldev *dev, u16 offset, s16 val);
 296 void bcm43xx_nrssi_hw_update(struct bcm43xx_wldev *dev, u16 val);
 297 void bcm43xx_nrssi_mem_update(struct bcm43xx_wldev *dev);
 298
 299 void bcm43xx_radio_set_tx_iq(struct bcm43xx_wldev *dev);
 300 u16 bcm43xx_radio_calibrationvalue(struct bcm43xx_wldev *dev);
 301
 302 void bcm43xx_put_attenuation_into_ranges(struct bcm43xx_wldev *dev,
 303                                          int *_bbatt, int *_rfatt);
 304
 305 void bcm43xx_set_txpower_g(struct bcm43xx_wldev *dev,
 306                            const struct bcm43xx_bbatt *bbatt,
 307                            const struct bcm43xx_rfatt *rfatt,
 308                            u8 tx_control);
 309
 310 #endif /* BCM43xx_PHY_H_ */