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[s3c24xx] It's to late...
[openwrt.git] / target / linux / s3c24xx / files-2.6.30 / drivers / mfd / glamo / glamo-mci.c
1 /*
2 * linux/drivers/mmc/host/glamo-mmc.c - Glamo MMC driver
3 *
4 * Copyright (C) 2007 Openmoko, Inc, Andy Green <andy@openmoko.com>
5 * Based on S3C MMC driver that was:
6 * Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <tk@maintech.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/mmc/mmc.h>
15 #include <linux/mmc/sd.h>
16 #include <linux/mmc/host.h>
17 #include <linux/platform_device.h>
18 #include <linux/irq.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/workqueue.h>
22 #include <linux/crc7.h>
23 #include <linux/scatterlist.h>
24 #include <linux/io.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/mfd/glamo.h>
27
28 #include "glamo-core.h"
29 #include "glamo-regs.h"
30
31 #define DRIVER_NAME "glamo-mci"
32
33 struct glamo_mci_host {
34 struct glamo_mmc_platform_data *pdata;
35 struct platform_device *pdev;
36 struct glamo_core *core;
37 struct mmc_host *mmc;
38 struct resource *mmio_mem;
39 struct resource *data_mem;
40 void __iomem *mmio_base;
41 u16 __iomem *data_base;
42
43 struct regulator *regulator;
44 struct mmc_request *mrq;
45
46 unsigned int clk_rate;
47
48 unsigned short vdd;
49 char power_mode;
50
51 unsigned char request_counter;
52
53 struct timer_list disable_timer;
54
55 struct work_struct irq_work;
56 struct work_struct read_work;
57
58 unsigned clk_enabled : 1;
59
60 };
61
62 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request* mrq);
63 static void glamo_mci_send_command(struct glamo_mci_host *host,
64 struct mmc_command *cmd);
65
66 /*
67 * Max SD clock rate
68 *
69 * held at /(3 + 1) due to concerns of 100R recommended series resistor
70 * allows 16MHz @ 4-bit --> 8MBytes/sec raw
71 *
72 * you can override this on kernel commandline using
73 *
74 * glamo_mci.sd_max_clk=10000000
75 *
76 * for example
77 */
78
79 static int sd_max_clk = 21000000;
80 module_param(sd_max_clk, int, 0644);
81
82 /*
83 * Slow SD clock rate
84 *
85 * you can override this on kernel commandline using
86 *
87 * glamo_mci.sd_slow_ratio=8
88 *
89 * for example
90 *
91 * platform callback is used to decide effective clock rate, if not
92 * defined then max is used, if defined and returns nonzero, rate is
93 * divided by this factor
94 */
95
96 static int sd_slow_ratio = 8;
97 module_param(sd_slow_ratio, int, 0644);
98
99 /*
100 * Post-power SD clock rate
101 *
102 * you can override this on kernel commandline using
103 *
104 * glamo_mci.sd_post_power_clock=1000000
105 *
106 * for example
107 *
108 * After changing power to card, clock is held at this rate until first bulk
109 * transfer completes
110 */
111
112 static int sd_post_power_clock = 1000000;
113 module_param(sd_post_power_clock, int, 0644);
114
115
116 static inline void glamo_reg_write(struct glamo_mci_host *glamo,
117 u_int16_t reg, u_int16_t val)
118 {
119 writew(val, glamo->mmio_base + reg);
120 }
121
122 static inline u_int16_t glamo_reg_read(struct glamo_mci_host *glamo,
123 u_int16_t reg)
124 {
125 return readw(glamo->mmio_base + reg);
126 }
127
128 static void glamo_reg_set_bit_mask(struct glamo_mci_host *glamo,
129 u_int16_t reg, u_int16_t mask,
130 u_int16_t val)
131 {
132 u_int16_t tmp;
133
134 val &= mask;
135
136 tmp = glamo_reg_read(glamo, reg);
137 tmp &= ~mask;
138 tmp |= val;
139 glamo_reg_write(glamo, reg, tmp);
140 }
141
142 static void glamo_mci_clock_disable(struct glamo_mci_host *host) {
143 if (host->clk_enabled) {
144 glamo_engine_div_disable(host->core, GLAMO_ENGINE_MMC);
145 host->clk_enabled = 0;
146 }
147 }
148
149 static void glamo_mci_clock_enable(struct glamo_mci_host *host) {
150 del_timer_sync(&host->disable_timer);
151
152 if (!host->clk_enabled) {
153 glamo_engine_div_enable(host->core, GLAMO_ENGINE_MMC);
154 host->clk_enabled = 1;
155 }
156 }
157
158 static void glamo_mci_disable_timer(unsigned long data) {
159 struct glamo_mci_host *host = (struct glamo_mci_host *)data;
160 glamo_mci_clock_disable(host);
161 }
162
163
164 static void do_pio_read(struct glamo_mci_host *host, struct mmc_data *data)
165 {
166 struct scatterlist *sg;
167 u16 __iomem *from_ptr = host->data_base;
168 void *sg_pointer;
169
170 dev_dbg(&host->pdev->dev, "pio_read():\n");
171 for (sg = data->sg; sg; sg = sg_next(sg)) {
172 sg_pointer = page_address(sg_page(sg)) + sg->offset;
173
174
175 memcpy(sg_pointer, from_ptr, sg->length);
176 from_ptr += sg->length >> 1;
177
178 data->bytes_xfered += sg->length;
179 }
180
181 dev_dbg(&host->pdev->dev, "pio_read(): "
182 "complete (no more data).\n");
183 }
184
185 static void do_pio_write(struct glamo_mci_host *host, struct mmc_data *data)
186 {
187 struct scatterlist *sg;
188 u16 __iomem *to_ptr = host->data_base;
189 void *sg_pointer;
190
191 dev_dbg(&host->pdev->dev, "pio_write():\n");
192 for (sg = data->sg; sg; sg = sg_next(sg)) {
193 sg_pointer = page_address(sg_page(sg)) + sg->offset;
194
195 data->bytes_xfered += sg->length;
196
197 memcpy(to_ptr, sg_pointer, sg->length);
198 to_ptr += sg->length >> 1;
199 }
200
201 dev_dbg(&host->pdev->dev, "pio_write(): complete\n");
202 }
203
204 static int glamo_mci_set_card_clock(struct glamo_mci_host *host, int freq)
205 {
206 int real_rate = 0;
207
208 if (freq) {
209 glamo_mci_clock_enable(host);
210 real_rate = glamo_engine_reclock(host->core, GLAMO_ENGINE_MMC, freq);
211 } else {
212 glamo_mci_clock_disable(host);
213 }
214
215 return real_rate;
216 }
217
218 static void glamo_mci_request_done(struct glamo_mci_host *host, struct
219 mmc_request *mrq) {
220 mod_timer(&host->disable_timer, jiffies + HZ / 16);
221 mmc_request_done(host->mmc, mrq);
222 }
223
224
225 static void glamo_mci_irq_worker(struct work_struct *work)
226 {
227 struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
228 irq_work);
229 struct mmc_command *cmd;
230 uint16_t status;
231 if (!host->mrq || !host->mrq->cmd)
232 return;
233
234 cmd = host->mrq->cmd;
235
236 #if 0
237 if (cmd->data->flags & MMC_DATA_READ) {
238 return;
239 }
240 #endif
241
242 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
243 dev_dbg(&host->pdev->dev, "status = 0x%04x\n", status);
244
245 /* we ignore a data timeout report if we are also told the data came */
246 if (status & GLAMO_STAT1_MMC_RB_DRDY)
247 status &= ~GLAMO_STAT1_MMC_DTOUT;
248
249 if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
250 cmd->error = -ETIMEDOUT;
251 if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR)) {
252 cmd->error = -EILSEQ;
253 }
254 if (cmd->error) {
255 dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
256 goto done;
257 }
258
259 /* issue STOP if we have been given one to use */
260 if (host->mrq->stop) {
261 glamo_mci_send_command(host, host->mrq->stop);
262 }
263
264 if (cmd->data->flags & MMC_DATA_READ)
265 do_pio_read(host, cmd->data);
266
267 done:
268 host->mrq = NULL;
269 glamo_mci_request_done(host, cmd->mrq);
270 }
271
272 static void glamo_mci_read_worker(struct work_struct *work)
273 {
274 struct glamo_mci_host *host = container_of(work, struct glamo_mci_host,
275 read_work);
276 struct mmc_command *cmd;
277 uint16_t status;
278 uint16_t blocks_ready;
279 size_t data_read = 0;
280 size_t data_ready;
281 struct scatterlist *sg;
282 u16 __iomem *from_ptr = host->data_base;
283 void *sg_pointer;
284
285
286 cmd = host->mrq->cmd;
287 sg = cmd->data->sg;
288 do {
289 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
290
291 if (status & (GLAMO_STAT1_MMC_RTOUT | GLAMO_STAT1_MMC_DTOUT))
292 cmd->error = -ETIMEDOUT;
293 if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR))
294 cmd->error = -EILSEQ;
295 if (cmd->error) {
296 dev_info(&host->pdev->dev, "Error after cmd: 0x%x\n", status);
297 goto done;
298 }
299
300 blocks_ready = glamo_reg_read(host, GLAMO_REG_MMC_RB_BLKCNT);
301 data_ready = blocks_ready * cmd->data->blksz;
302
303 if (data_ready == data_read)
304 yield();
305
306 while(sg && data_read + sg->length <= data_ready) {
307 sg_pointer = page_address(sg_page(sg)) + sg->offset;
308 memcpy(sg_pointer, from_ptr, sg->length);
309 from_ptr += sg->length >> 1;
310
311 data_read += sg->length;
312 sg = sg_next(sg);
313 }
314
315 } while(sg);
316 cmd->data->bytes_xfered = data_read;
317
318 do {
319 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
320 } while (!(status & GLAMO_STAT1_MMC_IDLE));
321
322 if (host->mrq->stop)
323 glamo_mci_send_command(host, host->mrq->stop);
324
325 do {
326 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
327 } while (!(status & GLAMO_STAT1_MMC_IDLE));
328 done:
329 host->mrq = NULL;
330 glamo_mci_request_done(host, cmd->mrq);
331 }
332
333 static irqreturn_t glamo_mci_irq(int irq, void *devid)
334 {
335 struct glamo_mci_host *host = (struct glamo_mci_host*)devid;
336 schedule_work(&host->irq_work);
337
338 return IRQ_HANDLED;
339 }
340
341 static void glamo_mci_send_command(struct glamo_mci_host *host,
342 struct mmc_command *cmd)
343 {
344 u8 u8a[6];
345 u16 fire = 0;
346 unsigned int timeout = 1000000;
347 u16 * reg_resp = (u16 *)(host->mmio_base + GLAMO_REG_MMC_CMD_RSP1);
348 u16 status;
349 int triggers_int = 1;
350
351 /* if we can't do it, reject as busy */
352 if (!glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1) &
353 GLAMO_STAT1_MMC_IDLE) {
354 cmd->error = -EBUSY;
355 return;
356 }
357
358 /* create an array in wire order for CRC computation */
359 u8a[0] = 0x40 | (cmd->opcode & 0x3f);
360 u8a[1] = (u8)(cmd->arg >> 24);
361 u8a[2] = (u8)(cmd->arg >> 16);
362 u8a[3] = (u8)(cmd->arg >> 8);
363 u8a[4] = (u8)cmd->arg;
364 u8a[5] = (crc7(0, u8a, 5) << 1) | 0x01; /* crc7 on first 5 bytes of packet */
365
366 /* issue the wire-order array including CRC in register order */
367 glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG1, ((u8a[4] << 8) | u8a[5]));
368 glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG2, ((u8a[2] << 8) | u8a[3]));
369 glamo_reg_write(host, GLAMO_REG_MMC_CMD_REG3, ((u8a[0] << 8) | u8a[1]));
370
371 /* command index toggle */
372 fire |= (host->request_counter & 1) << 12;
373
374 /* set type of command */
375 switch (mmc_cmd_type(cmd)) {
376 case MMC_CMD_BC:
377 fire |= GLAMO_FIRE_MMC_CMDT_BNR;
378 break;
379 case MMC_CMD_BCR:
380 fire |= GLAMO_FIRE_MMC_CMDT_BR;
381 break;
382 case MMC_CMD_AC:
383 fire |= GLAMO_FIRE_MMC_CMDT_AND;
384 break;
385 case MMC_CMD_ADTC:
386 fire |= GLAMO_FIRE_MMC_CMDT_AD;
387 break;
388 }
389 /*
390 * if it expects a response, set the type expected
391 *
392 * R1, Length : 48bit, Normal response
393 * R1b, Length : 48bit, same R1, but added card busy status
394 * R2, Length : 136bit (really 128 bits with CRC snipped)
395 * R3, Length : 48bit (OCR register value)
396 * R4, Length : 48bit, SDIO_OP_CONDITION, Reverse SDIO Card
397 * R5, Length : 48bit, IO_RW_DIRECTION, Reverse SDIO Card
398 * R6, Length : 48bit (RCA register)
399 * R7, Length : 48bit (interface condition, VHS(voltage supplied),
400 * check pattern, CRC7)
401 */
402 switch (mmc_resp_type(cmd)) {
403 case MMC_RSP_R1: /* same index as R6 and R7 */
404 fire |= GLAMO_FIRE_MMC_RSPT_R1;
405 break;
406 case MMC_RSP_R1B:
407 fire |= GLAMO_FIRE_MMC_RSPT_R1b;
408 break;
409 case MMC_RSP_R2:
410 fire |= GLAMO_FIRE_MMC_RSPT_R2;
411 break;
412 case MMC_RSP_R3:
413 fire |= GLAMO_FIRE_MMC_RSPT_R3;
414 break;
415 /* R4 and R5 supported by chip not defined in linux/mmc/core.h (sdio) */
416 }
417 /*
418 * From the command index, set up the command class in the host ctrllr
419 *
420 * missing guys present on chip but couldn't figure out how to use yet:
421 * 0x0 "stream read"
422 * 0x9 "cancel running command"
423 */
424 switch (cmd->opcode) {
425 case MMC_READ_SINGLE_BLOCK:
426 fire |= GLAMO_FIRE_MMC_CC_SBR; /* single block read */
427 break;
428 case MMC_SWITCH: /* 64 byte payload */
429 case SD_APP_SEND_SCR:
430 case MMC_READ_MULTIPLE_BLOCK:
431 /* we will get an interrupt off this */
432 if (!cmd->mrq->stop)
433 /* multiblock no stop */
434 fire |= GLAMO_FIRE_MMC_CC_MBRNS;
435 else
436 /* multiblock with stop */
437 fire |= GLAMO_FIRE_MMC_CC_MBRS;
438 break;
439 case MMC_WRITE_BLOCK:
440 fire |= GLAMO_FIRE_MMC_CC_SBW; /* single block write */
441 break;
442 case MMC_WRITE_MULTIPLE_BLOCK:
443 if (cmd->mrq->stop)
444 /* multiblock with stop */
445 fire |= GLAMO_FIRE_MMC_CC_MBWS;
446 else
447 /* multiblock NO stop-- 'RESERVED'? */
448 fire |= GLAMO_FIRE_MMC_CC_MBWNS;
449 break;
450 case MMC_STOP_TRANSMISSION:
451 fire |= GLAMO_FIRE_MMC_CC_STOP; /* STOP */
452 triggers_int = 0;
453 break;
454 default:
455 fire |= GLAMO_FIRE_MMC_CC_BASIC; /* "basic command" */
456 triggers_int = 0;
457 break;
458 }
459
460 if (cmd->data)
461 host->mrq = cmd->mrq;
462
463 /* always largest timeout */
464 glamo_reg_write(host, GLAMO_REG_MMC_TIMEOUT, 0xfff);
465
466 /* Generate interrupt on txfer */
467 glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC, 0xff36,
468 0x0800 |
469 GLAMO_BASIC_MMC_NO_CLK_RD_WAIT |
470 GLAMO_BASIC_MMC_EN_COMPL_INT |
471 GLAMO_BASIC_MMC_EN_DATA_PUPS |
472 GLAMO_BASIC_MMC_EN_CMD_PUP);
473
474 /* send the command out on the wire */
475 /* dev_info(&host->pdev->dev, "Using FIRE %04X\n", fire); */
476 glamo_reg_write(host, GLAMO_REG_MMC_CMD_FIRE, fire);
477
478 /* we are deselecting card? because it isn't going to ack then... */
479 if ((cmd->opcode == 7) && (cmd->arg == 0))
480 return;
481
482 /*
483 * we must spin until response is ready or timed out
484 * -- we don't get interrupts unless there is a bulk rx
485 */
486 do
487 status = glamo_reg_read(host, GLAMO_REG_MMC_RB_STAT1);
488 while (((((status >> 15) & 1) != (host->request_counter & 1)) ||
489 (!(status & (GLAMO_STAT1_MMC_RB_RRDY |
490 GLAMO_STAT1_MMC_RTOUT |
491 GLAMO_STAT1_MMC_DTOUT |
492 GLAMO_STAT1_MMC_BWERR |
493 GLAMO_STAT1_MMC_BRERR)))) && (timeout--));
494
495 if ((status & (GLAMO_STAT1_MMC_RTOUT |
496 GLAMO_STAT1_MMC_DTOUT)) ||
497 (timeout == 0)) {
498 cmd->error = -ETIMEDOUT;
499 } else if (status & (GLAMO_STAT1_MMC_BWERR | GLAMO_STAT1_MMC_BRERR)) {
500 cmd->error = -EILSEQ;
501 }
502
503 if (cmd->flags & MMC_RSP_PRESENT) {
504 if (cmd->flags & MMC_RSP_136) {
505 cmd->resp[3] = readw(&reg_resp[0]) |
506 (readw(&reg_resp[1]) << 16);
507 cmd->resp[2] = readw(&reg_resp[2]) |
508 (readw(&reg_resp[3]) << 16);
509 cmd->resp[1] = readw(&reg_resp[4]) |
510 (readw(&reg_resp[5]) << 16);
511 cmd->resp[0] = readw(&reg_resp[6]) |
512 (readw(&reg_resp[7]) << 16);
513 } else {
514 cmd->resp[0] = (readw(&reg_resp[0]) >> 8) |
515 (readw(&reg_resp[1]) << 8) |
516 ((readw(&reg_resp[2])) << 24);
517 }
518 }
519
520 #if 0
521 /* We'll only get an interrupt when all data has been transfered.
522 By starting to copy data when it's avaiable we can increase throughput by
523 up to 30%. */
524 if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
525 schedule_work(&host->read_work);
526 #endif
527
528 }
529
530 static int glamo_mci_prepare_pio(struct glamo_mci_host *host,
531 struct mmc_data *data)
532 {
533 /* set up the block info */
534 glamo_reg_write(host, GLAMO_REG_MMC_DATBLKLEN, data->blksz);
535 glamo_reg_write(host, GLAMO_REG_MMC_DATBLKCNT, data->blocks);
536
537 data->bytes_xfered = 0;
538
539 /* if write, prep the write into the shared RAM before the command */
540 if (data->flags & MMC_DATA_WRITE) {
541 do_pio_write(host, data);
542 }
543
544 dev_dbg(&host->pdev->dev, "(blksz=%d, count=%d)\n",
545 data->blksz, data->blocks);
546 return 0;
547 }
548
549 static int glamo_mci_irq_poll(struct glamo_mci_host *host,
550 struct mmc_command *cmd)
551 {
552 int timeout = 1000000;
553 /*
554 * if the glamo INT# line isn't wired (*cough* it can happen)
555 * I'm afraid we have to spin on the IRQ status bit and "be
556 * our own INT# line"
557 */
558 /*
559 * we have faith we will get an "interrupt"...
560 * but something insane like suspend problems can mean
561 * we spin here forever, so we timeout after a LONG time
562 */
563 while ((!(readw(host->core->base +
564 GLAMO_REG_IRQ_STATUS) & GLAMO_IRQ_MMC)) &&
565 (timeout--));
566
567 if (timeout < 0) {
568 if (cmd->data->error)
569 cmd->data->error = -ETIMEDOUT;
570 dev_err(&host->pdev->dev, "Payload timeout\n");
571 return -ETIMEDOUT;
572 }
573 /* ack this interrupt source */
574 writew(GLAMO_IRQ_MMC, host->core->base +
575 GLAMO_REG_IRQ_CLEAR);
576
577 /* yay we are an interrupt controller! -- call the ISR
578 * it will stop clock to card
579 */
580 glamo_mci_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
581
582 return 0;
583 }
584
585 static void glamo_mci_send_request(struct mmc_host *mmc, struct mmc_request *mrq)
586 {
587 struct glamo_mci_host *host = mmc_priv(mmc);
588 struct mmc_command *cmd = mrq->cmd;
589
590 glamo_mci_clock_enable(host);
591 host->request_counter++;
592 if (cmd->data) {
593 if(glamo_mci_prepare_pio(host, cmd->data)) {
594 cmd->error = -EIO;
595 cmd->data->error = -EIO;
596 goto done;
597 }
598 }
599
600 dev_dbg(&host->pdev->dev,"cmd 0x%x, "
601 "arg 0x%x data=%p mrq->stop=%p flags 0x%x\n",
602 cmd->opcode, cmd->arg, cmd->data, cmd->mrq->stop,
603 cmd->flags);
604
605 glamo_mci_send_command(host, cmd);
606
607 /*
608 * if we don't have bulk data to take care of, we're done
609 */
610 if (!cmd->data || cmd->error)
611 goto done;
612
613
614 if (!host->core->irq_works) {
615 if (glamo_mci_irq_poll(host, mrq->cmd))
616 goto done;
617 }
618
619 /*
620 * Otherwise can can use the interrupt as async completion --
621 * if there is read data coming, or we wait for write data to complete,
622 * exit without mmc_request_done() as the payload interrupt
623 * will service it
624 */
625 dev_dbg(&host->pdev->dev, "Waiting for payload data\n");
626 return;
627 done:
628 glamo_mci_request_done(host, mrq);
629 }
630
631 static void glamo_mci_set_power_mode(struct glamo_mci_host *host,
632 unsigned char power_mode) {
633 int ret;
634
635 if (power_mode == host->power_mode)
636 return;
637
638 switch(power_mode) {
639 case MMC_POWER_UP:
640 if (host->power_mode == MMC_POWER_OFF) {
641 ret = regulator_enable(host->regulator);
642 if (ret)
643 dev_err(&host->pdev->dev, "Failed to enable regulator: %d\n", ret);
644 }
645 break;
646 case MMC_POWER_ON:
647 break;
648 case MMC_POWER_OFF:
649 default:
650 glamo_engine_disable(host->core,
651 GLAMO_ENGINE_MMC);
652
653 ret = regulator_disable(host->regulator);
654 if (ret)
655 dev_warn(&host->pdev->dev, "Failed to disable regulator: %d\n", ret);
656 break;
657 }
658 host->power_mode = power_mode;
659 }
660
661 static void glamo_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
662 {
663 struct glamo_mci_host *host = mmc_priv(mmc);
664 int bus_width = 0;
665 int rate;
666 int sd_drive;
667 int ret;
668
669 /* Set power */
670 glamo_mci_set_power_mode(host, ios->power_mode);
671
672 if (host->vdd != ios->vdd) {
673 ret = mmc_regulator_set_ocr(host->regulator, ios->vdd);
674 if (ret)
675 dev_err(&host->pdev->dev, "Failed to set regulator voltage: %d\n", ret);
676 else
677 host->vdd = ios->vdd;
678 }
679 rate = glamo_mci_set_card_clock(host, ios->clock);
680
681 if ((ios->power_mode == MMC_POWER_ON) ||
682 (ios->power_mode == MMC_POWER_UP)) {
683 dev_info(&host->pdev->dev,
684 "powered (vdd = %hu) clk: %dkHz div=%hu (req: %ukHz). "
685 "Bus width=%d\n", ios->vdd,
686 rate / 1000, 0,
687 ios->clock / 1000, (int)ios->bus_width);
688 } else {
689 dev_info(&host->pdev->dev, "glamo_mci_set_ios: power down.\n");
690 }
691
692 /* set bus width */
693 if (ios->bus_width == MMC_BUS_WIDTH_4)
694 bus_width = GLAMO_BASIC_MMC_EN_4BIT_DATA;
695
696 sd_drive = (rate * 4) / host->clk_rate;
697 if (sd_drive > 3)
698 sd_drive = 3;
699
700 glamo_reg_set_bit_mask(host, GLAMO_REG_MMC_BASIC,
701 GLAMO_BASIC_MMC_EN_4BIT_DATA | 0xb0,
702 bus_width | sd_drive << 6);
703 }
704
705
706 /*
707 * no physical write protect supported by us
708 */
709 static int glamo_mci_get_ro(struct mmc_host *mmc)
710 {
711 return 0;
712 }
713
714 static struct mmc_host_ops glamo_mci_ops = {
715 .request = glamo_mci_send_request,
716 .set_ios = glamo_mci_set_ios,
717 .get_ro = glamo_mci_get_ro,
718 };
719
720 static int glamo_mci_probe(struct platform_device *pdev)
721 {
722 struct mmc_host *mmc;
723 struct glamo_mci_host *host;
724 struct glamo_core *core = dev_get_drvdata(pdev->dev.parent);
725 int ret;
726
727 dev_info(&pdev->dev, "glamo_mci driver (C)2007 Openmoko, Inc\n");
728
729 mmc = mmc_alloc_host(sizeof(struct glamo_mci_host), &pdev->dev);
730 if (!mmc) {
731 ret = -ENOMEM;
732 goto probe_out;
733 }
734
735 host = mmc_priv(mmc);
736 host->mmc = mmc;
737 host->pdev = pdev;
738 if (core->pdata)
739 host->pdata = core->pdata->mmc_data;
740 host->power_mode = MMC_POWER_OFF;
741 host->clk_enabled = 0;
742 host->core = core;
743
744 INIT_WORK(&host->irq_work, glamo_mci_irq_worker);
745 INIT_WORK(&host->read_work, glamo_mci_read_worker);
746
747 host->regulator = regulator_get(pdev->dev.parent, "SD_3V3");
748 if (!host->regulator) {
749 dev_err(&pdev->dev, "Cannot proceed without regulator.\n");
750 ret = -ENODEV;
751 goto probe_free_host;
752 }
753
754 host->mmio_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
755 if (!host->mmio_mem) {
756 dev_err(&pdev->dev,
757 "failed to get io memory region resouce.\n");
758 ret = -ENOENT;
759 goto probe_regulator_put;
760 }
761
762 host->mmio_mem = request_mem_region(host->mmio_mem->start,
763 resource_size(host->mmio_mem),
764 pdev->name);
765
766 if (!host->mmio_mem) {
767 dev_err(&pdev->dev, "failed to request io memory region.\n");
768 ret = -ENOENT;
769 goto probe_regulator_put;
770 }
771
772 host->mmio_base = ioremap(host->mmio_mem->start,
773 resource_size(host->mmio_mem));
774 if (!host->mmio_base) {
775 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
776 ret = -EINVAL;
777 goto probe_free_mem_region_mmio;
778 }
779
780
781 /* Get ahold of our data buffer we use for data in and out on MMC */
782 host->data_mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
783 if (!host->data_mem) {
784 dev_err(&pdev->dev,
785 "failed to get io memory region resource.\n");
786 ret = -ENOENT;
787 goto probe_iounmap_mmio;
788 }
789
790 host->data_mem = request_mem_region(host->data_mem->start,
791 resource_size(host->data_mem),
792 pdev->name);
793
794 if (!host->data_mem) {
795 dev_err(&pdev->dev, "failed to request io memory region.\n");
796 ret = -ENOENT;
797 goto probe_iounmap_mmio;
798 }
799 host->data_base = ioremap(host->data_mem->start,
800 resource_size(host->data_mem));
801
802 if (host->data_base == 0) {
803 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
804 ret = -EINVAL;
805 goto probe_free_mem_region_data;
806 }
807
808 ret = request_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), glamo_mci_irq, IRQF_SHARED,
809 pdev->name, host);
810 if (ret) {
811 dev_err(&pdev->dev, "failed to register irq.\n");
812 goto probe_iounmap_data;
813 }
814
815
816 host->vdd = 0;
817 host->clk_rate = glamo_pll_rate(host->core, GLAMO_PLL1);
818
819 /* explain our host controller capabilities */
820 mmc->ops = &glamo_mci_ops;
821 mmc->ocr_avail = mmc_regulator_get_ocrmask(host->regulator);
822 mmc->caps = MMC_CAP_4_BIT_DATA |
823 MMC_CAP_MMC_HIGHSPEED |
824 MMC_CAP_SD_HIGHSPEED;
825 mmc->f_min = host->clk_rate / 256;
826 mmc->f_max = sd_max_clk;
827
828 mmc->max_blk_count = (1 << 16) - 1; /* GLAMO_REG_MMC_RB_BLKCNT */
829 mmc->max_blk_size = (1 << 12) - 1; /* GLAMO_REG_MMC_RB_BLKLEN */
830 mmc->max_req_size = resource_size(host->data_mem);
831 mmc->max_seg_size = mmc->max_req_size;
832 mmc->max_phys_segs = 128;
833 mmc->max_hw_segs = 128;
834
835 if (mmc->ocr_avail < 0) {
836 dev_warn(&pdev->dev, "Failed to get ocr list for regulator: %d.\n",
837 mmc->ocr_avail);
838 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
839 }
840
841 platform_set_drvdata(pdev, mmc);
842
843 glamo_engine_enable(host->core, GLAMO_ENGINE_MMC);
844 glamo_engine_reset(host->core, GLAMO_ENGINE_MMC);
845
846 glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
847 (u16)(host->data_mem->start));
848 glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
849 (u16)(host->data_mem->start >> 16));
850
851 glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
852 (u16)(host->data_mem->start));
853 glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
854 (u16)(host->data_mem->start >> 16));
855
856 setup_timer(&host->disable_timer, glamo_mci_disable_timer,
857 (unsigned long)host);
858
859 if ((ret = mmc_add_host(mmc))) {
860 dev_err(&pdev->dev, "failed to add mmc host.\n");
861 goto probe_freeirq;
862 }
863
864 dev_info(&pdev->dev,"initialisation done.\n");
865 return 0;
866
867 probe_freeirq:
868 free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
869 probe_iounmap_data:
870 iounmap(host->data_base);
871 probe_free_mem_region_data:
872 release_mem_region(host->data_mem->start, resource_size(host->data_mem));
873 probe_iounmap_mmio:
874 iounmap(host->mmio_base);
875 probe_free_mem_region_mmio:
876 release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
877 probe_regulator_put:
878 regulator_put(host->regulator);
879 probe_free_host:
880 mmc_free_host(mmc);
881 probe_out:
882 return ret;
883 }
884
885 static int glamo_mci_remove(struct platform_device *pdev)
886 {
887 struct mmc_host *mmc = platform_get_drvdata(pdev);
888 struct glamo_mci_host *host = mmc_priv(mmc);
889
890 free_irq(IRQ_GLAMO(GLAMO_IRQIDX_MMC), host);
891
892 mmc_remove_host(mmc);
893 iounmap(host->mmio_base);
894 iounmap(host->data_base);
895 release_mem_region(host->mmio_mem->start, resource_size(host->mmio_mem));
896 release_mem_region(host->data_mem->start, resource_size(host->data_mem));
897
898 regulator_put(host->regulator);
899
900 mmc_free_host(mmc);
901
902 glamo_engine_disable(host->core, GLAMO_ENGINE_MMC);
903 return 0;
904 }
905
906
907 #ifdef CONFIG_PM
908
909 static int glamo_mci_suspend(struct device *dev)
910 {
911 struct mmc_host *mmc = dev_get_drvdata(dev);
912 struct glamo_mci_host *host = mmc_priv(mmc);
913 int ret;
914
915 cancel_work_sync(&host->irq_work);
916
917 ret = mmc_suspend_host(mmc, PMSG_SUSPEND);
918 glamo_mci_clock_enable(host);
919
920 return ret;
921 }
922
923 static int glamo_mci_resume(struct device *dev)
924 {
925 struct mmc_host *mmc = dev_get_drvdata(dev);
926 struct glamo_mci_host *host = mmc_priv(mmc);
927 int ret;
928
929 glamo_engine_enable(host->core, GLAMO_ENGINE_MMC);
930 glamo_engine_reset(host->core, GLAMO_ENGINE_MMC);
931
932 glamo_reg_write(host, GLAMO_REG_MMC_WDATADS1,
933 (u16)(host->data_mem->start));
934 glamo_reg_write(host, GLAMO_REG_MMC_WDATADS2,
935 (u16)(host->data_mem->start >> 16));
936
937 glamo_reg_write(host, GLAMO_REG_MMC_RDATADS1,
938 (u16)(host->data_mem->start));
939 glamo_reg_write(host, GLAMO_REG_MMC_RDATADS2,
940 (u16)(host->data_mem->start >> 16));
941 mdelay(5);
942
943 ret = mmc_resume_host(host->mmc);
944 /* glamo_mci_clock_disable(host);*/
945
946 return 0;
947 }
948
949 static struct dev_pm_ops glamo_mci_pm_ops = {
950 .suspend = glamo_mci_suspend,
951 .resume = glamo_mci_resume,
952 };
953 #define GLAMO_MCI_PM_OPS (&glamo_mci_pm_ops)
954
955 #else /* CONFIG_PM */
956 #define GLAMO_MCI_PM_OPS NULL
957 #endif /* CONFIG_PM */
958
959
960 static struct platform_driver glamo_mci_driver =
961 {
962 .probe = glamo_mci_probe,
963 .remove = glamo_mci_remove,
964 .driver = {
965 .name = "glamo-mci",
966 .owner = THIS_MODULE,
967 .pm = GLAMO_MCI_PM_OPS,
968 },
969 };
970
971 static int __init glamo_mci_init(void)
972 {
973 platform_driver_register(&glamo_mci_driver);
974 return 0;
975 }
976
977 static void __exit glamo_mci_exit(void)
978 {
979 platform_driver_unregister(&glamo_mci_driver);
980 }
981
982 module_init(glamo_mci_init);
983 module_exit(glamo_mci_exit);
984
985 MODULE_DESCRIPTION("Glamo MMC/SD Card Interface driver");
986 MODULE_LICENSE("GPL");
987 MODULE_AUTHOR("Andy Green <andy@openmoko.com>");
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