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[lantiq]
[openwrt.git] / target / linux / lantiq / patches-2.6.39 / 540-gptu.patch
1 --- /dev/null
2 +++ b/arch/mips/lantiq/xway/timer.c
3 @@ -0,0 +1,830 @@
4 +#include <linux/kernel.h>
5 +#include <linux/module.h>
6 +#include <linux/version.h>
7 +#include <linux/types.h>
8 +#include <linux/fs.h>
9 +#include <linux/miscdevice.h>
10 +#include <linux/init.h>
11 +#include <linux/uaccess.h>
12 +#include <linux/unistd.h>
13 +#include <linux/errno.h>
14 +#include <linux/interrupt.h>
15 +#include <linux/sched.h>
16 +
17 +#include <asm/irq.h>
18 +#include <asm/div64.h>
19 +
20 +#include <lantiq_soc.h>
21 +#include <lantiq_irq.h>
22 +#include <lantiq_timer.h>
23 +
24 +#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6
25 +
26 +#ifdef TIMER1A
27 +#define FIRST_TIMER TIMER1A
28 +#else
29 +#define FIRST_TIMER 2
30 +#endif
31 +
32 +/*
33 + * GPTC divider is set or not.
34 + */
35 +#define GPTU_CLC_RMC_IS_SET 0
36 +
37 +/*
38 + * Timer Interrupt (IRQ)
39 + */
40 +/* Must be adjusted when ICU driver is available */
41 +#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22)
42 +
43 +/*
44 + * Bits Operation
45 + */
46 +#define GET_BITS(x, msb, lsb) \
47 + (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb))
48 +#define SET_BITS(x, msb, lsb, value) \
49 + (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \
50 + (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb)))
51 +
52 +/*
53 + * GPTU Register Mapping
54 + */
55 +#define LQ_GPTU (KSEG1 + 0x1E100A00)
56 +#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000))
57 +#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008))
58 +#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
59 +#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
60 +#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
61 +#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */
62 +#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4))
63 +#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8))
64 +#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC))
65 +
66 +/*
67 + * Clock Control Register
68 + */
69 +#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16)
70 +#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8)
71 +#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5))
72 +#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3))
73 +#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2))
74 +#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1))
75 +#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0))
76 +
77 +#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value))
78 +#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value))
79 +#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0)
80 +#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0)
81 +#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0)
82 +#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0)
83 +#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0)
84 +
85 +/*
86 + * ID Register
87 + */
88 +#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8)
89 +#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5)
90 +#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0)
91 +
92 +/*
93 + * Control Register of Timer/Counter nX
94 + * n is the index of block (1 based index)
95 + * X is either A or B
96 + */
97 +#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10))
98 +#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9))
99 +#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8))
100 +#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6)
101 +#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5))
102 +#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */
103 +#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3))
104 +#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2))
105 +#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1))
106 +#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0))
107 +
108 +#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10))
109 +#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0)
110 +#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0)
111 +#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value))
112 +#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0)
113 +#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0)
114 +#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0)
115 +#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0)
116 +#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0)
117 +
118 +#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0)
119 +#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0)
120 +#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0)
121 +
122 +#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
123 +#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0)
124 +
125 +#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001)
126 +#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002)
127 +#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004)
128 +#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008)
129 +#define TIMER_FLAG_NONE_EDGE 0x0000
130 +#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030)
131 +#define TIMER_FLAG_REAL 0x0000
132 +#define TIMER_FLAG_INVERT 0x0040
133 +#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040)
134 +#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070)
135 +#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080)
136 +#define TIMER_FLAG_CALLBACK_IN_HB 0x0200
137 +#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300)
138 +#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000)
139 +
140 +struct timer_dev_timer {
141 + unsigned int f_irq_on;
142 + unsigned int irq;
143 + unsigned int flag;
144 + unsigned long arg1;
145 + unsigned long arg2;
146 +};
147 +
148 +struct timer_dev {
149 + struct mutex gptu_mutex;
150 + unsigned int number_of_timers;
151 + unsigned int occupation;
152 + unsigned int f_gptu_on;
153 + struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2];
154 +};
155 +
156 +unsigned int ltq_get_fpi_bus_clock(int fpi);
157 +
158 +static long gptu_ioctl(struct file *, unsigned int, unsigned long);
159 +static int gptu_open(struct inode *, struct file *);
160 +static int gptu_release(struct inode *, struct file *);
161 +
162 +static struct file_operations gptu_fops = {
163 + .owner = THIS_MODULE,
164 + .unlocked_ioctl = gptu_ioctl,
165 + .open = gptu_open,
166 + .release = gptu_release
167 +};
168 +
169 +static struct miscdevice gptu_miscdev = {
170 + .minor = MISC_DYNAMIC_MINOR,
171 + .name = "gptu",
172 + .fops = &gptu_fops,
173 +};
174 +
175 +static struct timer_dev timer_dev;
176 +
177 +static irqreturn_t timer_irq_handler(int irq, void *p)
178 +{
179 + unsigned int timer;
180 + unsigned int flag;
181 + struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p;
182 +
183 + timer = irq - TIMER_INTERRUPT;
184 + if (timer < timer_dev.number_of_timers
185 + && dev_timer == &timer_dev.timer[timer]) {
186 + /* Clear interrupt. */
187 + ltq_w32(1 << timer, LQ_GPTU_IRNCR);
188 +
189 + /* Call user hanler or signal. */
190 + flag = dev_timer->flag;
191 + if (!(timer & 0x01)
192 + || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
193 + /* 16-bit timer or timer A of 32-bit timer */
194 + switch (TIMER_FLAG_MASK_HANDLE(flag)) {
195 + case TIMER_FLAG_CALLBACK_IN_IRQ:
196 + case TIMER_FLAG_CALLBACK_IN_HB:
197 + if (dev_timer->arg1)
198 + (*(timer_callback)dev_timer->arg1)(dev_timer->arg2);
199 + break;
200 + case TIMER_FLAG_SIGNAL:
201 + send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0);
202 + break;
203 + }
204 + }
205 + }
206 + return IRQ_HANDLED;
207 +}
208 +
209 +static inline void lq_enable_gptu(void)
210 +{
211 + ltq_pmu_enable(PMU_GPT);
212 +
213 + /* Set divider as 1, disable write protection for SPEN, enable module. */
214 + *LQ_GPTU_CLC =
215 + GPTU_CLC_SMC_SET(0x00) |
216 + GPTU_CLC_RMC_SET(0x01) |
217 + GPTU_CLC_FSOE_SET(0) |
218 + GPTU_CLC_SBWE_SET(1) |
219 + GPTU_CLC_EDIS_SET(0) |
220 + GPTU_CLC_SPEN_SET(0) |
221 + GPTU_CLC_DISR_SET(0);
222 +}
223 +
224 +static inline void lq_disable_gptu(void)
225 +{
226 + ltq_w32(0x00, LQ_GPTU_IRNEN);
227 + ltq_w32(0xfff, LQ_GPTU_IRNCR);
228 +
229 + /* Set divider as 0, enable write protection for SPEN, disable module. */
230 + *LQ_GPTU_CLC =
231 + GPTU_CLC_SMC_SET(0x00) |
232 + GPTU_CLC_RMC_SET(0x00) |
233 + GPTU_CLC_FSOE_SET(0) |
234 + GPTU_CLC_SBWE_SET(0) |
235 + GPTU_CLC_EDIS_SET(0) |
236 + GPTU_CLC_SPEN_SET(0) |
237 + GPTU_CLC_DISR_SET(1);
238 +
239 + ltq_pmu_disable(PMU_GPT);
240 +}
241 +
242 +int lq_request_timer(unsigned int timer, unsigned int flag,
243 + unsigned long value, unsigned long arg1, unsigned long arg2)
244 +{
245 + int ret = 0;
246 + unsigned int con_reg, irnen_reg;
247 + int n, X;
248 +
249 + if (timer >= FIRST_TIMER + timer_dev.number_of_timers)
250 + return -EINVAL;
251 +
252 + printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...",
253 + timer, flag, value);
254 +
255 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT)
256 + value &= 0xFFFF;
257 + else
258 + timer &= ~0x01;
259 +
260 + mutex_lock(&timer_dev.gptu_mutex);
261 +
262 + /*
263 + * Allocate timer.
264 + */
265 + if (timer < FIRST_TIMER) {
266 + unsigned int mask;
267 + unsigned int shift;
268 + /* This takes care of TIMER1B which is the only choice for Voice TAPI system */
269 + unsigned int offset = TIMER2A;
270 +
271 + /*
272 + * Pick up a free timer.
273 + */
274 + if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) {
275 + mask = 1 << offset;
276 + shift = 1;
277 + } else {
278 + mask = 3 << offset;
279 + shift = 2;
280 + }
281 + for (timer = offset;
282 + timer < offset + timer_dev.number_of_timers;
283 + timer += shift, mask <<= shift)
284 + if (!(timer_dev.occupation & mask)) {
285 + timer_dev.occupation |= mask;
286 + break;
287 + }
288 + if (timer >= offset + timer_dev.number_of_timers) {
289 + printk("failed![%d]\n", __LINE__);
290 + mutex_unlock(&timer_dev.gptu_mutex);
291 + return -EINVAL;
292 + } else
293 + ret = timer;
294 + } else {
295 + register unsigned int mask;
296 +
297 + /*
298 + * Check if the requested timer is free.
299 + */
300 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
301 + if ((timer_dev.occupation & mask)) {
302 + printk("failed![%d] mask %#x, timer_dev.occupation %#x\n",
303 + __LINE__, mask, timer_dev.occupation);
304 + mutex_unlock(&timer_dev.gptu_mutex);
305 + return -EBUSY;
306 + } else {
307 + timer_dev.occupation |= mask;
308 + ret = 0;
309 + }
310 + }
311 +
312 + /*
313 + * Prepare control register value.
314 + */
315 + switch (TIMER_FLAG_MASK_EDGE(flag)) {
316 + default:
317 + case TIMER_FLAG_NONE_EDGE:
318 + con_reg = GPTU_CON_EDGE_SET(0x00);
319 + break;
320 + case TIMER_FLAG_RISE_EDGE:
321 + con_reg = GPTU_CON_EDGE_SET(0x01);
322 + break;
323 + case TIMER_FLAG_FALL_EDGE:
324 + con_reg = GPTU_CON_EDGE_SET(0x02);
325 + break;
326 + case TIMER_FLAG_ANY_EDGE:
327 + con_reg = GPTU_CON_EDGE_SET(0x03);
328 + break;
329 + }
330 + if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER)
331 + con_reg |=
332 + TIMER_FLAG_MASK_SRC(flag) ==
333 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) :
334 + GPTU_CON_SRC_EXT_SET(0);
335 + else
336 + con_reg |=
337 + TIMER_FLAG_MASK_SRC(flag) ==
338 + TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) :
339 + GPTU_CON_SRC_EG_SET(0);
340 + con_reg |=
341 + TIMER_FLAG_MASK_SYNC(flag) ==
342 + TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) :
343 + GPTU_CON_SYNC_SET(1);
344 + con_reg |=
345 + TIMER_FLAG_MASK_INVERT(flag) ==
346 + TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
347 + con_reg |=
348 + TIMER_FLAG_MASK_SIZE(flag) ==
349 + TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) :
350 + GPTU_CON_EXT_SET(1);
351 + con_reg |=
352 + TIMER_FLAG_MASK_STOP(flag) ==
353 + TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
354 + con_reg |=
355 + TIMER_FLAG_MASK_TYPE(flag) ==
356 + TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) :
357 + GPTU_CON_CNT_SET(1);
358 + con_reg |=
359 + TIMER_FLAG_MASK_DIR(flag) ==
360 + TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
361 +
362 + /*
363 + * Fill up running data.
364 + */
365 + timer_dev.timer[timer - FIRST_TIMER].flag = flag;
366 + timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1;
367 + timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2;
368 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
369 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag;
370 +
371 + /*
372 + * Enable GPTU module.
373 + */
374 + if (!timer_dev.f_gptu_on) {
375 + lq_enable_gptu();
376 + timer_dev.f_gptu_on = 1;
377 + }
378 +
379 + /*
380 + * Enable IRQ.
381 + */
382 + if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) {
383 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL)
384 + timer_dev.timer[timer - FIRST_TIMER].arg1 =
385 + (unsigned long) find_task_by_vpid((int) arg1);
386 +
387 + irnen_reg = 1 << (timer - FIRST_TIMER);
388 +
389 + if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL
390 + || (TIMER_FLAG_MASK_HANDLE(flag) ==
391 + TIMER_FLAG_CALLBACK_IN_IRQ
392 + && timer_dev.timer[timer - FIRST_TIMER].arg1)) {
393 + enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
394 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1;
395 + }
396 + } else
397 + irnen_reg = 0;
398 +
399 + /*
400 + * Write config register, reload value and enable interrupt.
401 + */
402 + n = timer >> 1;
403 + X = timer & 0x01;
404 + *LQ_GPTU_CON(n, X) = con_reg;
405 + *LQ_GPTU_RELOAD(n, X) = value;
406 + /* printk("reload value = %d\n", (u32)value); */
407 + *LQ_GPTU_IRNEN |= irnen_reg;
408 +
409 + mutex_unlock(&timer_dev.gptu_mutex);
410 + printk("successful!\n");
411 + return ret;
412 +}
413 +EXPORT_SYMBOL(lq_request_timer);
414 +
415 +int lq_free_timer(unsigned int timer)
416 +{
417 + unsigned int flag;
418 + unsigned int mask;
419 + int n, X;
420 +
421 + if (!timer_dev.f_gptu_on)
422 + return -EINVAL;
423 +
424 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
425 + return -EINVAL;
426 +
427 + mutex_lock(&timer_dev.gptu_mutex);
428 +
429 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
430 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
431 + timer &= ~0x01;
432 +
433 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
434 + if (((timer_dev.occupation & mask) ^ mask)) {
435 + mutex_unlock(&timer_dev.gptu_mutex);
436 + return -EINVAL;
437 + }
438 +
439 + n = timer >> 1;
440 + X = timer & 0x01;
441 +
442 + if (GPTU_CON_EN(n, X))
443 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
444 +
445 + *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1);
446 + *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1);
447 +
448 + if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) {
449 + disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq);
450 + timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0;
451 + }
452 +
453 + timer_dev.occupation &= ~mask;
454 + if (!timer_dev.occupation && timer_dev.f_gptu_on) {
455 + lq_disable_gptu();
456 + timer_dev.f_gptu_on = 0;
457 + }
458 +
459 + mutex_unlock(&timer_dev.gptu_mutex);
460 +
461 + return 0;
462 +}
463 +EXPORT_SYMBOL(lq_free_timer);
464 +
465 +int lq_start_timer(unsigned int timer, int is_resume)
466 +{
467 + unsigned int flag;
468 + unsigned int mask;
469 + int n, X;
470 +
471 + if (!timer_dev.f_gptu_on)
472 + return -EINVAL;
473 +
474 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
475 + return -EINVAL;
476 +
477 + mutex_lock(&timer_dev.gptu_mutex);
478 +
479 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
480 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
481 + timer &= ~0x01;
482 +
483 + mask = (TIMER_FLAG_MASK_SIZE(flag) ==
484 + TIMER_FLAG_16BIT ? 1 : 3) << timer;
485 + if (((timer_dev.occupation & mask) ^ mask)) {
486 + mutex_unlock(&timer_dev.gptu_mutex);
487 + return -EINVAL;
488 + }
489 +
490 + n = timer >> 1;
491 + X = timer & 0x01;
492 +
493 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1);
494 +
495 + mutex_unlock(&timer_dev.gptu_mutex);
496 +
497 + return 0;
498 +}
499 +EXPORT_SYMBOL(lq_start_timer);
500 +
501 +int lq_stop_timer(unsigned int timer)
502 +{
503 + unsigned int flag;
504 + unsigned int mask;
505 + int n, X;
506 +
507 + if (!timer_dev.f_gptu_on)
508 + return -EINVAL;
509 +
510 + if (timer < FIRST_TIMER
511 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
512 + return -EINVAL;
513 +
514 + mutex_lock(&timer_dev.gptu_mutex);
515 +
516 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
517 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
518 + timer &= ~0x01;
519 +
520 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
521 + if (((timer_dev.occupation & mask) ^ mask)) {
522 + mutex_unlock(&timer_dev.gptu_mutex);
523 + return -EINVAL;
524 + }
525 +
526 + n = timer >> 1;
527 + X = timer & 0x01;
528 +
529 + *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1);
530 +
531 + mutex_unlock(&timer_dev.gptu_mutex);
532 +
533 + return 0;
534 +}
535 +EXPORT_SYMBOL(lq_stop_timer);
536 +
537 +int lq_reset_counter_flags(u32 timer, u32 flags)
538 +{
539 + unsigned int oflag;
540 + unsigned int mask, con_reg;
541 + int n, X;
542 +
543 + if (!timer_dev.f_gptu_on)
544 + return -EINVAL;
545 +
546 + if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers)
547 + return -EINVAL;
548 +
549 + mutex_lock(&timer_dev.gptu_mutex);
550 +
551 + oflag = timer_dev.timer[timer - FIRST_TIMER].flag;
552 + if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT)
553 + timer &= ~0x01;
554 +
555 + mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
556 + if (((timer_dev.occupation & mask) ^ mask)) {
557 + mutex_unlock(&timer_dev.gptu_mutex);
558 + return -EINVAL;
559 + }
560 +
561 + switch (TIMER_FLAG_MASK_EDGE(flags)) {
562 + default:
563 + case TIMER_FLAG_NONE_EDGE:
564 + con_reg = GPTU_CON_EDGE_SET(0x00);
565 + break;
566 + case TIMER_FLAG_RISE_EDGE:
567 + con_reg = GPTU_CON_EDGE_SET(0x01);
568 + break;
569 + case TIMER_FLAG_FALL_EDGE:
570 + con_reg = GPTU_CON_EDGE_SET(0x02);
571 + break;
572 + case TIMER_FLAG_ANY_EDGE:
573 + con_reg = GPTU_CON_EDGE_SET(0x03);
574 + break;
575 + }
576 + if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER)
577 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0);
578 + else
579 + con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0);
580 + con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1);
581 + con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1);
582 + con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1);
583 + con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0);
584 + con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1);
585 + con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0);
586 +
587 + timer_dev.timer[timer - FIRST_TIMER].flag = flags;
588 + if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT)
589 + timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags;
590 +
591 + n = timer >> 1;
592 + X = timer & 0x01;
593 +
594 + *LQ_GPTU_CON(n, X) = con_reg;
595 + smp_wmb();
596 + printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X));
597 + mutex_unlock(&timer_dev.gptu_mutex);
598 + return 0;
599 +}
600 +EXPORT_SYMBOL(lq_reset_counter_flags);
601 +
602 +int lq_get_count_value(unsigned int timer, unsigned long *value)
603 +{
604 + unsigned int flag;
605 + unsigned int mask;
606 + int n, X;
607 +
608 + if (!timer_dev.f_gptu_on)
609 + return -EINVAL;
610 +
611 + if (timer < FIRST_TIMER
612 + || timer >= FIRST_TIMER + timer_dev.number_of_timers)
613 + return -EINVAL;
614 +
615 + mutex_lock(&timer_dev.gptu_mutex);
616 +
617 + flag = timer_dev.timer[timer - FIRST_TIMER].flag;
618 + if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT)
619 + timer &= ~0x01;
620 +
621 + mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer;
622 + if (((timer_dev.occupation & mask) ^ mask)) {
623 + mutex_unlock(&timer_dev.gptu_mutex);
624 + return -EINVAL;
625 + }
626 +
627 + n = timer >> 1;
628 + X = timer & 0x01;
629 +
630 + *value = *LQ_GPTU_COUNT(n, X);
631 +
632 + mutex_unlock(&timer_dev.gptu_mutex);
633 +
634 + return 0;
635 +}
636 +EXPORT_SYMBOL(lq_get_count_value);
637 +
638 +u32 lq_cal_divider(unsigned long freq)
639 +{
640 + u64 module_freq, fpi = ltq_get_fpi_bus_clock(2);
641 + u32 clock_divider = 1;
642 + module_freq = fpi * 1000;
643 + do_div(module_freq, clock_divider * freq);
644 + return module_freq;
645 +}
646 +EXPORT_SYMBOL(lq_cal_divider);
647 +
648 +int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic,
649 + int is_ext_src, unsigned int handle_flag, unsigned long arg1,
650 + unsigned long arg2)
651 +{
652 + unsigned long divider;
653 + unsigned int flag;
654 +
655 + divider = lq_cal_divider(freq);
656 + if (divider == 0)
657 + return -EINVAL;
658 + flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT)
659 + | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE)
660 + | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC)
661 + | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN
662 + | TIMER_FLAG_MASK_HANDLE(handle_flag);
663 +
664 + printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n",
665 + timer, freq, divider);
666 + return lq_request_timer(timer, flag, divider, arg1, arg2);
667 +}
668 +EXPORT_SYMBOL(lq_set_timer);
669 +
670 +int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload,
671 + unsigned long arg1, unsigned long arg2)
672 +{
673 + printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload);
674 + return lq_request_timer(timer, flag, reload, arg1, arg2);
675 +}
676 +EXPORT_SYMBOL(lq_set_counter);
677 +
678 +static long gptu_ioctl(struct file *file, unsigned int cmd,
679 + unsigned long arg)
680 +{
681 + int ret;
682 + struct gptu_ioctl_param param;
683 +
684 + if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param)))
685 + return -EFAULT;
686 + copy_from_user(&param, (void *) arg, sizeof(param));
687 +
688 + if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER
689 + || GPTU_SET_COUNTER) && param.timer < 2)
690 + || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER)
691 + && !access_ok(VERIFY_WRITE, arg,
692 + sizeof(struct gptu_ioctl_param)))
693 + return -EFAULT;
694 +
695 + switch (cmd) {
696 + case GPTU_REQUEST_TIMER:
697 + ret = lq_request_timer(param.timer, param.flag, param.value,
698 + (unsigned long) param.pid,
699 + (unsigned long) param.sig);
700 + if (ret > 0) {
701 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
702 + timer, &ret, sizeof(&ret));
703 + ret = 0;
704 + }
705 + break;
706 + case GPTU_FREE_TIMER:
707 + ret = lq_free_timer(param.timer);
708 + break;
709 + case GPTU_START_TIMER:
710 + ret = lq_start_timer(param.timer, param.flag);
711 + break;
712 + case GPTU_STOP_TIMER:
713 + ret = lq_stop_timer(param.timer);
714 + break;
715 + case GPTU_GET_COUNT_VALUE:
716 + ret = lq_get_count_value(param.timer, &param.value);
717 + if (!ret)
718 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
719 + value, &param.value,
720 + sizeof(param.value));
721 + break;
722 + case GPTU_CALCULATE_DIVIDER:
723 + param.value = lq_cal_divider(param.value);
724 + if (param.value == 0)
725 + ret = -EINVAL;
726 + else {
727 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
728 + value, &param.value,
729 + sizeof(param.value));
730 + ret = 0;
731 + }
732 + break;
733 + case GPTU_SET_TIMER:
734 + ret = lq_set_timer(param.timer, param.value,
735 + TIMER_FLAG_MASK_STOP(param.flag) !=
736 + TIMER_FLAG_ONCE ? 1 : 0,
737 + TIMER_FLAG_MASK_SRC(param.flag) ==
738 + TIMER_FLAG_EXT_SRC ? 1 : 0,
739 + TIMER_FLAG_MASK_HANDLE(param.flag) ==
740 + TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL :
741 + TIMER_FLAG_NO_HANDLE,
742 + (unsigned long) param.pid,
743 + (unsigned long) param.sig);
744 + if (ret > 0) {
745 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
746 + timer, &ret, sizeof(&ret));
747 + ret = 0;
748 + }
749 + break;
750 + case GPTU_SET_COUNTER:
751 + lq_set_counter(param.timer, param.flag, param.value, 0, 0);
752 + if (ret > 0) {
753 + copy_to_user(&((struct gptu_ioctl_param *) arg)->
754 + timer, &ret, sizeof(&ret));
755 + ret = 0;
756 + }
757 + break;
758 + default:
759 + ret = -ENOTTY;
760 + }
761 +
762 + return ret;
763 +}
764 +
765 +static int gptu_open(struct inode *inode, struct file *file)
766 +{
767 + return 0;
768 +}
769 +
770 +static int gptu_release(struct inode *inode, struct file *file)
771 +{
772 + return 0;
773 +}
774 +
775 +int __init lq_gptu_init(void)
776 +{
777 + int ret;
778 + unsigned int i;
779 +
780 + ltq_w32(0, LQ_GPTU_IRNEN);
781 + ltq_w32(0xfff, LQ_GPTU_IRNCR);
782 +
783 + memset(&timer_dev, 0, sizeof(timer_dev));
784 + mutex_init(&timer_dev.gptu_mutex);
785 +
786 + lq_enable_gptu();
787 + timer_dev.number_of_timers = GPTU_ID_CFG * 2;
788 + lq_disable_gptu();
789 + if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2)
790 + timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2;
791 + printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers);
792 +
793 + ret = misc_register(&gptu_miscdev);
794 + if (ret) {
795 + printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret);
796 + return ret;
797 + } else {
798 + printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor);
799 + }
800 +
801 + for (i = 0; i < timer_dev.number_of_timers; i++) {
802 + ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]);
803 + if (ret) {
804 + for (; i >= 0; i--)
805 + free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]);
806 + misc_deregister(&gptu_miscdev);
807 + printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret);
808 + return ret;
809 + } else {
810 + timer_dev.timer[i].irq = TIMER_INTERRUPT + i;
811 + disable_irq(timer_dev.timer[i].irq);
812 + printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq);
813 + }
814 + }
815 +
816 + return 0;
817 +}
818 +
819 +void __exit lq_gptu_exit(void)
820 +{
821 + unsigned int i;
822 +
823 + for (i = 0; i < timer_dev.number_of_timers; i++) {
824 + if (timer_dev.timer[i].f_irq_on)
825 + disable_irq(timer_dev.timer[i].irq);
826 + free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]);
827 + }
828 + lq_disable_gptu();
829 + misc_deregister(&gptu_miscdev);
830 +}
831 +
832 +module_init(lq_gptu_init);
833 +module_exit(lq_gptu_exit);
834 --- /dev/null
835 +++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h
836 @@ -0,0 +1,155 @@
837 +#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
838 +#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__
839 +
840 +
841 +/******************************************************************************
842 + Copyright (c) 2002, Infineon Technologies. All rights reserved.
843 +
844 + No Warranty
845 + Because the program is licensed free of charge, there is no warranty for
846 + the program, to the extent permitted by applicable law. Except when
847 + otherwise stated in writing the copyright holders and/or other parties
848 + provide the program "as is" without warranty of any kind, either
849 + expressed or implied, including, but not limited to, the implied
850 + warranties of merchantability and fitness for a particular purpose. The
851 + entire risk as to the quality and performance of the program is with
852 + you. should the program prove defective, you assume the cost of all
853 + necessary servicing, repair or correction.
854 +
855 + In no event unless required by applicable law or agreed to in writing
856 + will any copyright holder, or any other party who may modify and/or
857 + redistribute the program as permitted above, be liable to you for
858 + damages, including any general, special, incidental or consequential
859 + damages arising out of the use or inability to use the program
860 + (including but not limited to loss of data or data being rendered
861 + inaccurate or losses sustained by you or third parties or a failure of
862 + the program to operate with any other programs), even if such holder or
863 + other party has been advised of the possibility of such damages.
864 +******************************************************************************/
865 +
866 +
867 +/*
868 + * ####################################
869 + * Definition
870 + * ####################################
871 + */
872 +
873 +/*
874 + * Available Timer/Counter Index
875 + */
876 +#define TIMER(n, X) (n * 2 + (X ? 1 : 0))
877 +#define TIMER_ANY 0x00
878 +#define TIMER1A TIMER(1, 0)
879 +#define TIMER1B TIMER(1, 1)
880 +#define TIMER2A TIMER(2, 0)
881 +#define TIMER2B TIMER(2, 1)
882 +#define TIMER3A TIMER(3, 0)
883 +#define TIMER3B TIMER(3, 1)
884 +
885 +/*
886 + * Flag of Timer/Counter
887 + * These flags specify the way in which timer is configured.
888 + */
889 +/* Bit size of timer/counter. */
890 +#define TIMER_FLAG_16BIT 0x0000
891 +#define TIMER_FLAG_32BIT 0x0001
892 +/* Switch between timer and counter. */
893 +#define TIMER_FLAG_TIMER 0x0000
894 +#define TIMER_FLAG_COUNTER 0x0002
895 +/* Stop or continue when overflowing/underflowing. */
896 +#define TIMER_FLAG_ONCE 0x0000
897 +#define TIMER_FLAG_CYCLIC 0x0004
898 +/* Count up or counter down. */
899 +#define TIMER_FLAG_UP 0x0000
900 +#define TIMER_FLAG_DOWN 0x0008
901 +/* Count on specific level or edge. */
902 +#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000
903 +#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040
904 +#define TIMER_FLAG_RISE_EDGE 0x0010
905 +#define TIMER_FLAG_FALL_EDGE 0x0020
906 +#define TIMER_FLAG_ANY_EDGE 0x0030
907 +/* Signal is syncronous to module clock or not. */
908 +#define TIMER_FLAG_UNSYNC 0x0000
909 +#define TIMER_FLAG_SYNC 0x0080
910 +/* Different interrupt handle type. */
911 +#define TIMER_FLAG_NO_HANDLE 0x0000
912 +#if defined(__KERNEL__)
913 + #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100
914 +#endif // defined(__KERNEL__)
915 +#define TIMER_FLAG_SIGNAL 0x0300
916 +/* Internal clock source or external clock source */
917 +#define TIMER_FLAG_INT_SRC 0x0000
918 +#define TIMER_FLAG_EXT_SRC 0x1000
919 +
920 +
921 +/*
922 + * ioctl Command
923 + */
924 +#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */
925 +#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */
926 +#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */
927 +#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */
928 +#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */
929 +#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/
930 +#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */
931 +#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */
932 +
933 +/*
934 + * Data Type Used to Call ioctl
935 + */
936 +struct gptu_ioctl_param {
937 + unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
938 + * GPTU_SET_COUNTER, this field is ID of expected *
939 + * timer/counter. If it's zero, a timer/counter would *
940 + * be dynamically allocated and ID would be stored in *
941 + * this field. *
942 + * In command GPTU_GET_COUNT_VALUE, this field is *
943 + * ignored. *
944 + * In other command, this field is ID of timer/counter *
945 + * allocated. */
946 + unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and *
947 + * GPTU_SET_COUNTER, this field contains flags to *
948 + * specify how to configure timer/counter. *
949 + * In command GPTU_START_TIMER, zero indicate start *
950 + * and non-zero indicate resume timer/counter. *
951 + * In other command, this field is ignored. */
952 + unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains *
953 + * init/reload value. *
954 + * In command GPTU_SET_TIMER, this field contains *
955 + * frequency (0.001Hz) of timer. *
956 + * In command GPTU_GET_COUNT_VALUE, current count *
957 + * value would be stored in this field. *
958 + * In command GPTU_CALCULATE_DIVIDER, this field *
959 + * contains frequency wanted, and after calculation, *
960 + * divider would be stored in this field to overwrite *
961 + * the frequency. *
962 + * In other command, this field is ignored. */
963 + int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
964 + * if signal is required, this field contains process *
965 + * ID to which signal would be sent. *
966 + * In other command, this field is ignored. */
967 + int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, *
968 + * if signal is required, this field contains signal *
969 + * number which would be sent. *
970 + * In other command, this field is ignored. */
971 +};
972 +
973 +/*
974 + * ####################################
975 + * Data Type
976 + * ####################################
977 + */
978 +typedef void (*timer_callback)(unsigned long arg);
979 +
980 +extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long);
981 +extern int lq_free_timer(unsigned int);
982 +extern int lq_start_timer(unsigned int, int);
983 +extern int lq_stop_timer(unsigned int);
984 +extern int lq_reset_counter_flags(u32 timer, u32 flags);
985 +extern int lq_get_count_value(unsigned int, unsigned long *);
986 +extern u32 lq_cal_divider(unsigned long);
987 +extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long);
988 +extern int lq_set_counter(unsigned int timer, unsigned int flag,
989 + u32 reload, unsigned long arg1, unsigned long arg2);
990 +
991 +#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */
992 --- a/arch/mips/lantiq/xway/Makefile
993 +++ b/arch/mips/lantiq/xway/Makefile
994 @@ -1,4 +1,4 @@
995 -obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o
996 +obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o timer.o
997
998 obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o
999 obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o
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