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[s3c24xx] Replace gta02 led driver with generic gpio led driver.
[openwrt.git] / target / linux / coldfire / patches / 023-mcfv4e_cache_base_update.patch
1 From 3592cd3db82e5b010df590079f1e310b5d317248 Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Mon, 3 Dec 2007 23:03:07 -0700
4 Subject: [PATCH] Rewrite Coldfire cache code.
5
6 LTIBName: mcfv4e-cache-base-update
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
8 ---
9 arch/m68k/coldfire/cache.c | 196 +-------------
10 arch/m68k/coldfire/head.S | 6 +-
11 arch/m68k/coldfire/signal.c | 4 +-
12 arch/m68k/kernel/sys_m68k.c | 16 ++
13 arch/m68k/mm/cache.c | 31 +---
14 arch/m68k/mm/memory.c | 76 +-----
15 include/asm-m68k/cf_cacheflush.h | 525 +++++++++++++++++++++++++++++---------
16 include/asm-m68k/cfcache.h | 95 ++++----
17 8 files changed, 495 insertions(+), 454 deletions(-)
18
19 --- a/arch/m68k/coldfire/cache.c
20 +++ b/arch/m68k/coldfire/cache.c
21 @@ -1,7 +1,8 @@
22 /*
23 - * linux/arch/m68k/coldifre/cache.c
24 + * linux/arch/m68k/coldfire/cache.c
25 *
26 * Matt Waddel Matt.Waddel@freescale.com
27 + * Kurt Mahan kmahan@freescale.com
28 * Copyright Freescale Semiconductor, Inc. 2007
29 *
30 * This program is free software; you can redistribute it and/or modify
31 @@ -15,191 +16,13 @@
32 #include <asm/coldfire.h>
33 #include <asm/system.h>
34
35 -#define _DCACHE_SIZE (2*16384)
36 -#define _ICACHE_SIZE (2*16384)
37 -
38 -#define _SET_SHIFT 4
39 -
40 -/*
41 - * Masks for cache sizes. Programming note: because the set size is a
42 - * power of two, the mask is also the last address in the set.
43 - */
44 -
45 -#define _DCACHE_SET_MASK ((_DCACHE_SIZE/64-1)<<_SET_SHIFT)
46 -#define _ICACHE_SET_MASK ((_ICACHE_SIZE/64-1)<<_SET_SHIFT)
47 -#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
48 -#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
49 -
50 -/************************************************************
51 - * Routine to cleanly flush the cache, pushing all lines and
52 - * invalidating them.
53 - *
54 - * The is the flash-resident version, used after copying the .text
55 - * segment from flash to ram.
56 - *************************************************************/
57 -void FLASHDcacheFlushInvalidate(void)
58 - __attribute__ ((section (".text_loader")));
59 -
60 -void FLASHDcacheFlushInvalidate()
61 -{
62 - unsigned long set;
63 - unsigned long start_set;
64 - unsigned long end_set;
65 -
66 - start_set = 0;
67 - end_set = (unsigned long)LAST_DCACHE_ADDR;
68 -
69 - for (set = start_set; set < end_set; set += (0x10 - 3))
70 - asm volatile("cpushl %%dc,(%0)\n"
71 - "\taddq%.l #1,%0\n"
72 - "\tcpushl %%dc,(%0)\n"
73 - "\taddq%.l #1,%0\n"
74 - "\tcpushl %%dc,(%0)\n"
75 - "\taddq%.l #1,%0\n"
76 - "\tcpushl %%dc,(%0)" : : "a" (set));
77 -}
78 -
79 -/************************************************************
80 - * Routine to cleanly flush the cache, pushing all lines and
81 - * invalidating them.
82 - *
83 - *************************************************************/
84 -void DcacheFlushInvalidate()
85 -{
86 - unsigned long set;
87 - unsigned long start_set;
88 - unsigned long end_set;
89 -
90 - start_set = 0;
91 - end_set = (unsigned long)LAST_DCACHE_ADDR;
92 -
93 - for (set = start_set; set < end_set; set += (0x10 - 3))
94 - asm volatile("cpushl %%dc,(%0)\n"
95 - "\taddq%.l #1,%0\n"
96 - "\tcpushl %%dc,(%0)\n"
97 - "\taddq%.l #1,%0\n"
98 - "\tcpushl %%dc,(%0)\n"
99 - "\taddq%.l #1,%0\n"
100 - "\tcpushl %%dc,(%0)" : : "a" (set));
101 -}
102 -
103 -
104 -
105 -/******************************************************************************
106 - * Routine to cleanly flush the a block of cache, pushing all relevant lines
107 - * and invalidating them.
108 - *
109 - ******************************************************************************/
110 -void DcacheFlushInvalidateCacheBlock(void *start, unsigned long size)
111 -{
112 - unsigned long set;
113 - unsigned long start_set;
114 - unsigned long end_set;
115 -
116 - /* if size is bigger than the cache can store
117 - * set the size to the maximum amount
118 - */
119 -
120 - if (size > LAST_DCACHE_ADDR)
121 - size = LAST_DCACHE_ADDR;
122 -
123 - start_set = ((unsigned long)start) & _DCACHE_SET_MASK;
124 - end_set = ((unsigned long)(start+size-1)) & _DCACHE_SET_MASK;
125 -
126 - if (start_set > end_set) {
127 - /* from the begining to the lowest address */
128 - for (set = 0; set <= end_set; set += (0x10 - 3))
129 - asm volatile("cpushl %%dc,(%0)\n"
130 - "\taddq%.l #1,%0\n"
131 - "\tcpushl %%dc,(%0)\n"
132 - "\taddq%.l #1,%0\n"
133 - "\tcpushl %%dc,(%0)\n"
134 - "\taddq%.l #1,%0\n"
135 - "\tcpushl %%dc,(%0)" : : "a" (set));
136 -
137 - /* next loop will finish the cache ie pass the hole */
138 - end_set = LAST_DCACHE_ADDR;
139 - }
140 - for (set = start_set; set <= end_set; set += (0x10 - 3))
141 - asm volatile("cpushl %%dc,(%0)\n"
142 - "\taddq%.l #1,%0\n"
143 - "\tcpushl %%dc,(%0)\n"
144 - "\taddq%.l #1,%0\n"
145 - "\tcpushl %%dc,(%0)\n"
146 - "\taddq%.l #1,%0\n"
147 - "\tcpushl %%dc,(%0)" : : "a" (set));
148 -}
149 -
150 -
151 -void IcacheInvalidateCacheBlock(void *start, unsigned long size)
152 -{
153 - unsigned long set;
154 - unsigned long start_set;
155 - unsigned long end_set;
156 -
157 - /* if size is bigger than the cache can store
158 - * set the size to the maximum ammount
159 - */
160 -
161 - if (size > LAST_ICACHE_ADDR)
162 - size = LAST_ICACHE_ADDR;
163 -
164 - start_set = ((unsigned long)start) & _ICACHE_SET_MASK;
165 - end_set = ((unsigned long)(start+size-1)) & _ICACHE_SET_MASK;
166 -
167 - if (start_set > end_set) {
168 - /* from the begining to the lowest address */
169 - for (set = 0; set <= end_set; set += (0x10 - 3))
170 - asm volatile("cpushl %%ic,(%0)\n"
171 - "\taddq%.l #1,%0\n"
172 - "\tcpushl %%ic,(%0)\n"
173 - "\taddq%.l #1,%0\n"
174 - "\tcpushl %%ic,(%0)\n"
175 - "\taddq%.l #1,%0\n"
176 - "\tcpushl %%ic,(%0)" : : "a" (set));
177 -
178 - /* next loop will finish the cache ie pass the hole */
179 - end_set = LAST_ICACHE_ADDR;
180 - }
181 - for (set = start_set; set <= end_set; set += (0x10 - 3))
182 - asm volatile("cpushl %%ic,(%0)\n"
183 - "\taddq%.l #1,%0\n"
184 - "\tcpushl %%ic,(%0)\n"
185 - "\taddq%.l #1,%0\n"
186 - "\tcpushl %%ic,(%0)\n"
187 - "\taddq%.l #1,%0\n"
188 - "\tcpushl %%ic,(%0)" : : "a" (set));
189 -}
190 -
191 -
192 -/********************************************************************
193 - * Disable the data cache completely
194 - ********************************************************************/
195 -void DcacheDisable(void)
196 -{
197 - int newValue;
198 - unsigned long flags;
199 -
200 - local_save_flags(flags);
201 - local_irq_disable();
202 -
203 - DcacheFlushInvalidate(); /* begin by flushing the cache */
204 - newValue = CACHE_DISABLE_MODE; /* disable it */
205 - cacr_set(newValue);
206 - local_irq_restore(flags);
207 -}
208 -
209 -/********************************************************************
210 - * Unconditionally enable the data cache
211 - ********************************************************************/
212 -void DcacheEnable(void)
213 -{
214 - cacr_set(CACHE_INITIAL_MODE);
215 -}
216 -
217 -
218 +/* Cache Control Reg shadow reg */
219 unsigned long shadow_cacr;
220
221 +/**
222 + * cacr_set - Set the Cache Control Register
223 + * @x Value to set
224 + */
225 void cacr_set(unsigned long x)
226 {
227 shadow_cacr = x;
228 @@ -209,6 +32,11 @@ void cacr_set(unsigned long x)
229 : "r" (shadow_cacr));
230 }
231
232 +/**
233 + * cacr_get - Get the current value of the Cache Control Register
234 + *
235 + * @return CACR value
236 + */
237 unsigned long cacr_get(void)
238 {
239 return shadow_cacr;
240 --- a/arch/m68k/coldfire/head.S
241 +++ b/arch/m68k/coldfire/head.S
242 @@ -244,7 +244,7 @@ ENTRY(__start)
243 /* Setup initial stack pointer */
244 movel #0x40001000,%sp
245
246 -/* Clear usp */
247 +/* Setup usp */
248 subl %a0,%a0
249 movel %a0,%usp
250
251 @@ -252,6 +252,10 @@ ENTRY(__start)
252 movec %d0, %rambar1
253 movew #0x2700,%sr
254
255 +/* reset cache */
256 + movel #(CF_CACR_ICINVA + CF_CACR_DCINVA),%d0
257 + movecl %d0,%cacr
258 +
259 movel #(MMU_BASE+1),%d0
260 movecl %d0,%mmubar
261 movel #MMUOR_CA,%a0 /* Clear tlb entries */
262 --- a/arch/m68k/coldfire/signal.c
263 +++ b/arch/m68k/coldfire/signal.c
264 @@ -37,6 +37,7 @@
265 #include <asm/cf_pgtable.h>
266 #include <asm/traps.h>
267 #include <asm/ucontext.h>
268 +#include <asm/cacheflush.h>
269
270 #define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
271
272 @@ -605,10 +606,9 @@ static inline int rt_setup_ucontext(stru
273 return err;
274 }
275
276 -extern void IcacheInvalidateCacheBlock(void *, unsigned long);
277 static inline void push_cache(unsigned long vaddr)
278 {
279 - IcacheInvalidateCacheBlock((void *)vaddr, 8);
280 + cf_cache_push(__pa(vaddr), 8);
281 }
282
283 static inline void __user *
284 --- a/arch/m68k/kernel/sys_m68k.c
285 +++ b/arch/m68k/kernel/sys_m68k.c
286 @@ -29,6 +29,9 @@
287 #include <asm/traps.h>
288 #include <asm/page.h>
289 #include <asm/unistd.h>
290 +#ifdef CONFIG_COLDFIRE
291 +#include <asm/cacheflush.h>
292 +#endif
293
294 /*
295 * sys_pipe() is the normal C calling standard for creating
296 @@ -257,6 +260,7 @@ asmlinkage int sys_ipc (uint call, int f
297 return -EINVAL;
298 }
299
300 +#ifndef CONFIG_COLDFIRE
301 /* Convert virtual (user) address VADDR to physical address PADDR */
302 #define virt_to_phys_040(vaddr) \
303 ({ \
304 @@ -580,6 +584,7 @@ cache_flush_060 (unsigned long addr, int
305 }
306 return 0;
307 }
308 +#endif /* CONFIG_COLDFIRE */
309
310 /* sys_cacheflush -- flush (part of) the processor cache. */
311 asmlinkage int
312 @@ -612,6 +617,7 @@ sys_cacheflush (unsigned long addr, int
313 goto out;
314 }
315
316 +#ifndef CONFIG_COLDFIRE
317 if (CPU_IS_020_OR_030) {
318 if (scope == FLUSH_SCOPE_LINE && len < 256) {
319 unsigned long cacr;
320 @@ -656,6 +662,16 @@ sys_cacheflush (unsigned long addr, int
321 ret = cache_flush_060 (addr, scope, cache, len);
322 }
323 }
324 +#else /* CONFIG_COLDFIRE */
325 + if ((cache & FLUSH_CACHE_INSN) && (cache & FLUSH_CACHE_DATA))
326 + flush_bcache();
327 + else if (cache & FLUSH_CACHE_INSN)
328 + flush_icache();
329 + else
330 + flush_dcache();
331 +
332 + ret = 0;
333 +#endif /* CONFIG_COLDFIRE */
334 out:
335 unlock_kernel();
336 return ret;
337 --- a/arch/m68k/mm/cache.c
338 +++ b/arch/m68k/mm/cache.c
339 @@ -81,36 +81,7 @@ static unsigned long virt_to_phys_slow(u
340 void flush_icache_range(unsigned long address, unsigned long endaddr)
341 {
342 #ifdef CONFIG_COLDFIRE
343 - unsigned long set;
344 - unsigned long start_set;
345 - unsigned long end_set;
346 -
347 - start_set = address & _ICACHE_SET_MASK;
348 - end_set = endaddr & _ICACHE_SET_MASK;
349 -
350 - if (start_set > end_set) {
351 - /* from the begining to the lowest address */
352 - for (set = 0; set <= end_set; set += (0x10 - 3))
353 - asm volatile ("cpushl %%ic,(%0)\n"
354 - "\taddq%.l #1,%0\n"
355 - "\tcpushl %%ic,(%0)\n"
356 - "\taddq%.l #1,%0\n"
357 - "\tcpushl %%ic,(%0)\n"
358 - "\taddq%.l #1,%0\n"
359 - "\tcpushl %%ic,(%0)" : : "a" (set));
360 -
361 - /* next loop will finish the cache ie pass the hole */
362 - end_set = LAST_ICACHE_ADDR;
363 - }
364 - for (set = start_set; set <= end_set; set += (0x10 - 3))
365 - asm volatile ("cpushl %%ic,(%0)\n"
366 - "\taddq%.l #1,%0\n"
367 - "\tcpushl %%ic,(%0)\n"
368 - "\taddq%.l #1,%0\n"
369 - "\tcpushl %%ic,(%0)\n"
370 - "\taddq%.l #1,%0\n"
371 - "\tcpushl %%ic,(%0)" : : "a" (set));
372 -
373 + cf_icache_flush_range(address, endaddr);
374 #else /* !CONFIG_COLDFIRE */
375
376 if (CPU_IS_040_OR_060) {
377 --- a/arch/m68k/mm/memory.c
378 +++ b/arch/m68k/mm/memory.c
379 @@ -127,6 +127,7 @@ int free_pointer_table (pmd_t *ptable)
380 return 0;
381 }
382
383 +#ifndef CONFIG_COLDFIRE
384 /* invalidate page in both caches */
385 static inline void clear040(unsigned long paddr)
386 {
387 @@ -173,6 +174,7 @@ static inline void pushcl040(unsigned lo
388 clear040(paddr);
389 local_irq_restore(flags);
390 }
391 +#endif /* CONFIG_COLDFIRE */
392
393 /*
394 * 040: Hit every page containing an address in the range paddr..paddr+len-1.
395 @@ -203,38 +205,10 @@ static inline void pushcl040(unsigned lo
396
397 void cache_clear (unsigned long paddr, int len)
398 {
399 - if (CPU_IS_CFV4E) {
400 - unsigned long set;
401 - unsigned long start_set;
402 - unsigned long end_set;
403 -
404 - start_set = paddr & _ICACHE_SET_MASK;
405 - end_set = (paddr+len-1) & _ICACHE_SET_MASK;
406 -
407 - if (start_set > end_set) {
408 - /* from the begining to the lowest address */
409 - for (set = 0; set <= end_set; set += (0x10 - 3))
410 - asm volatile("cpushl %%bc,(%0)\n"
411 - "\taddq%.l #1,%0\n"
412 - "\tcpushl %%bc,(%0)\n"
413 - "\taddq%.l #1,%0\n"
414 - "\tcpushl %%bc,(%0)\n"
415 - "\taddq%.l #1,%0\n"
416 - "\tcpushl %%bc,(%0)" : : "a" (set));
417 -
418 - /* next loop will finish the cache ie pass the hole */
419 - end_set = LAST_ICACHE_ADDR;
420 - }
421 - for (set = start_set; set <= end_set; set += (0x10 - 3))
422 - asm volatile("cpushl %%bc,(%0)\n"
423 - "\taddq%.l #1,%0\n"
424 - "\tcpushl %%bc,(%0)\n"
425 - "\taddq%.l #1,%0\n"
426 - "\tcpushl %%bc,(%0)\n"
427 - "\taddq%.l #1,%0\n"
428 - "\tcpushl %%bc,(%0)" : : "a" (set));
429 -
430 - } else if (CPU_IS_040_OR_060) {
431 +#ifdef CONFIG_COLDFIRE
432 + cf_cache_clear(paddr, len);
433 +#else
434 + if (CPU_IS_040_OR_060) {
435 int tmp;
436
437 /*
438 @@ -268,6 +242,7 @@ void cache_clear (unsigned long paddr, i
439 if(mach_l2_flush)
440 mach_l2_flush(0);
441 #endif
442 +#endif /* CONFIG_COLDFIRE */
443 }
444 EXPORT_SYMBOL(cache_clear);
445
446 @@ -281,38 +256,10 @@ EXPORT_SYMBOL(cache_clear);
447
448 void cache_push (unsigned long paddr, int len)
449 {
450 - if (CPU_IS_CFV4E) {
451 - unsigned long set;
452 - unsigned long start_set;
453 - unsigned long end_set;
454 -
455 - start_set = paddr & _ICACHE_SET_MASK;
456 - end_set = (paddr+len-1) & _ICACHE_SET_MASK;
457 -
458 - if (start_set > end_set) {
459 - /* from the begining to the lowest address */
460 - for (set = 0; set <= end_set; set += (0x10 - 3))
461 - asm volatile("cpushl %%bc,(%0)\n"
462 - "\taddq%.l #1,%0\n"
463 - "\tcpushl %%bc,(%0)\n"
464 - "\taddq%.l #1,%0\n"
465 - "\tcpushl %%bc,(%0)\n"
466 - "\taddq%.l #1,%0\n"
467 - "\tcpushl %%bc,(%0)" : : "a" (set));
468 -
469 - /* next loop will finish the cache ie pass the hole */
470 - end_set = LAST_ICACHE_ADDR;
471 - }
472 - for (set = start_set; set <= end_set; set += (0x10 - 3))
473 - asm volatile("cpushl %%bc,(%0)\n"
474 - "\taddq%.l #1,%0\n"
475 - "\tcpushl %%bc,(%0)\n"
476 - "\taddq%.l #1,%0\n"
477 - "\tcpushl %%bc,(%0)\n"
478 - "\taddq%.l #1,%0\n"
479 - "\tcpushl %%bc,(%0)" : : "a" (set));
480 -
481 - } else if (CPU_IS_040_OR_060) {
482 +#ifdef CONFIG_COLDFIRE
483 + cf_cache_push(paddr, len);
484 +#else
485 + if (CPU_IS_040_OR_060) {
486 int tmp = PAGE_SIZE;
487
488 /*
489 @@ -352,6 +299,7 @@ void cache_push (unsigned long paddr, in
490 if(mach_l2_flush)
491 mach_l2_flush(1);
492 #endif
493 +#endif /* CONFIG_COLDFIRE */
494 }
495 EXPORT_SYMBOL(cache_push);
496
497 --- a/include/asm-m68k/cf_cacheflush.h
498 +++ b/include/asm-m68k/cf_cacheflush.h
499 @@ -1,160 +1,439 @@
500 +/*
501 + * include/asm-m68k/cf_cacheflush.h - Coldfire Cache
502 + *
503 + * Based on include/asm-m68k/cacheflush.h
504 + *
505 + * Coldfire pieces by:
506 + * Kurt Mahan kmahan@freescale.com
507 + *
508 + * Copyright Freescale Semiconductor, Inc. 2007
509 + *
510 + * This program is free software; you can redistribute it and/or modify it
511 + * under the terms of the GNU General Public License as published by the
512 + * Free Software Foundation; either version 2 of the License, or (at your
513 + * option) any later version.
514 + */
515 #ifndef M68K_CF_CACHEFLUSH_H
516 #define M68K_CF_CACHEFLUSH_H
517
518 #include <asm/cfcache.h>
519
520 /*
521 - * Cache handling functions
522 + * Coldfire Cache Model
523 + *
524 + * The Coldfire processors use a Harvard architecture cache configured
525 + * as four-way set associative. The cache does not implement bus snooping
526 + * so cache coherency with other masters must be maintained in software.
527 + *
528 + * The cache is managed via the CPUSHL instruction in conjunction with
529 + * bits set in the CACR (cache control register). Currently the code
530 + * uses the CPUSHL enhancement which adds the ability to
531 + * invalidate/clear/push a cacheline by physical address. This feature
532 + * is designated in the Hardware Configuration Register [D1-CPES].
533 + *
534 + * CACR Bits:
535 + * DPI[28] cpushl invalidate disable for d-cache
536 + * IDPI[12] cpushl invalidate disable for i-cache
537 + * SPA[14] cpushl search by physical address
538 + * IVO[20] cpushl invalidate only
539 + *
540 + * Random Terminology:
541 + * * invalidate = reset the cache line's valid bit
542 + * * push = generate a line-sized store of the data if its contents are marked
543 + * as modifed (the modified flag is cleared after the store)
544 + * * clear = push + invalidate
545 */
546
547 -#define flush_icache() \
548 -({ \
549 - unsigned long set; \
550 - unsigned long start_set; \
551 - unsigned long end_set; \
552 - \
553 - start_set = 0; \
554 - end_set = (unsigned long)LAST_DCACHE_ADDR; \
555 - \
556 - for (set = start_set; set <= end_set; set += (0x10 - 3)) \
557 - asm volatile("cpushl %%ic,(%0)\n" \
558 - "\taddq%.l #1,%0\n" \
559 - "\tcpushl %%ic,(%0)\n" \
560 - "\taddq%.l #1,%0\n" \
561 - "\tcpushl %%ic,(%0)\n" \
562 - "\taddq%.l #1,%0\n" \
563 - "\tcpushl %%ic,(%0)" : : "a" (set)); \
564 -})
565 +/**
566 + * flush_icache - Flush all of the instruction cache
567 + */
568 +static inline void flush_icache(void)
569 +{
570 + asm volatile("nop\n"
571 + "moveq%.l #0,%%d0\n"
572 + "moveq%.l #0,%%d1\n"
573 + "move%.l %%d0,%%a0\n"
574 + "1:\n"
575 + "cpushl %%ic,(%%a0)\n"
576 + "add%.l #0x0010,%%a0\n"
577 + "addq%.l #1,%%d1\n"
578 + "cmpi%.l %0,%%d1\n"
579 + "bne 1b\n"
580 + "moveq%.l #0,%%d1\n"
581 + "addq%.l #1,%%d0\n"
582 + "move%.l %%d0,%%a0\n"
583 + "cmpi%.l #4,%%d0\n"
584 + "bne 1b\n"
585 + : : "i" (CACHE_SETS)
586 + : "a0", "d0", "d1");
587 +}
588
589 -/*
590 - * invalidate the cache for the specified memory range.
591 - * It starts at the physical address specified for
592 - * the given number of bytes.
593 +/**
594 + * flush_dcache - Flush all of the data cache
595 */
596 -extern void cache_clear(unsigned long paddr, int len);
597 -/*
598 - * push any dirty cache in the specified memory range.
599 - * It starts at the physical address specified for
600 - * the given number of bytes.
601 +static inline void flush_dcache(void)
602 +{
603 + asm volatile("nop\n"
604 + "moveq%.l #0,%%d0\n"
605 + "moveq%.l #0,%%d1\n"
606 + "move%.l %%d0,%%a0\n"
607 + "1:\n"
608 + "cpushl %%dc,(%%a0)\n"
609 + "add%.l #0x0010,%%a0\n"
610 + "addq%.l #1,%%d1\n"
611 + "cmpi%.l %0,%%d1\n"
612 + "bne 1b\n"
613 + "moveq%.l #0,%%d1\n"
614 + "addq%.l #1,%%d0\n"
615 + "move%.l %%d0,%%a0\n"
616 + "cmpi%.l #4,%%d0\n"
617 + "bne 1b\n"
618 + : : "i" (CACHE_SETS)
619 + : "a0", "d0", "d1");
620 +}
621 +
622 +/**
623 + * flush_bcache - Flush all of both caches
624 */
625 -extern void cache_push(unsigned long paddr, int len);
626 +static inline void flush_bcache(void)
627 +{
628 + asm volatile("nop\n"
629 + "moveq%.l #0,%%d0\n"
630 + "moveq%.l #0,%%d1\n"
631 + "move%.l %%d0,%%a0\n"
632 + "1:\n"
633 + "cpushl %%bc,(%%a0)\n"
634 + "add%.l #0x0010,%%a0\n"
635 + "addq%.l #1,%%d1\n"
636 + "cmpi%.l %0,%%d1\n"
637 + "bne 1b\n"
638 + "moveq%.l #0,%%d1\n"
639 + "addq%.l #1,%%d0\n"
640 + "move%.l %%d0,%%a0\n"
641 + "cmpi%.l #4,%%d0\n"
642 + "bne 1b\n"
643 + : : "i" (CACHE_SETS)
644 + : "a0", "d0", "d1");
645 +}
646
647 -/*
648 - * push and invalidate pages in the specified user virtual
649 - * memory range.
650 +/**
651 + * cf_cache_clear - invalidate cache
652 + * @paddr: starting physical address
653 + * @len: number of bytes
654 + *
655 + * Invalidate cache lines starting at paddr for len bytes.
656 + * Those lines are not pushed.
657 + */
658 +static inline void cf_cache_clear(unsigned long paddr, int len)
659 +{
660 + /* number of lines */
661 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
662 +
663 + /* align on set boundary */
664 + paddr &= 0xfffffff0;
665 +
666 + asm volatile("nop\n"
667 + "move%.l %2,%%d0\n"
668 + "or%.l %3,%%d0\n"
669 + "movec %%d0,%%cacr\n"
670 + "move%.l %0,%%a0\n"
671 + "move%.l %1,%%d0\n"
672 + "1:\n"
673 + "cpushl %%bc,(%%a0)\n"
674 + "lea 0x10(%%a0),%%a0\n"
675 + "subq%.l #1,%%d0\n"
676 + "bne%.b 1b\n"
677 + "movec %2,%%cacr\n"
678 + : : "a" (paddr), "r" (len),
679 + "r" (shadow_cacr),
680 + "i" (CF_CACR_SPA+CF_CACR_IVO)
681 + : "a0", "d0");
682 +}
683 +
684 +/**
685 + * cf_cache_push - Push dirty cache out with no invalidate
686 + * @paddr: starting physical address
687 + * @len: number of bytes
688 + *
689 + * Push the any dirty lines starting at paddr for len bytes.
690 + * Those lines are not invalidated.
691 + */
692 +static inline void cf_cache_push(unsigned long paddr, int len)
693 +{
694 + /* number of lines */
695 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
696 +
697 + /* align on set boundary */
698 + paddr &= 0xfffffff0;
699 +
700 + asm volatile("nop\n"
701 + "move%.l %2,%%d0\n"
702 + "or%.l %3,%%d0\n"
703 + "movec %%d0,%%cacr\n"
704 + "move%.l %0,%%a0\n"
705 + "move%.l %1,%%d0\n"
706 + "1:\n"
707 + "cpushl %%bc,(%%a0)\n"
708 + "lea 0x10(%%a0),%%a0\n"
709 + "subq%.l #1,%%d0\n"
710 + "bne.b 1b\n"
711 + "movec %2,%%cacr\n"
712 + : : "a" (paddr), "r" (len),
713 + "r" (shadow_cacr),
714 + "i" (CF_CACR_SPA+CF_CACR_DPI+CF_CACR_IDPI)
715 + : "a0", "d0");
716 +}
717 +
718 +/**
719 + * cf_cache_flush - Push dirty cache out and invalidate
720 + * @paddr: starting physical address
721 + * @len: number of bytes
722 + *
723 + * Push the any dirty lines starting at paddr for len bytes and
724 + * invalidate those lines.
725 + */
726 +static inline void cf_cache_flush(unsigned long paddr, int len)
727 +{
728 + /* number of lines */
729 + len = (len + (CACHE_LINE_SIZE-1)) / CACHE_LINE_SIZE;
730 +
731 + /* align on set boundary */
732 + paddr &= 0xfffffff0;
733 +
734 + asm volatile("nop\n"
735 + "move%.l %2,%%d0\n"
736 + "or%.l %3,%%d0\n"
737 + "movec %%d0,%%cacr\n"
738 + "move%.l %0,%%a0\n"
739 + "move%.l %1,%%d0\n"
740 + "1:\n"
741 + "cpushl %%bc,(%%a0)\n"
742 + "lea 0x10(%%a0),%%a0\n"
743 + "subq%.l #1,%%d0\n"
744 + "bne.b 1b\n"
745 + "movec %2,%%cacr\n"
746 + : : "a" (paddr), "r" (len),
747 + "r" (shadow_cacr),
748 + "i" (CF_CACR_SPA)
749 + : "a0", "d0");
750 +}
751 +
752 +/**
753 + * cf_cache_flush_range - Push dirty data/inst cache in range out and invalidate
754 + * @vstart - starting virtual address
755 + * @vend: ending virtual address
756 + *
757 + * Push the any dirty data/instr lines starting at paddr for len bytes and
758 + * invalidate those lines.
759 + */
760 +static inline void cf_cache_flush_range(unsigned long vstart, unsigned long vend)
761 +{
762 + int len;
763 +
764 + /* align on set boundary */
765 + vstart &= 0xfffffff0;
766 + vend = PAGE_ALIGN((vend + (CACHE_LINE_SIZE-1))) & 0xfffffff0;
767 + len = vend - vstart;
768 + vstart = __pa(vstart);
769 + vend = vstart + len;
770 +
771 + asm volatile("nop\n"
772 + "move%.l %2,%%d0\n"
773 + "or%.l %3,%%d0\n"
774 + "movec %%d0,%%cacr\n"
775 + "move%.l %0,%%a0\n"
776 + "move%.l %1,%%a1\n"
777 + "1:\n"
778 + "cpushl %%bc,(%%a0)\n"
779 + "lea 0x10(%%a0),%%a0\n"
780 + "cmpa%.l %%a0,%%a1\n"
781 + "bne.b 1b\n"
782 + "movec %2,%%cacr\n"
783 + : /* no return */
784 + : "a" (vstart), "a" (vend),
785 + "r" (shadow_cacr),
786 + "i" (CF_CACR_SPA)
787 + : "a0", "a1", "d0");
788 +}
789 +
790 +/**
791 + * cf_dcache_flush_range - Push dirty data cache in range out and invalidate
792 + * @vstart - starting virtual address
793 + * @vend: ending virtual address
794 + *
795 + * Push the any dirty data lines starting at paddr for len bytes and
796 + * invalidate those lines.
797 + */
798 +static inline void cf_dcache_flush_range(unsigned long vstart, unsigned long vend)
799 +{
800 + /* align on set boundary */
801 + vstart &= 0xfffffff0;
802 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
803 +
804 + asm volatile("nop\n"
805 + "move%.l %2,%%d0\n"
806 + "or%.l %3,%%d0\n"
807 + "movec %%d0,%%cacr\n"
808 + "move%.l %0,%%a0\n"
809 + "move%.l %1,%%a1\n"
810 + "1:\n"
811 + "cpushl %%dc,(%%a0)\n"
812 + "lea 0x10(%%a0),%%a0\n"
813 + "cmpa%.l %%a0,%%a1\n"
814 + "bne.b 1b\n"
815 + "movec %2,%%cacr\n"
816 + : /* no return */
817 + : "a" (__pa(vstart)), "a" (__pa(vend)),
818 + "r" (shadow_cacr),
819 + "i" (CF_CACR_SPA)
820 + : "a0", "a1", "d0");
821 +}
822 +
823 +/**
824 + * cf_icache_flush_range - Push dirty inst cache in range out and invalidate
825 + * @vstart - starting virtual address
826 + * @vend: ending virtual address
827 + *
828 + * Push the any dirty instr lines starting at paddr for len bytes and
829 + * invalidate those lines. This should just be an invalidate since you
830 + * shouldn't be able to have dirty instruction cache.
831 */
832 -extern void cache_push_v(unsigned long vaddr, int len);
833 +static inline void cf_icache_flush_range(unsigned long vstart, unsigned long vend)
834 +{
835 + /* align on set boundary */
836 + vstart &= 0xfffffff0;
837 + vend = (vend + (CACHE_LINE_SIZE-1)) & 0xfffffff0;
838 +
839 + asm volatile("nop\n"
840 + "move%.l %2,%%d0\n"
841 + "or%.l %3,%%d0\n"
842 + "movec %%d0,%%cacr\n"
843 + "move%.l %0,%%a0\n"
844 + "move%.l %1,%%a1\n"
845 + "1:\n"
846 + "cpushl %%ic,(%%a0)\n"
847 + "lea 0x10(%%a0),%%a0\n"
848 + "cmpa%.l %%a0,%%a1\n"
849 + "bne.b 1b\n"
850 + "movec %2,%%cacr\n"
851 + : /* no return */
852 + : "a" (__pa(vstart)), "a" (__pa(vend)),
853 + "r" (shadow_cacr),
854 + "i" (CF_CACR_SPA)
855 + : "a0", "a1", "d0");
856 +}
857
858 -/* This is needed whenever the virtual mapping of the current
859 - process changes. */
860 +/**
861 + * flush_cache_mm - Flush an mm_struct
862 + * @mm: mm_struct to flush
863 + */
864 +static inline void flush_cache_mm(struct mm_struct *mm)
865 +{
866 + if (mm == current->mm)
867 + flush_bcache();
868 +}
869
870 +#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
871
872 -#define flush_cache_all() do { } while (0)
873 -#define flush_cache_mm(mm) do { } while (0)
874 -#define flush_cache_range(mm, a, b) do { } while (0)
875 -#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
876 -
877 -#define flush_dcache_range(paddr, len) do { } while (0)
878 -
879 -/* Push the page at kernel virtual address and clear the icache */
880 -/* use cpush %bc instead of cpush %dc, cinv %ic */
881 -#define flush_page_to_ram(page) __flush_page_to_ram((void *) page_address(page))
882 -extern inline void __flush_page_to_ram(void *address)
883 -{
884 - unsigned long set;
885 - unsigned long start_set;
886 - unsigned long end_set;
887 - unsigned long addr = (unsigned long) address;
888 -
889 - addr &= ~(PAGE_SIZE - 1); /* round down to page start address */
890 -
891 - start_set = addr & _ICACHE_SET_MASK;
892 - end_set = (addr + PAGE_SIZE-1) & _ICACHE_SET_MASK;
893 -
894 - if (start_set > end_set) {
895 - /* from the begining to the lowest address */
896 - for (set = 0; set <= end_set; set += (0x10 - 3))
897 - asm volatile("cpushl %%bc,(%0)\n"
898 - "\taddq%.l #1,%0\n"
899 - "\tcpushl %%bc,(%0)\n"
900 - "\taddq%.l #1,%0\n"
901 - "\tcpushl %%bc,(%0)\n"
902 - "\taddq%.l #1,%0\n"
903 - "\tcpushl %%bc,(%0)" : : "a" (set));
904 -
905 - /* next loop will finish the cache ie pass the hole */
906 - end_set = LAST_ICACHE_ADDR;
907 - }
908 - for (set = start_set; set <= end_set; set += (0x10 - 3))
909 - asm volatile("cpushl %%bc,(%0)\n"
910 - "\taddq%.l #1,%0\n"
911 - "\tcpushl %%bc,(%0)\n"
912 - "\taddq%.l #1,%0\n"
913 - "\tcpushl %%bc,(%0)\n"
914 - "\taddq%.l #1,%0\n"
915 - "\tcpushl %%bc,(%0)" : : "a" (set));
916 -}
917 -
918 -#define flush_dcache_page(page) do { } while (0)
919 -#define flush_icache_page(vma, pg) do { } while (0)
920 -#define flush_icache_user_range(adr, len) do { } while (0)
921 -/* NL */
922 -#define flush_icache_user_page(vma, page, addr, len) do { } while (0)
923 -
924 -/* Push n pages at kernel virtual address and clear the icache */
925 -/* use cpush %bc instead of cpush %dc, cinv %ic */
926 -extern inline void flush_icache_range(unsigned long address,
927 - unsigned long endaddr)
928 -{
929 - unsigned long set;
930 - unsigned long start_set;
931 - unsigned long end_set;
932 -
933 - start_set = address & _ICACHE_SET_MASK;
934 - end_set = endaddr & _ICACHE_SET_MASK;
935 -
936 - if (start_set > end_set) {
937 - /* from the begining to the lowest address */
938 - for (set = 0; set <= end_set; set += (0x10 - 3))
939 - asm volatile("cpushl %%ic,(%0)\n"
940 - "\taddq%.l #1,%0\n"
941 - "\tcpushl %%ic,(%0)\n"
942 - "\taddq%.l #1,%0\n"
943 - "\tcpushl %%ic,(%0)\n"
944 - "\taddq%.l #1,%0\n"
945 - "\tcpushl %%ic,(%0)" : : "a" (set));
946 -
947 - /* next loop will finish the cache ie pass the hole */
948 - end_set = LAST_ICACHE_ADDR;
949 - }
950 - for (set = start_set; set <= end_set; set += (0x10 - 3))
951 - asm volatile("cpushl %%ic,(%0)\n"
952 - "\taddq%.l #1,%0\n"
953 - "\tcpushl %%ic,(%0)\n"
954 - "\taddq%.l #1,%0\n"
955 - "\tcpushl %%ic,(%0)\n"
956 - "\taddq%.l #1,%0\n"
957 - "\tcpushl %%ic,(%0)" : : "a" (set));
958 +/**
959 + * flush_cache_range - Flush a cache range
960 + * @vma: vma struct
961 + * @start: Starting address
962 + * @end: Ending address
963 + *
964 + * flush_cache_range must be a macro to avoid a dependency on
965 + * linux/mm.h which includes this file.
966 + */
967 +static inline void flush_cache_range(struct vm_area_struct *vma,
968 + unsigned long start, unsigned long end)
969 +{
970 + if (vma->vm_mm == current->mm)
971 + cf_cache_flush_range(start, end);
972 }
973
974 +/**
975 + * flush_cache_page - Flush a page of the cache
976 + * @vma: vma struct
977 + * @vmaddr:
978 + * @pfn: page numer
979 + *
980 + * flush_cache_page must be a macro to avoid a dependency on
981 + * linux/mm.h which includes this file.
982 + */
983 +static inline void flush_cache_page(struct vm_area_struct *vma,
984 + unsigned long vmaddr, unsigned long pfn)
985 +{
986 + if (vma->vm_mm == current->mm)
987 + cf_cache_flush_range(vmaddr, vmaddr+PAGE_SIZE);
988 +}
989 +
990 +/**
991 + * __flush_page_to_ram - Push a page out of the cache
992 + * @vaddr: Virtual address at start of page
993 + *
994 + * Push the page at kernel virtual address *vaddr* and clear
995 + * the icache.
996 + */
997 +static inline void __flush_page_to_ram(void *vaddr)
998 +{
999 + asm volatile("nop\n"
1000 + "move%.l %2,%%d0\n"
1001 + "or%.l %3,%%d0\n"
1002 + "movec %%d0,%%cacr\n"
1003 + "move%.l %0,%%d0\n"
1004 + "and%.l #0xfffffff0,%%d0\n"
1005 + "move%.l %%d0,%%a0\n"
1006 + "move%.l %1,%%d0\n"
1007 + "1:\n"
1008 + "cpushl %%bc,(%%a0)\n"
1009 + "lea 0x10(%%a0),%%a0\n"
1010 + "subq%.l #1,%%d0\n"
1011 + "bne.b 1b\n"
1012 + "movec %2,%%cacr\n"
1013 + : : "a" (__pa(vaddr)), "i" (PAGE_SIZE / CACHE_LINE_SIZE),
1014 + "r" (shadow_cacr), "i" (CF_CACR_SPA)
1015 + : "a0", "d0");
1016 +}
1017 +
1018 +/*
1019 + * Various defines for the kernel.
1020 + */
1021 +
1022 +extern void cache_clear(unsigned long paddr, int len);
1023 +extern void cache_push(unsigned long paddr, int len);
1024 +extern void flush_icache_range(unsigned long address, unsigned long endaddr);
1025 +
1026 +#define flush_cache_all() flush_bcache()
1027 +#define flush_cache_vmap(start, end) flush_bcache()
1028 +#define flush_cache_vunmap(start, end) flush_bcache()
1029 +
1030 +#define flush_dcache_range(vstart, vend) cf_dcache_flush_range(vstart, vend)
1031 +#define flush_dcache_page(page) __flush_page_to_ram(page_address(page))
1032 +#define flush_dcache_mmap_lock(mapping) do { } while (0)
1033 +#define flush_dcache_mmap_unlock(mapping) do { } while (0)
1034 +
1035 +#define flush_icache_page(vma, page) __flush_page_to_ram(page_address(page))
1036 +
1037 +/**
1038 + * copy_to_user_page - Copy memory to user page
1039 + */
1040 static inline void copy_to_user_page(struct vm_area_struct *vma,
1041 struct page *page, unsigned long vaddr,
1042 void *dst, void *src, int len)
1043 {
1044 memcpy(dst, src, len);
1045 - flush_icache_user_page(vma, page, vaddr, len);
1046 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
1047 }
1048 +
1049 +/**
1050 + * copy_from_user_page - Copy memory from user page
1051 + */
1052 static inline void copy_from_user_page(struct vm_area_struct *vma,
1053 struct page *page, unsigned long vaddr,
1054 void *dst, void *src, int len)
1055 {
1056 + cf_cache_flush(page_to_phys(page), PAGE_SIZE);
1057 memcpy(dst, src, len);
1058 }
1059
1060 -#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
1061 -#define flush_cache_vmap(start, end) flush_cache_all()
1062 -#define flush_cache_vunmap(start, end) flush_cache_all()
1063 -#define flush_dcache_mmap_lock(mapping) do { } while (0)
1064 -#define flush_dcache_mmap_unlock(mapping) do { } while (0)
1065 -
1066 #endif /* M68K_CF_CACHEFLUSH_H */
1067 --- a/include/asm-m68k/cfcache.h
1068 +++ b/include/asm-m68k/cfcache.h
1069 @@ -1,19 +1,32 @@
1070 /*
1071 - * include/asm-m68k/cfcache.h
1072 + * include/asm-m68k/cfcache.h - Coldfire Cache Controller
1073 + *
1074 + * Kurt Mahan kmahan@freescale.com
1075 + *
1076 + * Copyright Freescale Semiconductor, Inc. 2007
1077 + *
1078 + * This program is free software; you can redistribute it and/or modify it
1079 + * under the terms of the GNU General Public License as published by the
1080 + * Free Software Foundation; either version 2 of the License, or (at your
1081 + * option) any later version.
1082 */
1083 #ifndef CF_CFCACHE_H
1084 #define CF_CFCACHE_H
1085
1086 +/*
1087 + * CACR Cache Control Register
1088 + */
1089 #define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
1090 #define CF_CACR_DW (0x40000000) /* Data default Write-protect */
1091 #define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
1092 -#define CF_CACR_DDPI (0x10000000) /* Data Disable CPUSHL Invalidate */
1093 +#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
1094 #define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
1095 #define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
1096 #define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
1097 #define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
1098 #define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
1099 #define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
1100 +#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
1101 #define CF_CACR_IVO (0x00100000) /* Invalidate only */
1102 #define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
1103 #define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
1104 @@ -24,61 +37,43 @@
1105 #define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
1106 #define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
1107 #define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
1108 +#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
1109 #define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
1110
1111 -#define DCACHE_LINE_SIZE 0x0010 /* bytes per line */
1112 -#define DCACHE_WAY_SIZE 0x2000 /* words per cache block */
1113 -#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+CF_CACR_BCINVA+CF_CACR_ICINVA)
1114 -#ifdef CONFIG_M5445X_DISABLE_CACHE
1115 -/* disable cache for testing rev0 silicon */
1116 -#define CACHE_INITIAL_MODE (CF_CACR_EUSP)
1117 -#else
1118 -#define CACHE_INITIAL_MODE (CF_CACR_DEC+CF_CACR_BEC+CF_CACR_IEC+CF_CACR_EUSP)
1119 -#endif
1120 -
1121 -#define _DCACHE_SIZE (2*16384)
1122 -#define _ICACHE_SIZE (2*16384)
1123 -
1124 -#define _SET_SHIFT 4
1125 -
1126 +#ifdef CONFIG_M54455
1127 /*
1128 - * Masks for cache sizes. Programming note: because the set size is a
1129 - * power of two, the mask is also the last address in the set.
1130 - * This may need to be #ifdef for other Coldfire processors.
1131 + * M5445x Cache Configuration
1132 + * - cache line size is 16 bytes
1133 + * - cache is 4-way set associative
1134 + * - each cache has 256 sets (64k / 16bytes / 4way)
1135 + * - I-Cache size is 16KB
1136 + * - D-Cache size is 16KB
1137 */
1138 +#define ICACHE_SIZE 0x4000 /* instruction - 16k */
1139 +#define DCACHE_SIZE 0x4000 /* data - 16k */
1140
1141 -#define _DCACHE_SET_MASK ((_DCACHE_SIZE/64-1)<<_SET_SHIFT)
1142 -#define _ICACHE_SET_MASK ((_ICACHE_SIZE/64-1)<<_SET_SHIFT)
1143 -#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
1144 -#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
1145 -
1146 +#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
1147 +#define CACHE_SETS 0x0100 /* 256 sets */
1148 +#define CACHE_WAYS 0x0004 /* 4 way */
1149 +
1150 +#define CACHE_DISABLE_MODE (CF_CACR_DCINVA+ \
1151 + CF_CACR_BCINVA+ \
1152 + CF_CACR_ICINVA)
1153 +
1154 +#ifndef CONFIG_M5445X_DISABLE_CACHE
1155 +#define CACHE_INITIAL_MODE (CF_CACR_DEC+ \
1156 + CF_CACR_BEC+ \
1157 + CF_CACR_IEC+ \
1158 + CF_CACR_EUSP)
1159 +#else
1160 +/* cache disabled for testing */
1161 +#define CACHE_INITIAL_MODE (CF_CACR_EUSP)
1162 +#endif /* CONFIG_M5445X_DISABLE_CACHE */
1163 +#endif /* CONFIG_M54455 */
1164
1165 #ifndef __ASSEMBLY__
1166
1167 -extern void DcacheFlushInvalidate(void);
1168 -
1169 -extern void DcacheDisable(void);
1170 -extern void DcacheEnable(void);
1171 -
1172 -/******************************************************************************/
1173 -/*** Unimplemented Cache functionality ***/
1174 -/******************************************************************************/
1175 -#define preDcacheInvalidateBlockMark()
1176 -#define postDcacheInvalidateBlockMark()
1177 -#define DcacheZeroBlock(p, l) fast_bzero((char *)(p), (long)(l))
1178 -#define loadDcacheInvalidateBlock() ASSERT(!"Not Implemented on V4e")
1179 -#define IcacheInvalidateBlock() ASSERT(!"Not Implemented on V4e")
1180 -
1181 -/******************************************************************************/
1182 -/*** Redundant Cache functionality on ColdFire ***/
1183 -/******************************************************************************/
1184 -#define DcacheInvalidateBlock(p, l) DcacheFlushInvalidateCacheBlock(p, l)
1185 -#define DcacheFlushCacheBlock(p, l) DcacheFlushInvalidateCacheBlock(p, l)
1186 -#define DcacheFlushBlock(p, l) DcacheFlushInvalidateCacheBlock(p, l)
1187 -
1188 -extern void DcacheFlushInvalidateCacheBlock(void *start, unsigned long size);
1189 -extern void FLASHDcacheFlushInvalidate(void);
1190 -
1191 +extern unsigned long shadow_cacr;
1192 extern void cacr_set(unsigned long x);
1193
1194 #endif /* !__ASSEMBLY__ */
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