+ ddr_pll = nint * ar71xx_ref_freq / ref_div;
+ ddr_pll += frac * ar71xx_ref_freq / (ref_div * (2 << 10));
+ ddr_pll /= (1 << out_div);
+
+ clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
+
+ if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS) {
+ ar71xx_cpu_freq = ar71xx_ref_freq;
+ } else {
+ postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
+
+ if (clk_ctrl & AR934X_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
+ ar71xx_cpu_freq = cpu_pll / (postdiv + 1);
+ else
+ ar71xx_cpu_freq = ddr_pll / (postdiv + 1);
+ }