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disable dsp freq use for vlynq bus clock init, disable external clocking (it locks...
[openwrt.git]
/
target
/
linux
/
rdc
/
profiles
/
drwxr-xr-x
..
-rw-r--r--
275
AR525W.mk
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-rw-r--r--
270
WL-153.mk
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