+The LPC1343 is a modern, entry level 32-bit ARM Cortex M3 processor with
+**32KB flash, 8KB SRAM**, and can be run at up to **72MHz**. It also includes
+full-speed USB 2.0, along with all the main peripherals you'd expect to find
+(I2C, SPI, PWM, ADC, UART, etc.).
+
+The LPC1000 family from NXP contains a wide variety of ARM Cortex M0 and
+Cortex M3 cores, but the LPC1343 is particularly attractive in situations
+where price is an issue, but a decent amount of performance is needed. It has
+an efficient instruction set (most commands execute in a single clock cycle,
+including single-cycle multiply, etc.), and excellent code-density thanks to
+the Thumb-2 instruction set, meaning 32KB stretches a lot further than it
+did with the older ARM7 or ARM9 cores even in Thumb mode.
+
+The ARM Cortex M0 based LPC1114 is cheaper (ridiculously cheap!), and represents
+one of the best values out there when both price and power consumption are an issue,
+but the Cortex M0 has a minor performance bottleneck compared to the Cortex M3 that
+may or may not be important to you: The smaller, lighter-weight M0 LPC1114 is based
+on a Von Nuemann architecture with a single pipeline for both instructions and
+data. This means that it usually takes two clock cycles to do something on the M0 that can
+be done in one clock cycle on the ARM Cortex M3 LPC1343. The M3 LPC1343 implements
+a Harvard architecture with a three-stage pipeline, meaning seperate pipelines for
+instructions, data and peripherals that can all be filled in the same clock cycle.
+
+This means that in certain situations 72MHz on the M3 LPC1343 can
+actually be more than twice as fast as the 50MHz LPC1114, though this comes at the
+expense of a larger and more complicated core that consumes more power and requires a
+slightly larger die due to the increased gate count.
+
+> **M0 Sidenote:** The single-pipeline bottleneck on the M0 is addressed in the recently announced
+ARM Cortex M0+, which will contain a dual pipeline, while still maintaining a very
+light-weight, efficient and inexpensive core. This is probably the most important
+change in the M0+ since it offers much better performance per clock cycle, meaning
+you can switch back to a low-power sleep mode that much quicker for better battery life.
projects / hackover2013-badge-firmware.git / blobdiff