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[PATCH 1/2] Fix race between device reset and start_xmit
[openwrt.git] / target / linux / ar7 / files / drivers / net / cpmac.c
1 /*
2 * Copyright (C) 2006, 2007 OpenWrt.org
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/platform_device.h>
38 #include <linux/dma-mapping.h>
39 #include <asm/gpio.h>
40 #include <asm/atomic.h>
41
42 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
44 MODULE_LICENSE("GPL");
45
46 static int debug_level = 8;
47 static int dumb_switch;
48
49 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
50 module_param(debug_level, int, 0444);
51 module_param(dumb_switch, int, 0444);
52
53 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
54 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
55
56 #define CPMAC_VERSION "0.5.0"
57 /* stolen from net/ieee80211.h */
58 #ifndef MAC_FMT
59 #define MAC_FMT "%02x:%02x:%02x:%02x:%02x:%02x"
60 #define MAC_ARG(x) ((u8*)(x))[0], ((u8*)(x))[1], ((u8*)(x))[2], \
61 ((u8*)(x))[3], ((u8*)(x))[4], ((u8*)(x))[5]
62 #endif
63 /* frame size + 802.1q tag */
64 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
65 #define CPMAC_QUEUES 8
66
67 /* Ethernet registers */
68 #define CPMAC_TX_CONTROL 0x0004
69 #define CPMAC_TX_TEARDOWN 0x0008
70 #define CPMAC_RX_CONTROL 0x0014
71 #define CPMAC_RX_TEARDOWN 0x0018
72 #define CPMAC_MBP 0x0100
73 # define MBP_RXPASSCRC 0x40000000
74 # define MBP_RXQOS 0x20000000
75 # define MBP_RXNOCHAIN 0x10000000
76 # define MBP_RXCMF 0x01000000
77 # define MBP_RXSHORT 0x00800000
78 # define MBP_RXCEF 0x00400000
79 # define MBP_RXPROMISC 0x00200000
80 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
81 # define MBP_RXBCAST 0x00002000
82 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
83 # define MBP_RXMCAST 0x00000020
84 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
85 #define CPMAC_UNICAST_ENABLE 0x0104
86 #define CPMAC_UNICAST_CLEAR 0x0108
87 #define CPMAC_MAX_LENGTH 0x010c
88 #define CPMAC_BUFFER_OFFSET 0x0110
89 #define CPMAC_MAC_CONTROL 0x0160
90 # define MAC_TXPTYPE 0x00000200
91 # define MAC_TXPACE 0x00000040
92 # define MAC_MII 0x00000020
93 # define MAC_TXFLOW 0x00000010
94 # define MAC_RXFLOW 0x00000008
95 # define MAC_MTEST 0x00000004
96 # define MAC_LOOPBACK 0x00000002
97 # define MAC_FDX 0x00000001
98 #define CPMAC_MAC_STATUS 0x0164
99 # define MAC_STATUS_QOS 0x00000004
100 # define MAC_STATUS_RXFLOW 0x00000002
101 # define MAC_STATUS_TXFLOW 0x00000001
102 #define CPMAC_TX_INT_ENABLE 0x0178
103 #define CPMAC_TX_INT_CLEAR 0x017c
104 #define CPMAC_MAC_INT_VECTOR 0x0180
105 # define MAC_INT_STATUS 0x00080000
106 # define MAC_INT_HOST 0x00040000
107 # define MAC_INT_RX 0x00020000
108 # define MAC_INT_TX 0x00010000
109 #define CPMAC_MAC_EOI_VECTOR 0x0184
110 #define CPMAC_RX_INT_ENABLE 0x0198
111 #define CPMAC_RX_INT_CLEAR 0x019c
112 #define CPMAC_MAC_INT_ENABLE 0x01a8
113 #define CPMAC_MAC_INT_CLEAR 0x01ac
114 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
115 #define CPMAC_MAC_ADDR_MID 0x01d0
116 #define CPMAC_MAC_ADDR_HI 0x01d4
117 #define CPMAC_MAC_HASH_LO 0x01d8
118 #define CPMAC_MAC_HASH_HI 0x01dc
119 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
120 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
121 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
122 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
123 #define CPMAC_REG_END 0x0680
124 /*
125 * Rx/Tx statistics
126 * TODO: use some of them to fill stats in cpmac_stats()
127 */
128 #define CPMAC_STATS_RX_GOOD 0x0200
129 #define CPMAC_STATS_RX_BCAST 0x0204
130 #define CPMAC_STATS_RX_MCAST 0x0208
131 #define CPMAC_STATS_RX_PAUSE 0x020c
132 #define CPMAC_STATS_RX_CRC 0x0210
133 #define CPMAC_STATS_RX_ALIGN 0x0214
134 #define CPMAC_STATS_RX_OVER 0x0218
135 #define CPMAC_STATS_RX_JABBER 0x021c
136 #define CPMAC_STATS_RX_UNDER 0x0220
137 #define CPMAC_STATS_RX_FRAG 0x0224
138 #define CPMAC_STATS_RX_FILTER 0x0228
139 #define CPMAC_STATS_RX_QOSFILTER 0x022c
140 #define CPMAC_STATS_RX_OCTETS 0x0230
141
142 #define CPMAC_STATS_TX_GOOD 0x0234
143 #define CPMAC_STATS_TX_BCAST 0x0238
144 #define CPMAC_STATS_TX_MCAST 0x023c
145 #define CPMAC_STATS_TX_PAUSE 0x0240
146 #define CPMAC_STATS_TX_DEFER 0x0244
147 #define CPMAC_STATS_TX_COLLISION 0x0248
148 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
149 #define CPMAC_STATS_TX_MULTICOLL 0x0250
150 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
151 #define CPMAC_STATS_TX_LATECOLL 0x0258
152 #define CPMAC_STATS_TX_UNDERRUN 0x025c
153 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
154 #define CPMAC_STATS_TX_OCTETS 0x0264
155
156 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
157 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
158 (reg)))
159
160 /* MDIO bus */
161 #define CPMAC_MDIO_VERSION 0x0000
162 #define CPMAC_MDIO_CONTROL 0x0004
163 # define MDIOC_IDLE 0x80000000
164 # define MDIOC_ENABLE 0x40000000
165 # define MDIOC_PREAMBLE 0x00100000
166 # define MDIOC_FAULT 0x00080000
167 # define MDIOC_FAULTDETECT 0x00040000
168 # define MDIOC_INTTEST 0x00020000
169 # define MDIOC_CLKDIV(div) ((div) & 0xff)
170 #define CPMAC_MDIO_ALIVE 0x0008
171 #define CPMAC_MDIO_LINK 0x000c
172 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
173 # define MDIO_BUSY 0x80000000
174 # define MDIO_WRITE 0x40000000
175 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
176 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
177 # define MDIO_DATA(data) ((data) & 0xffff)
178 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
179 # define PHYSEL_LINKSEL 0x00000040
180 # define PHYSEL_LINKINT 0x00000020
181
182 struct cpmac_desc {
183 u32 hw_next;
184 u32 hw_data;
185 u16 buflen;
186 u16 bufflags;
187 u16 datalen;
188 u16 dataflags;
189 #define CPMAC_SOP 0x8000
190 #define CPMAC_EOP 0x4000
191 #define CPMAC_OWN 0x2000
192 #define CPMAC_EOQ 0x1000
193 struct sk_buff *skb;
194 struct cpmac_desc *next;
195 dma_addr_t mapping;
196 dma_addr_t data_mapping;
197 };
198
199 struct cpmac_priv {
200 spinlock_t lock;
201 spinlock_t rx_lock;
202 struct cpmac_desc *rx_head;
203 int ring_size;
204 struct cpmac_desc *desc_ring;
205 dma_addr_t dma_ring;
206 void __iomem *regs;
207 struct mii_bus *mii_bus;
208 struct phy_device *phy;
209 char phy_name[BUS_ID_SIZE];
210 int oldlink, oldspeed, oldduplex;
211 u32 msg_enable;
212 struct net_device *dev;
213 struct work_struct reset_work;
214 struct platform_device *pdev;
215 atomic_t reset_pending;
216 };
217
218 static irqreturn_t cpmac_irq(int, void *);
219 static void cpmac_hw_start(struct net_device *dev);
220 static void cpmac_hw_stop(struct net_device *dev);
221 static int cpmac_stop(struct net_device *dev);
222 static int cpmac_open(struct net_device *dev);
223
224 static void cpmac_dump_regs(struct net_device *dev)
225 {
226 int i;
227 struct cpmac_priv *priv = netdev_priv(dev);
228 for (i = 0; i < CPMAC_REG_END; i += 4) {
229 if (i % 16 == 0) {
230 if (i)
231 printk("\n");
232 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
233 priv->regs + i);
234 }
235 printk(" %08x", cpmac_read(priv->regs, i));
236 }
237 printk("\n");
238 }
239
240 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
241 {
242 int i;
243 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
244 for (i = 0; i < sizeof(*desc) / 4; i++)
245 printk(" %08x", ((u32 *)desc)[i]);
246 printk("\n");
247 }
248
249 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
250 {
251 int i;
252 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
253 for (i = 0; i < skb->len; i++) {
254 if (i % 16 == 0) {
255 if (i)
256 printk("\n");
257 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
258 skb->data + i);
259 }
260 printk(" %02x", ((u8 *)skb->data)[i]);
261 }
262 printk("\n");
263 }
264
265 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
266 {
267 u32 val;
268
269 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
270 cpu_relax();
271 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
272 MDIO_PHY(phy_id));
273 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
274 cpu_relax();
275 return MDIO_DATA(val);
276 }
277
278 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
279 int reg, u16 val)
280 {
281 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
282 cpu_relax();
283 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
284 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
285 return 0;
286 }
287
288 static int cpmac_mdio_reset(struct mii_bus *bus)
289 {
290 ar7_device_reset(AR7_RESET_BIT_MDIO);
291 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
292 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
293 return 0;
294 }
295
296 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
297
298 static struct mii_bus cpmac_mii = {
299 .name = "cpmac-mii",
300 .read = cpmac_mdio_read,
301 .write = cpmac_mdio_write,
302 .reset = cpmac_mdio_reset,
303 .irq = mii_irqs,
304 };
305
306 static int cpmac_config(struct net_device *dev, struct ifmap *map)
307 {
308 if (dev->flags & IFF_UP)
309 return -EBUSY;
310
311 /* Don't allow changing the I/O address */
312 if (map->base_addr != dev->base_addr)
313 return -EOPNOTSUPP;
314
315 /* ignore other fields */
316 return 0;
317 }
318
319 static void cpmac_set_multicast_list(struct net_device *dev)
320 {
321 struct dev_mc_list *iter;
322 int i;
323 u8 tmp;
324 u32 mbp, bit, hash[2] = { 0, };
325 struct cpmac_priv *priv = netdev_priv(dev);
326
327 mbp = cpmac_read(priv->regs, CPMAC_MBP);
328 if (dev->flags & IFF_PROMISC) {
329 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
330 MBP_RXPROMISC);
331 } else {
332 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
333 if (dev->flags & IFF_ALLMULTI) {
334 /* enable all multicast mode */
335 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
336 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
337 } else {
338 /*
339 * cpmac uses some strange mac address hashing
340 * (not crc32)
341 */
342 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
343 i++, iter = iter->next) {
344 bit = 0;
345 tmp = iter->dmi_addr[0];
346 bit ^= (tmp >> 2) ^ (tmp << 4);
347 tmp = iter->dmi_addr[1];
348 bit ^= (tmp >> 4) ^ (tmp << 2);
349 tmp = iter->dmi_addr[2];
350 bit ^= (tmp >> 6) ^ tmp;
351 tmp = iter->dmi_addr[3];
352 bit ^= (tmp >> 2) ^ (tmp << 4);
353 tmp = iter->dmi_addr[4];
354 bit ^= (tmp >> 4) ^ (tmp << 2);
355 tmp = iter->dmi_addr[5];
356 bit ^= (tmp >> 6) ^ tmp;
357 bit &= 0x3f;
358 hash[bit / 32] |= 1 << (bit % 32);
359 }
360
361 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
362 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
363 }
364 }
365 }
366
367 static struct sk_buff *cpmac_rx_one(struct net_device *dev,
368 struct cpmac_priv *priv,
369 struct cpmac_desc *desc)
370 {
371 struct sk_buff *skb, *result = NULL;
372
373 if (unlikely(netif_msg_hw(priv)))
374 cpmac_dump_desc(dev, desc);
375 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
376 if (unlikely(!desc->datalen)) {
377 if (netif_msg_rx_err(priv) && net_ratelimit())
378 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
379 dev->name);
380 return NULL;
381 }
382
383 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
384 if (likely(skb)) {
385 skb_reserve(skb, 2);
386 skb_put(desc->skb, desc->datalen);
387 desc->skb->protocol = eth_type_trans(desc->skb, dev);
388 desc->skb->ip_summed = CHECKSUM_NONE;
389 dev->stats.rx_packets++;
390 dev->stats.rx_bytes += desc->datalen;
391 result = desc->skb;
392 dma_unmap_single(&dev->dev, desc->data_mapping, CPMAC_SKB_SIZE,
393 DMA_FROM_DEVICE);
394 desc->skb = skb;
395 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
396 CPMAC_SKB_SIZE,
397 DMA_FROM_DEVICE);
398 desc->hw_data = (u32)desc->data_mapping;
399 if (unlikely(netif_msg_pktdata(priv))) {
400 printk(KERN_DEBUG "%s: received packet:\n", dev->name);
401 cpmac_dump_skb(dev, result);
402 }
403 } else {
404 if (netif_msg_rx_err(priv) && net_ratelimit())
405 printk(KERN_WARNING
406 "%s: low on skbs, dropping packet\n", dev->name);
407 dev->stats.rx_dropped++;
408 }
409
410 desc->buflen = CPMAC_SKB_SIZE;
411 desc->dataflags = CPMAC_OWN;
412
413 return result;
414 }
415
416 static int cpmac_poll(struct net_device *dev, int *budget)
417 {
418 struct sk_buff *skb;
419 struct cpmac_desc *desc;
420 int received = 0, quota = min(dev->quota, *budget);
421 struct cpmac_priv *priv = netdev_priv(dev);
422
423 spin_lock(&priv->rx_lock);
424 if (unlikely(!priv->rx_head)) {
425 if (netif_msg_rx_err(priv) && net_ratelimit())
426 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
427 dev->name);
428 netif_rx_complete(dev);
429 return 0;
430 }
431
432 desc = priv->rx_head;
433 while ((received < quota) && ((desc->dataflags & CPMAC_OWN) == 0)) {
434 skb = cpmac_rx_one(dev, priv, desc);
435 if (likely(skb)) {
436 netif_receive_skb(skb);
437 received++;
438 }
439 desc = desc->next;
440 }
441
442 priv->rx_head = desc;
443 spin_unlock(&priv->rx_lock);
444 *budget -= received;
445 dev->quota -= received;
446 if (unlikely(netif_msg_rx_status(priv)))
447 printk(KERN_DEBUG "%s: poll processed %d packets\n", dev->name,
448 received);
449 if (desc->dataflags & CPMAC_OWN) {
450 netif_rx_complete(dev);
451 cpmac_write(priv->regs, CPMAC_RX_PTR(0), (u32)desc->mapping);
452 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
453 return 0;
454 }
455
456 return 1;
457 }
458
459 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
460 {
461 int queue, len;
462 struct cpmac_desc *desc;
463 struct cpmac_priv *priv = netdev_priv(dev);
464
465 if (unlikely(atomic_read(&priv->reset_pending)))
466 return NETDEV_TX_BUSY;
467
468 if (unlikely(skb_padto(skb, ETH_ZLEN)))
469 return NETDEV_TX_OK;
470
471 len = max(skb->len, ETH_ZLEN);
472 queue = skb->queue_mapping;
473 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
474 netif_stop_subqueue(dev, queue);
475 #else
476 netif_stop_queue(dev);
477 #endif
478
479 desc = &priv->desc_ring[queue];
480 if (unlikely(desc->dataflags & CPMAC_OWN)) {
481 if (netif_msg_tx_err(priv) && net_ratelimit())
482 printk(KERN_WARNING "%s: tx dma ring full\n",
483 dev->name);
484 return NETDEV_TX_BUSY;
485 }
486
487 spin_lock(&priv->lock);
488 dev->trans_start = jiffies;
489 spin_unlock(&priv->lock);
490 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
491 desc->skb = skb;
492 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
493 DMA_TO_DEVICE);
494 desc->hw_data = (u32)desc->data_mapping;
495 desc->datalen = len;
496 desc->buflen = len;
497 if (unlikely(netif_msg_tx_queued(priv)))
498 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
499 skb->len);
500 if (unlikely(netif_msg_hw(priv)))
501 cpmac_dump_desc(dev, desc);
502 if (unlikely(netif_msg_pktdata(priv)))
503 cpmac_dump_skb(dev, skb);
504 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
505
506 return NETDEV_TX_OK;
507 }
508
509 static void cpmac_end_xmit(struct net_device *dev, int queue)
510 {
511 struct cpmac_desc *desc;
512 struct cpmac_priv *priv = netdev_priv(dev);
513
514 desc = &priv->desc_ring[queue];
515 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
516 if (likely(desc->skb)) {
517 spin_lock(&priv->lock);
518 dev->stats.tx_packets++;
519 dev->stats.tx_bytes += desc->skb->len;
520 spin_unlock(&priv->lock);
521 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
522 DMA_TO_DEVICE);
523
524 if (unlikely(netif_msg_tx_done(priv)))
525 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
526 desc->skb, desc->skb->len);
527
528 dev_kfree_skb_irq(desc->skb);
529 desc->skb = NULL;
530 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
531 if (netif_subqueue_stopped(dev, queue))
532 netif_wake_subqueue(dev, queue);
533 #else
534 if (netif_queue_stopped(dev))
535 netif_wake_queue(dev);
536 #endif
537 } else {
538 if (netif_msg_tx_err(priv) && net_ratelimit())
539 printk(KERN_WARNING
540 "%s: end_xmit: spurious interrupt\n", dev->name);
541 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
542 if (netif_subqueue_stopped(dev, queue))
543 netif_wake_subqueue(dev, queue);
544 #else
545 if (netif_queue_stopped(dev))
546 netif_wake_queue(dev);
547 #endif
548 }
549 }
550
551 static void cpmac_hw_stop(struct net_device *dev)
552 {
553 int i;
554 struct cpmac_priv *priv = netdev_priv(dev);
555 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
556
557 ar7_device_reset(pdata->reset_bit);
558 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
559 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
560 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
561 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
562 for (i = 0; i < 8; i++) {
563 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
564 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
565 }
566 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
567 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
568 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
569 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
570 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
571 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
572 }
573
574 static void cpmac_hw_start(struct net_device *dev)
575 {
576 int i;
577 struct cpmac_priv *priv = netdev_priv(dev);
578 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
579
580 ar7_device_reset(pdata->reset_bit);
581 for (i = 0; i < 8; i++) {
582 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
583 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
584 }
585 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
586
587 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
588 MBP_RXMCAST);
589 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
590 for (i = 0; i < 8; i++)
591 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
592 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
593 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
594 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
595 (dev->dev_addr[3] << 24));
596 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
597 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
598 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
599 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
600 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
601 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
602 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
603 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
604 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
605
606 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
607 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
608 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
609 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
610 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
611 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
612 MAC_FDX);
613 }
614
615 static void cpmac_clear_rx(struct net_device *dev)
616 {
617 struct cpmac_priv *priv = netdev_priv(dev);
618 struct cpmac_desc *desc;
619 int i;
620 if (unlikely(!priv->rx_head))
621 return;
622 desc = priv->rx_head;
623 for (i = 0; i < priv->ring_size; i++) {
624 if ((desc->dataflags & CPMAC_OWN) == 0) {
625 if (netif_msg_rx_err(priv) && net_ratelimit())
626 printk(KERN_WARNING "%s: packet dropped\n",
627 dev->name);
628 if (unlikely(netif_msg_hw(priv)))
629 cpmac_dump_desc(dev, desc);
630 desc->dataflags = CPMAC_OWN;
631 dev->stats.rx_dropped++;
632 }
633 desc = desc->next;
634 }
635 }
636
637 static void cpmac_clear_tx(struct net_device *dev)
638 {
639 struct cpmac_priv *priv = netdev_priv(dev);
640 int i;
641 if (unlikely(!priv->desc_ring))
642 return;
643 for (i = 0; i < CPMAC_QUEUES; i++) {
644 priv->desc_ring[i].dataflags = 0;
645 if (priv->desc_ring[i].skb) {
646 dev_kfree_skb_any(priv->desc_ring[i].skb);
647 priv->desc_ring[i].skb = NULL;
648 }
649 }
650 }
651
652 static void cpmac_hw_error(struct work_struct *work)
653 {
654 int i;
655 struct cpmac_priv *priv =
656 container_of(work, struct cpmac_priv, reset_work);
657
658 spin_lock(&priv->rx_lock);
659 cpmac_clear_rx(priv->dev);
660 spin_unlock(&priv->rx_lock);
661 cpmac_clear_tx(priv->dev);
662 cpmac_hw_start(priv->dev);
663 barrier();
664 atomic_dec(&priv->reset_pending);
665
666 for (i = 0; i < CPMAC_QUEUES; i++) {
667 netif_wake_subqueue(priv->dev, i);
668 }
669 netif_wake_queue(priv->dev);
670 }
671
672 static void cpmac_check_status(struct net_device *dev)
673 {
674 struct cpmac_priv *priv = netdev_priv(dev);
675
676 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
677 int rx_channel = (macstatus >> 8) & 7;
678 int rx_code = (macstatus >> 12) & 15;
679 int tx_channel = (macstatus >> 16) & 7;
680 int tx_code = (macstatus >> 20) & 15;
681
682 if (rx_code || tx_code) {
683 if (netif_msg_drv(priv) && net_ratelimit()) {
684 /* Can't find any documentation on what these error codes actually are.
685 * So just log them and hope..
686 */
687 if (rx_code)
688 printk(KERN_WARNING "%s: host error %d on rx channel %d (macstatus %08x), resetting\n",
689 dev->name, rx_code, rx_channel, macstatus);
690 if (tx_code)
691 printk(KERN_WARNING "%s: host error %d on tx channel %d (macstatus %08x), resetting\n",
692 dev->name, tx_code, tx_channel, macstatus);
693 }
694
695 netif_stop_queue(dev);
696 cpmac_hw_stop(dev);
697 if (schedule_work(&priv->reset_work))
698 atomic_inc(&priv->reset_pending);
699 if (unlikely(netif_msg_hw(priv)))
700 cpmac_dump_regs(dev);
701 }
702 }
703
704 static irqreturn_t cpmac_irq(int irq, void *dev_id)
705 {
706 struct net_device *dev = dev_id;
707 struct cpmac_priv *priv;
708 int queue;
709 u32 status;
710
711 if (!dev)
712 return IRQ_NONE;
713
714 priv = netdev_priv(dev);
715
716 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
717
718 if (unlikely(netif_msg_intr(priv)))
719 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
720 status);
721
722 if (status & MAC_INT_TX)
723 cpmac_end_xmit(dev, (status & 7));
724
725 if (status & MAC_INT_RX) {
726 queue = (status >> 8) & 7;
727 netif_rx_schedule(dev);
728 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
729 }
730
731 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
732
733 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
734 cpmac_check_status(dev);
735
736 return IRQ_HANDLED;
737 }
738
739 static void cpmac_tx_timeout(struct net_device *dev)
740 {
741 int i;
742 struct cpmac_priv *priv = netdev_priv(dev);
743
744 spin_lock(&priv->lock);
745 dev->stats.tx_errors++;
746 spin_unlock(&priv->lock);
747 if (netif_msg_tx_err(priv) && net_ratelimit())
748 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
749
750 atomic_inc(&priv->reset_pending);
751 barrier();
752 cpmac_clear_tx(dev);
753 barrier();
754 atomic_dec(&priv->reset_pending);
755
756 netif_wake_queue(priv->dev);
757 for (i = 0; i < CPMAC_QUEUES; i++) {
758 netif_wake_subqueue(dev, i);
759 }
760 }
761
762 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
763 {
764 struct cpmac_priv *priv = netdev_priv(dev);
765 if (!(netif_running(dev)))
766 return -EINVAL;
767 if (!priv->phy)
768 return -EINVAL;
769 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
770 (cmd == SIOCSMIIREG))
771 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
772
773 return -EOPNOTSUPP;
774 }
775
776 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
777 {
778 struct cpmac_priv *priv = netdev_priv(dev);
779
780 if (priv->phy)
781 return phy_ethtool_gset(priv->phy, cmd);
782
783 return -EINVAL;
784 }
785
786 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
787 {
788 struct cpmac_priv *priv = netdev_priv(dev);
789
790 if (!capable(CAP_NET_ADMIN))
791 return -EPERM;
792
793 if (priv->phy)
794 return phy_ethtool_sset(priv->phy, cmd);
795
796 return -EINVAL;
797 }
798
799 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
800 {
801 struct cpmac_priv *priv = netdev_priv(dev);
802
803 ring->rx_max_pending = 1024;
804 ring->rx_mini_max_pending = 1;
805 ring->rx_jumbo_max_pending = 1;
806 ring->tx_max_pending = 1;
807
808 ring->rx_pending = priv->ring_size;
809 ring->rx_mini_pending = 1;
810 ring->rx_jumbo_pending = 1;
811 ring->tx_pending = 1;
812 }
813
814 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
815 {
816 struct cpmac_priv *priv = netdev_priv(dev);
817
818 if (netif_running(dev))
819 return -EBUSY;
820 priv->ring_size = ring->rx_pending;
821 return 0;
822 }
823
824 static void cpmac_get_drvinfo(struct net_device *dev,
825 struct ethtool_drvinfo *info)
826 {
827 strcpy(info->driver, "cpmac");
828 strcpy(info->version, CPMAC_VERSION);
829 info->fw_version[0] = '\0';
830 sprintf(info->bus_info, "%s", "cpmac");
831 info->regdump_len = 0;
832 }
833
834 static const struct ethtool_ops cpmac_ethtool_ops = {
835 .get_settings = cpmac_get_settings,
836 .set_settings = cpmac_set_settings,
837 .get_drvinfo = cpmac_get_drvinfo,
838 .get_link = ethtool_op_get_link,
839 .get_ringparam = cpmac_get_ringparam,
840 .set_ringparam = cpmac_set_ringparam,
841 };
842
843 static void cpmac_adjust_link(struct net_device *dev)
844 {
845 struct cpmac_priv *priv = netdev_priv(dev);
846 int new_state = 0;
847
848 spin_lock(&priv->lock);
849 if (priv->phy->link) {
850 netif_start_queue(dev);
851 if (priv->phy->duplex != priv->oldduplex) {
852 new_state = 1;
853 priv->oldduplex = priv->phy->duplex;
854 }
855
856 if (priv->phy->speed != priv->oldspeed) {
857 new_state = 1;
858 priv->oldspeed = priv->phy->speed;
859 }
860
861 if (!priv->oldlink) {
862 new_state = 1;
863 priv->oldlink = 1;
864 netif_schedule(dev);
865 }
866 } else if (priv->oldlink) {
867 netif_stop_queue(dev);
868 new_state = 1;
869 priv->oldlink = 0;
870 priv->oldspeed = 0;
871 priv->oldduplex = -1;
872 }
873
874 if (new_state && netif_msg_link(priv) && net_ratelimit())
875 phy_print_status(priv->phy);
876
877 spin_unlock(&priv->lock);
878 }
879
880 static int cpmac_open(struct net_device *dev)
881 {
882 int i, size, res;
883 struct cpmac_priv *priv = netdev_priv(dev);
884 struct resource *mem;
885 struct cpmac_desc *desc;
886 struct sk_buff *skb;
887
888 priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link,
889 0, PHY_INTERFACE_MODE_MII);
890 if (IS_ERR(priv->phy)) {
891 if (netif_msg_drv(priv))
892 printk(KERN_ERR "%s: Could not attach to PHY\n",
893 dev->name);
894 return PTR_ERR(priv->phy);
895 }
896
897 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
898 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
899 if (netif_msg_drv(priv))
900 printk(KERN_ERR "%s: failed to request registers\n",
901 dev->name);
902 res = -ENXIO;
903 goto fail_reserve;
904 }
905
906 priv->regs = ioremap(mem->start, mem->end - mem->start);
907 if (!priv->regs) {
908 if (netif_msg_drv(priv))
909 printk(KERN_ERR "%s: failed to remap registers\n",
910 dev->name);
911 res = -ENXIO;
912 goto fail_remap;
913 }
914
915 size = priv->ring_size + CPMAC_QUEUES;
916 priv->desc_ring = dma_alloc_coherent(&dev->dev,
917 sizeof(struct cpmac_desc) * size,
918 &priv->dma_ring,
919 GFP_KERNEL);
920 if (!priv->desc_ring) {
921 res = -ENOMEM;
922 goto fail_alloc;
923 }
924
925 for (i = 0; i < size; i++)
926 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
927
928 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
929 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
930 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
931 if (unlikely(!skb)) {
932 res = -ENOMEM;
933 goto fail_desc;
934 }
935 skb_reserve(skb, 2);
936 desc->skb = skb;
937 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
938 CPMAC_SKB_SIZE,
939 DMA_FROM_DEVICE);
940 desc->hw_data = (u32)desc->data_mapping;
941 desc->buflen = CPMAC_SKB_SIZE;
942 desc->dataflags = CPMAC_OWN;
943 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
944 desc->hw_next = (u32)desc->next->mapping;
945 }
946
947 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
948 dev->name, dev))) {
949 if (netif_msg_drv(priv))
950 printk(KERN_ERR "%s: failed to obtain irq\n",
951 dev->name);
952 goto fail_irq;
953 }
954
955 atomic_set(&priv->reset_pending, 0);
956 INIT_WORK(&priv->reset_work, cpmac_hw_error);
957 cpmac_hw_start(dev);
958
959 priv->phy->state = PHY_CHANGELINK;
960 phy_start(priv->phy);
961
962 return 0;
963
964 fail_irq:
965 fail_desc:
966 for (i = 0; i < priv->ring_size; i++) {
967 if (priv->rx_head[i].skb) {
968 dma_unmap_single(&dev->dev,
969 priv->rx_head[i].data_mapping,
970 CPMAC_SKB_SIZE,
971 DMA_FROM_DEVICE);
972 kfree_skb(priv->rx_head[i].skb);
973 }
974 }
975 fail_alloc:
976 kfree(priv->desc_ring);
977 iounmap(priv->regs);
978
979 fail_remap:
980 release_mem_region(mem->start, mem->end - mem->start);
981
982 fail_reserve:
983 phy_disconnect(priv->phy);
984
985 return res;
986 }
987
988 static int cpmac_stop(struct net_device *dev)
989 {
990 int i;
991 struct cpmac_priv *priv = netdev_priv(dev);
992 struct resource *mem;
993
994 netif_stop_queue(dev);
995
996 cancel_work_sync(&priv->reset_work);
997 phy_stop(priv->phy);
998 phy_disconnect(priv->phy);
999 priv->phy = NULL;
1000
1001 cpmac_hw_stop(dev);
1002
1003 for (i = 0; i < 8; i++)
1004 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1005 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1006 cpmac_write(priv->regs, CPMAC_MBP, 0);
1007
1008 free_irq(dev->irq, dev);
1009 iounmap(priv->regs);
1010 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1011 release_mem_region(mem->start, mem->end - mem->start);
1012 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1013 for (i = 0; i < priv->ring_size; i++) {
1014 if (priv->rx_head[i].skb) {
1015 dma_unmap_single(&dev->dev,
1016 priv->rx_head[i].data_mapping,
1017 CPMAC_SKB_SIZE,
1018 DMA_FROM_DEVICE);
1019 kfree_skb(priv->rx_head[i].skb);
1020 }
1021 }
1022
1023 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1024 (CPMAC_QUEUES + priv->ring_size),
1025 priv->desc_ring, priv->dma_ring);
1026 return 0;
1027 }
1028
1029 static int external_switch;
1030
1031 static int __devinit cpmac_probe(struct platform_device *pdev)
1032 {
1033 int rc, phy_id;
1034 struct resource *mem;
1035 struct cpmac_priv *priv;
1036 struct net_device *dev;
1037 struct plat_cpmac_data *pdata;
1038
1039 pdata = pdev->dev.platform_data;
1040
1041 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1042 if (!(pdata->phy_mask & (1 << phy_id)))
1043 continue;
1044 if (!cpmac_mii.phy_map[phy_id])
1045 continue;
1046 break;
1047 }
1048
1049 if (phy_id == PHY_MAX_ADDR) {
1050 if (external_switch || dumb_switch)
1051 phy_id = 0;
1052 else {
1053 printk(KERN_ERR "cpmac: no PHY present\n");
1054 return -ENODEV;
1055 }
1056 }
1057
1058 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1059
1060 if (!dev) {
1061 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1062 return -ENOMEM;
1063 }
1064
1065 platform_set_drvdata(pdev, dev);
1066 priv = netdev_priv(dev);
1067
1068 priv->pdev = pdev;
1069 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1070 if (!mem) {
1071 rc = -ENODEV;
1072 goto fail;
1073 }
1074
1075 dev->irq = platform_get_irq_byname(pdev, "irq");
1076
1077 dev->open = cpmac_open;
1078 dev->stop = cpmac_stop;
1079 dev->set_config = cpmac_config;
1080 dev->hard_start_xmit = cpmac_start_xmit;
1081 dev->do_ioctl = cpmac_ioctl;
1082 dev->set_multicast_list = cpmac_set_multicast_list;
1083 dev->tx_timeout = cpmac_tx_timeout;
1084 dev->ethtool_ops = &cpmac_ethtool_ops;
1085 dev->poll = cpmac_poll;
1086 dev->weight = 64;
1087 dev->features |= NETIF_F_MULTI_QUEUE;
1088
1089 spin_lock_init(&priv->lock);
1090 spin_lock_init(&priv->rx_lock);
1091 priv->dev = dev;
1092 priv->ring_size = 64;
1093 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1094 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1095 if (phy_id == 31) {
1096 snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT,
1097 cpmac_mii.id, phy_id);
1098 } else
1099 snprintf(priv->phy_name, BUS_ID_SIZE, "fixed@%d:%d", 100, 1);
1100
1101 if ((rc = register_netdev(dev))) {
1102 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1103 dev->name);
1104 goto fail;
1105 }
1106
1107 if (netif_msg_probe(priv)) {
1108 printk(KERN_INFO
1109 "cpmac: device %s (regs: %p, irq: %d, phy: %s, mac: "
1110 MAC_FMT ")\n", dev->name, (void *)mem->start, dev->irq,
1111 priv->phy_name, MAC_ARG(dev->dev_addr));
1112 }
1113 return 0;
1114
1115 fail:
1116 free_netdev(dev);
1117 return rc;
1118 }
1119
1120 static int __devexit cpmac_remove(struct platform_device *pdev)
1121 {
1122 struct net_device *dev = platform_get_drvdata(pdev);
1123 unregister_netdev(dev);
1124 free_netdev(dev);
1125 return 0;
1126 }
1127
1128 static struct platform_driver cpmac_driver = {
1129 .driver.name = "cpmac",
1130 .probe = cpmac_probe,
1131 .remove = __devexit_p(cpmac_remove),
1132 };
1133
1134 int __devinit cpmac_init(void)
1135 {
1136 u32 mask;
1137 int i, res;
1138
1139 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1140
1141 if (!cpmac_mii.priv) {
1142 printk(KERN_ERR "Can't ioremap mdio registers\n");
1143 return -ENXIO;
1144 }
1145
1146 #warning FIXME: unhardcode gpio&reset bits
1147 ar7_gpio_disable(26);
1148 ar7_gpio_disable(27);
1149 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1150 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1151 ar7_device_reset(AR7_RESET_BIT_EPHY);
1152
1153 cpmac_mii.reset(&cpmac_mii);
1154
1155 for (i = 0; i < 300000; i++)
1156 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1157 break;
1158 else
1159 cpu_relax();
1160
1161 mask &= 0x7fffffff;
1162 if (mask & (mask - 1)) {
1163 external_switch = 1;
1164 mask = 0;
1165 }
1166
1167 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1168
1169 res = mdiobus_register(&cpmac_mii);
1170 if (res)
1171 goto fail_mii;
1172
1173 res = platform_driver_register(&cpmac_driver);
1174 if (res)
1175 goto fail_cpmac;
1176
1177 return 0;
1178
1179 fail_cpmac:
1180 mdiobus_unregister(&cpmac_mii);
1181
1182 fail_mii:
1183 iounmap(cpmac_mii.priv);
1184
1185 return res;
1186 }
1187
1188 void __devexit cpmac_exit(void)
1189 {
1190 platform_driver_unregister(&cpmac_driver);
1191 mdiobus_unregister(&cpmac_mii);
1192 iounmap(cpmac_mii.priv);
1193 }
1194
1195 module_init(cpmac_init);
1196 module_exit(cpmac_exit);
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