target/linux/ar71xx/files/arch/mips/pci/pci-ar71xx.c

   1 /*
   2  *  Atheros AR71xx PCI host controller driver
   3  *
   4  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   6  *
   7  *  Parts of this file are based on Atheros' 2.6.15 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/resource.h>
  15 #include <linux/types.h>
  16 #include <linux/delay.h>
  17 #include <linux/bitops.h>
  18 #include <linux/pci.h>
  19 #include <linux/pci_regs.h>
  20 #include <linux/interrupt.h>
  21
  22 #include <asm/mach-ar71xx/ar71xx.h>
  23 #include <asm/mach-ar71xx/pci.h>
  24
  25 #undef DEBUG
  26 #ifdef DEBUG
  27 #define DBG(fmt, args...)       printk(KERN_DEBUG fmt, ## args)
  28 #else
  29 #define DBG(fmt, args...)
  30 #endif
  31
  32 #define AR71XX_PCI_DELAY        100 /* msecs */
  33
  34 #if 0
  35 #define PCI_IDSEL_BASE  PCI_IDSEL_ADL_START
  36 #else
  37 #define PCI_IDSEL_BASE  0
  38 #endif
  39
  40 static void __iomem *ar71xx_pcicfg_base;
  41 static DEFINE_SPINLOCK(ar71xx_pci_lock);
  42 static int ar71xx_pci_fixup_enable;
  43
  44 static inline void ar71xx_pci_delay(void)
  45 {
  46         mdelay(AR71XX_PCI_DELAY);
  47 }
  48
  49 /* Byte lane enable bits */
  50 static u8 ble_table[4][4] = {
  51         {0x0, 0xf, 0xf, 0xf},
  52         {0xe, 0xd, 0xb, 0x7},
  53         {0xc, 0xf, 0x3, 0xf},
  54         {0xf, 0xf, 0xf, 0xf},
  55 };
  56
  57 static inline u32 ar71xx_pci_get_ble(int where, int size, int local)
  58 {
  59         u32 t;
  60
  61         t = ble_table[size & 3][where & 3];
  62         BUG_ON(t == 0xf);
  63         t <<= (local) ? 20 : 4;
  64         return t;
  65 }
  66
  67 static inline u32 ar71xx_pci_bus_addr(struct pci_bus *bus, unsigned int devfn,
  68                                         int where)
  69 {
  70         u32 ret;
  71
  72         if (!bus->number) {
  73                 /* type 0 */
  74                 ret = (1 << (PCI_IDSEL_BASE + PCI_SLOT(devfn)))
  75                     | (PCI_FUNC(devfn) << 8) | (where & ~3);
  76         } else {
  77                 /* type 1 */
  78                 ret = (bus->number << 16) | (PCI_SLOT(devfn) << 11)
  79                     | (PCI_FUNC(devfn) << 8) | (where & ~3) | 1;
  80         }
  81
  82         return ret;
  83 }
  84
  85 int ar71xx_pci_be_handler(int is_fixup)
  86 {
  87         void __iomem *base = ar71xx_pcicfg_base;
  88         u32 pci_err;
  89         u32 ahb_err;
  90
  91         pci_err = __raw_readl(base + PCI_REG_PCI_ERR) & 3;
  92         if (pci_err) {
  93                 if (!is_fixup)
  94                         printk(KERN_ALERT "PCI error %d at PCI addr 0x%x\n",
  95                                 pci_err,
  96                                 __raw_readl(base + PCI_REG_PCI_ERR_ADDR));
  97
  98                 __raw_writel(pci_err, base + PCI_REG_PCI_ERR);
  99         }
 100
 101         ahb_err = __raw_readl(base + PCI_REG_AHB_ERR) & 1;
 102         if (ahb_err) {
 103                 if (!is_fixup)
 104                         printk(KERN_ALERT "AHB error at AHB address 0x%x\n",
 105                                 __raw_readl(base + PCI_REG_AHB_ERR_ADDR));
 106
 107                 __raw_writel(ahb_err, base + PCI_REG_AHB_ERR);
 108         }
 109
 110         return (ahb_err | pci_err) ? 1 : 0;
 111 }
 112
 113 static inline int ar71xx_pci_set_cfgaddr(struct pci_bus *bus,
 114                         unsigned int devfn, int where, int size, u32 cmd)
 115 {
 116         void __iomem *base = ar71xx_pcicfg_base;
 117         u32 addr;
 118
 119         addr = ar71xx_pci_bus_addr(bus, devfn, where);
 120
 121         DBG("PCI: set cfgaddr: %02x:%02x.%01x/%02x:%01d, addr=%08x\n",
 122                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 123                 where, size, addr);
 124
 125         __raw_writel(addr, base + PCI_REG_CFG_AD);
 126         __raw_writel(cmd | ar71xx_pci_get_ble(where, size, 0),
 127                      base + PCI_REG_CFG_CBE);
 128
 129         return ar71xx_pci_be_handler(1);
 130 }
 131
 132 static int ar71xx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 133                                   int where, int size, u32 *value)
 134 {
 135         void __iomem *base = ar71xx_pcicfg_base;
 136         static u32 mask[8] = {0, 0xff, 0xffff, 0, 0xffffffff, 0, 0, 0};
 137         unsigned long flags;
 138         u32 data;
 139         int retry = 0;
 140         int ret;
 141
 142         ret = PCIBIOS_SUCCESSFUL;
 143
 144         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d\n", bus->number,
 145                         PCI_SLOT(devfn), PCI_FUNC(devfn), where, size);
 146
 147 retry:
 148         spin_lock_irqsave(&ar71xx_pci_lock, flags);
 149
 150         if (bus->number == 0 && devfn == 0) {
 151                 u32 t;
 152
 153                 t = PCI_CRP_CMD_READ | (where & ~3);
 154
 155                 __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
 156                 data = __raw_readl(base + PCI_REG_CRP_RDDATA);
 157
 158                 DBG("PCI: rd local cfg, ad_cbe:%08x, data:%08x\n", t, data);
 159
 160         } else {
 161                 int err;
 162
 163                 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 164                                                 PCI_CFG_CMD_READ);
 165
 166                 if (err == 0) {
 167                         data = __raw_readl(base + PCI_REG_CFG_RDDATA);
 168                 } else {
 169                         ret = PCIBIOS_DEVICE_NOT_FOUND;
 170                         data = ~0;
 171                 }
 172         }
 173
 174         spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 175
 176         DBG("PCI: read config: data=%08x raw=%08x\n",
 177                 (data >> (8 * (where & 3))) & mask[size & 7], data);
 178
 179         *value = (data >> (8 * (where & 3))) & mask[size & 7];
 180
 181         /*
 182          * PCI controller bug: sometimes reads to the PCI_COMMAND register
 183          * return 0xffff, even though the PCI trace shows the correct value.
 184          * Work around this by retrying reads to this register
 185          */
 186         if (where == PCI_COMMAND && (*value & 0xffff) == 0xffff && retry++ < 2)
 187                 goto retry;
 188
 189         return ret;
 190 }
 191
 192 static int ar71xx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 193                                    int where, int size, u32 value)
 194 {
 195         void __iomem *base = ar71xx_pcicfg_base;
 196         unsigned long flags;
 197         int ret;
 198
 199         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d value=%08x\n",
 200                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 201                 where, size, value);
 202
 203         value = value << (8 * (where & 3));
 204         ret = PCIBIOS_SUCCESSFUL;
 205
 206         spin_lock_irqsave(&ar71xx_pci_lock, flags);
 207         if (bus->number == 0 && devfn == 0) {
 208                 u32 t;
 209
 210                 t = PCI_CRP_CMD_WRITE | (where & ~3);
 211                 t |= ar71xx_pci_get_ble(where, size, 1);
 212
 213                 DBG("PCI: wr local cfg, ad_cbe:%08x, value:%08x\n", t, value);
 214
 215                 __raw_writel(t, base + PCI_REG_CRP_AD_CBE);
 216                 __raw_writel(value, base + PCI_REG_CRP_WRDATA);
 217         } else {
 218                 int err;
 219
 220                 err = ar71xx_pci_set_cfgaddr(bus, devfn, where, size,
 221                                                 PCI_CFG_CMD_WRITE);
 222
 223                 if (err == 0)
 224                         __raw_writel(value, base + PCI_REG_CFG_WRDATA);
 225                 else
 226                         ret = PCIBIOS_DEVICE_NOT_FOUND;
 227         }
 228         spin_unlock_irqrestore(&ar71xx_pci_lock, flags);
 229
 230         return ret;
 231 }
 232
 233 static void ar71xx_pci_fixup(struct pci_dev *dev)
 234 {
 235         u32 t;
 236
 237         if (!ar71xx_pci_fixup_enable)
 238                 return;
 239
 240         if (dev->bus->number != 0 || dev->devfn != 0)
 241                 return;
 242
 243         DBG("PCI: fixup host controller %s (%04x:%04x)\n", pci_name(dev),
 244                 dev->vendor, dev->device);
 245
 246         /* setup COMMAND register */
 247         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE
 248           | PCI_COMMAND_PARITY | PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK;
 249
 250         pci_write_config_word(dev, PCI_COMMAND, t);
 251 }
 252 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar71xx_pci_fixup);
 253
 254 int __init ar71xx_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 255                                   uint8_t pin)
 256 {
 257         int irq = -1;
 258         int i;
 259
 260         slot -= PCI_IDSEL_ADL_START - PCI_IDSEL_BASE;
 261
 262         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 263                 struct ar71xx_pci_irq *entry;
 264
 265                 entry = &ar71xx_pci_irq_map[i];
 266                 if (entry->slot == slot && entry->pin == pin) {
 267                         irq = entry->irq;
 268                         break;
 269                 }
 270         }
 271
 272         if (irq < 0) {
 273                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 274                                 pin, pci_name((struct pci_dev *)dev));
 275         } else {
 276                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 277                                 irq, pin, pci_name((struct pci_dev *)dev));
 278         }
 279
 280         return irq;
 281 }
 282
 283 static struct pci_ops ar71xx_pci_ops = {
 284         .read   = ar71xx_pci_read_config,
 285         .write  = ar71xx_pci_write_config,
 286 };
 287
 288 static struct resource ar71xx_pci_io_resource = {
 289         .name           = "PCI IO space",
 290         .start          = 0,
 291         .end            = 0,
 292         .flags          = IORESOURCE_IO,
 293 };
 294
 295 static struct resource ar71xx_pci_mem_resource = {
 296         .name           = "PCI memory space",
 297         .start          = AR71XX_PCI_MEM_BASE,
 298         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 299         .flags          = IORESOURCE_MEM
 300 };
 301
 302 static struct pci_controller ar71xx_pci_controller = {
 303         .pci_ops        = &ar71xx_pci_ops,
 304         .mem_resource   = &ar71xx_pci_mem_resource,
 305         .io_resource    = &ar71xx_pci_io_resource,
 306 };
 307
 308 static void ar71xx_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 309 {
 310         void __iomem *base = ar71xx_reset_base;
 311         u32 pending;
 312
 313         pending = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_STATUS) &
 314                   __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 315
 316         if (pending & PCI_INT_DEV0)
 317                 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
 318
 319         else if (pending & PCI_INT_DEV1)
 320                 generic_handle_irq(AR71XX_PCI_IRQ_DEV1);
 321
 322         else if (pending & PCI_INT_DEV2)
 323                 generic_handle_irq(AR71XX_PCI_IRQ_DEV2);
 324
 325         else if (pending & PCI_INT_CORE)
 326                 generic_handle_irq(AR71XX_PCI_IRQ_CORE);
 327
 328         else
 329                 spurious_interrupt();
 330 }
 331
 332 static void ar71xx_pci_irq_unmask(unsigned int irq)
 333 {
 334         void __iomem *base = ar71xx_reset_base;
 335         u32 t;
 336
 337         irq -= AR71XX_PCI_IRQ_BASE;
 338
 339         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 340         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 341
 342         /* flush write */
 343         (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 344 }
 345
 346 static void ar71xx_pci_irq_mask(unsigned int irq)
 347 {
 348         void __iomem *base = ar71xx_reset_base;
 349         u32 t;
 350
 351         irq -= AR71XX_PCI_IRQ_BASE;
 352
 353         t = __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 354         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 355
 356         /* flush write */
 357         (void) __raw_readl(base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 358 }
 359
 360 static struct irq_chip ar71xx_pci_irq_chip = {
 361         .name           = "AR71XX PCI ",
 362         .mask           = ar71xx_pci_irq_mask,
 363         .unmask         = ar71xx_pci_irq_unmask,
 364         .mask_ack       = ar71xx_pci_irq_mask,
 365 };
 366
 367 static void __init ar71xx_pci_irq_init(void)
 368 {
 369         void __iomem *base = ar71xx_reset_base;
 370         int i;
 371
 372         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_ENABLE);
 373         __raw_writel(0, base + AR71XX_RESET_REG_PCI_INT_STATUS);
 374
 375         for (i = AR71XX_PCI_IRQ_BASE;
 376              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 377                 irq_desc[i].status = IRQ_DISABLED;
 378                 set_irq_chip_and_handler(i, &ar71xx_pci_irq_chip,
 379                                          handle_level_irq);
 380         }
 381
 382         set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar71xx_pci_irq_handler);
 383 }
 384
 385 int __init ar71xx_pcibios_init(void)
 386 {
 387         void __iomem *ddr_base = ar71xx_ddr_base;
 388
 389         ar71xx_device_stop(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
 390         ar71xx_pci_delay();
 391
 392         ar71xx_device_start(RESET_MODULE_PCI_BUS | RESET_MODULE_PCI_CORE);
 393         ar71xx_pci_delay();
 394
 395         ar71xx_pcicfg_base = ioremap_nocache(AR71XX_PCI_CFG_BASE,
 396                                                 AR71XX_PCI_CFG_SIZE);
 397         if (ar71xx_pcicfg_base == NULL)
 398                 return -ENOMEM;
 399
 400         __raw_writel(PCI_WIN0_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN0);
 401         __raw_writel(PCI_WIN1_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN1);
 402         __raw_writel(PCI_WIN2_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN2);
 403         __raw_writel(PCI_WIN3_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN3);
 404         __raw_writel(PCI_WIN4_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN4);
 405         __raw_writel(PCI_WIN5_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN5);
 406         __raw_writel(PCI_WIN6_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN6);
 407         __raw_writel(PCI_WIN7_OFFS, ddr_base + AR71XX_DDR_REG_PCI_WIN7);
 408
 409         ar71xx_pci_delay();
 410
 411         /* clear bus errors */
 412         (void)ar71xx_pci_be_handler(1);
 413
 414         ar71xx_pci_fixup_enable = 1;
 415         ar71xx_pci_irq_init();
 416         register_pci_controller(&ar71xx_pci_controller);
 417
 418         return 0;
 419 }