target/linux/brcm-2.4/patches/014-bcm5354.patch

   1 --- a/arch/mips/bcm947xx/include/sbchipc.h      2007-11-23 12:12:01.000000000 -0500
   2 +++ b/arch/mips/bcm947xx/include/sbchipc.h      2007-11-25 06:16:42.000000000 -0500
   3 @@ -188,6 +188,7 @@
   4  #define CAP_JTAGP              0x00400000      /* JTAG Master Present */
   5  #define CAP_ROM                        0x00800000      /* Internal boot rom active */
   6  #define CAP_BKPLN64            0x08000000      /* 64-bit backplane */
   7 +#define CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */
   8
   9  /* PLL type */
  10  #define PLL_NONE               0x00000000
  11 @@ -199,6 +200,9 @@
  12  #define PLL_TYPE6              0x00028000      /* 100/200 or 120/240 only */
  13  #define PLL_TYPE7              0x00038000      /* 25Mhz, 4 dividers */
  14
  15 +/* watchdog clock */
  16 +#define WATCHDOG_CLOCK_5354 32000 /* Hz */
  17 +
  18  /* corecontrol */
  19  #define CC_UARTCLKO            0x00000001      /* Drive UART with internal clock */
  20  #define        CC_SE                   0x00000002      /* sync clk out enable (corerev >= 3) */
  21 --- a/arch/mips/bcm947xx/include/bcmdevs.h      2007-11-23 12:12:01.000000000 -0500
  22 +++ b/arch/mips/bcm947xx/include/bcmdevs.h      2007-11-25 05:58:20.000000000 -0500
  23 @@ -121,6 +121,7 @@
  24  #define BCM5365_CHIP_ID                0x5365          /* 5365 chipcommon chipid */
  25  #define        BCM5350_CHIP_ID         0x5350          /* bcm5350 chipcommon chipid */
  26  #define        BCM5352_CHIP_ID         0x5352          /* bcm5352 chipcommon chipid */
  27 +#define        BCM5354_CHIP_ID         0x5354          /* bcm5354 chipcommon chipid */
  28
  29  #define        BCM4320_CHIP_ID         0x4320          /* bcm4320 chipcommon chipid */
  30
  31 --- a/arch/mips/bcm947xx/sbmips.c       2007-11-23 12:12:02.000000000 -0500
  32 +++ b/arch/mips/bcm947xx/sbmips.c       2007-11-25 05:40:40.000000000 -0500
  33 @@ -290,6 +290,12 @@
  34                 n = R_REG(osh, &eir->clockcontrol_n);
  35                 m = R_REG(osh, &eir->clockcontrol_sb);
  36         } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
  37 +   /* 5354 chip uses a non programmable PLL of frequency 240MHz */
  38 +   if (sb_chip(sbh) == BCM5354_CHIP_ID) {
  39 +     rate = 240000000;
  40 +     goto out;
  41 +   }
  42 +
  43                 pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
  44                 n = R_REG(osh, &cc->clockcontrol_n);
  45                 if ((pll_type == PLL_TYPE2) ||
  46 @@ -612,6 +618,15 @@
  47                 clockcontrol_pci = &eir->clockcontrol_pci;
  48                 clockcontrol_m2 = &cc->clockcontrol_m2;
  49         } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
  50 +
  51 +   /* 5354 chipcommon pll setting can't be changed.
  52 +    * The PMU on power up comes up with the default clk frequency
  53 +    * of 240MHz
  54 +    */
  55 +  if (sb_chip(sbh) == BCM5354_CHIP_ID) {
  56 +    ret = TRUE;
  57 +    goto done;
  58 +  }
  59                 pll_type = R_REG(osh, &cc->capabilities) & CAP_PLL_MASK;
  60                 if (pll_type == PLL_TYPE6) {
  61                         clockcontrol_n = NULL;
  62 --- a/arch/mips/bcm947xx/sbutils.c      2007-11-23 12:12:02.000000000 -0500
  63 +++ b/arch/mips/bcm947xx/sbutils.c      2007-11-25 06:22:43.000000000 -0500
  64 @@ -791,8 +791,14 @@
  65         /* readback */
  66         if (regoff >= SBCONFIGOFF)
  67                 w = R_SBREG(si, r);
  68 -       else
  69 +       else {
  70 +   if ((si->sb.chip == BCM5354_CHIP_ID) &&
  71 +       (coreidx == SB_CC_IDX) &&
  72 +       (regoff == OFFSETOF(chipcregs_t, watchdog))) {
  73 +         w = val;
  74 +   } else
  75                 w = R_REG(si->osh, r);
  76 + }
  77
  78         if (!fast) {
  79                 /* restore core index */
  80 @@ -1902,6 +1908,15 @@
  81                 n = R_REG(si->osh, &eir->clockcontrol_n);
  82                 m = R_REG(si->osh, &eir->clockcontrol_sb);
  83         } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
  84 +
  85 +   if (R_REG(si->osh, &cc->capabilities) & CAP_PMU) {
  86 +      if (sb_chip(sbh) == BCM5354_CHIP_ID) {
  87 +        /* 5354 has a constant sb clock of 120MHz */
  88 +        rate = 120000000;
  89 +        goto end;
  90 +      } else
  91 +     ASSERT(0);
  92 +   }
  93                 pll_type = R_REG(si->osh, &cc->capabilities) & CAP_PLL_MASK;
  94                 if (pll_type == PLL_NONE) {
  95                         INTR_RESTORE(si, intr_val);
  96 @@ -1929,6 +1944,7 @@
  97                         rate = rate / 2;
  98         }
  99
 100 +end:
 101         /* switch back to previous core */
 102         sb_setcoreidx(sbh, idx);
 103
 104 --- a/arch/mips/bcm947xx/hndchipc.c     2007-11-23 12:12:02.000000000 -0500
 105 +++ b/arch/mips/bcm947xx/hndchipc.c     2007-11-25 06:31:15.000000000 -0500
 106 @@ -93,6 +93,9 @@
 107                 chipcregs_t *cc = (chipcregs_t *) regs;
 108                 uint32 rev, cap, pll, baud_base, div;
 109
 110 +  /* Default value */
 111 +  div = 48;
 112 +
 113                 /* Determine core revision and capabilities */
 114                 rev = sb_corerev(sbh);
 115                 cap = R_REG(osh, &cc->capabilities);
 116 @@ -108,22 +111,29 @@
 117                                                   R_REG(osh, &cc->clockcontrol_m2));
 118                         div = 1;
 119                 } else {
 120 -                       /* Fixed ALP clock */
 121 -                       if (rev >= 11 && rev != 15) {
 122 -                               baud_base = 20000000;
 123 +/* 5354 chip common uart uses a constant clock
 124 + * frequency of 25MHz */
 125 +         if (sb_corerev(sbh) == 20) {
 126 +                 /* Set the override bit so we don't divide it */
 127 +                 W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
 128 +                 baud_base = 25000000;
 129 +         } else if (rev >= 11 && rev != 15) {
 130 +                 /* Fixed ALP clock */
 131 +//                 baud_base = sb_alp_clock(sbh);
 132 +                 baud_base = 20000000;
 133                                 div = 1;
 134                                 /* Set the override bit so we don't divide it */
 135                                 W_REG(osh, &cc->corecontrol, CC_UARTCLKO);
 136 -                       }
 137 +
 138                         /* Internal backplane clock */
 139 -                       else if (rev >= 3) {
 140 -                               baud_base = sb_clock(sbh);
 141 -                               div = 2;        /* Minimum divisor */
 142 -                               W_REG(osh, &cc->clkdiv,
 143 +   } else if (rev >= 3) {
 144 +                                 baud_base = sb_clock(sbh);
 145 +                                 div = 2;      /* Minimum divisor */
 146 +                                 W_REG(osh, &cc->clkdiv,
 147                                       ((R_REG(osh, &cc->clkdiv) & ~CLKD_UART) | div));
 148 -                       }
 149 +
 150                         /* Fixed internal backplane clock */
 151 -                       else {
 152 +   } else {
 153                                 baud_base = 88000000;
 154                                 div = 48;
 155                         }