package/rt2x00/src/rt2500usb.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500usb
  23         Abstract: Data structures and registers for the rt2500usb module.
  24         Supported chipsets: RT2570.
  25  */
  26
  27 #ifndef RT2500USB_H
  28 #define RT2500USB_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF2522                          0x0000
  34 #define RF2523                          0x0001
  35 #define RF2524                          0x0002
  36 #define RF2525                          0x0003
  37 #define RF2525E                         0x0005
  38 #define RF5222                          0x0010
  39
  40 /*
  41  * Max RSSI value, required for RSSI <-> dBm conversion.
  42  */
  43 #define MAX_RX_SSI                      120
  44 #define MAX_RX_NOISE                    -110
  45
  46 /*
  47  * Register layout information.
  48  */
  49 #define CSR_REG_BASE                    0x0400
  50 #define CSR_REG_SIZE                    0x0100
  51 #define EEPROM_BASE                     0x0000
  52 #define EEPROM_SIZE                     0x006a
  53 #define BBP_SIZE                        0x0060
  54
  55 /*
  56  * Control/Status Registers(CSR).
  57  * Some values are set in TU, whereas 1 TU == 1024 us.
  58  */
  59
  60 /*
  61  * MAC_CSR0: ASIC revision number.
  62  */
  63 #define MAC_CSR0                        0x0400
  64
  65 /*
  66  * MAC_CSR1: System control.
  67  */
  68 #define MAC_CSR1                        0x0402
  69
  70 /*
  71  * MAC_CSR2: STA MAC register 0.
  72  */
  73 #define MAC_CSR2                        0x0404
  74 #define MAC_CSR2_BYTE0                  FIELD16(0x00ff)
  75 #define MAC_CSR2_BYTE1                  FIELD16(0xff00)
  76
  77 /*
  78  * MAC_CSR3: STA MAC register 1.
  79  */
  80 #define MAC_CSR3                        0x0406
  81 #define MAC_CSR3_BYTE2                  FIELD16(0x00ff)
  82 #define MAC_CSR3_BYTE3                  FIELD16(0xff00)
  83
  84 /*
  85  * MAC_CSR4: STA MAC register 2.
  86  */
  87 #define MAC_CSR4                        0X0408
  88 #define MAC_CSR4_BYTE4                  FIELD16(0x00ff)
  89 #define MAC_CSR4_BYTE5                  FIELD16(0xff00)
  90
  91 /*
  92  * MAC_CSR5: BSSID register 0.
  93  */
  94 #define MAC_CSR5                        0x040a
  95 #define MAC_CSR5_BYTE0                  FIELD16(0x00ff)
  96 #define MAC_CSR5_BYTE1                  FIELD16(0xff00)
  97
  98 /*
  99  * MAC_CSR6: BSSID register 1.
 100  */
 101 #define MAC_CSR6                        0x040c
 102 #define MAC_CSR6_BYTE2                  FIELD16(0x00ff)
 103 #define MAC_CSR6_BYTE3                  FIELD16(0xff00)
 104
 105 /*
 106  * MAC_CSR7: BSSID register 2.
 107  */
 108 #define MAC_CSR7                        0x040e
 109 #define MAC_CSR7_BYTE4                  FIELD16(0x00ff)
 110 #define MAC_CSR7_BYTE5                  FIELD16(0xff00)
 111
 112 /*
 113  * MAC_CSR8: Max frame length.
 114  */
 115 #define MAC_CSR8                        0x0410
 116 #define MAC_CSR8_MAX_FRAME_UNIT         FIELD16(0x0fff)
 117
 118 /*
 119  * Misc MAC_CSR registers.
 120  * MAC_CSR9: Timer control.
 121  * MAC_CSR10: Slot time.
 122  * MAC_CSR11: IFS.
 123  * MAC_CSR12: EIFS.
 124  * MAC_CSR13: Power mode0.
 125  * MAC_CSR14: Power mode1.
 126  * MAC_CSR15: Power saving transition0
 127  * MAC_CSR16: Power saving transition1
 128  */
 129 #define MAC_CSR9                        0x0412
 130 #define MAC_CSR10                       0x0414
 131 #define MAC_CSR11                       0x0416
 132 #define MAC_CSR12                       0x0418
 133 #define MAC_CSR13                       0x041a
 134 #define MAC_CSR14                       0x041c
 135 #define MAC_CSR15                       0x041e
 136 #define MAC_CSR16                       0x0420
 137
 138 /*
 139  * MAC_CSR17: Manual power control / status register.
 140  * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
 141  * SET_STATE: Set state. Write 1 to trigger, self cleared.
 142  * BBP_DESIRE_STATE: BBP desired state.
 143  * RF_DESIRE_STATE: RF desired state.
 144  * BBP_CURRENT_STATE: BBP current state.
 145  * RF_CURRENT_STATE: RF current state.
 146  * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
 147  */
 148 #define MAC_CSR17                       0x0422
 149 #define MAC_CSR17_SET_STATE             FIELD16(0x0001)
 150 #define MAC_CSR17_BBP_DESIRE_STATE      FIELD16(0x0006)
 151 #define MAC_CSR17_RF_DESIRE_STATE       FIELD16(0x0018)
 152 #define MAC_CSR17_BBP_CURR_STATE        FIELD16(0x0060)
 153 #define MAC_CSR17_RF_CURR_STATE         FIELD16(0x0180)
 154 #define MAC_CSR17_PUT_TO_SLEEP          FIELD16(0x0200)
 155
 156 /*
 157  * MAC_CSR18: Wakeup timer register.
 158  * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
 159  * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
 160  * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
 161  */
 162 #define MAC_CSR18                       0x0424
 163 #define MAC_CSR18_DELAY_AFTER_BEACON    FIELD16(0x00ff)
 164 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
 165 #define MAC_CSR18_AUTO_WAKE             FIELD16(0x8000)
 166
 167 /*
 168  * MAC_CSR19: GPIO control register.
 169  */
 170 #define MAC_CSR19                       0x0426
 171
 172 /*
 173  * MAC_CSR20: LED control register.
 174  * ACTIVITY: 0: idle, 1: active.
 175  * LINK: 0: linkoff, 1: linkup.
 176  * ACTIVITY_POLARITY: 0: active low, 1: active high.
 177  */
 178 #define MAC_CSR20                       0x0428
 179 #define MAC_CSR20_ACTIVITY              FIELD16(0x0001)
 180 #define MAC_CSR20_LINK                  FIELD16(0x0002)
 181 #define MAC_CSR20_ACTIVITY_POLARITY     FIELD16(0x0004)
 182
 183 /*
 184  * MAC_CSR21: LED control register.
 185  * ON_PERIOD: On period, default 70ms.
 186  * OFF_PERIOD: Off period, default 30ms.
 187  */
 188 #define MAC_CSR21                       0x042a
 189 #define MAC_CSR21_ON_PERIOD             FIELD16(0x00ff)
 190 #define MAC_CSR21_OFF_PERIOD            FIELD16(0xff00)
 191
 192 /*
 193  * Collision window control register.
 194  */
 195 #define MAC_CSR22                       0x042c
 196
 197 /*
 198  * Transmit related CSRs.
 199  * Some values are set in TU, whereas 1 TU == 1024 us.
 200  */
 201
 202 /*
 203  * TXRX_CSR0: Security control register.
 204  */
 205 #define TXRX_CSR0                       0x0440
 206 #define TXRX_CSR0_ALGORITHM             FIELD16(0x0007)
 207 #define TXRX_CSR0_IV_OFFSET             FIELD16(0x01f8)
 208 #define TXRX_CSR0_KEY_ID                FIELD16(0x1e00)
 209
 210 /*
 211  * TXRX_CSR1: TX configuration.
 212  * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
 213  * TSF_OFFSET: TSF offset in MAC header.
 214  * AUTO_SEQUENCE: Let ASIC control frame sequence number.
 215  */
 216 #define TXRX_CSR1                       0x0442
 217 #define TXRX_CSR1_ACK_TIMEOUT           FIELD16(0x00ff)
 218 #define TXRX_CSR1_TSF_OFFSET            FIELD16(0x7f00)
 219 #define TXRX_CSR1_AUTO_SEQUENCE         FIELD16(0x8000)
 220
 221 /*
 222  * TXRX_CSR2: RX control.
 223  * DISABLE_RX: Disable rx engine.
 224  * DROP_CRC: Drop crc error.
 225  * DROP_PHYSICAL: Drop physical error.
 226  * DROP_CONTROL: Drop control frame.
 227  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 228  * DROP_TODS: Drop frame tods bit is true.
 229  * DROP_VERSION_ERROR: Drop version error frame.
 230  * DROP_MCAST: Drop multicast frames.
 231  * DROP_BCAST: Drop broadcast frames.
 232  */
 233 #define TXRX_CSR2                       0x0444
 234 #define TXRX_CSR2_DISABLE_RX            FIELD16(0x0001)
 235 #define TXRX_CSR2_DROP_CRC              FIELD16(0x0002)
 236 #define TXRX_CSR2_DROP_PHYSICAL         FIELD16(0x0004)
 237 #define TXRX_CSR2_DROP_CONTROL          FIELD16(0x0008)
 238 #define TXRX_CSR2_DROP_NOT_TO_ME        FIELD16(0x0010)
 239 #define TXRX_CSR2_DROP_TODS             FIELD16(0x0020)
 240 #define TXRX_CSR2_DROP_VERSION_ERROR    FIELD16(0x0040)
 241 #define TXRX_CSR2_DROP_MCAST            FIELD16(0x0200)
 242 #define TXRX_CSR2_DROP_BCAST            FIELD16(0x0400)
 243
 244 /*
 245  * RX BBP ID registers
 246  * TXRX_CSR3: CCK RX BBP ID.
 247  * TXRX_CSR4: OFDM RX BBP ID.
 248  */
 249 #define TXRX_CSR3                       0x0446
 250 #define TXRX_CSR4                       0x0448
 251
 252 /*
 253  * TX BBP ID registers
 254  * TXRX_CSR5: CCK TX BBP ID0.
 255  * TXRX_CSR5: CCK TX BBP ID1.
 256  * TXRX_CSR5: OFDM TX BBP ID0.
 257  * TXRX_CSR5: OFDM TX BBP ID1.
 258  */
 259 #define TXRX_CSR5                       0x044a
 260 #define TXRX_CSR6                       0x044c
 261 #define TXRX_CSR7                       0x044e
 262 #define TXRX_CSR8                       0x0450
 263
 264 /*
 265  * TXRX_CSR9: TX ACK time-out.
 266  */
 267 #define TXRX_CSR9                       0x0452
 268
 269 /*
 270  * TXRX_CSR10: Auto responder control.
 271  */
 272 #define TXRX_CSR10                      0x0454
 273 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
 274
 275 /*
 276  * TXRX_CSR11: Auto responder basic rate.
 277  */
 278 #define TXRX_CSR11                      0x0456
 279
 280 /*
 281  * ACK/CTS time registers.
 282  */
 283 #define TXRX_CSR12                      0x0458
 284 #define TXRX_CSR13                      0x045a
 285 #define TXRX_CSR14                      0x045c
 286 #define TXRX_CSR15                      0x045e
 287 #define TXRX_CSR16                      0x0460
 288 #define TXRX_CSR17                      0x0462
 289
 290 /*
 291  * TXRX_CSR18: Synchronization control register.
 292  */
 293 #define TXRX_CSR18                      0x0464
 294 #define TXRX_CSR18_OFFSET               FIELD16(0x000f)
 295 #define TXRX_CSR18_INTERVAL             FIELD16(0xfff0)
 296
 297 /*
 298  * TXRX_CSR19: Synchronization control register.
 299  * TSF_COUNT: Enable TSF auto counting.
 300  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 301  * TBCN: Enable Tbcn with reload value.
 302  * BEACON_GEN: Enable beacon generator.
 303  */
 304 #define TXRX_CSR19                      0x0466
 305 #define TXRX_CSR19_TSF_COUNT            FIELD16(0x0001)
 306 #define TXRX_CSR19_TSF_SYNC             FIELD16(0x0006)
 307 #define TXRX_CSR19_TBCN                 FIELD16(0x0008)
 308 #define TXRX_CSR19_BEACON_GEN           FIELD16(0x0010)
 309
 310 /*
 311  * TXRX_CSR20: Tx BEACON offset time control register.
 312  * OFFSET: In units of usec.
 313  * BCN_EXPECT_WINDOW: Default: 2^CWmin
 314  */
 315 #define TXRX_CSR20                      0x0468
 316 #define TXRX_CSR20_OFFSET               FIELD16(0x1fff)
 317 #define TXRX_CSR20_BCN_EXPECT_WINDOW    FIELD16(0xe000)
 318
 319 /*
 320  * TXRX_CSR21
 321  */
 322 #define TXRX_CSR21                      0x046a
 323
 324 /*
 325  * Encryption related CSRs.
 326  *
 327  */
 328
 329 /*
 330  * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
 331  */
 332 #define SEC_CSR0                        0x0480
 333 #define SEC_CSR1                        0x0482
 334 #define SEC_CSR2                        0x0484
 335 #define SEC_CSR3                        0x0486
 336 #define SEC_CSR4                        0x0488
 337 #define SEC_CSR5                        0x048a
 338 #define SEC_CSR6                        0x048c
 339 #define SEC_CSR7                        0x048e
 340
 341 /*
 342  * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
 343  */
 344 #define SEC_CSR8                        0x0490
 345 #define SEC_CSR9                        0x0492
 346 #define SEC_CSR10                       0x0494
 347 #define SEC_CSR11                       0x0496
 348 #define SEC_CSR12                       0x0498
 349 #define SEC_CSR13                       0x049a
 350 #define SEC_CSR14                       0x049c
 351 #define SEC_CSR15                       0x049e
 352
 353 /*
 354  * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
 355  */
 356 #define SEC_CSR16                       0x04a0
 357 #define SEC_CSR17                       0x04a2
 358 #define SEC_CSR18                       0X04A4
 359 #define SEC_CSR19                       0x04a6
 360 #define SEC_CSR20                       0x04a8
 361 #define SEC_CSR21                       0x04aa
 362 #define SEC_CSR22                       0x04ac
 363 #define SEC_CSR23                       0x04ae
 364
 365 /*
 366  * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
 367  */
 368 #define SEC_CSR24                       0x04b0
 369 #define SEC_CSR25                       0x04b2
 370 #define SEC_CSR26                       0x04b4
 371 #define SEC_CSR27                       0x04b6
 372 #define SEC_CSR28                       0x04b8
 373 #define SEC_CSR29                       0x04ba
 374 #define SEC_CSR30                       0x04bc
 375 #define SEC_CSR31                       0x04be
 376
 377 /*
 378  * PHY control registers.
 379  */
 380
 381 /*
 382  * PHY_CSR0: RF switching timing control.
 383  */
 384 #define PHY_CSR0                        0x04c0
 385
 386 /*
 387  * PHY_CSR1: TX PA configuration.
 388  */
 389 #define PHY_CSR1                        0x04c2
 390
 391 /*
 392  * MAC configuration registers.
 393  * PHY_CSR2: TX MAC configuration.
 394  * PHY_CSR3: RX MAC configuration.
 395  */
 396 #define PHY_CSR2                        0x04c4
 397 #define PHY_CSR3                        0x04c6
 398
 399 /*
 400  * PHY_CSR4: Interface configuration.
 401  */
 402 #define PHY_CSR4                        0x04c8
 403
 404 /*
 405  * BBP pre-TX registers.
 406  * PHY_CSR5: BBP pre-TX CCK.
 407  */
 408 #define PHY_CSR5                        0x04ca
 409 #define PHY_CSR5_CCK                    FIELD16(0x0003)
 410 #define PHY_CSR5_CCK_FLIP               FIELD16(0x0004)
 411
 412 /*
 413  * BBP pre-TX registers.
 414  * PHY_CSR6: BBP pre-TX OFDM.
 415  */
 416 #define PHY_CSR6                        0x04cc
 417 #define PHY_CSR6_OFDM                   FIELD16(0x0003)
 418 #define PHY_CSR6_OFDM_FLIP              FIELD16(0x0004)
 419
 420 /*
 421  * PHY_CSR7: BBP access register 0.
 422  * BBP_DATA: BBP data.
 423  * BBP_REG_ID: BBP register ID.
 424  * BBP_READ_CONTROL: 0: write, 1: read.
 425  */
 426 #define PHY_CSR7                        0x04ce
 427 #define PHY_CSR7_DATA                   FIELD16(0x00ff)
 428 #define PHY_CSR7_REG_ID                 FIELD16(0x7f00)
 429 #define PHY_CSR7_READ_CONTROL           FIELD16(0x8000)
 430
 431 /*
 432  * PHY_CSR8: BBP access register 1.
 433  * BBP_BUSY: ASIC is busy execute BBP programming.
 434  */
 435 #define PHY_CSR8                        0x04d0
 436 #define PHY_CSR8_BUSY                   FIELD16(0x0001)
 437
 438 /*
 439  * PHY_CSR9: RF access register.
 440  * RF_VALUE: Register value + id to program into rf/if.
 441  */
 442 #define PHY_CSR9                        0x04d2
 443 #define PHY_CSR9_RF_VALUE               FIELD16(0xffff)
 444
 445 /*
 446  * PHY_CSR10: RF access register.
 447  * RF_VALUE: Register value + id to program into rf/if.
 448  * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
 449  * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
 450  * RF_PLL_LD: Rf pll_ld status.
 451  * RF_BUSY: 1: asic is busy execute rf programming.
 452  */
 453 #define PHY_CSR10                       0x04d4
 454 #define PHY_CSR10_RF_VALUE              FIELD16(0x00ff)
 455 #define PHY_CSR10_RF_NUMBER_OF_BITS     FIELD16(0x1f00)
 456 #define PHY_CSR10_RF_IF_SELECT          FIELD16(0x2000)
 457 #define PHY_CSR10_RF_PLL_LD             FIELD16(0x4000)
 458 #define PHY_CSR10_RF_BUSY               FIELD16(0x8000)
 459
 460 /*
 461  * STA_CSR0: FCS error count.
 462  * FCS_ERROR: FCS error count, cleared when read.
 463  */
 464 #define STA_CSR0                        0x04e0
 465 #define STA_CSR0_FCS_ERROR              FIELD16(0xffff)
 466
 467 /*
 468  * Statistic Register.
 469  * STA_CSR1: PLCP error.
 470  * STA_CSR2: LONG error.
 471  * STA_CSR3: CCA false alarm.
 472  * STA_CSR4: RX FIFO overflow.
 473  * STA_CSR5: Beacon sent counter.
 474  */
 475 #define STA_CSR1                        0x04e2
 476 #define STA_CSR2                        0x04e4
 477 #define STA_CSR3                        0x04e6
 478 #define STA_CSR4                        0x04e8
 479 #define STA_CSR5                        0x04ea
 480 #define STA_CSR6                        0x04ec
 481 #define STA_CSR7                        0x04ee
 482 #define STA_CSR8                        0x04f0
 483 #define STA_CSR9                        0x04f2
 484 #define STA_CSR10                       0x04f4
 485
 486 /*
 487  * RF registers.
 488  */
 489 #define RF1_TUNER                       FIELD32(0x00020000)
 490 #define RF3_TUNER                       FIELD32(0x00000100)
 491 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 492
 493 /*
 494  * EEPROM contents.
 495  */
 496
 497 /*
 498  * HW MAC address.
 499  */
 500 #define EEPROM_MAC_ADDR_0               0x0002
 501 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 502 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
 503 #define EEPROM_MAC_ADDR1                0x0003
 504 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
 505 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
 506 #define EEPROM_MAC_ADDR_2               0x0004
 507 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
 508 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
 509
 510 /*
 511  * EEPROM antenna.
 512  * ANTENNA_NUM: Number of antenna's.
 513  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 514  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
 515  * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
 516  * DYN_TXAGC: Dynamic TX AGC control.
 517  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
 518  * RF_TYPE: Rf_type of this adapter.
 519  */
 520 #define EEPROM_ANTENNA                  0x000b
 521 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
 522 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
 523 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
 524 #define EEPROM_ANTENNA_LED_MODE         FIELD16(0x01c0)
 525 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
 526 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
 527 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
 528
 529 /*
 530  * EEPROM NIC config.
 531  * CARDBUS_ACCEL: 0: enable, 1: disable.
 532  * DYN_BBP_TUNE: 0: enable, 1: disable.
 533  * CCK_TX_POWER: CCK TX power compensation.
 534  */
 535 #define EEPROM_NIC                      0x000c
 536 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0001)
 537 #define EEPROM_NIC_DYN_BBP_TUNE         FIELD16(0x0002)
 538 #define EEPROM_NIC_CCK_TX_POWER         FIELD16(0x000c)
 539
 540 /*
 541  * EEPROM geography.
 542  * GEO: Default geography setting for device.
 543  */
 544 #define EEPROM_GEOGRAPHY                0x000d
 545 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0x0f00)
 546
 547 /*
 548  * EEPROM BBP.
 549  */
 550 #define EEPROM_BBP_START                0x000e
 551 #define EEPROM_BBP_SIZE                 16
 552 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
 553 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
 554
 555 /*
 556  * EEPROM TXPOWER
 557  */
 558 #define EEPROM_TXPOWER_START            0x001e
 559 #define EEPROM_TXPOWER_SIZE             7
 560 #define EEPROM_TXPOWER_1                FIELD16(0x00ff)
 561 #define EEPROM_TXPOWER_2                FIELD16(0xff00)
 562
 563 /*
 564  * EEPROM Tuning threshold
 565  */
 566 #define EEPROM_BBPTUNE                  0x0030
 567 #define EEPROM_BBPTUNE_THRESHOLD        FIELD16(0x00ff)
 568
 569 /*
 570  * EEPROM BBP R24 Tuning.
 571  */
 572 #define EEPROM_BBPTUNE_R24              0x0031
 573 #define EEPROM_BBPTUNE_R24_LOW          FIELD16(0x00ff)
 574 #define EEPROM_BBPTUNE_R24_HIGH         FIELD16(0xff00)
 575
 576 /*
 577  * EEPROM BBP R25 Tuning.
 578  */
 579 #define EEPROM_BBPTUNE_R25              0x0032
 580 #define EEPROM_BBPTUNE_R25_LOW          FIELD16(0x00ff)
 581 #define EEPROM_BBPTUNE_R25_HIGH         FIELD16(0xff00)
 582
 583 /*
 584  * EEPROM BBP R24 Tuning.
 585  */
 586 #define EEPROM_BBPTUNE_R61              0x0033
 587 #define EEPROM_BBPTUNE_R61_LOW          FIELD16(0x00ff)
 588 #define EEPROM_BBPTUNE_R61_HIGH         FIELD16(0xff00)
 589
 590 /*
 591  * EEPROM BBP VGC Tuning.
 592  */
 593 #define EEPROM_BBPTUNE_VGC              0x0034
 594 #define EEPROM_BBPTUNE_VGCUPPER         FIELD16(0x00ff)
 595
 596 /*
 597  * EEPROM BBP R17 Tuning.
 598  */
 599 #define EEPROM_BBPTUNE_R17              0x0035
 600 #define EEPROM_BBPTUNE_R17_LOW          FIELD16(0x00ff)
 601 #define EEPROM_BBPTUNE_R17_HIGH         FIELD16(0xff00)
 602
 603 /*
 604  * RSSI <-> dBm offset calibration
 605  */
 606 #define EEPROM_CALIBRATE_OFFSET         0x0036
 607 #define EEPROM_CALIBRATE_OFFSET_RSSI    FIELD16(0x00ff)
 608
 609 /*
 610  * BBP content.
 611  * The wordsize of the BBP is 8 bits.
 612  */
 613
 614 /*
 615  * BBP_R2: TX antenna control
 616  */
 617 #define BBP_R2_TX_ANTENNA               FIELD8(0x03)
 618 #define BBP_R2_TX_IQ_FLIP               FIELD8(0x04)
 619
 620 /*
 621  * BBP_R14: RX antenna control
 622  */
 623 #define BBP_R14_RX_ANTENNA              FIELD8(0x03)
 624 #define BBP_R14_RX_IQ_FLIP              FIELD8(0x04)
 625
 626 /*
 627  * DMA descriptor defines.
 628  */
 629 #define TXD_DESC_SIZE                   ( 5 * sizeof(struct data_desc) )
 630 #define RXD_DESC_SIZE                   ( 4 * sizeof(struct data_desc) )
 631
 632 /*
 633  * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
 634  */
 635
 636 /*
 637  * Word0
 638  */
 639 #define TXD_W0_PACKET_ID                FIELD32(0x0000000f)
 640 #define TXD_W0_RETRY_LIMIT              FIELD32(0x000000f0)
 641 #define TXD_W0_MORE_FRAG                FIELD32(0x00000100)
 642 #define TXD_W0_ACK                      FIELD32(0x00000200)
 643 #define TXD_W0_TIMESTAMP                FIELD32(0x00000400)
 644 #define TXD_W0_OFDM                     FIELD32(0x00000800)
 645 #define TXD_W0_NEW_SEQ                  FIELD32(0x00001000)
 646 #define TXD_W0_IFS                      FIELD32(0x00006000)
 647 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 648 #define TXD_W0_CIPHER                   FIELD32(0x20000000)
 649 #define TXD_W0_KEY_ID                   FIELD32(0xc0000000)
 650
 651 /*
 652  * Word1
 653  */
 654 #define TXD_W1_IV_OFFSET                FIELD32(0x0000003f)
 655 #define TXD_W1_AIFS                     FIELD32(0x000000c0)
 656 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
 657 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
 658
 659 /*
 660  * Word2: PLCP information
 661  */
 662 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
 663 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
 664 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
 665 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
 666
 667 /*
 668  * Word3
 669  */
 670 #define TXD_W3_IV                       FIELD32(0xffffffff)
 671
 672 /*
 673  * Word4
 674  */
 675 #define TXD_W4_EIV                      FIELD32(0xffffffff)
 676
 677 /*
 678  * RX descriptor format for RX Ring.
 679  */
 680
 681 /*
 682  * Word0
 683  */
 684 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000002)
 685 #define RXD_W0_MULTICAST                FIELD32(0x00000004)
 686 #define RXD_W0_BROADCAST                FIELD32(0x00000008)
 687 #define RXD_W0_MY_BSS                   FIELD32(0x00000010)
 688 #define RXD_W0_CRC                      FIELD32(0x00000020)
 689 #define RXD_W0_OFDM                     FIELD32(0x00000040)
 690 #define RXD_W0_PHYSICAL_ERROR           FIELD32(0x00000080)
 691 #define RXD_W0_CIPHER                   FIELD32(0x00000100)
 692 #define RXD_W0_CI_ERROR                 FIELD32(0x00000200)
 693 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
 694
 695 /*
 696  * Word1
 697  */
 698 #define RXD_W1_RSSI                     FIELD32(0x000000ff)
 699 #define RXD_W1_SIGNAL                   FIELD32(0x0000ff00)
 700
 701 /*
 702  * Word2
 703  */
 704 #define RXD_W2_IV                       FIELD32(0xffffffff)
 705
 706 /*
 707  * Word3
 708  */
 709 #define RXD_W3_EIV                      FIELD32(0xffffffff)
 710
 711 /*
 712  * Macro's for converting txpower from EEPROM to dscape value
 713  * and from dscape value to register value.
 714  */
 715 #define MIN_TXPOWER     0
 716 #define MAX_TXPOWER     31
 717 #define DEFAULT_TXPOWER 24
 718
 719 #define TXPOWER_FROM_DEV(__txpower)             \
 720 ({                                              \
 721         ((__txpower) > MAX_TXPOWER) ?           \
 722                 DEFAULT_TXPOWER : (__txpower);  \
 723 })
 724
 725 #define TXPOWER_TO_DEV(__txpower)                       \
 726 ({                                                      \
 727         ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
 728         (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
 729         (__txpower));                                   \
 730 })
 731
 732 /*
 733  * Interrupt functions.
 734  */
 735 static void rt2500usb_interrupt_rxdone(struct urb *urb);
 736
 737 #endif /* RT2500USB_H */