package/rt2x00/src/rt61pci.h

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: Data structures and registers for the rt61pci module.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #ifndef RT61PCI_H
  28 #define RT61PCI_H
  29
  30 /*
  31  * RF chip defines.
  32  */
  33 #define RF5225                          0x0001
  34 #define RF5325                          0x0002
  35 #define RF2527                          0x0003
  36 #define RF2529                          0x0004
  37
  38 /*
  39  * Max RSSI value, required for RSSI <-> dBm conversion.
  40  */
  41 #define MAX_RX_SSI                      120
  42 #define MAX_RX_NOISE                    -110
  43
  44 /*
  45  * Register layout information.
  46  */
  47 #define CSR_REG_BASE                    0x3000
  48 #define CSR_REG_SIZE                    0x04b0
  49 #define EEPROM_BASE                     0x0000
  50 #define EEPROM_SIZE                     0x0100
  51 #define BBP_SIZE                        0x0080
  52
  53 /*
  54  * PCI registers.
  55  */
  56
  57 /*
  58  * PCI Configuration Header
  59  */
  60 #define PCI_CONFIG_HEADER_VENDOR        0x0000
  61 #define PCI_CONFIG_HEADER_DEVICE        0x0002
  62
  63 /*
  64  * HOST_CMD_CSR: For HOST to interrupt embedded processor
  65  */
  66 #define HOST_CMD_CSR                    0x0008
  67 #define HOST_CMD_CSR_HOST_COMMAND       FIELD32(0x0000007f)
  68 #define HOST_CMD_CSR_INTERRUPT_MCU      FIELD32(0x00000080)
  69
  70 /*
  71  * MCU_CNTL_CSR
  72  * SELECT_BANK: Select 8051 program bank.
  73  * RESET: Enable 8051 reset state.
  74  * READY: Ready state for 8051.
  75  */
  76 #define MCU_CNTL_CSR                    0x000c
  77 #define MCU_CNTL_CSR_SELECT_BANK        FIELD32(0x00000001)
  78 #define MCU_CNTL_CSR_RESET              FIELD32(0x00000002)
  79 #define MCU_CNTL_CSR_READY              FIELD32(0x00000004)
  80
  81 /*
  82  * SOFT_RESET_CSR
  83  */
  84 #define SOFT_RESET_CSR                  0x0010
  85
  86 /*
  87  * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
  88  */
  89 #define MCU_INT_SOURCE_CSR              0x0014
  90 #define MCU_INT_SOURCE_CSR_0            FIELD32(0x00000001)
  91 #define MCU_INT_SOURCE_CSR_1            FIELD32(0x00000002)
  92 #define MCU_INT_SOURCE_CSR_2            FIELD32(0x00000004)
  93 #define MCU_INT_SOURCE_CSR_3            FIELD32(0x00000008)
  94 #define MCU_INT_SOURCE_CSR_4            FIELD32(0x00000010)
  95 #define MCU_INT_SOURCE_CSR_5            FIELD32(0x00000020)
  96 #define MCU_INT_SOURCE_CSR_6            FIELD32(0x00000040)
  97 #define MCU_INT_SOURCE_CSR_7            FIELD32(0x00000080)
  98 #define MCU_INT_SOURCE_CSR_TWAKEUP      FIELD32(0x00000100)
  99 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE  FIELD32(0x00000200)
 100
 101 /*
 102  * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
 103  */
 104 #define MCU_INT_MASK_CSR                0x0018
 105 #define MCU_INT_MASK_CSR_0              FIELD32(0x00000001)
 106 #define MCU_INT_MASK_CSR_1              FIELD32(0x00000002)
 107 #define MCU_INT_MASK_CSR_2              FIELD32(0x00000004)
 108 #define MCU_INT_MASK_CSR_3              FIELD32(0x00000008)
 109 #define MCU_INT_MASK_CSR_4              FIELD32(0x00000010)
 110 #define MCU_INT_MASK_CSR_5              FIELD32(0x00000020)
 111 #define MCU_INT_MASK_CSR_6              FIELD32(0x00000040)
 112 #define MCU_INT_MASK_CSR_7              FIELD32(0x00000080)
 113 #define MCU_INT_MASK_CSR_TWAKEUP        FIELD32(0x00000100)
 114 #define MCU_INT_MASK_CSR_TBTT_EXPIRE    FIELD32(0x00000200)
 115
 116 /*
 117  * PCI_USEC_CSR
 118  */
 119 #define PCI_USEC_CSR                    0x001c
 120
 121 /*
 122  * Security key table memory.
 123  * 16 entries 32-byte for shared key table
 124  * 64 entries 32-byte for pairwise key table
 125  * 64 entries 8-byte for pairwise ta key table
 126  */
 127 #define SHARED_KEY_TABLE_BASE           0x1000
 128 #define PAIRWISE_KEY_TABLE_BASE         0x1200
 129 #define PAIRWISE_TA_TABLE_BASE          0x1a00
 130
 131 struct hw_key_entry {
 132         u8 key[16];
 133         u8 tx_mic[8];
 134         u8 rx_mic[8];
 135 } __attribute__ ((packed));
 136
 137 struct hw_pairwise_ta_entry {
 138         u8 address[6];
 139         u8 reserved[2];
 140 } __attribute__ ((packed));
 141
 142 /*
 143  * Other on-chip shared memory space.
 144  */
 145 #define HW_CIS_BASE                     0x2000
 146 #define HW_NULL_BASE                    0x2b00
 147
 148 /*
 149  * Since NULL frame won't be that long (256 byte),
 150  * We steal 16 tail bytes to save debugging settings.
 151  */
 152 #define HW_DEBUG_SETTING_BASE           0x2bf0
 153
 154 /*
 155  * On-chip BEACON frame space.
 156  */
 157 #define HW_BEACON_BASE0                 0x2c00
 158 #define HW_BEACON_BASE1                 0x2d00
 159 #define HW_BEACON_BASE2                 0x2e00
 160 #define HW_BEACON_BASE3                 0x2f00
 161 #define HW_BEACON_OFFSET                0x0100
 162
 163 /*
 164  * HOST-MCU shared memory.
 165  */
 166
 167 /*
 168  * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
 169  */
 170 #define H2M_MAILBOX_CSR                 0x2100
 171 #define H2M_MAILBOX_CSR_ARG0            FIELD32(0x000000ff)
 172 #define H2M_MAILBOX_CSR_ARG1            FIELD32(0x0000ff00)
 173 #define H2M_MAILBOX_CSR_CMD_TOKEN       FIELD32(0x00ff0000)
 174 #define H2M_MAILBOX_CSR_OWNER           FIELD32(0xff000000)
 175
 176 /*
 177  * MCU_LEDCS: LED control for MCU Mailbox.
 178  */
 179 #define MCU_LEDCS_LED_MODE              FIELD16(0x001f)
 180 #define MCU_LEDCS_RADIO_STATUS          FIELD16(0x0020)
 181 #define MCU_LEDCS_LINK_BG_STATUS        FIELD16(0x0040)
 182 #define MCU_LEDCS_LINK_A_STATUS         FIELD16(0x0080)
 183 #define MCU_LEDCS_POLARITY_GPIO_0       FIELD16(0x0100)
 184 #define MCU_LEDCS_POLARITY_GPIO_1       FIELD16(0x0200)
 185 #define MCU_LEDCS_POLARITY_GPIO_2       FIELD16(0x0400)
 186 #define MCU_LEDCS_POLARITY_GPIO_3       FIELD16(0x0800)
 187 #define MCU_LEDCS_POLARITY_GPIO_4       FIELD16(0x1000)
 188 #define MCU_LEDCS_POLARITY_ACT          FIELD16(0x2000)
 189 #define MCU_LEDCS_POLARITY_READY_BG     FIELD16(0x4000)
 190 #define MCU_LEDCS_POLARITY_READY_A      FIELD16(0x8000)
 191
 192 /*
 193  * M2H_CMD_DONE_CSR.
 194  */
 195 #define M2H_CMD_DONE_CSR                0x2104
 196
 197 /*
 198  * MCU_TXOP_ARRAY_BASE.
 199  */
 200 #define MCU_TXOP_ARRAY_BASE             0x2110
 201
 202 /*
 203  * MAC Control/Status Registers(CSR).
 204  * Some values are set in TU, whereas 1 TU == 1024 us.
 205  */
 206
 207 /*
 208  * MAC_CSR0: ASIC revision number.
 209  */
 210 #define MAC_CSR0                        0x3000
 211
 212 /*
 213  * MAC_CSR1: System control register.
 214  * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
 215  * BBP_RESET: Hardware reset BBP.
 216  * HOST_READY: Host is ready after initialization, 1: ready.
 217  */
 218 #define MAC_CSR1                        0x3004
 219 #define MAC_CSR1_SOFT_RESET             FIELD32(0x00000001)
 220 #define MAC_CSR1_BBP_RESET              FIELD32(0x00000002)
 221 #define MAC_CSR1_HOST_READY             FIELD32(0x00000004)
 222
 223 /*
 224  * MAC_CSR2: STA MAC register 0.
 225  */
 226 #define MAC_CSR2                        0x3008
 227 #define MAC_CSR2_BYTE0                  FIELD32(0x000000ff)
 228 #define MAC_CSR2_BYTE1                  FIELD32(0x0000ff00)
 229 #define MAC_CSR2_BYTE2                  FIELD32(0x00ff0000)
 230 #define MAC_CSR2_BYTE3                  FIELD32(0xff000000)
 231
 232 /*
 233  * MAC_CSR3: STA MAC register 1.
 234  */
 235 #define MAC_CSR3                        0x300c
 236 #define MAC_CSR3_BYTE4                  FIELD32(0x000000ff)
 237 #define MAC_CSR3_BYTE5                  FIELD32(0x0000ff00)
 238 #define MAC_CSR3_UNICAST_TO_ME_MASK     FIELD32(0x00ff0000)
 239
 240 /*
 241  * MAC_CSR4: BSSID register 0.
 242  */
 243 #define MAC_CSR4                        0x3010
 244 #define MAC_CSR4_BYTE0                  FIELD32(0x000000ff)
 245 #define MAC_CSR4_BYTE1                  FIELD32(0x0000ff00)
 246 #define MAC_CSR4_BYTE2                  FIELD32(0x00ff0000)
 247 #define MAC_CSR4_BYTE3                  FIELD32(0xff000000)
 248
 249 /*
 250  * MAC_CSR5: BSSID register 1.
 251  * BSS_ID_MASK: 3: one BSSID, 0: 4 BSSID, 2 or 1: 2 BSSID.
 252  */
 253 #define MAC_CSR5                        0x3014
 254 #define MAC_CSR5_BYTE4                  FIELD32(0x000000ff)
 255 #define MAC_CSR5_BYTE5                  FIELD32(0x0000ff00)
 256 #define MAC_CSR5_BSS_ID_MASK            FIELD32(0x00ff0000)
 257
 258 /*
 259  * MAC_CSR6: Maximum frame length register.
 260  */
 261 #define MAC_CSR6                        0x3018
 262 #define MAC_CSR6_MAX_FRAME_UNIT         FIELD32(0x000007ff)
 263
 264 /*
 265  * MAC_CSR7: Reserved
 266  */
 267 #define MAC_CSR7                        0x301c
 268
 269 /*
 270  * MAC_CSR8: SIFS/EIFS register.
 271  * All units are in US.
 272  */
 273 #define MAC_CSR8                        0x3020
 274 #define MAC_CSR8_SIFS                   FIELD32(0x000000ff)
 275 #define MAC_CSR8_SIFS_AFTER_RX_OFDM     FIELD32(0x0000ff00)
 276 #define MAC_CSR8_EIFS                   FIELD32(0xffff0000)
 277
 278 /*
 279  * MAC_CSR9: Back-Off control register.
 280  * SLOT_TIME: Slot time, default is 20us for 802.11BG.
 281  * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
 282  * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
 283  * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
 284  */
 285 #define MAC_CSR9                        0x3024
 286 #define MAC_CSR9_SLOT_TIME              FIELD32(0x000000ff)
 287 #define MAC_CSR9_CWMIN                  FIELD32(0x00000f00)
 288 #define MAC_CSR9_CWMAX                  FIELD32(0x0000f000)
 289 #define MAC_CSR9_CW_SELECT              FIELD32(0x00010000)
 290
 291 /*
 292  * MAC_CSR10: Power state configuration.
 293  */
 294 #define MAC_CSR10                       0x3028
 295
 296 /*
 297  * MAC_CSR11: Power saving transition time register.
 298  * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
 299  * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
 300  * WAKEUP_LATENCY: In unit of TU.
 301  */
 302 #define MAC_CSR11                       0x302c
 303 #define MAC_CSR11_DELAY_AFTER_TBCN      FIELD32(0x000000ff)
 304 #define MAC_CSR11_TBCN_BEFORE_WAKEUP    FIELD32(0x00007f00)
 305 #define MAC_CSR11_AUTOWAKE              FIELD32(0x00008000)
 306 #define MAC_CSR11_WAKEUP_LATENCY        FIELD32(0x000f0000)
 307
 308 /*
 309  * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
 310  * CURRENT_STATE: 0:sleep, 1:awake.
 311  * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
 312  * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
 313  */
 314 #define MAC_CSR12                       0x3030
 315 #define MAC_CSR12_CURRENT_STATE         FIELD32(0x00000001)
 316 #define MAC_CSR12_PUT_TO_SLEEP          FIELD32(0x00000002)
 317 #define MAC_CSR12_FORCE_WAKEUP          FIELD32(0x00000004)
 318 #define MAC_CSR12_BBP_CURRENT_STATE     FIELD32(0x00000008)
 319
 320 /*
 321  * MAC_CSR13: GPIO.
 322  */
 323 #define MAC_CSR13                       0x3034
 324 #define MAC_CSR13_BIT0                  FIELD32(0x00000001)
 325 #define MAC_CSR13_BIT1                  FIELD32(0x00000002)
 326 #define MAC_CSR13_BIT2                  FIELD32(0x00000004)
 327 #define MAC_CSR13_BIT3                  FIELD32(0x00000008)
 328 #define MAC_CSR13_BIT4                  FIELD32(0x00000010)
 329 #define MAC_CSR13_BIT5                  FIELD32(0x00000020)
 330 #define MAC_CSR13_BIT6                  FIELD32(0x00000040)
 331 #define MAC_CSR13_BIT7                  FIELD32(0x00000080)
 332
 333 /*
 334  * MAC_CSR14: LED control register.
 335  * ON_PERIOD: On period, default 70ms.
 336  * OFF_PERIOD: Off period, default 30ms.
 337  * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
 338  * SW_LED: s/w LED, 1: ON, 0: OFF.
 339  * HW_LED_POLARITY: 0: active low, 1: active high.
 340  */
 341 #define MAC_CSR14                       0x3038
 342 #define MAC_CSR14_ON_PERIOD             FIELD32(0x000000ff)
 343 #define MAC_CSR14_OFF_PERIOD            FIELD32(0x0000ff00)
 344 #define MAC_CSR14_HW_LED                FIELD32(0x00010000)
 345 #define MAC_CSR14_SW_LED                FIELD32(0x00020000)
 346 #define MAC_CSR14_HW_LED_POLARITY       FIELD32(0x00040000)
 347 #define MAC_CSR14_SW_LED2               FIELD32(0x00080000)
 348
 349 /*
 350  * MAC_CSR15: NAV control.
 351  */
 352 #define MAC_CSR15                       0x303c
 353
 354 /*
 355  * TXRX control registers.
 356  * Some values are set in TU, whereas 1 TU == 1024 us.
 357  */
 358
 359 /*
 360  * TXRX_CSR0: TX/RX configuration register.
 361  * TSF_OFFSET: Default is 24.
 362  * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
 363  * DISABLE_RX: Disable Rx engine.
 364  * DROP_CRC: Drop CRC error.
 365  * DROP_PHYSICAL: Drop physical error.
 366  * DROP_CONTROL: Drop control frame.
 367  * DROP_NOT_TO_ME: Drop not to me unicast frame.
 368  * DROP_TO_DS: Drop fram ToDs bit is true.
 369  * DROP_VERSION_ERROR: Drop version error frame.
 370  * DROP_MULTICAST: Drop multicast frames.
 371  * DROP_BORADCAST: Drop broadcast frames.
 372  * ROP_ACK_CTS: Drop received ACK and CTS.
 373  */
 374 #define TXRX_CSR0                       0x3040
 375 #define TXRX_CSR0_RX_ACK_TIMEOUT        FIELD32(0x000001ff)
 376 #define TXRX_CSR0_TSF_OFFSET            FIELD32(0x00007e00)
 377 #define TXRX_CSR0_AUTO_TX_SEQ           FIELD32(0x00008000)
 378 #define TXRX_CSR0_DISABLE_RX            FIELD32(0x00010000)
 379 #define TXRX_CSR0_DROP_CRC              FIELD32(0x00020000)
 380 #define TXRX_CSR0_DROP_PHYSICAL         FIELD32(0x00040000)
 381 #define TXRX_CSR0_DROP_CONTROL          FIELD32(0x00080000)
 382 #define TXRX_CSR0_DROP_NOT_TO_ME        FIELD32(0x00100000)
 383 #define TXRX_CSR0_DROP_TO_DS            FIELD32(0x00200000)
 384 #define TXRX_CSR0_DROP_VERSION_ERROR    FIELD32(0x00400000)
 385 #define TXRX_CSR0_DROP_MULTICAST        FIELD32(0x00800000)
 386 #define TXRX_CSR0_DROP_BORADCAST        FIELD32(0x01000000)
 387 #define TXRX_CSR0_DROP_ACK_CTS          FIELD32(0x02000000)
 388 #define TXRX_CSR0_TX_WITHOUT_WAITING    FIELD32(0x04000000)
 389
 390 /*
 391  * TXRX_CSR1
 392  */
 393 #define TXRX_CSR1                       0x3044
 394
 395 /*
 396  * TXRX_CSR2
 397  */
 398 #define TXRX_CSR2                       0x3048
 399
 400 /*
 401  * TXRX_CSR3
 402  */
 403 #define TXRX_CSR3                       0x304c
 404
 405 /*
 406  * TXRX_CSR4: Auto-Responder/Tx-retry register.
 407  * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
 408  * OFDM_TX_RATE_DOWN: 1:enable.
 409  * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
 410  * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
 411  */
 412 #define TXRX_CSR4                       0x3050
 413 #define TXRX_CSR4_TX_ACK_TIMEOUT        FIELD32(0x000000ff)
 414 #define TXRX_CSR4_CNTL_ACK_POLICY       FIELD32(0x00000700)
 415 #define TXRX_CSR4_ACK_CTS_PSM           FIELD32(0x00010000)
 416 #define TXRX_CSR4_AUTORESPOND_ENABLE    FIELD32(0x00020000)
 417 #define TXRX_CSR4_AUTORESPOND_PREAMBLE  FIELD32(0x00040000)
 418 #define TXRX_CSR4_OFDM_TX_RATE_DOWN     FIELD32(0x00080000)
 419 #define TXRX_CSR4_OFDM_TX_RATE_STEP     FIELD32(0x00300000)
 420 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK  FIELD32(0x00400000)
 421 #define TXRX_CSR4_LONG_RETRY_LIMIT      FIELD32(0x0f000000)
 422 #define TXRX_CSR4_SHORT_RETRY_LIMIT     FIELD32(0xf0000000)
 423
 424 /*
 425  * TXRX_CSR5
 426  */
 427 #define TXRX_CSR5                       0x3054
 428
 429 /*
 430  * ACK/CTS payload consumed time registers.
 431  */
 432 #define TXRX_CSR6                       0x3058
 433 #define TXRX_CSR7                       0x305c
 434 #define TXRX_CSR8                       0x3060
 435
 436 /*
 437  * TXRX_CSR9: Synchronization control register.
 438  * BEACON_INTERVAL: In unit of 1/16 TU.
 439  * TSF_TICKING: Enable TSF auto counting.
 440  * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
 441  * BEACON_GEN: Enable beacon generator.
 442  */
 443 #define TXRX_CSR9                       0x3064
 444 #define TXRX_CSR9_BEACON_INTERVAL       FIELD32(0x0000ffff)
 445 #define TXRX_CSR9_TSF_TICKING           FIELD32(0x00010000)
 446 #define TXRX_CSR9_TSF_SYNC              FIELD32(0x00060000)
 447 #define TXRX_CSR9_TBTT_ENABLE           FIELD32(0x00080000)
 448 #define TXRX_CSR9_BEACON_GEN            FIELD32(0x00100000)
 449 #define TXRX_CSR9_TIMESTAMP_COMPENSATE  FIELD32(0xff000000)
 450
 451 /*
 452  * TXRX_CSR10: BEACON alignment.
 453  */
 454 #define TXRX_CSR10                      0x3068
 455
 456 /*
 457  * TXRX_CSR11: AES mask.
 458  */
 459 #define TXRX_CSR11                      0x306c
 460
 461 /*
 462  * TXRX_CSR12: TSF low 32.
 463  */
 464 #define TXRX_CSR12                      0x3070
 465 #define TXRX_CSR12_LOW_TSFTIMER         FIELD32(0xffffffff)
 466
 467 /*
 468  * TXRX_CSR13: TSF high 32.
 469  */
 470 #define TXRX_CSR13                      0x3074
 471 #define TXRX_CSR13_HIGH_TSFTIMER        FIELD32(0xffffffff)
 472
 473 /*
 474  * TXRX_CSR14: TBTT timer.
 475  */
 476 #define TXRX_CSR14                      0x3078
 477
 478 /*
 479  * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
 480  */
 481 #define TXRX_CSR15                      0x307c
 482
 483
 484 /*
 485  * PHY control registers.
 486  * Some values are set in TU, whereas 1 TU == 1024 us.
 487  */
 488
 489 /*
 490  * PHY_CSR0: RF/PS control.
 491  */
 492 #define PHY_CSR0                        0x3080
 493 #define PHY_CSR0_PA_PE_BG               FIELD32(0x00010000)
 494 #define PHY_CSR0_PA_PE_A                FIELD32(0x00020000)
 495
 496 /*
 497  * PHY_CSR1
 498  */
 499 #define PHY_CSR1                        0x3084
 500
 501 /*
 502  * PHY_CSR2: Pre-TX BBP control.
 503  */
 504 #define PHY_CSR2                        0x3088
 505
 506 /*
 507  * PHY_CSR3: BBP serial control register.
 508  * VALUE: Register value to program into BBP.
 509  * REG_NUM: Selected BBP register.
 510  * READ_CONTROL: 0: Write BBP, 1: Read BBP.
 511  * BUSY: 1: ASIC is busy execute BBP programming.
 512  */
 513 #define PHY_CSR3                        0x308c
 514 #define PHY_CSR3_VALUE                  FIELD32(0x000000ff)
 515 #define PHY_CSR3_REGNUM                 FIELD32(0x00007f00)
 516 #define PHY_CSR3_READ_CONTROL           FIELD32(0x00008000)
 517 #define PHY_CSR3_BUSY                   FIELD32(0x00010000)
 518
 519 /*
 520  * PHY_CSR4: RF serial control register
 521  * VALUE: Register value (include register id) serial out to RF/IF chip.
 522  * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
 523  * IF_SELECT: 1: select IF to program, 0: select RF to program.
 524  * PLL_LD: RF PLL_LD status.
 525  * BUSY: 1: ASIC is busy execute RF programming.
 526  */
 527 #define PHY_CSR4                        0x3090
 528 #define PHY_CSR4_VALUE                  FIELD32(0x00ffffff)
 529 #define PHY_CSR4_NUMBER_OF_BITS         FIELD32(0x1f000000)
 530 #define PHY_CSR4_IF_SELECT              FIELD32(0x20000000)
 531 #define PHY_CSR4_PLL_LD                 FIELD32(0x40000000)
 532 #define PHY_CSR4_BUSY                   FIELD32(0x80000000)
 533
 534 /*
 535  * PHY_CSR5: RX to TX signal switch timing control.
 536  */
 537 #define PHY_CSR5                        0x3094
 538
 539 /*
 540  * PHY_CSR6: TX to RX signal timing control.
 541  */
 542 #define PHY_CSR6                        0x3098
 543
 544 /*
 545  * PHY_CSR7: TX DAC switching timing control.
 546  */
 547 #define PHY_CSR7                        0x309c
 548
 549 /*
 550  * Security control register.
 551  */
 552
 553 /*
 554  * SEC_CSR0: Shared key table control.
 555  */
 556 #define SEC_CSR0                        0x30a0
 557
 558 /*
 559  * SEC_CSR1: Shared key table security mode register.
 560  */
 561 #define SEC_CSR1                        0x30a4
 562 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 563 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 564 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 565 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 566 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 567 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 568 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 569 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 570
 571 /*
 572  * Pairwise key table valid bitmap registers.
 573  * SEC_CSR2: pairwise key table valid bitmap 0.
 574  * SEC_CSR3: pairwise key table valid bitmap 1.
 575  */
 576 #define SEC_CSR2                        0x30a8
 577 #define SEC_CSR3                        0x30ac
 578
 579 /*
 580  * SEC_CSR4: Pairwise key table lookup control.
 581  */
 582 #define SEC_CSR4                        0x30b0
 583
 584 /*
 585  * SEC_CSR5: shared key table security mode register.
 586  */
 587 #define SEC_CSR5                        0x30b4
 588 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG   FIELD32(0x00000007)
 589 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG   FIELD32(0x00000070)
 590 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG   FIELD32(0x00000700)
 591 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG   FIELD32(0x00007000)
 592 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG   FIELD32(0x00070000)
 593 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG   FIELD32(0x00700000)
 594 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG   FIELD32(0x07000000)
 595 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG   FIELD32(0x70000000)
 596
 597 /*
 598  * STA control registers.
 599  */
 600
 601 /*
 602  * STA_CSR0: RX PLCP error count & RX FCS error count.
 603  */
 604 #define STA_CSR0                        0x30c0
 605 #define STA_CSR0_FCS_ERROR              FIELD32(0x0000ffff)
 606 #define STA_CSR0_PLCP_ERROR             FIELD32(0xffff0000)
 607
 608 /*
 609  * STA_CSR1: RX False CCA count & RX LONG frame count.
 610  */
 611 #define STA_CSR1                        0x30c4
 612 #define STA_CSR1_PHYSICAL_ERROR         FIELD32(0x0000ffff)
 613 #define STA_CSR1_FALSE_CCA_ERROR        FIELD32(0xffff0000)
 614
 615 /*
 616  * STA_CSR2: TX Beacon count and RX FIFO overflow count.
 617  */
 618 #define STA_CSR2                        0x30c8
 619 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
 620 #define STA_CSR2_RX_OVERFLOW_COUNT      FIELD32(0xffff0000)
 621
 622 /*
 623  * STA_CSR3: TX Beacon count.
 624  */
 625 #define STA_CSR3                        0x30cc
 626 #define STA_CSR3_TX_BEACON_COUNT        FIELD32(0x0000ffff)
 627
 628 /*
 629  * STA_CSR4: TX Result status register.
 630  * VALID: 1:This register contains a valid TX result.
 631  */
 632 #define STA_CSR4                        0x30d0
 633 #define STA_CSR4_VALID                  FIELD32(0x00000001)
 634 #define STA_CSR4_TX_RESULT              FIELD32(0x0000000e)
 635 #define STA_CSR4_RETRY_COUNT            FIELD32(0x000000f0)
 636 #define STA_CSR4_PID_SUBTYPE            FIELD32(0x00001f00)
 637 #define STA_CSR4_PID_TYPE               FIELD32(0x0000e000)
 638 #define STA_CSR4_TXRATE                 FIELD32(0x000f0000)
 639
 640 /*
 641  * QOS control registers.
 642  */
 643
 644 /*
 645  * QOS_CSR0: TXOP holder MAC address register.
 646  */
 647 #define QOS_CSR0                        0x30e0
 648 #define QOS_CSR0_BYTE0                  FIELD32(0x000000ff)
 649 #define QOS_CSR0_BYTE1                  FIELD32(0x0000ff00)
 650 #define QOS_CSR0_BYTE2                  FIELD32(0x00ff0000)
 651 #define QOS_CSR0_BYTE3                  FIELD32(0xff000000)
 652
 653 /*
 654  * QOS_CSR1: TXOP holder MAC address register.
 655  */
 656 #define QOS_CSR1                        0x30e4
 657 #define QOS_CSR1_BYTE4                  FIELD32(0x000000ff)
 658 #define QOS_CSR1_BYTE5                  FIELD32(0x0000ff00)
 659
 660 /*
 661  * QOS_CSR2: TXOP holder timeout register.
 662  */
 663 #define QOS_CSR2                        0x30e8
 664
 665 /*
 666  * RX QOS-CFPOLL MAC address register.
 667  * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
 668  * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
 669  */
 670 #define QOS_CSR3                        0x30ec
 671 #define QOS_CSR4                        0x30f0
 672
 673 /*
 674  * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
 675  */
 676 #define QOS_CSR5                        0x30f4
 677
 678 /*
 679  * Host DMA registers.
 680  */
 681
 682 /*
 683  * AC0_BASE_CSR: AC_BK base address.
 684  */
 685 #define AC0_BASE_CSR                    0x3400
 686 #define AC0_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 687
 688 /*
 689  * AC1_BASE_CSR: AC_BE base address.
 690  */
 691 #define AC1_BASE_CSR                    0x3404
 692 #define AC1_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 693
 694 /*
 695  * AC2_BASE_CSR: AC_VI base address.
 696  */
 697 #define AC2_BASE_CSR                    0x3408
 698 #define AC2_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 699
 700 /*
 701  * AC3_BASE_CSR: AC_VO base address.
 702  */
 703 #define AC3_BASE_CSR                    0x340c
 704 #define AC3_BASE_CSR_RING_REGISTER      FIELD32(0xffffffff)
 705
 706 /*
 707  * MGMT_BASE_CSR: MGMT ring base address.
 708  */
 709 #define MGMT_BASE_CSR                   0x3410
 710 #define MGMT_BASE_CSR_RING_REGISTER     FIELD32(0xffffffff)
 711
 712 /*
 713  * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
 714  */
 715 #define TX_RING_CSR0                    0x3418
 716 #define TX_RING_CSR0_AC0_RING_SIZE      FIELD32(0x000000ff)
 717 #define TX_RING_CSR0_AC1_RING_SIZE      FIELD32(0x0000ff00)
 718 #define TX_RING_CSR0_AC2_RING_SIZE      FIELD32(0x00ff0000)
 719 #define TX_RING_CSR0_AC3_RING_SIZE      FIELD32(0xff000000)
 720
 721 /*
 722  * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
 723  * TXD_SIZE: In unit of 32-bit.
 724  */
 725 #define TX_RING_CSR1                    0x341c
 726 #define TX_RING_CSR1_MGMT_RING_SIZE     FIELD32(0x000000ff)
 727 #define TX_RING_CSR1_HCCA_RING_SIZE     FIELD32(0x0000ff00)
 728 #define TX_RING_CSR1_TXD_SIZE           FIELD32(0x003f0000)
 729
 730 /*
 731  * AIFSN_CSR: AIFSN for each EDCA AC.
 732  * AIFSN0: For AC_BK.
 733  * AIFSN1: For AC_BE.
 734  * AIFSN2: For AC_VI.
 735  * AIFSN3: For AC_VO.
 736  */
 737 #define AIFSN_CSR                       0x3420
 738 #define AIFSN_CSR_AIFSN0                FIELD32(0x0000000f)
 739 #define AIFSN_CSR_AIFSN1                FIELD32(0x000000f0)
 740 #define AIFSN_CSR_AIFSN2                FIELD32(0x00000f00)
 741 #define AIFSN_CSR_AIFSN3                FIELD32(0x0000f000)
 742
 743 /*
 744  * CWMIN_CSR: CWmin for each EDCA AC.
 745  * CWMIN0: For AC_BK.
 746  * CWMIN1: For AC_BE.
 747  * CWMIN2: For AC_VI.
 748  * CWMIN3: For AC_VO.
 749  */
 750 #define CWMIN_CSR                       0x3424
 751 #define CWMIN_CSR_CWMIN0                FIELD32(0x0000000f)
 752 #define CWMIN_CSR_CWMIN1                FIELD32(0x000000f0)
 753 #define CWMIN_CSR_CWMIN2                FIELD32(0x00000f00)
 754 #define CWMIN_CSR_CWMIN3                FIELD32(0x0000f000)
 755
 756 /*
 757  * CWMAX_CSR: CWmax for each EDCA AC.
 758  * CWMAX0: For AC_BK.
 759  * CWMAX1: For AC_BE.
 760  * CWMAX2: For AC_VI.
 761  * CWMAX3: For AC_VO.
 762  */
 763 #define CWMAX_CSR                       0x3428
 764 #define CWMAX_CSR_CWMAX0                FIELD32(0x0000000f)
 765 #define CWMAX_CSR_CWMAX1                FIELD32(0x000000f0)
 766 #define CWMAX_CSR_CWMAX2                FIELD32(0x00000f00)
 767 #define CWMAX_CSR_CWMAX3                FIELD32(0x0000f000)
 768
 769 /*
 770  * TX_DMA_DST_CSR
 771  */
 772 #define TX_DMA_DST_CSR                  0x342c
 773
 774 /*
 775  * TX_CNTL_CSR: KICK/Abort TX.
 776  * KICK_TX_AC0: For AC_BK.
 777  * KICK_TX_AC1: For AC_BE.
 778  * KICK_TX_AC2: For AC_VI.
 779  * KICK_TX_AC3: For AC_VO.
 780  * ABORT_TX_AC0: For AC_BK.
 781  * ABORT_TX_AC1: For AC_BE.
 782  * ABORT_TX_AC2: For AC_VI.
 783  * ABORT_TX_AC3: For AC_VO.
 784  */
 785 #define TX_CNTL_CSR                     0x3430
 786 #define TX_CNTL_CSR_KICK_TX_AC0         FIELD32(0x00000001)
 787 #define TX_CNTL_CSR_KICK_TX_AC1         FIELD32(0x00000002)
 788 #define TX_CNTL_CSR_KICK_TX_AC2         FIELD32(0x00000004)
 789 #define TX_CNTL_CSR_KICK_TX_AC3         FIELD32(0x00000008)
 790 #define TX_CNTL_CSR_KICK_TX_MGMT        FIELD32(0x00000010)
 791 #define TX_CNTL_CSR_ABORT_TX_AC0        FIELD32(0x00010000)
 792 #define TX_CNTL_CSR_ABORT_TX_AC1        FIELD32(0x00020000)
 793 #define TX_CNTL_CSR_ABORT_TX_AC2        FIELD32(0x00040000)
 794 #define TX_CNTL_CSR_ABORT_TX_AC3        FIELD32(0x00080000)
 795 #define TX_CNTL_CSR_ABORT_TX_MGMT       FIELD32(0x00100000)
 796
 797 /*
 798  * LOAD_TX_RING_CSR
 799  */
 800 #define LOAD_TX_RING_CSR                0x3434
 801
 802 /*
 803  * Several read-only registers, for debugging.
 804  */
 805 #define AC0_TXPTR_CSR                   0x3438
 806 #define AC1_TXPTR_CSR                   0x343c
 807 #define AC2_TXPTR_CSR                   0x3440
 808 #define AC3_TXPTR_CSR                   0x3444
 809 #define MGMT_TXPTR_CSR                  0x3448
 810
 811 /*
 812  * RX_BASE_CSR
 813  */
 814 #define RX_BASE_CSR                     0x3450
 815 #define RX_BASE_CSR_RING_REGISTER       FIELD32(0xffffffff)
 816
 817 /*
 818  * RX_RING_CSR.
 819  * RXD_SIZE: In unit of 32-bit.
 820  */
 821 #define RX_RING_CSR                     0x3454
 822 #define RX_RING_CSR_RING_SIZE           FIELD32(0x000000ff)
 823 #define RX_RING_CSR_RXD_SIZE            FIELD32(0x00003f00)
 824 #define RX_RING_CSR_RXD_WRITEBACK_SIZE  FIELD32(0x00070000)
 825
 826 /*
 827  * RX_CNTL_CSR
 828  */
 829 #define RX_CNTL_CSR                     0x3458
 830
 831 /*
 832  * RXPTR_CSR: Read-only, for debugging.
 833  */
 834 #define RXPTR_CSR                       0x345c
 835
 836 /*
 837  * PCI_CFG_CSR
 838  */
 839 #define PCI_CFG_CSR                     0x3460
 840
 841 /*
 842  * BUF_FORMAT_CSR
 843  */
 844 #define BUF_FORMAT_CSR                  0x3464
 845
 846 /*
 847  * INT_SOURCE_CSR: Interrupt source register.
 848  * Write one to clear corresponding bit.
 849  */
 850 #define INT_SOURCE_CSR                  0x3468
 851 #define INT_SOURCE_CSR_TXDONE           FIELD32(0x00000001)
 852 #define INT_SOURCE_CSR_RXDONE           FIELD32(0x00000002)
 853 #define INT_SOURCE_CSR_BEACON_DONE      FIELD32(0x00000004)
 854 #define INT_SOURCE_CSR_TX_ABORT_DONE    FIELD32(0x00000010)
 855 #define INT_SOURCE_CSR_AC0_DMA_DONE     FIELD32(0x00010000)
 856 #define INT_SOURCE_CSR_AC1_DMA_DONE     FIELD32(0x00020000)
 857 #define INT_SOURCE_CSR_AC2_DMA_DONE     FIELD32(0x00040000)
 858 #define INT_SOURCE_CSR_AC3_DMA_DONE     FIELD32(0x00080000)
 859 #define INT_SOURCE_CSR_MGMT_DMA_DONE    FIELD32(0x00100000)
 860 #define INT_SOURCE_CSR_HCCA_DMA_DONE    FIELD32(0x00200000)
 861
 862 /*
 863  * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
 864  * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
 865  */
 866 #define INT_MASK_CSR                    0x346c
 867 #define INT_MASK_CSR_TXDONE             FIELD32(0x00000001)
 868 #define INT_MASK_CSR_RXDONE             FIELD32(0x00000002)
 869 #define INT_MASK_CSR_BEACON_DONE        FIELD32(0x00000004)
 870 #define INT_MASK_CSR_TX_ABORT_DONE      FIELD32(0x00000010)
 871 #define INT_MASK_CSR_ENABLE_MITIGATION  FIELD32(0x00000080)
 872 #define INT_MASK_CSR_MITIGATION_PERIOD  FIELD32(0x0000ff00)
 873 #define INT_MASK_CSR_AC0_DMA_DONE       FIELD32(0x00010000)
 874 #define INT_MASK_CSR_AC1_DMA_DONE       FIELD32(0x00020000)
 875 #define INT_MASK_CSR_AC2_DMA_DONE       FIELD32(0x00040000)
 876 #define INT_MASK_CSR_AC3_DMA_DONE       FIELD32(0x00080000)
 877 #define INT_MASK_CSR_MGMT_DMA_DONE      FIELD32(0x00100000)
 878 #define INT_MASK_CSR_HCCA_DMA_DONE      FIELD32(0x00200000)
 879
 880 /*
 881  * E2PROM_CSR: EEPROM control register.
 882  * RELOAD: Write 1 to reload eeprom content.
 883  * TYPE_93C46: 1: 93c46, 0:93c66.
 884  * LOAD_STATUS: 1:loading, 0:done.
 885  */
 886 #define E2PROM_CSR                      0x3470
 887 #define E2PROM_CSR_RELOAD               FIELD32(0x00000001)
 888 #define E2PROM_CSR_DATA_CLOCK           FIELD32(0x00000002)
 889 #define E2PROM_CSR_CHIP_SELECT          FIELD32(0x00000004)
 890 #define E2PROM_CSR_DATA_IN              FIELD32(0x00000008)
 891 #define E2PROM_CSR_DATA_OUT             FIELD32(0x00000010)
 892 #define E2PROM_CSR_TYPE_93C46           FIELD32(0x00000020)
 893 #define E2PROM_CSR_LOAD_STATUS          FIELD32(0x00000040)
 894
 895 /*
 896  * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
 897  * AC0_TX_OP: For AC_BK, in unit of 32us.
 898  * AC1_TX_OP: For AC_BE, in unit of 32us.
 899  */
 900 #define AC_TXOP_CSR0                    0x3474
 901 #define AC_TXOP_CSR0_AC0_TX_OP          FIELD32(0x0000ffff)
 902 #define AC_TXOP_CSR0_AC1_TX_OP          FIELD32(0xffff0000)
 903
 904 /*
 905  * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
 906  * AC2_TX_OP: For AC_VI, in unit of 32us.
 907  * AC3_TX_OP: For AC_VO, in unit of 32us.
 908  */
 909 #define AC_TXOP_CSR1                    0x3478
 910 #define AC_TXOP_CSR1_AC2_TX_OP          FIELD32(0x0000ffff)
 911 #define AC_TXOP_CSR1_AC3_TX_OP          FIELD32(0xffff0000)
 912
 913 /*
 914  * DMA_STATUS_CSR
 915  */
 916 #define DMA_STATUS_CSR                  0x3480
 917
 918 /*
 919  * TEST_MODE_CSR
 920  */
 921 #define TEST_MODE_CSR                   0x3484
 922
 923 /*
 924  * UART0_TX_CSR
 925  */
 926 #define UART0_TX_CSR                    0x3488
 927
 928 /*
 929  * UART0_RX_CSR
 930  */
 931 #define UART0_RX_CSR                    0x348c
 932
 933 /*
 934  * UART0_FRAME_CSR
 935  */
 936 #define UART0_FRAME_CSR                 0x3490
 937
 938 /*
 939  * UART0_BUFFER_CSR
 940  */
 941 #define UART0_BUFFER_CSR                0x3494
 942
 943 /*
 944  * IO_CNTL_CSR
 945  */
 946 #define IO_CNTL_CSR                     0x3498
 947
 948 /*
 949  * UART_INT_SOURCE_CSR
 950  */
 951 #define UART_INT_SOURCE_CSR             0x34a8
 952
 953 /*
 954  * UART_INT_MASK_CSR
 955  */
 956 #define UART_INT_MASK_CSR               0x34ac
 957
 958 /*
 959  * PBF_QUEUE_CSR
 960  */
 961 #define PBF_QUEUE_CSR                   0x34b0
 962
 963 /*
 964  * Firmware DMA registers.
 965  * Firmware DMA registers are dedicated for MCU usage
 966  * and should not be touched by host driver.
 967  * Therefore we skip the definition of these registers.
 968  */
 969 #define FW_TX_BASE_CSR                  0x34c0
 970 #define FW_TX_START_CSR                 0x34c4
 971 #define FW_TX_LAST_CSR                  0x34c8
 972 #define FW_MODE_CNTL_CSR                0x34cc
 973 #define FW_TXPTR_CSR                    0x34d0
 974
 975 /*
 976  * 8051 firmware image.
 977  */
 978 #define FIRMWARE_RT2561                 "rt2561.bin"
 979 #define FIRMWARE_RT2561s                "rt2561s.bin"
 980 #define FIRMWARE_RT2661                 "rt2661.bin"
 981 #define FIRMWARE_IMAGE_BASE             0x4000
 982
 983 /*
 984  * RF registers
 985  */
 986 #define RF3_TXPOWER                     FIELD32(0x00003e00)
 987 #define RF4_FREQ_OFFSET                 FIELD32(0x0003f000)
 988
 989 /*
 990  * EEPROM content.
 991  * The wordsize of the EEPROM is 16 bits.
 992  */
 993
 994 /*
 995  * HW MAC address.
 996  */
 997 #define EEPROM_MAC_ADDR_0               0x0002
 998 #define EEPROM_MAC_ADDR_BYTE0           FIELD16(0x00ff)
 999 #define EEPROM_MAC_ADDR_BYTE1           FIELD16(0xff00)
1000 #define EEPROM_MAC_ADDR1                0x0004
1001 #define EEPROM_MAC_ADDR_BYTE2           FIELD16(0x00ff)
1002 #define EEPROM_MAC_ADDR_BYTE3           FIELD16(0xff00)
1003 #define EEPROM_MAC_ADDR_2               0x0006
1004 #define EEPROM_MAC_ADDR_BYTE4           FIELD16(0x00ff)
1005 #define EEPROM_MAC_ADDR_BYTE5           FIELD16(0xff00)
1006
1007 /*
1008  * EEPROM antenna.
1009  * ANTENNA_NUM: Number of antenna's.
1010  * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1011  * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1012  * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1013  * DYN_TXAGC: Dynamic TX AGC control.
1014  * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1015  * RF_TYPE: Rf_type of this adapter.
1016  */
1017 #define EEPROM_ANTENNA                  0x0010
1018 #define EEPROM_ANTENNA_NUM              FIELD16(0x0003)
1019 #define EEPROM_ANTENNA_TX_DEFAULT       FIELD16(0x000c)
1020 #define EEPROM_ANTENNA_RX_DEFAULT       FIELD16(0x0030)
1021 #define EEPROM_ANTENNA_FRAME_TYPE       FIELD16(0x0040)
1022 #define EEPROM_ANTENNA_DYN_TXAGC        FIELD16(0x0200)
1023 #define EEPROM_ANTENNA_HARDWARE_RADIO   FIELD16(0x0400)
1024 #define EEPROM_ANTENNA_RF_TYPE          FIELD16(0xf800)
1025
1026 /*
1027  * EEPROM NIC config.
1028  * ENABLE_DIVERSITY: 1:enable, 0:disable.
1029  * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1030  * CARDBUS_ACCEL: 0:enable, 1:disable.
1031  * EXTERNAL_LNA_A: External LNA enable for 5G.
1032  */
1033 #define EEPROM_NIC                      0x0011
1034 #define EEPROM_NIC_ENABLE_DIVERSITY     FIELD16(0x0001)
1035 #define EEPROM_NIC_TX_DIVERSITY         FIELD16(0x0002)
1036 #define EEPROM_NIC_TX_RX_FIXED          FIELD16(0x000c)
1037 #define EEPROM_NIC_EXTERNAL_LNA_BG      FIELD16(0x0010)
1038 #define EEPROM_NIC_CARDBUS_ACCEL        FIELD16(0x0020)
1039 #define EEPROM_NIC_EXTERNAL_LNA_A       FIELD16(0x0040)
1040
1041 /*
1042  * EEPROM geography.
1043  * GEO_A: Default geographical setting for 5GHz band
1044  * GEO: Default geographical setting.
1045  */
1046 #define EEPROM_GEOGRAPHY                0x0012
1047 #define EEPROM_GEOGRAPHY_GEO_A          FIELD16(0x00ff)
1048 #define EEPROM_GEOGRAPHY_GEO            FIELD16(0xff00)
1049
1050 /*
1051  * EEPROM BBP.
1052  */
1053 #define EEPROM_BBP_START                0x0013
1054 #define EEPROM_BBP_SIZE                 16
1055 #define EEPROM_BBP_VALUE                FIELD16(0x00ff)
1056 #define EEPROM_BBP_REG_ID               FIELD16(0xff00)
1057
1058 /*
1059  * EEPROM TXPOWER 802.11G
1060  */
1061 #define EEPROM_TXPOWER_G_START          0x0023
1062 #define EEPROM_TXPOWER_G_SIZE           7
1063 #define EEPROM_TXPOWER_G_1              FIELD16(0x00ff)
1064 #define EEPROM_TXPOWER_G_2              FIELD16(0xff00)
1065
1066 /*
1067  * EEPROM Frequency
1068  */
1069 #define EEPROM_FREQ                     0x002f
1070 #define EEPROM_FREQ_OFFSET              FIELD16(0x00ff)
1071 #define EEPROM_FREQ_SEQ_MASK            FIELD16(0xff00)
1072 #define EEPROM_FREQ_SEQ                 FIELD16(0x0300)
1073
1074 /*
1075  * EEPROM LED.
1076  * POLARITY_RDY_G: Polarity RDY_G setting.
1077  * POLARITY_RDY_A: Polarity RDY_A setting.
1078  * POLARITY_ACT: Polarity ACT setting.
1079  * POLARITY_GPIO_0: Polarity GPIO0 setting.
1080  * POLARITY_GPIO_1: Polarity GPIO1 setting.
1081  * POLARITY_GPIO_2: Polarity GPIO2 setting.
1082  * POLARITY_GPIO_3: Polarity GPIO3 setting.
1083  * POLARITY_GPIO_4: Polarity GPIO4 setting.
1084  * LED_MODE: Led mode.
1085  */
1086 #define EEPROM_LED                      0x0030
1087 #define EEPROM_LED_POLARITY_RDY_G       FIELD16(0x0001)
1088 #define EEPROM_LED_POLARITY_RDY_A       FIELD16(0x0002)
1089 #define EEPROM_LED_POLARITY_ACT         FIELD16(0x0004)
1090 #define EEPROM_LED_POLARITY_GPIO_0      FIELD16(0x0008)
1091 #define EEPROM_LED_POLARITY_GPIO_1      FIELD16(0x0010)
1092 #define EEPROM_LED_POLARITY_GPIO_2      FIELD16(0x0020)
1093 #define EEPROM_LED_POLARITY_GPIO_3      FIELD16(0x0040)
1094 #define EEPROM_LED_POLARITY_GPIO_4      FIELD16(0x0080)
1095 #define EEPROM_LED_LED_MODE             FIELD16(0x1f00)
1096
1097 /*
1098  * EEPROM TXPOWER 802.11A
1099  */
1100 #define EEPROM_TXPOWER_A_START          0x0031
1101 #define EEPROM_TXPOWER_A_SIZE           12
1102 #define EEPROM_TXPOWER_A_1              FIELD16(0x00ff)
1103 #define EEPROM_TXPOWER_A_2              FIELD16(0xff00)
1104
1105 /*
1106  * BBP content.
1107  * The wordsize of the BBP is 8 bits.
1108  */
1109
1110 /*
1111  * BBP_R2
1112  */
1113 #define BBP_R2_BG_MODE                  FIELD8(0x20)
1114
1115 /*
1116  * BBP_R3
1117  */
1118 #define BBP_R3_SMART_MODE               FIELD8(0x01)
1119
1120 /*
1121  * BBP_R4: RX antenna control
1122  * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1123  */
1124 #define BBP_R4_RX_ANTENNA               FIELD8(0x03)
1125 #define BBP_R4_RX_FRAME_END             FIELD8(0x10)
1126 #define BBP_R4_RX_BG_MODE               FIELD8(0x20)
1127
1128 /*
1129  * BBP_R77
1130  */
1131 #define BBP_R77_PAIR                    FIELD8(0x03)
1132
1133 /*
1134  * MCU mailbox commands.
1135  */
1136 #define MCU_SLEEP                       0x30
1137 #define MCU_WAKEUP                      0x31
1138 #define MCU_LED                         0x50
1139 #define MCU_LED_STRENGTH                0x52
1140
1141 /*
1142  * DMA descriptor defines.
1143  */
1144 #define TXD_DESC_SIZE                   ( 16 * sizeof(struct data_desc) )
1145 #define RXD_DESC_SIZE                   ( 16 * sizeof(struct data_desc) )
1146
1147 /*
1148  * TX descriptor format for TX, PRIO and Beacon Ring.
1149  */
1150
1151 /*
1152  * Word0
1153  * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1154  * KEY_TABLE: Use per-client pairwise KEY table.
1155  * KEY_INDEX:
1156  * Key index (0~31) to the pairwise KEY table.
1157  * 0~3 to shared KEY table 0 (BSS0).
1158  * 4~7 to shared KEY table 1 (BSS1).
1159  * 8~11 to shared KEY table 2 (BSS2).
1160  * 12~15 to shared KEY table 3 (BSS3).
1161  * BURST: Next frame belongs to same "burst" event.
1162  */
1163 #define TXD_W0_OWNER_NIC                FIELD32(0x00000001)
1164 #define TXD_W0_VALID                    FIELD32(0x00000002)
1165 #define TXD_W0_MORE_FRAG                FIELD32(0x00000004)
1166 #define TXD_W0_ACK                      FIELD32(0x00000008)
1167 #define TXD_W0_TIMESTAMP                FIELD32(0x00000010)
1168 #define TXD_W0_OFDM                     FIELD32(0x00000020)
1169 #define TXD_W0_IFS                      FIELD32(0x00000040)
1170 #define TXD_W0_RETRY_MODE               FIELD32(0x00000080)
1171 #define TXD_W0_TKIP_MIC                 FIELD32(0x00000100)
1172 #define TXD_W0_KEY_TABLE                FIELD32(0x00000200)
1173 #define TXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1174 #define TXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1175 #define TXD_W0_BURST                    FIELD32(0x10000000)
1176 #define TXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1177
1178 /*
1179  * Word1
1180  * HOST_Q_ID: EDCA/HCCA queue ID.
1181  * HW_SEQUENCE: MAC overwrites the frame sequence number.
1182  * BUFFER_COUNT: Number of buffers in this TXD.
1183  */
1184 #define TXD_W1_HOST_Q_ID                FIELD32(0x0000000f)
1185 #define TXD_W1_AIFSN                    FIELD32(0x000000f0)
1186 #define TXD_W1_CWMIN                    FIELD32(0x00000f00)
1187 #define TXD_W1_CWMAX                    FIELD32(0x0000f000)
1188 #define TXD_W1_IV_OFFSET                FIELD32(0x003f0000)
1189 #define TXD_W1_PIGGY_BACK               FIELD32(0x01000000)
1190 #define TXD_W1_HW_SEQUENCE              FIELD32(0x10000000)
1191 #define TXD_W1_BUFFER_COUNT             FIELD32(0xe0000000)
1192
1193 /*
1194  * Word2: PLCP information
1195  */
1196 #define TXD_W2_PLCP_SIGNAL              FIELD32(0x000000ff)
1197 #define TXD_W2_PLCP_SERVICE             FIELD32(0x0000ff00)
1198 #define TXD_W2_PLCP_LENGTH_LOW          FIELD32(0x00ff0000)
1199 #define TXD_W2_PLCP_LENGTH_HIGH         FIELD32(0xff000000)
1200
1201 /*
1202  * Word3
1203  */
1204 #define TXD_W3_IV                       FIELD32(0xffffffff)
1205
1206 /*
1207  * Word4
1208  */
1209 #define TXD_W4_EIV                      FIELD32(0xffffffff)
1210
1211 /*
1212  * Word5
1213  * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1214  * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1215  * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1216  * WAITING_DMA_DONE_INT: TXD been filled with data
1217  * and waiting for TxDoneISR housekeeping.
1218  */
1219 #define TXD_W5_FRAME_OFFSET             FIELD32(0x000000ff)
1220 #define TXD_W5_PID_SUBTYPE              FIELD32(0x00001f00)
1221 #define TXD_W5_PID_TYPE                 FIELD32(0x0000e000)
1222 #define TXD_W5_TX_POWER                 FIELD32(0x00ff0000)
1223 #define TXD_W5_WAITING_DMA_DONE_INT     FIELD32(0x01000000)
1224
1225 /*
1226  * the above 24-byte is called TXINFO and will be DMAed to MAC block
1227  * through TXFIFO. MAC block use this TXINFO to control the transmission
1228  * behavior of this frame.
1229  * The following fields are not used by MAC block.
1230  * They are used by DMA block and HOST driver only.
1231  * Once a frame has been DMA to ASIC, all the following fields are useless
1232  * to ASIC.
1233  */
1234
1235 /*
1236  * Word6-10: Buffer physical address
1237  */
1238 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1239 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1240 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1241 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1242 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1243
1244 /*
1245  * Word11-13: Buffer length
1246  */
1247 #define TXD_W11_BUFFER_LENGTH0          FIELD32(0x00000fff)
1248 #define TXD_W11_BUFFER_LENGTH1          FIELD32(0x0fff0000)
1249 #define TXD_W12_BUFFER_LENGTH2          FIELD32(0x00000fff)
1250 #define TXD_W12_BUFFER_LENGTH3          FIELD32(0x0fff0000)
1251 #define TXD_W13_BUFFER_LENGTH4          FIELD32(0x00000fff)
1252
1253 /*
1254  * Word14
1255  */
1256 #define TXD_W14_SK_BUFFER               FIELD32(0xffffffff)
1257
1258 /*
1259  * Word15
1260  */
1261 #define TXD_W15_NEXT_SK_BUFFER          FIELD32(0xffffffff)
1262
1263 /*
1264  * RX descriptor format for RX Ring.
1265  */
1266
1267 /*
1268  * Word0
1269  * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1270  * KEY_INDEX: Decryption key actually used.
1271  */
1272 #define RXD_W0_OWNER_NIC                FIELD32(0x00000001)
1273 #define RXD_W0_DROP                     FIELD32(0x00000002)
1274 #define RXD_W0_UNICAST_TO_ME            FIELD32(0x00000004)
1275 #define RXD_W0_MULTICAST                FIELD32(0x00000008)
1276 #define RXD_W0_BROADCAST                FIELD32(0x00000010)
1277 #define RXD_W0_MY_BSS                   FIELD32(0x00000020)
1278 #define RXD_W0_CRC                      FIELD32(0x00000040)
1279 #define RXD_W0_OFDM                     FIELD32(0x00000080)
1280 #define RXD_W0_CIPHER_ERROR             FIELD32(0x00000300)
1281 #define RXD_W0_KEY_INDEX                FIELD32(0x0000fc00)
1282 #define RXD_W0_DATABYTE_COUNT           FIELD32(0x0fff0000)
1283 #define RXD_W0_CIPHER_ALG               FIELD32(0xe0000000)
1284
1285 /*
1286  * Word1
1287  * SIGNAL: RX raw data rate reported by BBP.
1288  * RSSI: RSSI reported by BBP.
1289  */
1290 #define RXD_W1_SIGNAL                   FIELD32(0x000000ff)
1291 #define RXD_W1_RSSI                     FIELD32(0x0000ff00)
1292 #define RXD_W1_FRAME_OFFSET             FIELD32(0x7f000000)
1293
1294 /*
1295  * Word2
1296  * IV: Received IV of originally encrypted.
1297  */
1298 #define RXD_W2_IV                       FIELD32(0xffffffff)
1299
1300 /*
1301  * Word3
1302  * EIV: Received EIV of originally encrypted.
1303  */
1304 #define RXD_W3_EIV                      FIELD32(0xffffffff)
1305
1306 /*
1307  * Word4
1308  */
1309 #define RXD_W4_RESERVED                 FIELD32(0xffffffff)
1310
1311 /*
1312  * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1313  * and passed to the HOST driver.
1314  * The following fields are for DMA block and HOST usage only.
1315  * Can't be touched by ASIC MAC block.
1316  */
1317
1318 /*
1319  * Word5
1320  */
1321 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS  FIELD32(0xffffffff)
1322
1323 /*
1324  * Word6-15: Reserved
1325  */
1326 #define RXD_W6_RESERVED                 FIELD32(0xffffffff)
1327 #define RXD_W7_RESERVED                 FIELD32(0xffffffff)
1328 #define RXD_W8_RESERVED                 FIELD32(0xffffffff)
1329 #define RXD_W9_RESERVED                 FIELD32(0xffffffff)
1330 #define RXD_W10_RESERVED                FIELD32(0xffffffff)
1331 #define RXD_W11_RESERVED                FIELD32(0xffffffff)
1332 #define RXD_W12_RESERVED                FIELD32(0xffffffff)
1333 #define RXD_W13_RESERVED                FIELD32(0xffffffff)
1334 #define RXD_W14_RESERVED                FIELD32(0xffffffff)
1335 #define RXD_W15_RESERVED                FIELD32(0xffffffff)
1336
1337 /*
1338  * Macro's for converting txpower from EEPROM to dscape value
1339  * and from dscape value to register value.
1340  */
1341 #define MIN_TXPOWER     0
1342 #define MAX_TXPOWER     31
1343 #define DEFAULT_TXPOWER 24
1344
1345 #define TXPOWER_FROM_DEV(__txpower)             \
1346 ({                                              \
1347         ((__txpower) > MAX_TXPOWER) ?           \
1348                 DEFAULT_TXPOWER : (__txpower);  \
1349 })
1350
1351 #define TXPOWER_TO_DEV(__txpower)                       \
1352 ({                                                      \
1353         ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER :    \
1354         (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER :   \
1355         (__txpower));                                   \
1356 })
1357
1358 #endif /* RT61PCI_H */