target/linux/adm5120/files/arch/mips/pci/pci-adm5120.c

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 PCI Host Controller driver
   5  *
   6  *  Copyright (C) ADMtek Incorporated.
   7  *  Copyright (C) 2005 Jeroen Vreeken (pe1rxq@amsat.org)
   8  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   9  *  Copyright (C) 2007 OpenWrt.org
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version 2
  14  *  of the License, or (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the
  23  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  24  *  Boston, MA  02110-1301, USA.
  25  *
  26  */
  27 #include <linux/types.h>
  28 #include <linux/kernel.h>
  29 #include <linux/init.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/io.h>
  32
  33 #include <linux/pci.h>
  34 #include <linux/pci_ids.h>
  35 #include <linux/pci_regs.h>
  36
  37 #include <asm/delay.h>
  38 #include <asm/bootinfo.h>
  39
  40 #include <adm5120_defs.h>
  41 #include <adm5120_info.h>
  42 #include <adm5120_defs.h>
  43 #include <adm5120_platform.h>
  44
  45 #undef DEBUG
  46
  47 #ifdef DEBUG
  48 #define DBG(f, a...)    printk(KERN_DEBUG f, ## a)
  49 #else
  50 #define DBG(f, a...)    do {} while (0)
  51 #endif
  52
  53 #define PCI_ENABLE 0x80000000
  54
  55 /* -------------------------------------------------------------------------*/
  56
  57 static unsigned int adm5120_pci_nr_irqs __initdata;
  58 static struct adm5120_pci_irq *adm5120_pci_irq_map __initdata;
  59
  60 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
  61
  62 /* -------------------------------------------------------------------------*/
  63
  64 static inline void write_cfgaddr(u32 addr)
  65 {
  66         __raw_writel((addr | PCI_ENABLE),
  67                 (void __iomem *)(KSEG1ADDR(ADM5120_PCICFG_ADDR)));
  68 }
  69
  70 static inline void write_cfgdata(u32 data)
  71 {
  72         __raw_writel(data, (void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
  73 }
  74
  75 static inline u32 read_cfgdata(void)
  76 {
  77         return __raw_readl((void __iomem *)KSEG1ADDR(ADM5120_PCICFG_DATA));
  78 }
  79
  80 static inline u32 mkaddr(struct pci_bus *bus, unsigned int devfn, int where)
  81 {
  82         return (((bus->number & 0xFF) << 16) | ((devfn & 0xFF) << 8) | \
  83                 (where & 0xFC));
  84 }
  85
  86 /* -------------------------------------------------------------------------*/
  87
  88 static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
  89                 int size, u32 *val)
  90 {
  91         unsigned long flags;
  92         u32 data;
  93
  94         spin_lock_irqsave(&pci_lock, flags);
  95
  96         write_cfgaddr(mkaddr(bus, devfn, where));
  97         data = read_cfgdata();
  98
  99         DBG("PCI: cfg_read  %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
 100                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 101                 where, size, data);
 102
 103         switch (size) {
 104         case 1:
 105                 if (where & 1)
 106                         data >>= 8;
 107                 if (where & 2)
 108                         data >>= 16;
 109                 data &= 0xFF;
 110                 break;
 111         case 2:
 112                 if (where & 2)
 113                         data >>= 16;
 114                 data &= 0xFFFF;
 115                 break;
 116         }
 117
 118         *val = data;
 119         DBG(", 0x%08X returned\n", data);
 120
 121         spin_unlock_irqrestore(&pci_lock, flags);
 122
 123         return PCIBIOS_SUCCESSFUL;
 124 }
 125
 126 static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
 127                 int size, u32 val)
 128 {
 129         unsigned long flags;
 130         u32 data;
 131         int s;
 132
 133         spin_lock_irqsave(&pci_lock, flags);
 134
 135         write_cfgaddr(mkaddr(bus, devfn, where));
 136         data = read_cfgdata();
 137
 138         DBG("PCI: cfg_write %02u.%02u.%01u/%02X:%01d, cfg:0x%08X",
 139                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 140                 where, size, data);
 141
 142         switch (size) {
 143         case 1:
 144                 s = ((where & 3) << 3);
 145                 data &= ~(0xFF << s);
 146                 data |= ((val & 0xFF) << s);
 147                 break;
 148         case 2:
 149                 s = ((where & 2) << 4);
 150                 data &= ~(0xFFFF << s);
 151                 data |= ((val & 0xFFFF) << s);
 152                 break;
 153         case 4:
 154                 data = val;
 155                 break;
 156         }
 157
 158         write_cfgdata(data);
 159         DBG(", 0x%08X written\n", data);
 160
 161         spin_unlock_irqrestore(&pci_lock, flags);
 162
 163         return PCIBIOS_SUCCESSFUL;
 164 }
 165
 166 struct pci_ops adm5120_pci_ops = {
 167         .read   = pci_config_read,
 168         .write  = pci_config_write,
 169 };
 170
 171 /* -------------------------------------------------------------------------*/
 172
 173 static void adm5120_pci_fixup(struct pci_dev *dev)
 174 {
 175         if (dev->devfn != 0)
 176                 return;
 177
 178         /* setup COMMAND register */
 179         pci_write_config_word(dev, PCI_COMMAND,
 180                 (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER));
 181
 182         /* setup CACHE_LINE_SIZE register */
 183         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
 184
 185         /* setup BARS */
 186         pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0);
 187         pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, 0);
 188 }
 189
 190 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADMTEK, PCI_DEVICE_ID_ADMTEK_ADM5120,
 191         adm5120_pci_fixup);
 192
 193 /* -------------------------------------------------------------------------*/
 194
 195 void __init adm5120_pci_set_irq_map(unsigned int nr_irqs,
 196                 struct adm5120_pci_irq *map)
 197 {
 198         adm5120_pci_nr_irqs = nr_irqs;
 199         adm5120_pci_irq_map = map;
 200 }
 201
 202 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 203 {
 204         int irq = -1;
 205         int i;
 206
 207         if ((!adm5120_pci_nr_irqs) || (!adm5120_pci_irq_map)) {
 208                 printk(KERN_ALERT "PCI: pci_irq_map is not initialized\n");
 209                 goto out;
 210         }
 211
 212         if (slot < 1 || slot > 3) {
 213                 printk(KERN_ALERT "PCI: slot number %u is not supported\n",
 214                         slot);
 215                 goto out;
 216         }
 217
 218         for (i = 0; i < adm5120_pci_nr_irqs; i++) {
 219                 if ((adm5120_pci_irq_map[i].slot == slot)
 220                         && (adm5120_pci_irq_map[i].func == PCI_FUNC(dev->devfn))
 221                         && (adm5120_pci_irq_map[i].pin == pin)) {
 222                         irq = adm5120_pci_irq_map[i].irq;
 223                         break;
 224                 }
 225         }
 226
 227         if (irq < 0) {
 228                 printk(KERN_ALERT "PCI: no irq found for %s pin:%u\n",
 229                         pci_name((struct pci_dev *)dev), pin);
 230         } else {
 231                 printk(KERN_INFO "PCI: mapping irq for %s pin:%u, irq:%d\n",
 232                         pci_name((struct pci_dev *)dev), pin, irq);
 233         }
 234
 235 out:
 236         return irq;
 237 }
 238
 239 int pcibios_plat_dev_init(struct pci_dev *dev)
 240 {
 241         return 0;
 242 }
 243
 244 /* -------------------------------------------------------------------------*/
 245
 246 static struct resource pci_io_resource = {
 247         .name   = "ADM5120 PCI I/O",
 248         .start  = ADM5120_PCIIO_BASE,
 249         .end    = ADM5120_PCICFG_ADDR-1,
 250         .flags  = IORESOURCE_IO
 251 };
 252
 253 static struct resource pci_mem_resource = {
 254         .name   = "ADM5120 PCI MEM",
 255         .start  = ADM5120_PCIMEM_BASE,
 256         .end    = ADM5120_PCIIO_BASE-1,
 257         .flags  = IORESOURCE_MEM
 258 };
 259
 260 static struct pci_controller adm5120_controller = {
 261         .pci_ops        = &adm5120_pci_ops,
 262         .io_resource    = &pci_io_resource,
 263         .mem_resource   = &pci_mem_resource,
 264 };
 265
 266 static int __init adm5120_pci_setup(void)
 267 {
 268         int pci_bios;
 269
 270         pci_bios = adm5120_has_pci();
 271
 272         printk(KERN_INFO "adm5120: system has %sPCI BIOS\n",
 273                 pci_bios ? "" : "no ");
 274         if (pci_bios == 0)
 275                 return -1;
 276
 277         /* Avoid ISA compat ranges.  */
 278         PCIBIOS_MIN_IO = 0x00000000;
 279         PCIBIOS_MIN_MEM = 0x00000000;
 280
 281         /* Set I/O resource limits.  */
 282         ioport_resource.end = 0x1fffffff;
 283         iomem_resource.end = 0xffffffff;
 284
 285         register_pci_controller(&adm5120_controller);
 286         return 0;
 287 }
 288
 289 arch_initcall(adm5120_pci_setup);