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enable support of the kendin switch on the ap1000, too
[openwrt.git] / target / linux / ifxmips / files / drivers / net / ifxmips_mii0.c
1 /*
2 * drivers/net/ifxmips_mii0.c
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) 2005 Infineon
19 *
20 * Rewrite of Infineon IFXMips code, thanks to infineon for the support,
21 * software and hardware
22 *
23 * Copyright (C) 2007 John Crispin <blogic@openwrt.org>
24 *
25 */
26
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/types.h>
31 #include <linux/interrupt.h>
32 #include <asm/uaccess.h>
33 #include <linux/in.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/skbuff.h>
39 #include <linux/mm.h>
40 #include <linux/platform_device.h>
41 #include <linux/ethtool.h>
42 #include <asm/checksum.h>
43 #include <linux/init.h>
44 #include <asm/delay.h>
45 #include <asm/ifxmips/ifxmips.h>
46 #include <asm/ifxmips/ifxmips_mii0.h>
47 #include <asm/ifxmips/ifxmips_dma.h>
48 #include <asm/ifxmips/ifxmips_pmu.h>
49
50 #define DRVNAME "ifxmips_mii0"
51
52 static struct net_device ifxmips_mii0_dev;
53 static unsigned char u_boot_ethaddr[MAX_ADDR_LEN];
54
55 void
56 ifxmips_write_mdio (u32 phy_addr, u32 phy_reg, u16 phy_data)
57 {
58 u32 val = MDIO_ACC_REQUEST |
59 ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
60 ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET) |
61 phy_data;
62
63 while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST);
64 writel(val, IFXMIPS_PPE32_MDIO_ACC);
65 }
66
67 unsigned short
68 ifxmips_read_mdio (u32 phy_addr, u32 phy_reg)
69 {
70 u32 val = MDIO_ACC_REQUEST | MDIO_ACC_READ |
71 ((phy_addr & MDIO_ACC_ADDR_MASK) << MDIO_ACC_ADDR_OFFSET) |
72 ((phy_reg & MDIO_ACC_REG_MASK) << MDIO_ACC_REG_OFFSET);
73
74 writel(val, IFXMIPS_PPE32_MDIO_ACC);
75 while (readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_REQUEST){};
76 val = readl(IFXMIPS_PPE32_MDIO_ACC) & MDIO_ACC_VAL_MASK;
77
78 return val;
79 }
80
81 int
82 ifxmips_switch_open (struct net_device *dev)
83 {
84 struct switch_priv* priv = (struct switch_priv*)dev->priv;
85 struct dma_device_info* dma_dev = priv->dma_device;
86 int i;
87
88 for (i = 0; i < dma_dev->max_rx_chan_num; i++)
89 {
90 if ((dma_dev->rx_chan[i])->control == IFXMIPS_DMA_CH_ON)
91 (dma_dev->rx_chan[i])->open(dma_dev->rx_chan[i]);
92 }
93
94 netif_start_queue(dev);
95
96 return 0;
97 }
98
99 int
100 switch_release (struct net_device *dev){
101 struct switch_priv* priv = (struct switch_priv*)dev->priv;
102 struct dma_device_info* dma_dev = priv->dma_device;
103 int i;
104
105 for (i = 0; i < dma_dev->max_rx_chan_num; i++)
106 dma_dev->rx_chan[i]->close(dma_dev->rx_chan[i]);
107
108 netif_stop_queue(dev);
109
110 return 0;
111 }
112
113 int
114 switch_hw_receive (struct net_device* dev,struct dma_device_info* dma_dev)
115 {
116 struct switch_priv *priv = (struct switch_priv*)dev->priv;
117 unsigned char* buf = NULL;
118 struct sk_buff *skb = NULL;
119 int len = 0;
120
121 len = dma_device_read(dma_dev, &buf, (void**)&skb);
122
123 if (len >= ETHERNET_PACKET_DMA_BUFFER_SIZE)
124 {
125 printk(KERN_INFO DRVNAME ": packet too large %d\n",len);
126 goto switch_hw_receive_err_exit;
127 }
128
129 /* remove CRC */
130 len -= 4;
131 if (skb == NULL )
132 {
133 printk(KERN_INFO DRVNAME ": cannot restore pointer\n");
134 goto switch_hw_receive_err_exit;
135 }
136
137 if (len > (skb->end - skb->tail))
138 {
139 printk(KERN_INFO DRVNAME ": BUG, len:%d end:%p tail:%p\n", (len+4), skb->end, skb->tail);
140 goto switch_hw_receive_err_exit;
141 }
142
143 skb_put(skb, len);
144 skb->dev = dev;
145 skb->protocol = eth_type_trans(skb, dev);
146 netif_rx(skb);
147
148 priv->stats.rx_packets++;
149 priv->stats.rx_bytes += len;
150
151 return 0;
152
153 switch_hw_receive_err_exit:
154 if (len == 0)
155 {
156 if(skb)
157 dev_kfree_skb_any(skb);
158 priv->stats.rx_errors++;
159 priv->stats.rx_dropped++;
160
161 return -EIO;
162 } else {
163 return len;
164 }
165 }
166
167 int
168 switch_hw_tx (char *buf, int len, struct net_device *dev)
169 {
170 int ret = 0;
171 struct switch_priv *priv = dev->priv;
172 struct dma_device_info* dma_dev = priv->dma_device;
173
174 ret = dma_device_write(dma_dev, buf, len, priv->skb);
175
176 return ret;
177 }
178
179 int
180 switch_tx (struct sk_buff *skb, struct net_device *dev)
181 {
182 int len;
183 char *data;
184 struct switch_priv *priv = dev->priv;
185 struct dma_device_info* dma_dev = priv->dma_device;
186
187 len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
188 data = skb->data;
189 priv->skb = skb;
190 dev->trans_start = jiffies;
191 // TODO we got more than 1 dma channel, so we should do something intelligent
192 // here to select one
193 dma_dev->current_tx_chan = 0;
194
195 wmb();
196
197 if (switch_hw_tx(data, len, dev) != len)
198 {
199 dev_kfree_skb_any(skb);
200 priv->stats.tx_errors++;
201 priv->stats.tx_dropped++;
202 } else {
203 priv->stats.tx_packets++;
204 priv->stats.tx_bytes+=len;
205 }
206
207 return 0;
208 }
209
210 void
211 switch_tx_timeout (struct net_device *dev)
212 {
213 int i;
214 struct switch_priv* priv = (struct switch_priv*)dev->priv;
215
216 priv->stats.tx_errors++;
217
218 for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
219 {
220 priv->dma_device->tx_chan[i]->disable_irq(priv->dma_device->tx_chan[i]);
221 }
222
223 netif_wake_queue(dev);
224
225 return;
226 }
227
228 int
229 dma_intr_handler (struct dma_device_info* dma_dev, int status)
230 {
231 int i;
232
233 switch (status)
234 {
235 case RCV_INT:
236 switch_hw_receive(&ifxmips_mii0_dev, dma_dev);
237 break;
238
239 case TX_BUF_FULL_INT:
240 printk(KERN_INFO DRVNAME ": tx buffer full\n");
241 netif_stop_queue(&ifxmips_mii0_dev);
242 for (i = 0; i < dma_dev->max_tx_chan_num; i++)
243 {
244 if ((dma_dev->tx_chan[i])->control==IFXMIPS_DMA_CH_ON)
245 dma_dev->tx_chan[i]->enable_irq(dma_dev->tx_chan[i]);
246 }
247 break;
248
249 case TRANSMIT_CPT_INT:
250 for (i = 0; i < dma_dev->max_tx_chan_num; i++)
251 dma_dev->tx_chan[i]->disable_irq(dma_dev->tx_chan[i]);
252
253 netif_wake_queue(&ifxmips_mii0_dev);
254 break;
255 }
256
257 return 0;
258 }
259
260 unsigned char*
261 ifxmips_etop_dma_buffer_alloc (int len, int *byte_offset, void **opt)
262 {
263 unsigned char *buffer = NULL;
264 struct sk_buff *skb = NULL;
265
266 skb = dev_alloc_skb(ETHERNET_PACKET_DMA_BUFFER_SIZE);
267 if (skb == NULL)
268 return NULL;
269
270 buffer = (unsigned char*)(skb->data);
271 skb_reserve(skb, 2);
272 *(int*)opt = (int)skb;
273 *byte_offset = 2;
274
275 return buffer;
276 }
277
278 void
279 ifxmips_etop_dma_buffer_free (unsigned char *dataptr, void *opt)
280 {
281 struct sk_buff *skb = NULL;
282
283 if(opt == NULL)
284 {
285 kfree(dataptr);
286 } else {
287 skb = (struct sk_buff*)opt;
288 dev_kfree_skb_any(skb);
289 }
290 }
291
292 static struct net_device_stats*
293 ifxmips_get_stats (struct net_device *dev)
294 {
295 return (struct net_device_stats *)dev->priv;
296 }
297
298 static int
299 switch_init (struct net_device *dev)
300 {
301 u64 retval = 0;
302 int i;
303 struct switch_priv *priv;
304
305 ether_setup(dev);
306
307 printk(KERN_INFO DRVNAME ": %s is up\n", dev->name);
308
309 dev->open = ifxmips_switch_open;
310 dev->stop = switch_release;
311 dev->hard_start_xmit = switch_tx;
312 dev->get_stats = ifxmips_get_stats;
313 dev->tx_timeout = switch_tx_timeout;
314 dev->watchdog_timeo = 10 * HZ;
315 dev->priv = kmalloc(sizeof(struct switch_priv), GFP_KERNEL);
316
317 if (dev->priv == NULL)
318 return -ENOMEM;
319
320 memset(dev->priv, 0, sizeof(struct switch_priv));
321 priv = dev->priv;
322
323 priv->dma_device = dma_device_reserve("PPE");
324
325 if (!priv->dma_device){
326 BUG();
327 return -ENODEV;
328 }
329
330 priv->dma_device->buffer_alloc = &ifxmips_etop_dma_buffer_alloc;
331 priv->dma_device->buffer_free = &ifxmips_etop_dma_buffer_free;
332 priv->dma_device->intr_handler = &dma_intr_handler;
333 priv->dma_device->max_rx_chan_num = 4;
334
335 for (i = 0; i < priv->dma_device->max_rx_chan_num; i++)
336 {
337 priv->dma_device->rx_chan[i]->packet_size = ETHERNET_PACKET_DMA_BUFFER_SIZE;
338 priv->dma_device->rx_chan[i]->control = IFXMIPS_DMA_CH_ON;
339 }
340
341 for (i = 0; i < priv->dma_device->max_tx_chan_num; i++)
342 {
343 if(i == 0)
344 priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_ON;
345 else
346 priv->dma_device->tx_chan[i]->control = IFXMIPS_DMA_CH_OFF;
347 }
348
349 dma_device_register(priv->dma_device);
350
351 /*read the mac address from the mac table and put them into the mac table.*/
352 for (i = 0; i < 6; i++)
353 retval += u_boot_ethaddr[i];
354
355 //TODO
356 /* ethaddr not set in u-boot ? */
357 if (retval == 0)
358 {
359 printk(KERN_INFO DRVNAME ": using default MAC address\n");
360 dev->dev_addr[0] = 0x00;
361 dev->dev_addr[1] = 0x11;
362 dev->dev_addr[2] = 0x22;
363 dev->dev_addr[3] = 0x33;
364 dev->dev_addr[4] = 0x44;
365 dev->dev_addr[5] = 0x55;
366 } else {
367 for (i = 0; i < 6; i++)
368 dev->dev_addr[i] = u_boot_ethaddr[i];
369 }
370
371 return 0;
372 }
373
374 static void
375 ifxmips_sw_chip_init (int mode)
376 {
377 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_DMA);
378 ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_PPE);
379
380 if(mode == REV_MII_MODE)
381 writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_REVERSE, IFXMIPS_PPE32_CFG);
382 else if(mode == MII_MODE)
383 writel((readl(IFXMIPS_PPE32_CFG) & PPE32_MII_MASK) | PPE32_MII_NORMAL, IFXMIPS_PPE32_CFG);
384
385 writel(PPE32_PLEN_UNDER | PPE32_PLEN_OVER, IFXMIPS_PPE32_IG_PLEN_CTRL);
386
387 writel(PPE32_CGEN, IFXMIPS_PPE32_ENET_MAC_CFG);
388
389 wmb();
390 }
391
392 static int
393 ifxmips_mii_probe(struct platform_device *dev)
394 {
395 int result = 0;
396
397 ifxmips_mii0_dev.init = switch_init;
398
399 strcpy(ifxmips_mii0_dev.name, "eth%d");
400 SET_MODULE_OWNER(dev);
401
402 result = register_netdev(&ifxmips_mii0_dev);
403 if (result)
404 {
405 printk(KERN_INFO DRVNAME ": error %i registering device \"%s\"\n", result, ifxmips_mii0_dev.name);
406 goto out;
407 }
408
409 /* ifxmips eval kit connects the phy/switch in REV mode */
410 ifxmips_sw_chip_init(REV_MII_MODE);
411 printk(KERN_INFO DRVNAME ": driver loaded!\n");
412
413 out:
414 return result;
415 }
416
417 static int
418 ifxmips_mii_remove(struct platform_device *dev)
419 {
420 struct switch_priv *priv = (struct switch_priv*)ifxmips_mii0_dev.priv;
421
422 printk(KERN_INFO DRVNAME ": ifxmips_mii0 cleanup\n");
423
424 dma_device_unregister(priv->dma_device);
425 dma_device_release(priv->dma_device);
426 kfree(priv->dma_device);
427 kfree(ifxmips_mii0_dev.priv);
428 unregister_netdev(&ifxmips_mii0_dev);
429
430 return 0;
431 }
432
433 static struct
434 platform_driver ifxmips_mii_driver = {
435 .probe = ifxmips_mii_probe,
436 .remove = ifxmips_mii_remove,
437 .driver = {
438 .name = DRVNAME,
439 .owner = THIS_MODULE,
440 },
441 };
442
443 int __init
444 ifxmips_mii_init(void)
445 {
446 int ret = platform_driver_register(&ifxmips_mii_driver);
447 if (ret)
448 printk(KERN_INFO DRVNAME ": Error registering platfom driver!");
449
450 return ret;
451 }
452
453 static void __exit
454 ifxmips_mii_cleanup(void)
455 {
456 platform_driver_unregister(&ifxmips_mii_driver);
457 }
458
459 module_init(ifxmips_mii_init);
460 module_exit(ifxmips_mii_cleanup);
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