target/linux/brcm-2.4/files/arch/mips/bcm947xx/include/bcmsrom.h

   1 /*
   2  * Misc useful routines to access NIC local SROM/OTP .
   3  *
   4  * Copyright 2007, Broadcom Corporation
   5  * All Rights Reserved.
   6  *
   7  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
   8  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
   9  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  10  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  11  *
  12  */
  13
  14 #ifndef _bcmsrom_h_
  15 #define _bcmsrom_h_
  16
  17 /* Maximum srom: 4 Kilobits == 512 bytes */
  18 #define SROM_MAX                512
  19
  20
  21 #define SROM_WORDS              64
  22
  23 #define SROM3_SWRGN_OFF         28      /* s/w region offset in words */
  24
  25 #define SROM_SSID               2
  26
  27 #define SROM_WL1LHMAXP          29
  28
  29 #define SROM_WL1LPAB0           30
  30 #define SROM_WL1LPAB1           31
  31 #define SROM_WL1LPAB2           32
  32
  33 #define SROM_WL1HPAB0           33
  34 #define SROM_WL1HPAB1           34
  35 #define SROM_WL1HPAB2           35
  36
  37 #define SROM_MACHI_IL0          36
  38 #define SROM_MACMID_IL0         37
  39 #define SROM_MACLO_IL0          38
  40 #define SROM_MACHI_ET0          39
  41 #define SROM_MACMID_ET0         40
  42 #define SROM_MACLO_ET0          41
  43 #define SROM_MACHI_ET1          42
  44 #define SROM_MACMID_ET1         43
  45 #define SROM_MACLO_ET1          44
  46 #define SROM3_MACHI             37
  47 #define SROM3_MACMID            38
  48 #define SROM3_MACLO             39
  49
  50 #define SROM_BXARSSI2G          40
  51 #define SROM_BXARSSI5G          41
  52
  53 #define SROM_TRI52G             42
  54 #define SROM_TRI5GHL            43
  55
  56 #define SROM_RXPO52G            45
  57
  58 #define SROM2_ENETPHY           45
  59
  60 #define SROM_AABREV             46
  61 /* Fields in AABREV */
  62 #define SROM_BR_MASK            0x00ff
  63 #define SROM_CC_MASK            0x0f00
  64 #define SROM_CC_SHIFT           8
  65 #define SROM_AA0_MASK           0x3000
  66 #define SROM_AA0_SHIFT          12
  67 #define SROM_AA1_MASK           0xc000
  68 #define SROM_AA1_SHIFT          14
  69
  70 #define SROM_WL0PAB0            47
  71 #define SROM_WL0PAB1            48
  72 #define SROM_WL0PAB2            49
  73
  74 #define SROM_LEDBH10            50
  75 #define SROM_LEDBH32            51
  76
  77 #define SROM_WL10MAXP           52
  78
  79 #define SROM_WL1PAB0            53
  80 #define SROM_WL1PAB1            54
  81 #define SROM_WL1PAB2            55
  82
  83 #define SROM_ITT                56
  84
  85 #define SROM_BFL                57
  86 #define SROM_BFL2               28
  87 #define SROM3_BFL2              61
  88
  89 #define SROM_AG10               58
  90
  91 #define SROM_CCODE              59
  92
  93 #define SROM_OPO                60
  94
  95 #define SROM3_LEDDC             62
  96
  97 #define SROM_CRCREV             63
  98
  99 /* SROM Rev 4: Reallocate the software part of the srom to accomodate
 100  * MIMO features. It assumes up to two PCIE functions and 440 bytes
 101  * of useable srom i.e. the useable storage in chips with OTP that
 102  * implements hardware redundancy.
 103  */
 104
 105 #define SROM4_WORDS             220
 106
 107 #define SROM4_SIGN              32
 108 #define SROM4_SIGNATURE         0x5372
 109
 110 #define SROM4_BREV              33
 111
 112 #define SROM4_BFL0              34
 113 #define SROM4_BFL1              35
 114 #define SROM4_BFL2              36
 115 #define SROM4_BFL3              37
 116 #define SROM5_BFL0              37
 117 #define SROM5_BFL1              38
 118 #define SROM5_BFL2              39
 119 #define SROM5_BFL3              40
 120
 121 #define SROM4_MACHI             38
 122 #define SROM4_MACMID            39
 123 #define SROM4_MACLO             40
 124 #define SROM5_MACHI             41
 125 #define SROM5_MACMID            42
 126 #define SROM5_MACLO             43
 127
 128 #define SROM4_CCODE             41
 129 #define SROM4_REGREV            42
 130 #define SROM5_CCODE             34
 131 #define SROM5_REGREV            35
 132
 133 #define SROM4_LEDBH10           43
 134 #define SROM4_LEDBH32           44
 135 #define SROM5_LEDBH10           59
 136 #define SROM5_LEDBH32           60
 137
 138 #define SROM4_LEDDC             45
 139 #define SROM5_LEDDC             45
 140
 141 #define SROM4_AA                46
 142 #define SROM4_AA2G_MASK         0x00ff
 143 #define SROM4_AA2G_SHIFT        0
 144 #define SROM4_AA5G_MASK         0xff00
 145 #define SROM4_AA5G_SHIFT        8
 146
 147 #define SROM4_AG10              47
 148 #define SROM4_AG32              48
 149
 150 #define SROM4_TXPID2G           49
 151 #define SROM4_TXPID5G           51
 152 #define SROM4_TXPID5GL          53
 153 #define SROM4_TXPID5GH          55
 154
 155 #define SROM4_TXRXC             61
 156 #define SROM4_TXCHAIN_MASK      0x000f
 157 #define SROM4_TXCHAIN_SHIFT     0
 158 #define SROM4_RXCHAIN_MASK      0x00f0
 159 #define SROM4_RXCHAIN_SHIFT     4
 160 #define SROM4_SWITCH_MASK       0xff00
 161 #define SROM4_SWITCH_SHIFT      8
 162
 163 /* Per-path fields */
 164 #define MAX_PATH                4
 165 #define SROM4_PATH0             64
 166 #define SROM4_PATH1             87
 167 #define SROM4_PATH2             110
 168 #define SROM4_PATH3             133
 169
 170 #define SROM4_2G_ITT_MAXP       0
 171 #define SROM4_2G_PA             1
 172 #define SROM4_5G_ITT_MAXP       5
 173 #define SROM4_5GLH_MAXP         6
 174 #define SROM4_5G_PA             7
 175 #define SROM4_5GL_PA            11
 176 #define SROM4_5GH_PA            15
 177
 178 /* Fields in the ITT_MAXP and 5GLH_MAXP words */
 179 #define B2G_MAXP_MASK           0xff
 180 #define B2G_ITT_SHIFT           8
 181 #define B5G_MAXP_MASK           0xff
 182 #define B5G_ITT_SHIFT           8
 183 #define B5GH_MAXP_MASK          0xff
 184 #define B5GL_MAXP_SHIFT         8
 185
 186 /* All the miriad power offsets */
 187 #define SROM4_2G_CCKPO          156
 188 #define SROM4_2G_OFDMPO         157
 189 #define SROM4_5G_OFDMPO         159
 190 #define SROM4_5GL_OFDMPO        161
 191 #define SROM4_5GH_OFDMPO        163
 192 #define SROM4_2G_MCSPO          165
 193 #define SROM4_5G_MCSPO          173
 194 #define SROM4_5GL_MCSPO         181
 195 #define SROM4_5GH_MCSPO         189
 196 #define SROM4_CDDPO             197
 197 #define SROM4_STBCPO            198
 198 #define SROM4_BW40PO            199
 199 #define SROM4_BWDUPPO           200
 200
 201 #define SROM4_CRCREV            219
 202
 203
 204 /*SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
 205  * This is acombined srom for both MIMO and SISO boards, usable in
 206  * the .130 4Kilobit OTP with hardware redundancy.
 207  */
 208
 209 #define SROM8_SIGN              64
 210
 211 #define SROM8_BREV              65
 212
 213 #define SROM8_BFL0              66
 214 #define SROM8_BFL1              67
 215 #define SROM8_BFL2              68
 216 #define SROM8_BFL3              69
 217
 218 #define SROM8_MACHI             70
 219 #define SROM8_MACMID            71
 220 #define SROM8_MACLO             72
 221
 222 #define SROM8_CCODE             73
 223 #define SROM8_REGREV            74
 224
 225 #define SROM8_LEDBH10           75
 226 #define SROM8_LEDBH32           76
 227
 228 #define SROM8_LEDDC             77
 229
 230 #define SROM8_AA                78
 231
 232 #define SROM8_AG10              79
 233 #define SROM8_AG32              80
 234
 235 #define SROM8_TXRXC             81
 236
 237 #define SROM8_BXARSSI2G         82
 238 #define SROM8_BXARSSI5G         83
 239 #define SROM8_TRI52G            84
 240 #define SROM8_TRI5GHL           85
 241 #define SROM8_RXPO52G           86
 242
 243 /* Per-path offsets & fields */
 244 #define SROM8_PATH0             96
 245 #define SROM8_PATH1             112
 246 #define SROM8_PATH2             128
 247 #define SROM8_PATH3             144
 248
 249 #define SROM8_2G_ITT_MAXP       0
 250 #define SROM8_2G_PA             1
 251 #define SROM8_5G_ITT_MAXP       4
 252 #define SROM8_5GLH_MAXP         5
 253 #define SROM8_5G_PA             6
 254 #define SROM8_5GL_PA            9
 255 #define SROM8_5GH_PA            12
 256
 257 /* All the miriad power offsets */
 258 #define SROM8_2G_CCKPO          160
 259
 260 #define SROM8_2G_OFDMPO         161
 261 #define SROM8_5G_OFDMPO         163
 262 #define SROM8_5GL_OFDMPO        165
 263 #define SROM8_5GH_OFDMPO        167
 264
 265 #define SROM8_2G_MCSPO          169
 266 #define SROM8_5G_MCSPO          177
 267 #define SROM8_5GL_MCSPO         185
 268 #define SROM8_5GH_MCSPO         193
 269
 270 #define SROM8_CDDPO             201
 271 #define SROM8_STBCPO            202
 272 #define SROM8_BW40PO            203
 273 #define SROM8_BWDUPPO           204
 274
 275 /* SISO PA parameters are in the path0 spaces */
 276 #define SROM8_SISO              96
 277
 278 /* Legacy names for SISO PA paramters */
 279 #define SROM8_W0_ITTMAXP        (SROM8_SISO + SROM8_2G_ITT_MAXP)
 280 #define SROM8_W0_PAB0           (SROM8_SISO + SROM8_2G_PA)
 281 #define SROM8_W0_PAB1           (SROM8_SISO + SROM8_2G_PA + 1)
 282 #define SROM8_W0_PAB2           (SROM8_SISO + SROM8_2G_PA + 2)
 283 #define SROM8_W1_ITTMAXP        (SROM8_SISO + SROM8_5G_ITT_MAXP)
 284 #define SROM8_W1_MAXP_LCHC      (SROM8_SISO + SROM8_5GLH_MAXP)
 285 #define SROM8_W1_PAB0           (SROM8_SISO + SROM8_5G_PA)
 286 #define SROM8_W1_PAB1           (SROM8_SISO + SROM8_5G_PA + 1)
 287 #define SROM8_W1_PAB2           (SROM8_SISO + SROM8_5G_PA + 2)
 288 #define SROM8_W1_PAB0_LC        (SROM8_SISO + SROM8_5GL_PA)
 289 #define SROM8_W1_PAB1_LC        (SROM8_SISO + SROM8_5GL_PA + 1)
 290 #define SROM8_W1_PAB2_LC        (SROM8_SISO + SROM8_5GL_PA + 2)
 291 #define SROM8_W1_PAB0_HC        (SROM8_SISO + SROM8_5GH_PA)
 292 #define SROM8_W1_PAB1_HC        (SROM8_SISO + SROM8_5GH_PA + 1)
 293 #define SROM8_W1_PAB2_HC        (SROM8_SISO + SROM8_5GH_PA + 2)
 294
 295 #define SROM8_CRCREV            219
 296
 297 /* Prototypes */
 298 extern int srom_var_init(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
 299                          char **vars, uint *count);
 300
 301 extern int srom_read(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
 302                      uint byteoff, uint nbytes, uint16 *buf);
 303 extern int srom_write(sb_t *sbh, uint bus, void *curmap, osl_t *osh,
 304                       uint byteoff, uint nbytes, uint16 *buf);
 305
 306 extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
 307                          char **vars, uint *count);
 308
 309 #endif  /* _bcmsrom_h_ */