2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
69 #define AR7240_REG_TAG_PRIORITY 0x70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_S 0
100 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
101 #define AR7240_PORT_STATUS_SPEED_10 0
102 #define AR7240_PORT_STATUS_SPEED_100 1
103 #define AR7240_PORT_STATUS_SPEED_1000 2
104 #define AR7240_PORT_STATUS_TXMAC BIT(2)
105 #define AR7240_PORT_STATUS_RXMAC BIT(3)
106 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
107 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
108 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
109 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
110 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
111 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
113 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
114 #define AR7240_PORT_CTRL_STATE_M BITM(3)
115 #define AR7240_PORT_CTRL_STATE_DISABLED 0
116 #define AR7240_PORT_CTRL_STATE_BLOCK 1
117 #define AR7240_PORT_CTRL_STATE_LISTEN 2
118 #define AR7240_PORT_CTRL_STATE_LEARN 3
119 #define AR7240_PORT_CTRL_STATE_FORWARD 4
120 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
121 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
122 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
123 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
124 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
125 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
126 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
127 #define AR7240_PORT_CTRL_HEADER BIT(11)
128 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
129 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
130 #define AR7240_PORT_CTRL_LEARN BIT(14)
131 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
132 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
133 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
135 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
137 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
138 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
139 #define AR7240_PORT_VLAN_MODE_S 30
140 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
141 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
142 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
143 #define AR7240_PORT_VLAN_MODE_SECURE 3
146 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
148 #define AR7240_STATS_RXBROAD 0x00
149 #define AR7240_STATS_RXPAUSE 0x04
150 #define AR7240_STATS_RXMULTI 0x08
151 #define AR7240_STATS_RXFCSERR 0x0c
152 #define AR7240_STATS_RXALIGNERR 0x10
153 #define AR7240_STATS_RXRUNT 0x14
154 #define AR7240_STATS_RXFRAGMENT 0x18
155 #define AR7240_STATS_RX64BYTE 0x1c
156 #define AR7240_STATS_RX128BYTE 0x20
157 #define AR7240_STATS_RX256BYTE 0x24
158 #define AR7240_STATS_RX512BYTE 0x28
159 #define AR7240_STATS_RX1024BYTE 0x2c
160 #define AR7240_STATS_RX1518BYTE 0x30
161 #define AR7240_STATS_RXMAXBYTE 0x34
162 #define AR7240_STATS_RXTOOLONG 0x38
163 #define AR7240_STATS_RXGOODBYTE 0x3c
164 #define AR7240_STATS_RXBADBYTE 0x44
165 #define AR7240_STATS_RXOVERFLOW 0x4c
166 #define AR7240_STATS_FILTERED 0x50
167 #define AR7240_STATS_TXBROAD 0x54
168 #define AR7240_STATS_TXPAUSE 0x58
169 #define AR7240_STATS_TXMULTI 0x5c
170 #define AR7240_STATS_TXUNDERRUN 0x60
171 #define AR7240_STATS_TX64BYTE 0x64
172 #define AR7240_STATS_TX128BYTE 0x68
173 #define AR7240_STATS_TX256BYTE 0x6c
174 #define AR7240_STATS_TX512BYTE 0x70
175 #define AR7240_STATS_TX1024BYTE 0x74
176 #define AR7240_STATS_TX1518BYTE 0x78
177 #define AR7240_STATS_TXMAXBYTE 0x7c
178 #define AR7240_STATS_TXOVERSIZE 0x80
179 #define AR7240_STATS_TXBYTE 0x84
180 #define AR7240_STATS_TXCOLLISION 0x8c
181 #define AR7240_STATS_TXABORTCOL 0x90
182 #define AR7240_STATS_TXMULTICOL 0x94
183 #define AR7240_STATS_TXSINGLECOL 0x98
184 #define AR7240_STATS_TXEXCDEFER 0x9c
185 #define AR7240_STATS_TXDEFER 0xa0
186 #define AR7240_STATS_TXLATECOL 0xa4
188 #define AR7240_PORT_CPU 0
189 #define AR7240_NUM_PORTS 6
190 #define AR7240_NUM_PHYS 5
192 #define AR7240_PHY_ID1 0x004d
193 #define AR7240_PHY_ID2 0xd041
195 #define AR7240_MAX_VLANS 16
197 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
200 struct mii_bus
*mii_bus
;
201 struct switch_dev swdev
;
204 u16 vlan_id
[AR7240_MAX_VLANS
];
205 u8 vlan_table
[AR7240_MAX_VLANS
];
207 u16 pvid
[AR7240_NUM_PORTS
];
211 struct ar7240sw_hw_stat
{
212 char string
[ETH_GSTRING_LEN
];
217 static DEFINE_MUTEX(reg_mutex
);
219 static inline u32
ar7240sw_port_mask(struct ar7240sw
*as
, int port
)
224 static inline u32
ar7240sw_port_mask_all(struct ar7240sw
*as
)
226 return BIT(as
->swdev
.ports
) - 1;
229 static inline u32
ar7240sw_port_mask_but(struct ar7240sw
*as
, int port
)
231 return ar7240sw_port_mask_all(as
) & ~BIT(port
);
234 static inline u16
mk_phy_addr(u32 reg
)
236 return 0x17 & ((reg
>> 4) | 0x10);
239 static inline u16
mk_phy_reg(u32 reg
)
241 return (reg
<< 1) & 0x1e;
244 static inline u16
mk_high_addr(u32 reg
)
246 return (reg
>> 7) & 0x1ff;
249 static u32
__ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg
)
256 reg
= (reg
& 0xfffffffc) >> 2;
257 phy_addr
= mk_phy_addr(reg
);
258 phy_reg
= mk_phy_reg(reg
);
260 local_irq_save(flags
);
261 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
262 lo
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
);
263 hi
= (u32
) ag71xx_mdio_mii_read(mii
->priv
, phy_addr
, phy_reg
+ 1);
264 local_irq_restore(flags
);
266 return (hi
<< 16) | lo
;
269 static void __ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg
, u32 val
)
275 reg
= (reg
& 0xfffffffc) >> 2;
276 phy_addr
= mk_phy_addr(reg
);
277 phy_reg
= mk_phy_reg(reg
);
279 local_irq_save(flags
);
280 ag71xx_mdio_mii_write(mii
->priv
, 0x1f, 0x10, mk_high_addr(reg
));
281 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
+ 1, (val
>> 16));
282 ag71xx_mdio_mii_write(mii
->priv
, phy_addr
, phy_reg
, (val
& 0xffff));
283 local_irq_restore(flags
);
286 static u32
ar7240sw_reg_read(struct mii_bus
*mii
, u32 reg_addr
)
290 mutex_lock(®_mutex
);
291 ret
= __ar7240sw_reg_read(mii
, reg_addr
);
292 mutex_unlock(®_mutex
);
297 static void ar7240sw_reg_write(struct mii_bus
*mii
, u32 reg_addr
, u32 reg_val
)
299 mutex_lock(®_mutex
);
300 __ar7240sw_reg_write(mii
, reg_addr
, reg_val
);
301 mutex_unlock(®_mutex
);
304 static u32
ar7240sw_reg_rmw(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
)
308 mutex_lock(®_mutex
);
309 t
= __ar7240sw_reg_read(mii
, reg
);
312 __ar7240sw_reg_write(mii
, reg
, t
);
313 mutex_unlock(®_mutex
);
318 static void ar7240sw_reg_set(struct mii_bus
*mii
, u32 reg
, u32 val
)
322 mutex_lock(®_mutex
);
323 t
= __ar7240sw_reg_read(mii
, reg
);
325 __ar7240sw_reg_write(mii
, reg
, t
);
326 mutex_unlock(®_mutex
);
329 static int __ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
334 for (i
= 0; i
< timeout
; i
++) {
337 t
= __ar7240sw_reg_read(mii
, reg
);
338 if ((t
& mask
) == val
)
347 static int ar7240sw_reg_wait(struct mii_bus
*mii
, u32 reg
, u32 mask
, u32 val
,
352 mutex_lock(®_mutex
);
353 ret
= __ar7240sw_reg_wait(mii
, reg
, mask
, val
, timeout
);
354 mutex_unlock(®_mutex
);
358 u16
ar7240sw_phy_read(struct mii_bus
*mii
, unsigned phy_addr
,
364 if (phy_addr
>= AR7240_NUM_PHYS
)
367 mutex_lock(®_mutex
);
368 t
= (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
369 (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
370 AR7240_MDIO_CTRL_MASTER_EN
|
371 AR7240_MDIO_CTRL_BUSY
|
372 AR7240_MDIO_CTRL_CMD_READ
;
374 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
375 err
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
376 AR7240_MDIO_CTRL_BUSY
, 0, 5);
378 val
= __ar7240sw_reg_read(mii
, AR7240_REG_MDIO_CTRL
);
379 mutex_unlock(®_mutex
);
381 return val
& AR7240_MDIO_CTRL_DATA_M
;
384 int ar7240sw_phy_write(struct mii_bus
*mii
, unsigned phy_addr
,
385 unsigned reg_addr
, u16 reg_val
)
390 if (phy_addr
>= AR7240_NUM_PHYS
)
393 mutex_lock(®_mutex
);
394 t
= (phy_addr
<< AR7240_MDIO_CTRL_PHY_ADDR_S
) |
395 (reg_addr
<< AR7240_MDIO_CTRL_REG_ADDR_S
) |
396 AR7240_MDIO_CTRL_MASTER_EN
|
397 AR7240_MDIO_CTRL_BUSY
|
398 AR7240_MDIO_CTRL_CMD_WRITE
|
401 __ar7240sw_reg_write(mii
, AR7240_REG_MDIO_CTRL
, t
);
402 ret
= __ar7240sw_reg_wait(mii
, AR7240_REG_MDIO_CTRL
,
403 AR7240_MDIO_CTRL_BUSY
, 0, 5);
404 mutex_unlock(®_mutex
);
409 static void ar7240sw_disable_port(struct ar7240sw
*as
, unsigned port
)
411 ar7240sw_reg_write(as
->mii_bus
, AR7240_REG_PORT_CTRL(port
),
412 AR7240_PORT_CTRL_STATE_DISABLED
);
415 static void ar7240sw_setup(struct ar7240sw
*as
)
417 struct mii_bus
*mii
= as
->mii_bus
;
419 /* Enable CPU port, and disable mirror port */
420 ar7240sw_reg_write(mii
, AR7240_REG_CPU_PORT
,
422 (15 << AR7240_MIRROR_PORT_S
));
424 /* Setup TAG priority mapping */
425 ar7240sw_reg_write(mii
, AR7240_REG_TAG_PRIORITY
, 0xfa50);
427 /* Enable ARP frame acknowledge, aging, MAC replacing */
428 ar7240sw_reg_write(mii
, AR7240_REG_AT_CTRL
,
429 0x2b /* 5 min age time */ |
430 AR7240_AT_CTRL_AGE_EN
|
431 AR7240_AT_CTRL_ARP_EN
|
432 AR7240_AT_CTRL_LEARN_CHANGE
);
434 /* Enable Broadcast frames transmitted to the CPU */
435 ar7240sw_reg_set(mii
, AR7240_REG_FLOOD_MASK
,
436 AR7240_FLOOD_MASK_BROAD_TO_CPU
);
439 ar7240sw_reg_rmw(mii
, AR7240_REG_GLOBAL_CTRL
, AR7240_GLOBAL_CTRL_MTU_M
,
442 /* setup Service TAG */
443 ar7240sw_reg_rmw(mii
, AR7240_REG_SERVICE_TAG
, AR7240_SERVICE_TAG_M
, 0);
446 static int ar7240sw_reset(struct ar7240sw
*as
)
448 struct mii_bus
*mii
= as
->mii_bus
;
452 /* Set all ports to disabled state. */
453 for (i
= 0; i
< AR7240_NUM_PORTS
; i
++)
454 ar7240sw_disable_port(as
, i
);
456 /* Wait for transmit queues to drain. */
459 /* Reset the switch. */
460 ar7240sw_reg_write(mii
, AR7240_REG_MASK_CTRL
,
461 AR7240_MASK_CTRL_SOFT_RESET
);
463 ret
= ar7240sw_reg_wait(mii
, AR7240_REG_MASK_CTRL
,
464 AR7240_MASK_CTRL_SOFT_RESET
, 0, 1000);
470 static void ar7240sw_setup_port(struct ar7240sw
*as
, unsigned port
, u8 portmask
)
472 struct mii_bus
*mii
= as
->mii_bus
;
476 ctrl
= AR7240_PORT_CTRL_STATE_FORWARD
| AR7240_PORT_CTRL_LEARN
|
477 AR7240_PORT_CTRL_SINGLE_VLAN
;
479 if (port
== AR7240_PORT_CPU
) {
480 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
481 AR7240_PORT_STATUS_SPEED_1000
|
482 AR7240_PORT_STATUS_TXFLOW
|
483 AR7240_PORT_STATUS_RXFLOW
|
484 AR7240_PORT_STATUS_TXMAC
|
485 AR7240_PORT_STATUS_RXMAC
|
486 AR7240_PORT_STATUS_DUPLEX
);
488 ar7240sw_reg_write(mii
, AR7240_REG_PORT_STATUS(port
),
489 AR7240_PORT_STATUS_LINK_AUTO
);
492 /* Set the default VID for this port */
494 vlan
= as
->vlan_id
[as
->pvid
[port
]];
495 vlan
|= AR7240_PORT_VLAN_MODE_SECURE
<<
496 AR7240_PORT_VLAN_MODE_S
;
499 vlan
|= AR7240_PORT_VLAN_MODE_PORT_ONLY
<<
500 AR7240_PORT_VLAN_MODE_S
;
503 if (as
->vlan
&& (as
->vlan_tagged
& BIT(port
))) {
504 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_ADD
<<
505 AR7240_PORT_CTRL_VLAN_MODE_S
;
507 ctrl
|= AR7240_PORT_CTRL_VLAN_MODE_STRIP
<<
508 AR7240_PORT_CTRL_VLAN_MODE_S
;
512 if (port
== AR7240_PORT_CPU
)
513 portmask
= ar7240sw_port_mask_but(as
, AR7240_PORT_CPU
);
515 portmask
= ar7240sw_port_mask(as
, AR7240_PORT_CPU
);
518 /* allow the port to talk to all other ports, but exclude its
519 * own ID to prevent frames from being reflected back to the
520 * port that they came from */
521 portmask
&= ar7240sw_port_mask_but(as
, port
);
523 /* set default VID and and destination ports for this VLAN */
524 vlan
|= (portmask
<< AR7240_PORT_VLAN_DEST_PORTS_S
);
526 ar7240sw_reg_write(mii
, AR7240_REG_PORT_CTRL(port
), ctrl
);
527 ar7240sw_reg_write(mii
, AR7240_REG_PORT_VLAN(port
), vlan
);
530 static int ar7240_set_addr(struct ar7240sw
*as
, u8
*addr
)
532 struct mii_bus
*mii
= as
->mii_bus
;
535 t
= (addr
[4] << 8) | addr
[5];
536 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR0
, t
);
538 t
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
539 ar7240sw_reg_write(mii
, AR7240_REG_MAC_ADDR1
, t
);
545 ar7240_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
546 struct switch_val
*val
)
548 struct ar7240sw
*as
= sw_to_ar7240(dev
);
549 as
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
554 ar7240_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
555 struct switch_val
*val
)
557 struct ar7240sw
*as
= sw_to_ar7240(dev
);
558 val
->value
.i
= as
->vlan_id
[val
->port_vlan
];
563 ar7240_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
565 struct ar7240sw
*as
= sw_to_ar7240(dev
);
567 /* make sure no invalid PVIDs get set */
569 if (vlan
>= dev
->vlans
)
572 as
->pvid
[port
] = vlan
;
577 ar7240_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
579 struct ar7240sw
*as
= sw_to_ar7240(dev
);
580 *vlan
= as
->pvid
[port
];
585 ar7240_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
587 struct ar7240sw
*as
= sw_to_ar7240(dev
);
588 u8 ports
= as
->vlan_table
[val
->port_vlan
];
592 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
593 struct switch_port
*p
;
595 if (!(ports
& (1 << i
)))
598 p
= &val
->value
.ports
[val
->len
++];
600 if (as
->vlan_tagged
& (1 << i
))
601 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
609 ar7240_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
611 struct ar7240sw
*as
= sw_to_ar7240(dev
);
612 u8
*vt
= &as
->vlan_table
[val
->port_vlan
];
616 for (i
= 0; i
< val
->len
; i
++) {
617 struct switch_port
*p
= &val
->value
.ports
[i
];
619 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
))
620 as
->vlan_tagged
|= (1 << p
->id
);
622 as
->vlan_tagged
&= ~(1 << p
->id
);
623 as
->pvid
[p
->id
] = val
->port_vlan
;
625 /* make sure that an untagged port does not
626 * appear in other vlans */
627 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
628 if (j
== val
->port_vlan
)
630 as
->vlan_table
[j
] &= ~(1 << p
->id
);
640 ar7240_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
641 struct switch_val
*val
)
643 struct ar7240sw
*as
= sw_to_ar7240(dev
);
644 as
->vlan
= !!val
->value
.i
;
649 ar7240_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
650 struct switch_val
*val
)
652 struct ar7240sw
*as
= sw_to_ar7240(dev
);
653 val
->value
.i
= as
->vlan
;
658 ar7240_speed_str(u32 status
)
662 speed
= (status
>> AR7240_PORT_STATUS_SPEED_S
) &
663 AR7240_PORT_STATUS_SPEED_M
;
665 case AR7240_PORT_STATUS_SPEED_10
:
667 case AR7240_PORT_STATUS_SPEED_100
:
669 case AR7240_PORT_STATUS_SPEED_1000
:
677 ar7240_port_get_link(struct switch_dev
*dev
, const struct switch_attr
*attr
,
678 struct switch_val
*val
)
680 struct ar7240sw
*as
= sw_to_ar7240(dev
);
681 struct mii_bus
*mii
= as
->mii_bus
;
686 port
= val
->port_vlan
;
688 memset(as
->buf
, '\0', sizeof(as
->buf
));
689 status
= ar7240sw_reg_read(mii
, AR7240_REG_PORT_STATUS(port
));
691 if (status
& AR7240_PORT_STATUS_LINK_UP
) {
692 len
= snprintf(as
->buf
, sizeof(as
->buf
),
693 "port:%d link:up speed:%s %s-duplex %s%s%s",
695 ar7240_speed_str(status
),
696 (status
& AR7240_PORT_STATUS_DUPLEX
) ?
698 (status
& AR7240_PORT_STATUS_TXFLOW
) ?
700 (status
& AR7240_PORT_STATUS_RXFLOW
) ?
702 (status
& AR7240_PORT_STATUS_LINK_AUTO
) ?
705 len
= snprintf(as
->buf
, sizeof(as
->buf
),
706 "port:%d link:down", port
);
709 val
->value
.s
= as
->buf
;
716 ar7240_vtu_op(struct ar7240sw
*as
, u32 op
, u32 val
)
718 struct mii_bus
*mii
= as
->mii_bus
;
720 if (ar7240sw_reg_wait(mii
, AR7240_REG_VTU
, AR7240_VTU_ACTIVE
, 0, 5))
723 if ((op
& AR7240_VTU_OP
) == AR7240_VTU_OP_LOAD
) {
724 val
&= AR7240_VTUDATA_MEMBER
;
725 val
|= AR7240_VTUDATA_VALID
;
726 ar7240sw_reg_write(mii
, AR7240_REG_VTU_DATA
, val
);
728 op
|= AR7240_VTU_ACTIVE
;
729 ar7240sw_reg_write(mii
, AR7240_REG_VTU
, op
);
733 ar7240_hw_apply(struct switch_dev
*dev
)
735 struct ar7240sw
*as
= sw_to_ar7240(dev
);
736 u8 portmask
[AR7240_NUM_PORTS
];
739 /* flush all vlan translation unit entries */
740 ar7240_vtu_op(as
, AR7240_VTU_OP_FLUSH
, 0);
742 memset(portmask
, 0, sizeof(portmask
));
744 /* calculate the port destination masks and load vlans
745 * into the vlan translation unit */
746 for (j
= 0; j
< AR7240_MAX_VLANS
; j
++) {
747 u8 vp
= as
->vlan_table
[j
];
752 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
755 portmask
[i
] |= vp
& ~mask
;
760 (as
->vlan_id
[j
] << AR7240_VTU_VID_S
),
765 * isolate all ports, but connect them to the cpu port */
766 for (i
= 0; i
< as
->swdev
.ports
; i
++) {
767 if (i
== AR7240_PORT_CPU
)
770 portmask
[i
] = 1 << AR7240_PORT_CPU
;
771 portmask
[AR7240_PORT_CPU
] |= (1 << i
);
775 /* update the port destination mask registers and tag settings */
776 for (i
= 0; i
< as
->swdev
.ports
; i
++)
777 ar7240sw_setup_port(as
, i
, portmask
[i
]);
783 ar7240_reset_switch(struct switch_dev
*dev
)
785 struct ar7240sw
*as
= sw_to_ar7240(dev
);
790 static struct switch_attr ar7240_globals
[] = {
792 .type
= SWITCH_TYPE_INT
,
793 .name
= "enable_vlan",
794 .description
= "Enable VLAN mode",
795 .set
= ar7240_set_vlan
,
796 .get
= ar7240_get_vlan
,
801 static struct switch_attr ar7240_port
[] = {
803 .type
= SWITCH_TYPE_STRING
,
805 .description
= "Get port link information",
808 .get
= ar7240_port_get_link
,
812 static struct switch_attr ar7240_vlan
[] = {
814 .type
= SWITCH_TYPE_INT
,
816 .description
= "VLAN ID",
817 .set
= ar7240_set_vid
,
818 .get
= ar7240_get_vid
,
823 static const struct switch_dev_ops ar7240_ops
= {
825 .attr
= ar7240_globals
,
826 .n_attr
= ARRAY_SIZE(ar7240_globals
),
830 .n_attr
= ARRAY_SIZE(ar7240_port
),
834 .n_attr
= ARRAY_SIZE(ar7240_vlan
),
836 .get_port_pvid
= ar7240_get_pvid
,
837 .set_port_pvid
= ar7240_set_pvid
,
838 .get_vlan_ports
= ar7240_get_ports
,
839 .set_vlan_ports
= ar7240_set_ports
,
840 .apply_config
= ar7240_hw_apply
,
841 .reset_switch
= ar7240_reset_switch
,
844 static struct ar7240sw
*ar7240_probe(struct ag71xx
*ag
)
846 struct mii_bus
*mii
= ag
->mii_bus
;
848 struct switch_dev
*swdev
;
855 phy_id1
= ar7240sw_phy_read(mii
, 0, MII_PHYSID1
);
856 phy_id2
= ar7240sw_phy_read(mii
, 0, MII_PHYSID2
);
857 if (phy_id1
!= AR7240_PHY_ID1
|| phy_id2
!= AR7240_PHY_ID2
) {
858 pr_err("%s: unknown phy id '%04x:%04x'\n",
859 ag
->dev
->name
, phy_id1
, phy_id2
);
863 as
= kzalloc(sizeof(*as
), GFP_KERNEL
);
869 ctrl
= ar7240sw_reg_read(mii
, AR7240_REG_MASK_CTRL
);
870 ver
= (ctrl
>> AR7240_MASK_CTRL_VERSION_S
) & AR7240_MASK_CTRL_VERSION_M
;
872 pr_err("%s: unsupported chip, ctrl=%08x\n",
873 ag
->dev
->name
, ctrl
);
878 swdev
->name
= "AR7240 built-in switch";
879 swdev
->ports
= AR7240_NUM_PORTS
- 1;
880 swdev
->cpu_port
= AR7240_PORT_CPU
;
881 swdev
->vlans
= AR7240_MAX_VLANS
;
882 swdev
->ops
= &ar7240_ops
;
884 if (register_switch(&as
->swdev
, ag
->dev
) < 0) {
889 pr_info("%s: Found an AR7240 built-in switch\n", ag
->dev
->name
);
891 /* initialize defaults */
892 for (i
= 0; i
< AR7240_MAX_VLANS
; i
++)
895 as
->vlan_table
[0] = ar7240sw_port_mask_all(as
);
900 static void link_function(struct work_struct
*work
) {
901 struct ag71xx
*ag
= container_of(work
, struct ag71xx
, link_work
.work
);
906 for (i
= 0; i
< 4; i
++) {
907 int link
= ar7240sw_phy_read(ag
->mii_bus
, i
, MII_BMSR
);
908 if(link
& BMSR_LSTATUS
) {
914 spin_lock_irqsave(&ag
->lock
, flags
);
915 if(status
!= ag
->link
) {
917 ag71xx_link_adjust(ag
);
919 spin_unlock_irqrestore(&ag
->lock
, flags
);
921 schedule_delayed_work(&ag
->link_work
, HZ
/ 2);
924 void ag71xx_ar7240_start(struct ag71xx
*ag
)
926 struct ar7240sw
*as
= ag
->phy_priv
;
930 ag
->speed
= SPEED_1000
;
933 ar7240_set_addr(as
, ag
->dev
->dev_addr
);
934 ar7240_hw_apply(&as
->swdev
);
936 schedule_delayed_work(&ag
->link_work
, HZ
/ 10);
939 void ag71xx_ar7240_stop(struct ag71xx
*ag
)
941 cancel_delayed_work_sync(&ag
->link_work
);
944 int __devinit
ag71xx_ar7240_init(struct ag71xx
*ag
)
948 as
= ar7240_probe(ag
);
955 INIT_DELAYED_WORK(&ag
->link_work
, link_function
);
960 void ag71xx_ar7240_cleanup(struct ag71xx
*ag
)
962 struct ar7240sw
*as
= ag
->phy_priv
;
967 unregister_switch(&as
->swdev
);