target/linux/ifxmips/files/arch/mips/pci/pci-ifxmips.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/kernel.h>
   4 #include <linux/init.h>
   5 #include <linux/delay.h>
   6 #include <linux/mm.h>
   7 #include <asm/ifxmips/ifxmips.h>
   8 #include <asm/ifxmips/ifxmips_irq.h>
   9 #include <asm/ifxmips/ifxmips_cgu.h>
  10 #include <asm/addrspace.h>
  11 #include <linux/vmalloc.h>
  12
  13 #define IFXMIPS_PCI_MEM_BASE    0x18000000
  14 #define IFXMIPS_PCI_MEM_SIZE    0x02000000
  15 #define IFXMIPS_PCI_IO_BASE     0x1AE00000
  16 #define IFXMIPS_PCI_IO_SIZE     0x00200000
  17
  18 extern int ifxmips_pci_read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  19 extern int ifxmips_pci_write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  20
  21 struct pci_ops ifxmips_pci_ops =
  22 {
  23         .read = ifxmips_pci_read_config_dword,
  24         .write = ifxmips_pci_write_config_dword
  25 };
  26
  27 static struct resource pci_io_resource =
  28 {
  29         .name = "io pci IO space",
  30         .start = IFXMIPS_PCI_IO_BASE,
  31         .end = IFXMIPS_PCI_IO_BASE + IFXMIPS_PCI_IO_SIZE - 1,
  32         .flags = IORESOURCE_IO
  33 };
  34
  35 static struct resource pci_mem_resource =
  36 {
  37         .name = "ext pci memory space",
  38         .start = IFXMIPS_PCI_MEM_BASE,
  39         .end = IFXMIPS_PCI_MEM_BASE + IFXMIPS_PCI_MEM_SIZE - 1,
  40         .flags = IORESOURCE_MEM
  41 };
  42
  43 static struct pci_controller ifxmips_pci_controller =
  44 {
  45         .pci_ops = &ifxmips_pci_ops,
  46         .mem_resource = &pci_mem_resource,
  47         .mem_offset     = 0x00000000UL,
  48         .io_resource = &pci_io_resource,
  49         .io_offset      = 0x00000000UL,
  50 };
  51
  52 u32 ifxmips_pci_mapped_cfg;
  53 int ifxmips_pci_external_clock = 0;
  54
  55 static int __init
  56 ifxmips_pci_set_external_clk(char *str)
  57 {
  58         printk("cgu: setting up external pci clock\n");
  59         ifxmips_pci_external_clock = 1;
  60         return 1;
  61 }
  62 __setup("pci_external_clk", ifxmips_pci_set_external_clk);
  63
  64 int
  65 pcibios_plat_dev_init(struct pci_dev *dev)
  66 {
  67         u8 pin;
  68
  69         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
  70         switch(pin)
  71         {
  72                 case 0:
  73                         break;
  74                 case 1:
  75                         //falling edge level triggered:0x4, low level:0xc, rising edge:0x2
  76                         ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_CON) | 0xc, IFXMIPS_EBU_PCC_CON);
  77                         ifxmips_w32(ifxmips_r32(IFXMIPS_EBU_PCC_IEN) | 0x10, IFXMIPS_EBU_PCC_IEN);
  78                         break;
  79                 case 2:
  80                 case 3:
  81                 case 4:
  82                         printk ("WARNING: interrupt pin %d not supported yet!\n", pin);
  83                 default:
  84                         printk ("WARNING: invalid interrupt pin %d\n", pin);
  85                         return 1;
  86         }
  87         return 0;
  88 }
  89
  90 static void __init
  91 ifxmips_pci_startup(void)
  92 {
  93         u32 temp_buffer;
  94
  95         cgu_setup_pci_clk(ifxmips_pci_external_clock);
  96
  97         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
  98         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OD) | (1 << 5), IFXMIPS_GPIO_P1_OD);
  99         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | (1 << 5), IFXMIPS_GPIO_P1_DIR);
 100         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL1);
 101         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) & ~(1 << 5), IFXMIPS_GPIO_P1_ALTSEL0);
 102         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) & ~0x2000, IFXMIPS_GPIO_P1_DIR);
 103         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_DIR) | 0x4000, IFXMIPS_GPIO_P1_DIR);
 104         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL1) & ~0x6000, IFXMIPS_GPIO_P1_ALTSEL1);
 105         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_ALTSEL0) | 0x6000, IFXMIPS_GPIO_P1_ALTSEL0);
 106         /* enable auto-switching between PCI and EBU */
 107         ifxmips_w32(0xa, PCI_CR_CLK_CTRL);
 108         /* busy, i.e. configuration is not done, PCI access has to be retried */
 109         ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
 110         wmb ();
 111         /* BUS Master/IO/MEM access */
 112         ifxmips_w32(ifxmips_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
 113
 114         /* enable external 2 PCI masters */
 115         temp_buffer = ifxmips_r32(PCI_CR_PC_ARB);
 116         temp_buffer &= (~(0xf << 16));
 117         /* enable internal arbiter */
 118         temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
 119         /* enable internal PCI master reqest */
 120         temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
 121
 122         /* enable EBU reqest */
 123         temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
 124
 125         /* enable all external masters request */
 126         temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
 127         ifxmips_w32(temp_buffer, PCI_CR_PC_ARB);
 128         wmb ();
 129
 130         ifxmips_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
 131         ifxmips_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
 132         ifxmips_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
 133         ifxmips_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
 134         ifxmips_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
 135         ifxmips_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
 136         ifxmips_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
 137         ifxmips_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
 138         ifxmips_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
 139         ifxmips_w32(0x0e000008, PCI_CR_BAR11MASK);
 140         ifxmips_w32(0, PCI_CR_PCI_ADDR_MAP11);
 141         ifxmips_w32(0, PCI_CS_BASE_ADDR1);
 142 #ifdef CONFIG_SWAP_IO_SPACE
 143         /* both TX and RX endian swap are enabled */
 144         ifxmips_w32(ifxmips_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
 145         wmb ();
 146 #endif
 147         /*TODO: disable BAR2 & BAR3 - why was this in the origianl infineon code */
 148         ifxmips_w32(ifxmips_r32(PCI_CR_BAR12MASK) | 0x80000000, PCI_CR_BAR12MASK);
 149         ifxmips_w32(ifxmips_r32(PCI_CR_BAR13MASK) | 0x80000000, PCI_CR_BAR13MASK);
 150         /*use 8 dw burst length */
 151         ifxmips_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
 152         ifxmips_w32(ifxmips_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
 153         wmb();
 154         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) & ~(1 << 5), IFXMIPS_GPIO_P1_OUT);
 155         wmb();
 156         mdelay(1);
 157         ifxmips_w32(ifxmips_r32(IFXMIPS_GPIO_P1_OUT) | (1 << 5), IFXMIPS_GPIO_P1_OUT);
 158 }
 159
 160 int __init
 161 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin){
 162         switch(slot)
 163         {
 164                 case 13:
 165                         /* IDSEL = AD29 --> USB Host Controller */
 166                         return (INT_NUM_IM1_IRL0 + 17);
 167                 case 14:
 168                         /* IDSEL = AD30 --> mini PCI connector */
 169                         return (INT_NUM_IM0_IRL0 + 22);
 170                 default:
 171                         printk("Warning: no IRQ found for PCI device in slot %d, pin %d\n", slot, pin);
 172                         return 0;
 173         }
 174 }
 175
 176 int __init
 177 pcibios_init(void)
 178 {
 179         extern int pci_probe_only;
 180
 181         pci_probe_only = 0;
 182         printk("PCI: Probing PCI hardware on host bus 0.\n");
 183         ifxmips_pci_startup ();
 184         //      IFXMIPS_PCI_REG32(PCI_CR_CLK_CTRL_REG) &= (~8);
 185         ifxmips_pci_mapped_cfg = (u32)ioremap_nocache(0x17000000, 0x800 * 16);
 186         printk("IFXMips PCI mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_mapped_cfg);
 187         ifxmips_pci_controller.io_map_base = (unsigned long)ioremap(IFXMIPS_PCI_IO_BASE, IFXMIPS_PCI_IO_SIZE - 1);
 188         printk("IFXMips PCI I/O mapped to 0x%08lX\n", (unsigned long)ifxmips_pci_controller.io_map_base);
 189         register_pci_controller(&ifxmips_pci_controller);
 190         return 0;
 191 }
 192
 193 arch_initcall(pcibios_init);