target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_mpmc.h

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 MPMC (Multiport Memory Controller) register definitions
   5  *
   6  *  Copyright (C) 2007 OpenWrt.org
   7  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   8  *
   9  *  This program is free software; you can redistribute it and/or
  10  *  modify it under the terms of the GNU General Public License
  11  *  as published by the Free Software Foundation; either version 2
  12  *  of the License, or (at your option) any later version.
  13  *
  14  *  This program is distributed in the hope that it will be useful,
  15  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *  GNU General Public License for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License
  20  *  along with this program; if not, write to the
  21  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  22  *  Boston, MA  02110-1301, USA.
  23  *
  24  */
  25
  26 #ifndef _ADM5120_MPMC_H_
  27 #define _ADM5120_MPMC_H_
  28
  29 #define MPMC_READ_REG(r)        __raw_readl( \
  30         (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
  31 #define MPMC_WRITE_REG(r, v)    __raw_writel((v), \
  32         (void __iomem *)KSEG1ADDR(ADM5120_MPMC_BASE) + MPMC_REG_ ## r)
  33
  34 #define MPMC_REG_CTRL   0x0000
  35 #define MPMC_REG_STATUS 0x0004
  36 #define MPMC_REG_CONF   0x0008
  37 #define MPMC_REG_DC     0x0020
  38 #define MPMC_REG_DR     0x0024
  39 #define MPMC_REG_DRP    0x0030
  40
  41 #define MPMC_REG_DC0    0x0100
  42 #define MPMC_REG_DRC0   0x0104
  43 #define MPMC_REG_DC1    0x0120
  44 #define MPMC_REG_DRC1   0x0124
  45 #define MPMC_REG_DC2    0x0140
  46 #define MPMC_REG_DRC2   0x0144
  47 #define MPMC_REG_DC3    0x0160
  48 #define MPMC_REG_DRC3   0x0164
  49 #define MPMC_REG_SC0    0x0200  /* for F_CS1_N */
  50 #define MPMC_REG_SC1    0x0220  /* for F_CS0_N */
  51 #define MPMC_REG_SC2    0x0240
  52 #define MPMC_REG_WEN2   0x0244
  53 #define MPMC_REG_OEN2   0x0248
  54 #define MPMC_REG_RD2    0x024C
  55 #define MPMC_REG_PG2    0x0250
  56 #define MPMC_REG_WR2    0x0254
  57 #define MPMC_REG_TN2    0x0258
  58 #define MPMC_REG_SC3    0x0260
  59
  60 /* Control register bits */
  61 #define MPMC_CTRL_AM            ( 1 << 1 )      /* Address Mirror */
  62 #define MPMC_CTRL_LPM           ( 1 << 2 )      /* Low Power Mode */
  63 #define MPMC_CTRL_DWB           ( 1 << 3 )      /* Drain Write Buffers */
  64
  65 /* Status register bits */
  66 #define MPMC_STATUS_BUSY        ( 1 << 0 )      /* Busy */
  67 #define MPMC_STATUS_WBS         ( 1 << 1 )      /* Write Buffer Status */
  68 #define MPMC_STATUS_SRA         ( 1 << 2 )      /* Self-Refresh Acknowledge*/
  69
  70 /* Dynamic Control register bits */
  71 #define MPMC_DC_CE              ( 1 << 0 )
  72 #define MPMC_DC_DMC             ( 1 << 1 )
  73 #define MPMC_DC_SRR             ( 1 << 2 )
  74 #define MPMC_DC_SI_SHIFT        7
  75 #define MPMC_DC_SI_MASK         ( 3 << 7 )
  76 #define MPMC_DC_SI_NORMAL       ( 0 << 7 )
  77 #define MPMC_DC_SI_MODE         ( 1 << 7 )
  78 #define MPMC_DC_SI_PALL         ( 2 << 7 )
  79 #define MPMC_DC_SI_NOP          ( 3 << 7 )
  80
  81 #define SRAM_REG_CONF   0x00
  82 #define SRAM_REG_WWE    0x04
  83 #define SRAM_REG_WOE    0x08
  84 #define SRAM_REG_WRD    0x0C
  85 #define SRAM_REG_WPG    0x10
  86 #define SRAM_REG_WWR    0x14
  87 #define SRAM_REG_WTR    0x18
  88
  89 /* Dynamic Configuration register bits */
  90 #define DC_BE           (1 << 19) /* buffer enable */
  91 #define DC_RW_SHIFT     28      /* shift for number of rows */
  92 #define DC_RW_MASK      0x03
  93 #define DC_NB_SHIFT     26      /* shift for number of banks */
  94 #define DC_NB_MASK      0x01
  95 #define DC_CW_SHIFT     22      /* shift for number of columns */
  96 #define DC_CW_MASK      0x07
  97 #define DC_DW_SHIFT     7       /* shift for device width */
  98 #define DC_DW_MASK      0x03
  99
 100 /* Static Configuration register bits */
 101 #define SC_MW_MASK      0x03    /* memory width mask */
 102 #define SC_MW_8         0x00    /* 8 bit memory width */
 103 #define SC_MW_16        0x01    /* 16 bit memory width */
 104 #define SC_MW_32        0x02    /* 32 bit memory width */
 105
 106 #endif /* _ADM5120_MPMC_H_ */