target/linux/xburst/patches-2.6.34/053-adc.patch

   1 From 0ba56db361ac905ff2e2d4e6288206c73e3df523 Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Sat, 24 Apr 2010 12:18:01 +0200
   4 Subject: [PATCH] Add jz4740 adc driver
   5
   6 ---
   7  drivers/misc/Kconfig       |   11 ++
   8  drivers/misc/Makefile      |    1 +
   9  drivers/misc/jz4740-adc.c  |  410 ++++++++++++++++++++++++++++++++++++++++++++
  10  include/linux/jz4740-adc.h |   25 +++
  11  4 files changed, 447 insertions(+), 0 deletions(-)
  12  create mode 100644 drivers/misc/jz4740-adc.c
  13  create mode 100644 include/linux/jz4740-adc.h
  14
  15 diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
  16 index 0d0d625..c62f615 100644
  17 --- a/drivers/misc/Kconfig
  18 +++ b/drivers/misc/Kconfig
  19 @@ -327,6 +327,17 @@ config VMWARE_BALLOON
  20           To compile this driver as a module, choose M here: the
  21           module will be called vmware_balloon.
  22
  23 +config JZ4740_ADC
  24 +       tristate "Ingenic JZ4720/JZ4740 SoC ADC driver"
  25 +       depends on SOC_JZ4740
  26 +    help
  27 +      If you say yes here you get support for the Ingenic JZ4720/JZ4740 SoC ADC
  28 +      core. It is required for the JZ4720/JZ4740 battery and touchscreen driver
  29 +      and is used to synchronize access to the adc core between those two.
  30 +
  31 +      This driver can also be build as a module. If so, the module will be
  32 +      called jz4740-adc.
  33 +
  34  source "drivers/misc/c2port/Kconfig"
  35  source "drivers/misc/eeprom/Kconfig"
  36  source "drivers/misc/cb710/Kconfig"
  37 diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
  38 index 7b6f7ee..506bcf6 100644
  39 --- a/drivers/misc/Makefile
  40 +++ b/drivers/misc/Makefile
  41 @@ -27,6 +27,7 @@ obj-$(CONFIG_DS1682)          += ds1682.o
  42  obj-$(CONFIG_TI_DAC7512)       += ti_dac7512.o
  43  obj-$(CONFIG_C2PORT)           += c2port/
  44  obj-$(CONFIG_IWMC3200TOP)      += iwmc3200top/
  45 +obj-$(CONFIG_JZ4740_ADC)       += jz4740-adc.o
  46  obj-y                          += eeprom/
  47  obj-y                          += cb710/
  48  obj-$(CONFIG_VMWARE_BALLOON)   += vmware_balloon.o
  49 diff --git a/drivers/misc/jz4740-adc.c b/drivers/misc/jz4740-adc.c
  50 new file mode 100644
  51 index 0000000..a8a735a
  52 --- /dev/null
  53 +++ b/drivers/misc/jz4740-adc.c
  54 @@ -0,0 +1,410 @@
  55 +/*
  56 + * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
  57 + *             JZ4720/JZ4740 SoC ADC driver
  58 + *
  59 + * This program is free software; you can redistribute  it and/or modify it
  60 + * under  the terms of  the GNU General  Public License as published by the
  61 + * Free Software Foundation;  either version 2 of the  License, or (at your
  62 + * option) any later version.
  63 + *
  64 + * You should have received a copy of the  GNU General Public License along
  65 + * with this program; if not, write  to the Free Software Foundation, Inc.,
  66 + * 675 Mass Ave, Cambridge, MA 02139, USA.
  67 + *
  68 + * This driver is meant to synchronize access to the adc core for the battery
  69 + * and touchscreen driver. Thus these drivers should use the adc driver as a
  70 + * parent.
  71 + */
  72 +
  73 +#include <linux/err.h>
  74 +#include <linux/kernel.h>
  75 +#include <linux/module.h>
  76 +#include <linux/platform_device.h>
  77 +#include <linux/slab.h>
  78 +#include <linux/spinlock.h>
  79 +#include <linux/interrupt.h>
  80 +
  81 +#include <linux/clk.h>
  82 +
  83 +#include <linux/jz4740-adc.h>
  84 +
  85 +#define JZ_REG_ADC_ENABLE      0x00
  86 +#define JZ_REG_ADC_CFG         0x04
  87 +#define JZ_REG_ADC_CTRL                0x08
  88 +#define JZ_REG_ADC_STATUS      0x0C
  89 +#define JZ_REG_ADC_SAME                0x10
  90 +#define JZ_REG_ADC_WAIT                0x14
  91 +#define JZ_REG_ADC_TOUCH       0x18
  92 +#define JZ_REG_ADC_BATTERY     0x1C
  93 +#define JZ_REG_ADC_ADCIN       0x20
  94 +
  95 +#define JZ_ADC_ENABLE_TOUCH            BIT(2)
  96 +#define JZ_ADC_ENABLE_BATTERY          BIT(1)
  97 +#define JZ_ADC_ENABLE_ADCIN            BIT(0)
  98 +
  99 +#define JZ_ADC_CFG_SPZZ                        BIT(31)
 100 +#define JZ_ADC_CFG_EX_IN               BIT(30)
 101 +#define JZ_ADC_CFG_DNUM_MASK           (0x7 << 16)
 102 +#define JZ_ADC_CFG_DMA_ENABLE          BIT(15)
 103 +#define JZ_ADC_CFG_XYZ_MASK            (0x2 << 13)
 104 +#define JZ_ADC_CFG_SAMPLE_NUM_MASK     (0x7 << 10)
 105 +#define JZ_ADC_CFG_CLKDIV              (0xf << 5)
 106 +#define JZ_ADC_CFG_BAT_MB              BIT(4)
 107 +
 108 +#define JZ_ADC_CFG_DNUM_OFFSET         16
 109 +#define JZ_ADC_CFG_XYZ_OFFSET          13
 110 +#define JZ_ADC_CFG_SAMPLE_NUM_OFFSET   10
 111 +#define JZ_ADC_CFG_CLKDIV_OFFSET       5
 112 +
 113 +#define JZ_ADC_IRQ_PENDOWN             BIT(4)
 114 +#define JZ_ADC_IRQ_PENUP               BIT(3)
 115 +#define JZ_ADC_IRQ_TOUCH               BIT(2)
 116 +#define JZ_ADC_IRQ_BATTERY             BIT(1)
 117 +#define JZ_ADC_IRQ_ADCIN               BIT(0)
 118 +
 119 +#define JZ_ADC_TOUCH_TYPE1             BIT(31)
 120 +#define JZ_ADC_TOUCH_DATA1_MASK                0xfff
 121 +#define JZ_ADC_TOUCH_TYPE0             BIT(15)
 122 +#define JZ_ADC_TOUCH_DATA0_MASK                0xfff
 123 +
 124 +#define JZ_ADC_BATTERY_MASK            0xfff
 125 +
 126 +#define JZ_ADC_ADCIN_MASK              0xfff
 127 +
 128 +struct jz4740_adc {
 129 +       struct resource *mem;
 130 +       void __iomem *base;
 131 +
 132 +       int irq;
 133 +
 134 +       struct clk *clk;
 135 +       unsigned int clk_ref;
 136 +
 137 +       struct completion bat_completion;
 138 +       struct completion adc_completion;
 139 +
 140 +       spinlock_t lock;
 141 +};
 142 +
 143 +static irqreturn_t jz4740_adc_irq(int irq, void *data)
 144 +{
 145 +       struct jz4740_adc *adc = data;
 146 +       uint8_t status;
 147 +
 148 +       status = readb(adc->base + JZ_REG_ADC_STATUS);
 149 +
 150 +       if (status & JZ_ADC_IRQ_BATTERY)
 151 +               complete(&adc->bat_completion);
 152 +       if (status & JZ_ADC_IRQ_ADCIN)
 153 +               complete(&adc->adc_completion);
 154 +
 155 +       writeb(0xff, adc->base + JZ_REG_ADC_STATUS);
 156 +
 157 +       return IRQ_HANDLED;
 158 +}
 159 +
 160 +static void jz4740_adc_enable_irq(struct jz4740_adc *adc, int irq)
 161 +{
 162 +       unsigned long flags;
 163 +       uint8_t val;
 164 +
 165 +       spin_lock_irqsave(&adc->lock, flags);
 166 +
 167 +       val = readb(adc->base + JZ_REG_ADC_CTRL);
 168 +       val &= ~irq;
 169 +       writeb(val, adc->base + JZ_REG_ADC_CTRL);
 170 +
 171 +       spin_unlock_irqrestore(&adc->lock, flags);
 172 +}
 173 +
 174 +static void jz4740_adc_disable_irq(struct jz4740_adc *adc, int irq)
 175 +{
 176 +       unsigned long flags;
 177 +       uint8_t val;
 178 +
 179 +       spin_lock_irqsave(&adc->lock, flags);
 180 +
 181 +       val = readb(adc->base + JZ_REG_ADC_CTRL);
 182 +       val |= irq;
 183 +       writeb(val, adc->base + JZ_REG_ADC_CTRL);
 184 +
 185 +       spin_unlock_irqrestore(&adc->lock, flags);
 186 +}
 187 +
 188 +static void jz4740_adc_enable_adc(struct jz4740_adc *adc, int engine)
 189 +{
 190 +       unsigned long flags;
 191 +       uint8_t val;
 192 +
 193 +       spin_lock_irqsave(&adc->lock, flags);
 194 +
 195 +       val = readb(adc->base + JZ_REG_ADC_ENABLE);
 196 +       val |= engine;
 197 +       writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 198 +
 199 +       spin_unlock_irqrestore(&adc->lock, flags);
 200 +}
 201 +
 202 +static void jz4740_adc_disable_adc(struct jz4740_adc *adc, int engine)
 203 +{
 204 +       unsigned long flags;
 205 +       uint8_t val;
 206 +
 207 +       spin_lock_irqsave(&adc->lock, flags);
 208 +
 209 +       val = readb(adc->base + JZ_REG_ADC_ENABLE);
 210 +       val &= ~engine;
 211 +       writeb(val, adc->base + JZ_REG_ADC_ENABLE);
 212 +
 213 +       spin_unlock_irqrestore(&adc->lock, flags);
 214 +}
 215 +
 216 +static inline void jz4740_adc_set_cfg(struct jz4740_adc *adc, uint32_t mask,
 217 +uint32_t val)
 218 +{
 219 +       unsigned long flags;
 220 +       uint32_t cfg;
 221 +
 222 +       spin_lock_irqsave(&adc->lock, flags);
 223 +
 224 +       cfg = readl(adc->base + JZ_REG_ADC_CFG);
 225 +
 226 +       cfg &= ~mask;
 227 +       cfg |= val;
 228 +
 229 +       writel(cfg, adc->base + JZ_REG_ADC_CFG);
 230 +
 231 +       spin_unlock_irqrestore(&adc->lock, flags);
 232 +}
 233 +
 234 +static inline void jz4740_adc_clk_enable(struct jz4740_adc *adc)
 235 +{
 236 +       unsigned long flags;
 237 +
 238 +       spin_lock_irqsave(&adc->lock, flags);
 239 +       if (adc->clk_ref++ == 0)
 240 +               clk_enable(adc->clk);
 241 +       spin_unlock_irqrestore(&adc->lock, flags);
 242 +}
 243 +
 244 +static inline void jz4740_adc_clk_disable(struct jz4740_adc *adc)
 245 +{
 246 +       unsigned long flags;
 247 +
 248 +       spin_lock_irqsave(&adc->lock, flags);
 249 +       if (--adc->clk_ref == 0)
 250 +               clk_disable(adc->clk);
 251 +       spin_unlock_irqrestore(&adc->lock, flags);
 252 +}
 253 +
 254 +long jz4740_adc_read_battery_voltage(struct device *dev,
 255 +                                               enum jz_adc_battery_scale scale)
 256 +{
 257 +       struct jz4740_adc *adc = dev_get_drvdata(dev);
 258 +       unsigned long t;
 259 +       long long voltage;
 260 +       uint16_t val;
 261 +
 262 +       if (!adc)
 263 +               return -ENODEV;
 264 +
 265 +       jz4740_adc_clk_enable(adc);
 266 +
 267 +       if (scale == JZ_ADC_BATTERY_SCALE_2V5)
 268 +               jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, JZ_ADC_CFG_BAT_MB);
 269 +       else
 270 +               jz4740_adc_set_cfg(adc, JZ_ADC_CFG_BAT_MB, 0);
 271 +
 272 +       jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_BATTERY);
 273 +       jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_BATTERY);
 274 +
 275 +       t = wait_for_completion_interruptible_timeout(&adc->bat_completion,
 276 +                                                       HZ);
 277 +
 278 +       jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_BATTERY);
 279 +
 280 +       if (t <= 0) {
 281 +               jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_BATTERY);
 282 +               return t ? t : -ETIMEDOUT;
 283 +       }
 284 +
 285 +       val = readw(adc->base + JZ_REG_ADC_BATTERY);
 286 +
 287 +       jz4740_adc_clk_disable(adc);
 288 +
 289 +       if (scale == JZ_ADC_BATTERY_SCALE_2V5)
 290 +               voltage = (((long long)val) * 2500000LL) >> 12LL;
 291 +       else
 292 +               voltage = ((((long long)val) * 7395000LL) >> 12LL) + 33000LL;
 293 +
 294 +       return voltage;
 295 +}
 296 +EXPORT_SYMBOL_GPL(jz4740_adc_read_battery_voltage);
 297 +
 298 +static ssize_t jz4740_adc_read_adcin(struct device *dev,
 299 +                                       struct device_attribute *dev_attr,
 300 +                                       char *buf)
 301 +{
 302 +       struct jz4740_adc *adc = dev_get_drvdata(dev);
 303 +       unsigned long t;
 304 +       uint16_t val;
 305 +
 306 +       jz4740_adc_clk_enable(adc);
 307 +
 308 +       jz4740_adc_enable_irq(adc, JZ_ADC_IRQ_ADCIN);
 309 +       jz4740_adc_enable_adc(adc, JZ_ADC_ENABLE_ADCIN);
 310 +
 311 +       t = wait_for_completion_interruptible_timeout(&adc->adc_completion,
 312 +                                                       HZ);
 313 +
 314 +       jz4740_adc_disable_irq(adc, JZ_ADC_IRQ_ADCIN);
 315 +
 316 +       if (t <= 0) {
 317 +               jz4740_adc_disable_adc(adc, JZ_ADC_ENABLE_ADCIN);
 318 +               return t ? t : -ETIMEDOUT;
 319 +       }
 320 +
 321 +       val = readw(adc->base + JZ_REG_ADC_ADCIN);
 322 +       jz4740_adc_clk_disable(adc);
 323 +
 324 +       return sprintf(buf, "%d\n", val);
 325 +}
 326 +
 327 +static DEVICE_ATTR(adcin, S_IRUGO, jz4740_adc_read_adcin, NULL);
 328 +
 329 +static int __devinit jz4740_adc_probe(struct platform_device *pdev)
 330 +{
 331 +       int ret;
 332 +       struct jz4740_adc *adc;
 333 +
 334 +       adc = kmalloc(sizeof(*adc), GFP_KERNEL);
 335 +
 336 +       adc->irq = platform_get_irq(pdev, 0);
 337 +
 338 +       if (adc->irq < 0) {
 339 +               ret = adc->irq;
 340 +               dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
 341 +               goto err_free;
 342 +       }
 343 +
 344 +       adc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 345 +
 346 +       if (!adc->mem) {
 347 +               ret = -ENOENT;
 348 +               dev_err(&pdev->dev, "Failed to get platform mmio resource\n");
 349 +               goto err_free;
 350 +       }
 351 +
 352 +       adc->mem = request_mem_region(adc->mem->start, resource_size(adc->mem),
 353 +                                       pdev->name);
 354 +
 355 +       if (!adc->mem) {
 356 +               ret = -EBUSY;
 357 +               dev_err(&pdev->dev, "Failed to request mmio memory region\n");
 358 +               goto err_free;
 359 +       }
 360 +
 361 +       adc->base = ioremap_nocache(adc->mem->start, resource_size(adc->mem));
 362 +
 363 +       if (!adc->base) {
 364 +               ret = -EBUSY;
 365 +               dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
 366 +               goto err_release_mem_region;
 367 +       }
 368 +
 369 +       adc->clk = clk_get(&pdev->dev, "adc");
 370 +
 371 +       if (IS_ERR(adc->clk)) {
 372 +               ret = PTR_ERR(adc->clk);
 373 +               dev_err(&pdev->dev, "Failed to get clock: %d\n", ret);
 374 +               goto err_iounmap;
 375 +       }
 376 +
 377 +       init_completion(&adc->bat_completion);
 378 +       init_completion(&adc->adc_completion);
 379 +
 380 +       spin_lock_init(&adc->lock);
 381 +
 382 +       adc->clk_ref = 0;
 383 +
 384 +       platform_set_drvdata(pdev, adc);
 385 +
 386 +       ret = request_irq(adc->irq, jz4740_adc_irq, 0, pdev->name, adc);
 387 +
 388 +       if (ret) {
 389 +               dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
 390 +               goto err_clk_put;
 391 +       }
 392 +
 393 +       ret = device_create_file(&pdev->dev, &dev_attr_adcin);
 394 +       if (ret) {
 395 +               dev_err(&pdev->dev, "Failed to create sysfs file: %d\n", ret);
 396 +               goto err_free_irq;
 397 +       }
 398 +
 399 +       writeb(0x00, adc->base + JZ_REG_ADC_ENABLE);
 400 +       writeb(0xff, adc->base + JZ_REG_ADC_CTRL);
 401 +
 402 +       return 0;
 403 +
 404 +err_free_irq:
 405 +       free_irq(adc->irq, adc);
 406 +err_clk_put:
 407 +       clk_put(adc->clk);
 408 +err_iounmap:
 409 +       platform_set_drvdata(pdev, NULL);
 410 +       iounmap(adc->base);
 411 +err_release_mem_region:
 412 +       release_mem_region(adc->mem->start, resource_size(adc->mem));
 413 +err_free:
 414 +       kfree(adc);
 415 +
 416 +       return ret;
 417 +}
 418 +
 419 +static int __devexit jz4740_adc_remove(struct platform_device *pdev)
 420 +{
 421 +       struct jz4740_adc *adc = platform_get_drvdata(pdev);
 422 +
 423 +       device_remove_file(&pdev->dev, &dev_attr_adcin);
 424 +
 425 +       free_irq(adc->irq, adc);
 426 +
 427 +       iounmap(adc->base);
 428 +       release_mem_region(adc->mem->start, resource_size(adc->mem));
 429 +
 430 +       clk_put(adc->clk);
 431 +
 432 +       platform_set_drvdata(pdev, NULL);
 433 +
 434 +       kfree(adc);
 435 +
 436 +       return 0;
 437 +}
 438 +
 439 +struct platform_driver jz4740_adc_driver = {
 440 +       .probe  = jz4740_adc_probe,
 441 +       .remove = __devexit_p(jz4740_adc_remove),
 442 +       .driver = {
 443 +               .name = "jz4740-adc",
 444 +               .owner = THIS_MODULE,
 445 +       },
 446 +};
 447 +
 448 +static int __init jz4740_adc_init(void)
 449 +{
 450 +       return platform_driver_register(&jz4740_adc_driver);
 451 +}
 452 +module_init(jz4740_adc_init);
 453 +
 454 +static void __exit jz4740_adc_exit(void)
 455 +{
 456 +       platform_driver_unregister(&jz4740_adc_driver);
 457 +}
 458 +module_exit(jz4740_adc_exit);
 459 +
 460 +MODULE_DESCRIPTION("JZ4720/JZ4740 SoC ADC driver");
 461 +MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
 462 +MODULE_LICENSE("GPL");
 463 +MODULE_ALIAS("platform:jz4740-adc");
 464 +MODULE_ALIAS("platform:jz4720-adc");
 465 diff --git a/include/linux/jz4740-adc.h b/include/linux/jz4740-adc.h
 466 new file mode 100644
 467 index 0000000..59cfe63
 468 --- /dev/null
 469 +++ b/include/linux/jz4740-adc.h
 470 @@ -0,0 +1,25 @@
 471 +
 472 +#ifndef __LINUX_JZ4740_ADC
 473 +#define __LINUX_JZ4740_ADC
 474 +
 475 +#include <linux/device.h>
 476 +
 477 +enum jz_adc_battery_scale {
 478 +       JZ_ADC_BATTERY_SCALE_2V5, /* Mesures voltages up to 2.5V */
 479 +       JZ_ADC_BATTERY_SCALE_7V5, /* Mesures voltages up to 7.5V */
 480 +};
 481 +
 482 +/*
 483 + * jz4740_adc_read_battery_voltage - Read battery voltage from the ADC PBAT pin
 484 + * @dev: Pointer to a jz4740-adc device
 485 + * @scale: Whether to use 2.5V or 7.5V scale
 486 + *
 487 + * Returns: Battery voltage in mircovolts
 488 + *
 489 + * Context: Process
 490 +*/
 491 +long jz4740_adc_read_battery_voltage(struct device *dev,
 492 +                                       enum jz_adc_battery_scale scale);
 493 +
 494 +
 495 +#endif
 496 --
 497 1.5.6.5
 498