target/linux/rb532/files-2.6.24/include/asm-mips/rc32434/ddr.h

   1 #ifndef __IDT_DDR_H__
   2 #define __IDT_DDR_H__
   3
   4 /*******************************************************************************
   5  *
   6  * Copyright 2002 Integrated Device Technology, Inc.
   7  *              All rights reserved.
   8  *
   9  * DDR register definition.
  10  *
  11  * File   : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
  12  *
  13  * Author : ryan.holmQVist@idt.com
  14  * Date   : 20011005
  15  * Update :
  16  *          $Log: ddr.h,v $
  17  *          Revision 1.2  2002/06/06 18:34:03  astichte
  18  *          Added XXX_PhysicalAddress and XXX_VirtualAddress
  19  *
  20  *          Revision 1.1  2002/05/29 17:33:21  sysarch
  21  *          jba File moved from vcode/include/idt/acacia
  22  *
  23  *
  24  ******************************************************************************/
  25
  26 enum
  27 {
  28         DDR0_PhysicalAddress    = 0x18018000,
  29         DDR_PhysicalAddress     = DDR0_PhysicalAddress,         // Default
  30
  31         DDR0_VirtualAddress     = 0xb8018000,
  32         DDR_VirtualAddress      = DDR0_VirtualAddress,          // Default
  33 } ;
  34
  35 typedef struct DDR_s
  36 {
  37         u32     ddrbase ;
  38         u32     ddrmask ;
  39         u32     res1;
  40         u32     res2;
  41         u32     ddrc ;
  42         u32     ddrabase ;
  43         u32     ddramask ;
  44         u32     ddramap ;
  45         u32     ddrcust;
  46         u32     ddrrdc;
  47         u32     ddrspare;
  48 } volatile *DDR_t ;
  49
  50 enum
  51 {
  52         DDR0BASE_baseaddr_b     = 16,
  53         DDR0BASE_baseaddr_m     = 0xffff0000,
  54
  55         DDR0MASK_mask_b         = 16,
  56         DDR0MASK_mask_m         = 0xffff0000,
  57
  58         DDR1BASE_baseaddr_b     = 16,
  59         DDR1BASE_baseaddr_m     = 0xffff0000,
  60
  61         DDR1MASK_mask_b         = 16,
  62         DDR1MASK_mask_m         = 0xffff0000,
  63
  64         DDRC_ata_b              = 5,
  65         DDRC_ata_m              = 0x000000E0,
  66         DDRC_dbw_b              = 8,
  67         DDRC_dbw_m              = 0x00000100,
  68         DDRC_wr_b               = 9,
  69         DDRC_wr_m               = 0x00000600,
  70         DDRC_ps_b               = 11,
  71         DDRC_ps_m               = 0x00001800,
  72         DDRC_dtype_b            = 13,
  73         DDRC_dtype_m            = 0x0000e000,
  74         DDRC_rfc_b              = 16,
  75         DDRC_rfc_m              = 0x000f0000,
  76         DDRC_rp_b               = 20,
  77         DDRC_rp_m               = 0x00300000,
  78         DDRC_ap_b               = 22,
  79         DDRC_ap_m               = 0x00400000,
  80         DDRC_rcd_b              = 23,
  81         DDRC_rcd_m              = 0x01800000,
  82         DDRC_cl_b               = 25,
  83         DDRC_cl_m               = 0x06000000,
  84         DDRC_dbm_b              = 27,
  85         DDRC_dbm_m              = 0x08000000,
  86         DDRC_sds_b              = 28,
  87         DDRC_sds_m              = 0x10000000,
  88         DDRC_atp_b              = 29,
  89         DDRC_atp_m              = 0x60000000,
  90         DDRC_re_b               = 31,
  91         DDRC_re_m               = 0x80000000,
  92
  93         DDRRDC_ces_b            = 0,
  94         DDRRDC_ces_m            = 0x00000001,
  95         DDRRDC_ace_b            = 1,
  96         DDRRDC_ace_m            = 0x00000002,
  97
  98         DDRABASE_baseaddr_b     = 16,
  99         DDRABASE_baseaddr_m     = 0xffff0000,
 100
 101         DDRAMASK_mask_b         = 16,
 102         DDRAMASK_mask_m         = 0xffff0000,
 103
 104         DDRAMAP_map_b           = 16,
 105         DDRAMAP_map_m           = 0xffff0000,
 106
 107         DDRCUST_cs_b            = 0,
 108         DDRCUST_cs_m            = 0x00000003,
 109         DDRCUST_we_b            = 2,
 110         DDRCUST_we_m            = 0x00000004,
 111         DDRCUST_ras_b           = 3,
 112         DDRCUST_ras_m           = 0x00000008,
 113         DDRCUST_cas_b           = 4,
 114         DDRCUST_cas_m           = 0x00000010,
 115         DDRCUST_cke_b           = 5,
 116         DDRCUST_cke_m           = 0x00000020,
 117         DDRCUST_ba_b            = 6,
 118         DDRCUST_ba_m            = 0x000000c0,
 119
 120         RCOUNT_rcount_b         = 0,
 121         RCOUNT_rcount_m         = 0x0000ffff,
 122
 123         RCOMPARE_rcompare_b     = 0,
 124         RCOMPARE_rcompare_m     = 0x0000ffff,
 125
 126         RTC_ce_b                = 0,
 127         RTC_ce_m                = 0x00000001,
 128         RTC_to_b                = 1,
 129         RTC_to_m                = 0x00000002,
 130         RTC_rqe_b               = 2,
 131         RTC_rqe_m               = 0x00000004,
 132
 133         DDRDQSC_dm_b            = 0,
 134         DDRDQSC_dm_m            = 0x00000003,
 135         DDRDQSC_dqsbs_b         = 2,
 136         DDRDQSC_dqsbs_m         = 0x000000fc,
 137         DDRDQSC_db_b            = 8,
 138         DDRDQSC_db_m            = 0x00000100,
 139         DDRDQSC_dbsp_b          = 9,
 140         DDRDQSC_dbsp_m          = 0x01fffe00,
 141         DDRDQSC_bdp_b           = 25,
 142         DDRDQSC_bdp_m           = 0x7e000000,
 143
 144         DDRDLLC_eao_b           = 0,
 145         DDRDLLC_eao_m           = 0x00000001,
 146         DDRDLLC_eo_b            = 1,
 147         DDRDLLC_eo_m            = 0x0000003e,
 148         DDRDLLC_fs_b            = 6,
 149         DDRDLLC_fs_m            = 0x000000c0,
 150         DDRDLLC_as_b            = 8,
 151         DDRDLLC_as_m            = 0x00000700,
 152         DDRDLLC_sp_b            = 11,
 153         DDRDLLC_sp_m            = 0x001ff800,
 154
 155         DDRDLLFC_men_b          = 0,
 156         DDRDLLFC_men_m          = 0x00000001,
 157         DDRDLLFC_aen_b          = 1,
 158         DDRDLLFC_aen_m          = 0x00000002,
 159         DDRDLLFC_ff_b           = 2,
 160         DDRDLLFC_ff_m           = 0x00000004,
 161
 162         DDRDLLTA_addr_b         = 2,
 163         DDRDLLTA_addr_m         = 0xfffffffc,
 164
 165         DDRDLLED_dbe_b          = 0,
 166         DDRDLLED_dbe_m          = 0x00000001,
 167         DDRDLLED_dte_b          = 1,
 168         DDRDLLED_dte_m          = 0x00000002,
 169
 170
 171 } ;
 172
 173 #endif  // __IDT_DDR_H__