target/linux/orion/patches/017-add_linksys_wrt350n_v2_support.patch

   1 Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
   2 Tested-by: Dirk Teurlings <dirk@upexia.nl>
   3 Tested-by: Peter van Valderen <p.v.valderen@gmail.com>
   4 ---
   5  arch/arm/mach-orion5x/Kconfig            |    6 +
   6  arch/arm/mach-orion5x/Makefile           |    1 +
   7  arch/arm/mach-orion5x/wrt350n-v2-setup.c |  170 ++++++++++++++++++++++++++++++
   8  3 files changed, 177 insertions(+), 0 deletions(-)
   9  create mode 100644 arch/arm/mach-orion5x/wrt350n-v2-setup.c
  10
  11 --- a/arch/arm/mach-orion5x/Kconfig
  12 +++ b/arch/arm/mach-orion5x/Kconfig
  13 @@ -50,6 +50,12 @@
  14           Say 'Y' here if you want your kernel to support the
  15           QNAP TS-409 platform.
  16
  17 +config MACH_WRT350N_V2
  18 +       bool "Linksys WRT350N v2"
  19 +       help
  20 +         Say 'Y' here if you want your kernel to support the
  21 +         Linksys WRT350N v2 platform.
  22 +
  23  endmenu
  24
  25  endif
  26 --- a/arch/arm/mach-orion5x/Makefile
  27 +++ b/arch/arm/mach-orion5x/Makefile
  28 @@ -6,3 +6,4 @@
  29  obj-$(CONFIG_MACH_DNS323)      += dns323-setup.o
  30  obj-$(CONFIG_MACH_TS209)       += ts209-setup.o
  31  obj-$(CONFIG_MACH_TS409)       += ts409-setup.o
  32 +obj-$(CONFIG_MACH_WRT350N_V2)  += wrt350n-v2-setup.o
  33 --- /dev/null
  34 +++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
  35 @@ -0,0 +1,170 @@
  36 +/*
  37 + * arch/arm/mach-orion5x/wrt350n-v2-setup.c
  38 + *
  39 + * This file is licensed under the terms of the GNU General Public
  40 + * License version 2.  This program is licensed "as is" without any
  41 + * warranty of any kind, whether express or implied.
  42 + */
  43 +
  44 +#include <linux/kernel.h>
  45 +#include <linux/init.h>
  46 +#include <linux/platform_device.h>
  47 +#include <linux/pci.h>
  48 +#include <linux/irq.h>
  49 +#include <linux/delay.h>
  50 +#include <linux/mtd/physmap.h>
  51 +#include <linux/mv643xx_eth.h>
  52 +#include <asm/mach-types.h>
  53 +#include <asm/gpio.h>
  54 +#include <asm/mach/arch.h>
  55 +#include <asm/mach/pci.h>
  56 +#include <asm/arch/orion5x.h>
  57 +#include "common.h"
  58 +#include "mpp.h"
  59 +
  60 +/*
  61 + * 8M NOR flash Device bus boot chip select
  62 + */
  63 +#define WRT350N_V2_NOR_BOOT_BASE       0xf4000000
  64 +#define WRT350N_V2_NOR_BOOT_SIZE       SZ_8M
  65 +
  66 +static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
  67 +       {
  68 +               .name           = "kernel",
  69 +               .offset         = 0x00000000,
  70 +               .size           = 0x00760000,
  71 +       }, {
  72 +               .name           = "rootfs",
  73 +               .offset         = 0x001a0000,
  74 +               .size           = 0x005c0000,
  75 +       }, {
  76 +               .name           = "lang",
  77 +               .offset         = 0x00760000,
  78 +               .size           = 0x00040000,
  79 +       }, {
  80 +               .name           = "nvram",
  81 +               .offset         = 0x007a0000,
  82 +               .size           = 0x00020000,
  83 +       }, {
  84 +               .name           = "u-boot",
  85 +               .offset         = 0x007c0000,
  86 +               .size           = 0x00040000,
  87 +       },
  88 +};
  89 +
  90 +static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
  91 +       .width          = 1,
  92 +       .parts          = wrt350n_v2_nor_flash_partitions,
  93 +       .nr_parts       = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
  94 +};
  95 +
  96 +static struct resource wrt350n_v2_nor_flash_resource = {
  97 +       .flags          = IORESOURCE_MEM,
  98 +       .start          = WRT350N_V2_NOR_BOOT_BASE,
  99 +       .end            = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
 100 +};
 101 +
 102 +static struct platform_device wrt350n_v2_nor_flash = {
 103 +       .name                   = "physmap-flash",
 104 +       .id                     = 0,
 105 +       .dev            = {
 106 +               .platform_data  = &wrt350n_v2_nor_flash_data,
 107 +       },
 108 +       .num_resources          = 1,
 109 +       .resource               = &wrt350n_v2_nor_flash_resource,
 110 +};
 111 +
 112 +static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
 113 +       .phy_addr       = -1,
 114 +};
 115 +
 116 +static void __init wrt350n_v2_init(void)
 117 +{
 118 +       /*
 119 +        * Setup basic Orion functions. Need to be called early.
 120 +        */
 121 +       orion5x_init();
 122 +
 123 +       orion5x_mpp_conf(0, MPP_GPIO);          /* Power LED green (0=on) */
 124 +       orion5x_mpp_conf(1, MPP_GPIO);          /* Security LED (0=on) */
 125 +       orion5x_mpp_conf(2, MPP_GPIO);          /* Internal Button (0=on) */
 126 +       orion5x_mpp_conf(3, MPP_GPIO);          /* Reset Button (0=on) */
 127 +       orion5x_mpp_conf(4, MPP_GPIO);          /* PCI int */
 128 +       orion5x_mpp_conf(5, MPP_GPIO);          /* Power LED orange (0=on) */
 129 +       orion5x_mpp_conf(6, MPP_GPIO);          /* USB LED (0=on) */
 130 +       orion5x_mpp_conf(7, MPP_GPIO);          /* Wireless LED (0=on) */
 131 +       orion5x_mpp_conf(8, MPP_UNUSED);        /* ??? */
 132 +       orion5x_mpp_conf(9, MPP_GIGE);          /* GE_RXERR */
 133 +       orion5x_mpp_conf(10, MPP_UNUSED);       /* ??? */
 134 +       orion5x_mpp_conf(11, MPP_UNUSED);       /* ??? */
 135 +       orion5x_mpp_conf(12, MPP_GIGE);         /* GE_TXD[4] */
 136 +       orion5x_mpp_conf(13, MPP_GIGE);         /* GE_TXD[5] */
 137 +       orion5x_mpp_conf(14, MPP_GIGE);         /* GE_TXD[6] */
 138 +       orion5x_mpp_conf(15, MPP_GIGE);         /* GE_TXD[7] */
 139 +       orion5x_mpp_conf(16, MPP_GIGE);         /* GE_RXD[4] */
 140 +       orion5x_mpp_conf(17, MPP_GIGE);         /* GE_RXD[5] */
 141 +       orion5x_mpp_conf(18, MPP_GIGE);         /* GE_RXD[6] */
 142 +       orion5x_mpp_conf(19, MPP_GIGE);         /* GE_RXD[7] */
 143 +
 144 +       /*
 145 +        * Configure peripherals.
 146 +        */
 147 +       orion5x_ehci0_init();
 148 +       orion5x_eth_init(&wrt350n_v2_eth_data);
 149 +       orion5x_uart0_init();
 150 +
 151 +       orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
 152 +                                  WRT350N_V2_NOR_BOOT_SIZE);
 153 +       platform_device_register(&wrt350n_v2_nor_flash);
 154 +}
 155 +
 156 +static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 157 +{
 158 +       int irq;
 159 +
 160 +       /*
 161 +        * Check for devices with hard-wired IRQs.
 162 +        */
 163 +       irq = orion5x_pci_map_irq(dev, slot, pin);
 164 +       if (irq != -1)
 165 +               return irq;
 166 +
 167 +       /*
 168 +        * Mini-PCI slot.
 169 +        */
 170 +       if (slot == 7)
 171 +               return gpio_to_irq(4);
 172 +
 173 +       printk(KERN_ERR "wrt350n_v2_pci_map_irq failed, unknown bus\n");
 174 +
 175 +       return -1;
 176 +}
 177 +
 178 +static struct hw_pci wrt350n_v2_pci __initdata = {
 179 +       .nr_controllers = 2,
 180 +       .swizzle        = pci_std_swizzle,
 181 +       .setup          = orion5x_pci_sys_setup,
 182 +       .scan           = orion5x_pci_sys_scan_bus,
 183 +       .map_irq        = wrt350n_v2_pci_map_irq,
 184 +};
 185 +
 186 +static int __init wrt350n_v2_pci_init(void)
 187 +{
 188 +       if (machine_is_wrt350n_v2())
 189 +               pci_common_init(&wrt350n_v2_pci);
 190 +
 191 +       return 0;
 192 +}
 193 +subsys_initcall(wrt350n_v2_pci_init);
 194 +
 195 +MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
 196 +       /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
 197 +       .phys_io        = ORION5X_REGS_PHYS_BASE,
 198 +       .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
 199 +       .boot_params    = 0x00000100,
 200 +       .init_machine   = wrt350n_v2_init,
 201 +       .map_io         = orion5x_map_io,
 202 +       .init_irq       = orion5x_init_irq,
 203 +       .timer          = &orion5x_timer,
 204 +       .fixup          = tag_fixup_mem32,
 205 +MACHINE_END