1 From 58d1ae79d144e6725a68fab99ef6a9b20b25a765 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 21 Feb 2012 21:09:01 +0100
4 Subject: [PATCH 37/70] MIPS: lantiq: add ipi handlers to make vsmp work
6 Add IPI handlers to the interrupt code. This patch makes MIPS_MT_SMP work
9 Signed-off-by: John Crispin <blogic@openwrt.org>
11 arch/mips/lantiq/irq.c | 61 +++++++++++++++++++++++++++++++++++++++++++++++
12 arch/mips/lantiq/prom.c | 5 ++++
13 2 files changed, 66 insertions(+), 0 deletions(-)
15 --- a/arch/mips/lantiq/irq.c
16 +++ b/arch/mips/lantiq/irq.c
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 +#include <linux/sched.h>
23 #include <asm/bootinfo.h>
24 #include <asm/irq_cpu.h>
26 #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
27 #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
29 +/* our 2 ipi interrupts for VSMP */
30 +#define MIPS_CPU_IPI_RESCHED_IRQ 0
31 +#define MIPS_CPU_IPI_CALL_IRQ 1
33 +#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
37 static unsigned short ltq_eiu_irq[MAX_EIU] = {
40 @@ -219,6 +228,47 @@ static void ltq_hw5_irqdispatch(void)
41 do_IRQ(MIPS_CPU_TIMER_IRQ);
44 +#ifdef CONFIG_MIPS_MT_SMP
45 +void __init arch_init_ipiirq(int irq, struct irqaction *action)
47 + setup_irq(irq, action);
48 + irq_set_handler(irq, handle_percpu_irq);
51 +static void ltq_sw0_irqdispatch(void)
53 + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ);
56 +static void ltq_sw1_irqdispatch(void)
58 + do_IRQ(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ);
60 +static irqreturn_t ipi_resched_interrupt(int irq, void *dev_id)
66 +static irqreturn_t ipi_call_interrupt(int irq, void *dev_id)
68 + smp_call_function_interrupt();
72 +static struct irqaction irq_resched = {
73 + .handler = ipi_resched_interrupt,
74 + .flags = IRQF_PERCPU,
75 + .name = "IPI_resched"
78 +static struct irqaction irq_call = {
79 + .handler = ipi_call_interrupt,
80 + .flags = IRQF_PERCPU,
85 asmlinkage void plat_irq_dispatch(void)
87 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
88 @@ -314,6 +364,17 @@ void __init arch_init_irq(void)
89 irq_set_chip_and_handler(i, <q_irq_type,
92 +#if defined(CONFIG_MIPS_MT_SMP)
94 + pr_info("Setting up IPI vectored interrupts\n");
95 + set_vi_handler(MIPS_CPU_IPI_RESCHED_IRQ, ltq_sw0_irqdispatch);
96 + set_vi_handler(MIPS_CPU_IPI_CALL_IRQ, ltq_sw1_irqdispatch);
98 + arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ,
100 + arch_init_ipiirq(MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ, &irq_call);
103 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
104 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
105 IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
106 --- a/arch/mips/lantiq/prom.c
107 +++ b/arch/mips/lantiq/prom.c
108 @@ -108,4 +108,9 @@ void __init prom_init(void)
109 soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0';
110 pr_info("SoC: %s\n", soc_info.sys_type);
113 +#if defined(CONFIG_MIPS_MT_SMP)
114 + if (register_vsmp_smp_ops())
115 + panic("failed to register_vsmp_smp_ops()");