package/switch/src/switch-adm.c

   1 /*
   2  * ADMTEK Adm6996 switch configuration module
   3  *
   4  * Copyright (C) 2005 Felix Fietkau <nbd@nbd.name>
   5  *
   6  * Partially based on Broadcom Home Networking Division 10/100 Mbit/s
   7  * Ethernet Device Driver (from Montavista 2.4.20_mvl31 Kernel).
   8  * Copyright (C) 2004 Broadcom Corporation
   9  *
  10  * adm_rreg function from adm6996
  11  * Copyright (C) 2004 Nikki Chumakov <nikki@gattaca.ru>
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  26  * 02110-1301, USA.
  27  */
  28
  29 #include <linux/autoconf.h>
  30 #include <linux/module.h>
  31 #include <linux/init.h>
  32 #include <linux/if.h>
  33 #include <linux/if_arp.h>
  34 #include <linux/sockios.h>
  35 #include <linux/delay.h>
  36 #include <asm/uaccess.h>
  37
  38 #include "switch-core.h"
  39 #include "gpio.h"
  40
  41 #define DRIVER_NAME "adm6996"
  42 #define DRIVER_VERSION "0.01"
  43
  44 static int eecs = 0;
  45 static int eesk = 0;
  46 static int eedi = 0;
  47 static int eerc = 0;
  48 static int force = 0;
  49
  50 MODULE_AUTHOR("Felix Fietkau <openwrt@nbd.name>");
  51 MODULE_LICENSE("GPL");
  52 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,52)
  53 module_param(eecs, int, 0);
  54 module_param(eesk, int, 0);
  55 module_param(eedi, int, 0);
  56 module_param(eerc, int, 0);
  57 module_param(force, int, 0);
  58 #else
  59 MODULE_PARM(eecs, "i");
  60 MODULE_PARM(eesk, "i");
  61 MODULE_PARM(eedi, "i");
  62 MODULE_PARM(eerc, "i");
  63 MODULE_PARM(force, "i");
  64 #endif
  65
  66 /* Minimum timing constants */
  67 #define EECK_EDGE_TIME  3   /* 3us - max(adm 2.5us, 93c 1us) */
  68 #define EEDI_SETUP_TIME 1   /* 1us - max(adm 10ns, 93c 400ns) */
  69 #define EECS_SETUP_TIME 1   /* 1us - max(adm no, 93c 200ns) */
  70
  71 /* Handy macros for writing fixed length values */
  72 #define adm_write8(cs, b) { __u8 val = (__u8) (b); adm_write(cs, &val, sizeof(val)*8); }
  73 #define adm_write16(cs, w) { __u16 val = hton16(w); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
  74 #define adm_write32(cs, i) { uint32 val = hton32(i); adm_write(cs, (__u8 *)&val, sizeof(val)*8); }
  75
  76 #define atoi(str) simple_strtoul(((str != NULL) ? str : ""), NULL, 0)
  77
  78 #ifdef BROADCOM
  79 extern char *nvram_get(char *name);
  80
  81 /* Return gpio pin number assigned to the named pin */
  82 /*
  83 * Variable should be in format:
  84 *
  85 *       gpio<N>=pin_name
  86 *
  87 * 'def_pin' is returned if there is no such variable found.
  88 */
  89 static unsigned int get_gpiopin(char *pin_name, unsigned int def_pin)
  90 {
  91         char name[] = "gpioXXXX";
  92         char *val;
  93         unsigned int pin;
  94
  95         /* Go thru all possibilities till a match in pin name */
  96         for (pin = 0; pin < 16; pin ++) {
  97                 sprintf(name, "gpio%d", pin);
  98                 val = nvram_get(name);
  99                 if (val && !strcmp(val, pin_name))
 100                         return pin;
 101         }
 102         return def_pin;
 103 }
 104 #endif
 105
 106
 107 static void adm_write(int cs, char *buf, unsigned int bits)
 108 {
 109         int i, len = (bits + 7) / 8;
 110         __u8 mask;
 111
 112         gpio_out(eecs, (cs ? eecs : 0));
 113         udelay(EECK_EDGE_TIME);
 114
 115         /* Byte assemble from MSB to LSB */
 116         for (i = 0; i < len; i++) {
 117                 /* Bit bang from MSB to LSB */
 118                 for (mask = 0x80; mask && bits > 0; mask >>= 1, bits --) {
 119                         /* Clock low */
 120                         gpio_out(eesk, 0);
 121                         udelay(EECK_EDGE_TIME);
 122
 123                         /* Output on rising edge */
 124                         gpio_out(eedi, ((mask & buf[i]) ? eedi : 0));
 125                         udelay(EEDI_SETUP_TIME);
 126
 127                         /* Clock high */
 128                         gpio_out(eesk, eesk);
 129                         udelay(EECK_EDGE_TIME);
 130                 }
 131         }
 132
 133         /* Clock low */
 134         gpio_out(eesk, 0);
 135         udelay(EECK_EDGE_TIME);
 136
 137         if (cs)
 138                 gpio_out(eecs, 0);
 139 }
 140
 141
 142 static void adm_read(int cs, char *buf, unsigned int bits)
 143 {
 144         int i, len = (bits + 7) / 8;
 145         __u8 mask;
 146
 147         gpio_out(eecs, (cs ? eecs : 0));
 148         udelay(EECK_EDGE_TIME);
 149
 150         /* Byte assemble from MSB to LSB */
 151         for (i = 0; i < len; i++) {
 152                 __u8 byte;
 153
 154                 /* Bit bang from MSB to LSB */
 155                 for (mask = 0x80, byte = 0; mask && bits > 0; mask >>= 1, bits --) {
 156                         __u8 gp;
 157
 158                         /* Clock low */
 159                         gpio_out(eesk, 0);
 160                         udelay(EECK_EDGE_TIME);
 161
 162                         /* Input on rising edge */
 163                         gp = gpio_in();
 164                         if (gp & eedi)
 165                                 byte |= mask;
 166
 167                         /* Clock high */
 168                         gpio_out(eesk, eesk);
 169                         udelay(EECK_EDGE_TIME);
 170                 }
 171
 172                 *buf++ = byte;
 173         }
 174
 175         /* Clock low */
 176         gpio_out(eesk, 0);
 177         udelay(EECK_EDGE_TIME);
 178
 179         if (cs)
 180                 gpio_out(eecs, 0);
 181 }
 182
 183
 184 /* Enable outputs with specified value to the chip */
 185 static void adm_enout(__u8 pins, __u8 val)
 186 {
 187         /* Prepare GPIO output value */
 188         gpio_out(pins, val);
 189
 190         /* Enable GPIO outputs */
 191         gpio_outen(pins, pins);
 192         udelay(EECK_EDGE_TIME);
 193 }
 194
 195
 196 /* Disable outputs to the chip */
 197 static void adm_disout(__u8 pins)
 198 {
 199         /* Disable GPIO outputs */
 200         gpio_outen(pins, 0);
 201         udelay(EECK_EDGE_TIME);
 202 }
 203
 204
 205 /* Advance clock(s) */
 206 static void adm_adclk(int clocks)
 207 {
 208         int i;
 209         for (i = 0; i < clocks; i++) {
 210                 /* Clock high */
 211                 gpio_out(eesk, eesk);
 212                 udelay(EECK_EDGE_TIME);
 213
 214                 /* Clock low */
 215                 gpio_out(eesk, 0);
 216                 udelay(EECK_EDGE_TIME);
 217         }
 218 }
 219
 220 static __u32 adm_rreg(__u8 table, __u8 addr)
 221 {
 222         /* cmd: 01 10 T DD R RRRRRR */
 223         __u8 bits[6] = {
 224                 0xFF, 0xFF, 0xFF, 0xFF,
 225                 (0x06 << 4) | ((table & 0x01) << 3 | (addr&64)>>6),
 226                 ((addr&63)<<2)
 227         };
 228
 229         __u8 rbits[4];
 230
 231         /* Enable GPIO outputs with all pins to 0 */
 232         adm_enout((__u8)(eecs | eesk | eedi), 0);
 233
 234         adm_write(0, bits, 46);
 235         adm_disout((__u8)(eedi));
 236         adm_adclk(2);
 237         adm_read (0, rbits, 32);
 238
 239         /* Extra clock(s) required per datasheet */
 240         adm_adclk(2);
 241
 242         /* Disable GPIO outputs */
 243         adm_disout((__u8)(eecs | eesk));
 244
 245         if (!table) /* EEPROM has 16-bit registers, but pumps out two registers in one request */
 246                 return (addr & 0x01 ?  (rbits[0]<<8) | rbits[1] : (rbits[2]<<8) | (rbits[3]));
 247         else
 248                 return (rbits[0]<<24) | (rbits[1]<<16) | (rbits[2]<<8) | rbits[3];
 249 }
 250
 251
 252
 253 /* Write chip configuration register */
 254 /* Follow 93c66 timing and chip's min EEPROM timing requirement */
 255 void
 256 adm_wreg(__u8 addr, __u16 val)
 257 {
 258         /* cmd(27bits): sb(1) + opc(01) + addr(bbbbbbbb) + data(bbbbbbbbbbbbbbbb) */
 259         __u8 bits[4] = {
 260                 (0x05 << 5) | (addr >> 3),
 261                 (addr << 5) | (__u8)(val >> 11),
 262                 (__u8)(val >> 3),
 263                 (__u8)(val << 5)
 264         };
 265
 266         /* Enable GPIO outputs with all pins to 0 */
 267         adm_enout((__u8)(eecs | eesk | eedi), 0);
 268
 269         /* Write cmd. Total 27 bits */
 270         adm_write(1, bits, 27);
 271
 272         /* Extra clock(s) required per datasheet */
 273         adm_adclk(2);
 274
 275         /* Disable GPIO outputs */
 276         adm_disout((__u8)(eecs | eesk | eedi));
 277 }
 278
 279
 280 /* Port configuration registers */
 281 static int port_conf[] = { 0x01, 0x03, 0x05, 0x07, 0x08, 0x09 };
 282
 283 /* Bits in VLAN port mapping */
 284 static int vlan_ports[] = { 1 << 0, 1 << 2, 1 << 4, 1 << 6, 1 << 7, 1 << 8 };
 285
 286 static int handle_vlan_port_read(void *driver, char *buf, int nr)
 287 {
 288         int ports, i, c, len = 0;
 289
 290         if ((nr < 0) || (nr > 15))
 291                 return 0;
 292
 293         /* Get VLAN port map */
 294         ports = adm_rreg(0, 0x13 + nr);
 295
 296         for (i = 0; i <= 5; i++) {
 297                 if (ports & vlan_ports[i]) {
 298                         c = adm_rreg(0, port_conf[i]);
 299
 300                         len += sprintf(buf + len, "%d", i);
 301                         if (c & (1 << 4)) {
 302                                 buf[len++] = 't';
 303                                 if (((c & (0xf << 10)) >> 10) == nr)
 304                                         buf[len++] = '*';
 305                         } else if (i == 5)
 306                                 buf[len++] = 'u';
 307
 308                         buf[len++] = '\t';
 309                 }
 310         }
 311         len += sprintf(buf + len, "\n");
 312
 313         return len;
 314 }
 315
 316 static int handle_vlan_port_write(void *driver, char *buf, int nr)
 317 {
 318         int i, cfg, ports;
 319         switch_driver *d = (switch_driver *) driver;
 320         switch_vlan_config *c = switch_parse_vlan(d, buf);
 321
 322         if (c == NULL)
 323                 return -1;
 324
 325         ports = adm_rreg(0, 0x13 + nr);
 326         for (i = 0; i < d->ports; i++) {
 327                 if (c->port & (1 << i)) {
 328                         ports |= vlan_ports[i];
 329
 330                         cfg = adm_rreg(0, port_conf[i]);
 331
 332                         /* Tagging */
 333                         if (c->untag & (1 << i))
 334                                 cfg &= ~(1 << 4);
 335                         else
 336                                 cfg |= (1 << 4);
 337
 338                         if ((c->untag | c->pvid) & (1 << i)) {
 339                                 cfg = (cfg & ~(0xf << 10)) | (nr << 10);
 340                         }
 341
 342                         adm_wreg(port_conf[i], (__u16) cfg);
 343                 } else {
 344                         ports &= ~(vlan_ports[i]);
 345                 }
 346         }
 347         adm_wreg(0x13 + nr, (__u16) ports);
 348
 349         return 0;
 350 }
 351
 352 static int handle_port_enable_read(void *driver, char *buf, int nr)
 353 {
 354         return sprintf(buf, "%d\n", ((adm_rreg(0, port_conf[nr]) & (1 << 5)) ? 0 : 1));
 355 }
 356
 357 static int handle_port_enable_write(void *driver, char *buf, int nr)
 358 {
 359         int reg = adm_rreg(0, port_conf[nr]);
 360
 361         if (buf[0] == '0')
 362                 reg |= (1 << 5);
 363         else if (buf[0] == '1')
 364                 reg &= ~(1 << 5);
 365         else return -1;
 366
 367         adm_wreg(port_conf[nr], (__u16) reg);
 368         return 0;
 369 }
 370
 371 static int handle_port_media_read(void *driver, char *buf, int nr)
 372 {
 373         int len;
 374         int media = 0;
 375         int reg = adm_rreg(0, port_conf[nr]);
 376
 377         if (reg & (1 << 1))
 378                 media |= SWITCH_MEDIA_AUTO;
 379         if (reg & (1 << 2))
 380                 media |= SWITCH_MEDIA_100;
 381         if (reg & (1 << 3))
 382                 media |= SWITCH_MEDIA_FD;
 383
 384         len = switch_print_media(buf, media);
 385         return len + sprintf(buf + len, "\n");
 386 }
 387
 388 static int handle_port_media_write(void *driver, char *buf, int nr)
 389 {
 390         int media = switch_parse_media(buf);
 391         int reg = adm_rreg(0, port_conf[nr]);
 392
 393         if (media < 0)
 394                 return -1;
 395
 396         reg &= ~((1 << 1) | (1 << 2) | (1 << 3));
 397         if (media & SWITCH_MEDIA_AUTO)
 398                 reg |= 1 << 1;
 399         if (media & SWITCH_MEDIA_100)
 400                 reg |= 1 << 2;
 401         if (media & SWITCH_MEDIA_FD)
 402                 reg |= 1 << 3;
 403
 404         adm_wreg(port_conf[nr], reg);
 405
 406         return 0;
 407 }
 408
 409 static int handle_vlan_enable_read(void *driver, char *buf, int nr)
 410 {
 411         return sprintf(buf, "%d\n", ((adm_rreg(0, 0x11) & (1 << 5)) ? 1 : 0));
 412 }
 413
 414 static int handle_vlan_enable_write(void *driver, char *buf, int nr)
 415 {
 416         int reg = adm_rreg(0, 0x11);
 417
 418         if (buf[0] == '1')
 419                 reg |= (1 << 5);
 420         else if (buf[0] == '0')
 421                 reg &= ~(1 << 5);
 422         else return -1;
 423
 424         adm_wreg(0x11, (__u16) reg);
 425         return 0;
 426 }
 427
 428 static int handle_reset(void *driver, char *buf, int nr)
 429 {
 430         int i;
 431         u32 cfg;
 432
 433         /*
 434          * Reset sequence: RC high->low(100ms)->high(30ms)
 435          *
 436          * WAR: Certain boards don't have the correct power on
 437          * reset logic therefore we must explicitly perform the
 438          * sequence in software.
 439          */
 440         if (eerc) {
 441                 /* Keep RC high for at least 20ms */
 442                 adm_enout(eerc, eerc);
 443                 for (i = 0; i < 20; i ++)
 444                         udelay(1000);
 445                 /* Keep RC low for at least 100ms */
 446                 adm_enout(eerc, 0);
 447                 for (i = 0; i < 100; i++)
 448                         udelay(1000);
 449                 /* Set default configuration */
 450                 adm_enout((__u8)(eesk | eedi), eesk);
 451                 /* Keep RC high for at least 30ms */
 452                 adm_enout(eerc, eerc);
 453                 for (i = 0; i < 30; i++)
 454                         udelay(1000);
 455                 /* Leave RC high and disable GPIO outputs */
 456                 adm_disout((__u8)(eecs | eesk | eedi));
 457
 458         }
 459
 460         /* set up initial configuration for cpu port */
 461         cfg = (0x8000 | /* Auto MDIX */
 462               (0xf << 10) | /* PVID */
 463                   (1 << 4) | /* Tagging */
 464                   0xf); /* full duplex, 100Mbps, auto neg, flow ctrl */
 465         adm_wreg(port_conf[5], cfg);
 466
 467         /* vlan mode select register (0x11): vlan on, mac clone */
 468         adm_wreg(0x11, 0xff30);
 469
 470         return 0;
 471 }
 472
 473 static int handle_registers(void *driver, char *buf, int nr)
 474 {
 475         int i, len = 0;
 476
 477         for (i = 0; i <= 0x33; i++) {
 478                 len += sprintf(buf + len, "0x%02x: 0x%04x\n", i, adm_rreg(0, i));
 479         }
 480
 481         return len;
 482 }
 483
 484 static int handle_counters(void *driver, char *buf, int nr)
 485 {
 486         int i, len = 0;
 487
 488         for (i = 0; i <= 0x3c; i++) {
 489                 len += sprintf(buf + len, "0x%02x: 0x%08x\n", i, adm_rreg(1, i));
 490         }
 491
 492         return len;
 493 }
 494
 495 static int detect_adm(void)
 496 {
 497         int ret = 0;
 498
 499 #ifdef BROADCOM
 500         int boardflags = atoi(nvram_get("boardflags"));
 501         int boardnum = atoi(nvram_get("boardnum"));
 502
 503         if ((boardnum == 44) && (boardflags == 0x0388)) {  /* Trendware TEW-411BRP+ */
 504                 ret = 1;
 505
 506                 eecs = get_gpiopin("adm_eecs", 2);
 507                 eesk = get_gpiopin("adm_eesk", 3);
 508                 eedi = get_gpiopin("adm_eedi", 4);
 509                 eerc = get_gpiopin("adm_rc", 5);
 510
 511         } else if ((boardflags & 0x80) || force) {
 512                 ret = 1;
 513
 514                 eecs = get_gpiopin("adm_eecs", 2);
 515                 eesk = get_gpiopin("adm_eesk", 3);
 516                 eedi = get_gpiopin("adm_eedi", 4);
 517                 eerc = get_gpiopin("adm_rc", 0);
 518
 519         } else if ((strcmp(nvram_get("boardtype") ?: "", "bcm94710dev") == 0) &&
 520                         (strncmp(nvram_get("boardnum") ?: "", "42", 2) == 0)) {
 521                 /* WRT54G v1.1 hack */
 522                 eecs = 2;
 523                 eesk = 3;
 524                 eedi = 5;
 525
 526                 ret = 1;
 527         } else
 528                 printk("BFL_ENETADM not set in boardflags. Use force=1 to ignore.\n");
 529
 530         if (eecs)
 531                 eecs = (1 << eecs);
 532         if (eesk)
 533                 eesk = (1 << eesk);
 534         if (eedi)
 535                 eedi = (1 << eedi);
 536         if (eerc)
 537                 eerc = (1 << eerc);
 538 #else
 539         ret = 1;
 540 #endif
 541
 542         return ret;
 543 }
 544
 545 static int __init adm_init(void)
 546 {
 547         switch_config cfg[] = {
 548                 {"registers", handle_registers, NULL},
 549                 {"counters", handle_counters, NULL},
 550                 {"reset", NULL, handle_reset},
 551                 {"enable_vlan", handle_vlan_enable_read, handle_vlan_enable_write},
 552                 {NULL, NULL, NULL}
 553         };
 554         switch_config port[] = {
 555                 {"enable", handle_port_enable_read, handle_port_enable_write},
 556                 {"media", handle_port_media_read, handle_port_media_write},
 557                 {NULL, NULL, NULL}
 558         };
 559         switch_config vlan[] = {
 560                 {"ports", handle_vlan_port_read, handle_vlan_port_write},
 561                 {NULL, NULL, NULL}
 562         };
 563         switch_driver driver = {
 564                 name: DRIVER_NAME,
 565                 version: DRIVER_VERSION,
 566                 interface: "eth0",
 567                 ports: 6,
 568                 cpuport: 5,
 569                 vlans: 16,
 570                 driver_handlers: cfg,
 571                 port_handlers: port,
 572                 vlan_handlers: vlan,
 573         };
 574
 575         if (!detect_adm())
 576                 return -ENODEV;
 577
 578         return switch_register_driver(&driver);
 579 }
 580
 581 static void __exit adm_exit(void)
 582 {
 583         switch_unregister_driver(DRIVER_NAME);
 584 }
 585
 586
 587 module_init(adm_init);
 588 module_exit(adm_exit);