ramips: rt3883: add PCI support
[openwrt.git] / target / linux / ramips / files / arch / mips / pci / pci-rt3883.c
1 /*
2 * Ralink RT3883 SoC PCI support
3 *
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * Parts of this file are based on Ralink's 2.6.21 BSP
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 */
12
13 #include <linux/types.h>
14 #include <linux/pci.h>
15 #include <linux/io.h>
16 #include <linux/init.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19
20 #include <asm/mach-ralink/rt3883.h>
21 #include <asm/mach-ralink/rt3883_regs.h>
22
23 #define RT3883_MEMORY_BASE 0x00000000
24 #define RT3883_MEMORY_SIZE 0x02000000
25
26 #define RT3883_PCI_MEM_BASE 0x20000000
27 #define RT3883_PCI_MEM_SIZE 0x10000000
28 #define RT3883_PCI_IO_BASE 0x10160000
29 #define RT3883_PCI_IO_SIZE 0x00010000
30
31 #define RT3883_PCI_REG_PCICFG_ADDR 0x00
32 #define RT3883_PCI_REG_PCIRAW_ADDR 0x04
33 #define RT3883_PCI_REG_PCIINT_ADDR 0x08
34 #define RT3883_PCI_REG_PCIMSK_ADDR 0x0c
35 #define RT3833_PCI_PCIINT_PCIE BIT(20)
36 #define RT3833_PCI_PCIINT_PCI1 BIT(19)
37 #define RT3833_PCI_PCIINT_PCI0 BIT(18)
38
39 #define RT3883_PCI_REG_CONFIG_ADDR 0x20
40 #define RT3883_PCI_REG_CONFIG_DATA 0x24
41 #define RT3883_PCI_REG_MEMBASE 0x28
42 #define RT3883_PCI_REG_IOBASE 0x2c
43 #define RT3883_PCI_REG_ARBCTL 0x80
44
45 #define RT3883_PCI_REG_BASE(_x) (0x1000 + (_x) * 0x1000)
46 #define RT3883_PCI_REG_BAR0SETUP_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x10)
47 #define RT3883_PCI_REG_IMBASEBAR0_ADDR(_x) (RT3883_PCI_REG_BASE((_x)) + 0x18)
48 #define RT3883_PCI_REG_ID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x30)
49 #define RT3883_PCI_REG_CLASS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x34)
50 #define RT3883_PCI_REG_SUBID(_x) (RT3883_PCI_REG_BASE((_x)) + 0x38)
51 #define RT3883_PCI_REG_STATUS(_x) (RT3883_PCI_REG_BASE((_x)) + 0x50)
52
53 static int (*rt3883_pci_plat_dev_init)(struct pci_dev *dev);
54 static void __iomem *rt3883_pci_base;
55 static DEFINE_SPINLOCK(rt3883_pci_lock);
56
57 static inline u32 rt3883_pci_rr(unsigned reg)
58 {
59 return readl(rt3883_pci_base + reg);
60 }
61
62 static inline void rt3883_pci_wr(u32 val, unsigned reg)
63 {
64 writel(val, rt3883_pci_base + reg);
65 }
66
67 static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
68 unsigned int func, unsigned int where)
69 {
70 return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
71 0x80000000);
72 }
73
74 static u32 rt3883_pci_read_u32(unsigned bus, unsigned slot,
75 unsigned func, unsigned reg)
76 {
77 unsigned long flags;
78 u32 address;
79 u32 ret;
80
81 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
82
83 spin_lock_irqsave(&rt3883_pci_lock, flags);
84 rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
85 ret = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
86 spin_unlock_irqrestore(&rt3883_pci_lock, flags);
87
88 return ret;
89 }
90
91 static void rt3883_pci_write_u32(unsigned bus, unsigned slot,
92 unsigned func, unsigned reg, u32 val)
93 {
94 unsigned long flags;
95 u32 address;
96
97 address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
98
99 spin_lock_irqsave(&rt3883_pci_lock, flags);
100 rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
101 rt3883_pci_wr(val, RT3883_PCI_REG_CONFIG_DATA);
102 spin_unlock_irqrestore(&rt3883_pci_lock, flags);
103 }
104
105 static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
106 {
107 u32 pending;
108
109 pending = rt3883_pci_rr(RT3883_PCI_REG_PCIINT_ADDR) &
110 rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
111
112 if (!pending) {
113 spurious_interrupt();
114 return;
115 }
116
117 if (pending & RT3833_PCI_PCIINT_PCI0)
118 generic_handle_irq(RT3883_PCI_IRQ_PCI0);
119
120 if (pending & RT3833_PCI_PCIINT_PCI1)
121 generic_handle_irq(RT3883_PCI_IRQ_PCI1);
122
123 if (pending & RT3833_PCI_PCIINT_PCIE)
124 generic_handle_irq(RT3883_PCI_IRQ_PCIE);
125 }
126
127 static void rt3883_pci_irq_unmask(struct irq_data *d)
128 {
129 int irq = d->irq;
130 u32 mask;
131 u32 t;
132
133 switch (irq) {
134 case RT3883_PCI_IRQ_PCI0:
135 mask = RT3833_PCI_PCIINT_PCI0;
136 break;
137 case RT3883_PCI_IRQ_PCI1:
138 mask = RT3833_PCI_PCIINT_PCI1;
139 break;
140 case RT3883_PCI_IRQ_PCIE:
141 mask = RT3833_PCI_PCIINT_PCIE;
142 break;
143 default:
144 BUG();
145 }
146
147 t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
148 rt3883_pci_wr(t | mask, RT3883_PCI_REG_PCIMSK_ADDR);
149 /* flush write */
150 rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
151 }
152
153 static void rt3883_pci_irq_mask(struct irq_data *d)
154 {
155 int irq = d->irq;
156 u32 mask;
157 u32 t;
158
159 switch (irq) {
160 case RT3883_PCI_IRQ_PCI0:
161 mask = RT3833_PCI_PCIINT_PCI0;
162 break;
163 case RT3883_PCI_IRQ_PCI1:
164 mask = RT3833_PCI_PCIINT_PCI1;
165 break;
166 case RT3883_PCI_IRQ_PCIE:
167 mask = RT3833_PCI_PCIINT_PCIE;
168 break;
169 default:
170 BUG();
171 }
172
173 t = rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
174 rt3883_pci_wr(t & ~mask, RT3883_PCI_REG_PCIMSK_ADDR);
175 /* flush write */
176 rt3883_pci_rr(RT3883_PCI_REG_PCIMSK_ADDR);
177 }
178
179 static struct irq_chip rt3883_pci_irq_chip = {
180 .name = "RT3883 PCI",
181 .irq_mask = rt3883_pci_irq_mask,
182 .irq_unmask = rt3883_pci_irq_unmask,
183 .irq_mask_ack = rt3883_pci_irq_mask,
184 };
185
186 static void __init rt3883_pci_irq_init(void)
187 {
188 int i;
189
190 /* disable all interrupts */
191 rt3883_pci_wr(0, RT3883_PCI_REG_PCIMSK_ADDR);
192
193 for (i = RT3883_PCI_IRQ_BASE;
194 i < RT3883_PCI_IRQ_BASE + RT3883_PCI_IRQ_COUNT; i++) {
195 irq_set_chip_and_handler(i, &rt3883_pci_irq_chip,
196 handle_level_irq);
197 }
198
199 irq_set_chained_handler(RT3883_CPU_IRQ_PCI, rt3883_pci_irq_handler);
200 }
201
202 static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
203 int where, int size, u32 *val)
204 {
205 unsigned long flags;
206 u32 address;
207 u32 data;
208
209 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
210 PCI_FUNC(devfn), where);
211
212 spin_lock_irqsave(&rt3883_pci_lock, flags);
213 rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
214 data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
215 spin_unlock_irqrestore(&rt3883_pci_lock, flags);
216
217 switch (size) {
218 case 1:
219 *val = (data >> ((where & 3) << 3)) & 0xff;
220 break;
221 case 2:
222 *val = (data >> ((where & 3) << 3)) & 0xffff;
223 break;
224 case 4:
225 *val = data;
226 break;
227 }
228
229 return PCIBIOS_SUCCESSFUL;
230 }
231
232 static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
233 int where, int size, u32 val)
234 {
235 unsigned long flags;
236 u32 address;
237 u32 data;
238
239 address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
240 PCI_FUNC(devfn), where);
241
242 spin_lock_irqsave(&rt3883_pci_lock, flags);
243 rt3883_pci_wr(address, RT3883_PCI_REG_CONFIG_ADDR);
244 data = rt3883_pci_rr(RT3883_PCI_REG_CONFIG_DATA);
245
246 switch (size) {
247 case 1:
248 data = (data & ~(0xff << ((where & 3) << 3))) |
249 (val << ((where & 3) << 3));
250 break;
251 case 2:
252 data = (data & ~(0xffff << ((where & 3) << 3))) |
253 (val << ((where & 3) << 3));
254 break;
255 case 4:
256 data = val;
257 break;
258 }
259
260 rt3883_pci_wr(data, RT3883_PCI_REG_CONFIG_DATA);
261 spin_unlock_irqrestore(&rt3883_pci_lock, flags);
262
263 return PCIBIOS_SUCCESSFUL;
264 }
265
266 static struct pci_ops rt3883_pci_ops = {
267 .read = rt3883_pci_config_read,
268 .write = rt3883_pci_config_write,
269 };
270
271 static struct resource rt3883_pci_mem_resource = {
272 .name = "PCI MEM space",
273 .start = RT3883_PCI_MEM_BASE,
274 .end = RT3883_PCI_MEM_BASE + RT3883_PCI_MEM_SIZE - 1,
275 .flags = IORESOURCE_MEM,
276 };
277
278 static struct resource rt3883_pci_io_resource = {
279 .name = "PCI IO space",
280 .start = RT3883_PCI_IO_BASE,
281 .end = RT3883_PCI_IO_BASE + RT3883_PCI_IO_SIZE - 1,
282 .flags = IORESOURCE_IO,
283 };
284
285 static struct pci_controller rt3883_pci_controller = {
286 .pci_ops = &rt3883_pci_ops,
287 .mem_resource = &rt3883_pci_mem_resource,
288 .io_resource = &rt3883_pci_io_resource,
289 };
290
291 static void rt3883_pci_preinit(unsigned mode)
292 {
293 u32 syscfg1;
294 u32 rstctrl;
295 u32 clkcfg1;
296
297 if (mode & RT3883_PCI_MODE_PCIE) {
298 u32 val;
299
300 val = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
301 val &= ~(0x30);
302 val |= (2 << 4);
303 rt3883_sysc_wr(val, RT3883_SYSC_REG_SYSCFG1);
304
305 val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
306 val &= ~BIT(31);
307 rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
308
309 val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
310 val &= 0x80ffffff;
311 rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
312
313 val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN1);
314 val |= 0xa << 24;
315 rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN1);
316
317 val = rt3883_sysc_rr(RT3883_SYSC_REG_PCIE_CLK_GEN0);
318 val |= BIT(31);
319 rt3883_sysc_wr(val, RT3883_SYSC_REG_PCIE_CLK_GEN0);
320
321 msleep(50);
322 }
323
324 syscfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_SYSCFG1);
325 syscfg1 &= ~(RT3883_SYSCFG1_PCIE_RC_MODE |
326 RT3883_SYSCFG1_PCI_HOST_MODE);
327
328 rstctrl = rt3883_sysc_rr(RT3883_SYSC_REG_RSTCTRL);
329 rstctrl |= (RT3883_RSTCTRL_PCI | RT3883_RSTCTRL_PCIE);
330
331 clkcfg1 = rt3883_sysc_rr(RT3883_SYSC_REG_CLKCFG1);
332 clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN |
333 RT3883_CLKCFG1_PCIE_CLK_EN);
334
335 if (mode & RT3883_PCI_MODE_PCI) {
336 syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE;
337 clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
338 rstctrl &= ~RT3883_RSTCTRL_PCI;
339 }
340 if (mode & RT3883_PCI_MODE_PCIE) {
341 syscfg1 |= RT3883_SYSCFG1_PCI_HOST_MODE |
342 RT3883_SYSCFG1_PCIE_RC_MODE;
343 clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
344 rstctrl &= ~RT3883_RSTCTRL_PCIE;
345 }
346
347 rt3883_sysc_wr(syscfg1, RT3883_SYSC_REG_SYSCFG1);
348 rt3883_sysc_wr(rstctrl, RT3883_SYSC_REG_RSTCTRL);
349 rt3883_sysc_wr(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
350
351 msleep(500);
352 }
353
354 static int rt3883_pcie_ready(void)
355 {
356 u32 status;
357
358 msleep(500);
359
360 status = rt3883_pci_rr(RT3883_PCI_REG_STATUS(1));
361 if (status & BIT(0))
362 return 0;
363
364 /* TODO: reset PCIe and turn off PCIe clock */
365
366 return -ENODEV;
367 }
368
369 void __init rt3883_pci_init(unsigned mode)
370 {
371 u32 val;
372 int err;
373
374 rt3883_pci_preinit(mode);
375
376 rt3883_pci_base = ioremap(RT3883_PCI_BASE, PAGE_SIZE);
377 if (rt3883_pci_base == NULL) {
378 pr_err("failed to ioremap PCI registers\n");
379 return;
380 }
381
382 rt3883_pci_wr(0, RT3883_PCI_REG_PCICFG_ADDR);
383 if (mode & RT3883_PCI_MODE_PCI)
384 rt3883_pci_wr(BIT(16), RT3883_PCI_REG_PCICFG_ADDR);
385
386 msleep(500);
387
388 if (mode & RT3883_PCI_MODE_PCIE) {
389 err = rt3883_pcie_ready();
390 if (err)
391 return;
392 }
393
394 if (mode & RT3883_PCI_MODE_PCI)
395 rt3883_pci_wr(0x79, RT3883_PCI_REG_ARBCTL);
396
397 rt3883_pci_wr(RT3883_PCI_MEM_BASE, RT3883_PCI_REG_MEMBASE);
398 rt3883_pci_wr(RT3883_PCI_IO_BASE, RT3883_PCI_REG_IOBASE);
399
400 /* PCI */
401 rt3883_pci_wr(0x03ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(0));
402 rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(0));
403 rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(0));
404 rt3883_pci_wr(0x00800001, RT3883_PCI_REG_CLASS(0));
405 rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(0));
406
407 /* PCIe */
408 rt3883_pci_wr(0x01ff0000, RT3883_PCI_REG_BAR0SETUP_ADDR(1));
409 rt3883_pci_wr(RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0_ADDR(1));
410 rt3883_pci_wr(0x08021814, RT3883_PCI_REG_ID(1));
411 rt3883_pci_wr(0x06040001, RT3883_PCI_REG_CLASS(1));
412 rt3883_pci_wr(0x28801814, RT3883_PCI_REG_SUBID(1));
413
414 rt3883_pci_irq_init();
415
416 /* PCIe */
417 val = rt3883_pci_read_u32(0, 0x01, 0, PCI_COMMAND);
418 val |= 0x7;
419 rt3883_pci_write_u32(0, 0x01, 0, PCI_COMMAND, val);
420
421 /* PCI */
422 val = rt3883_pci_read_u32(0, 0x00, 0, PCI_COMMAND);
423 val |= 0x7;
424 rt3883_pci_write_u32(0, 0x00, 0, PCI_COMMAND, val);
425
426 ioport_resource.start = rt3883_pci_io_resource.start;
427 ioport_resource.end = rt3883_pci_io_resource.end;
428
429 register_pci_controller(&rt3883_pci_controller);
430 }
431
432 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
433 {
434 int irq = -1;
435
436 switch (dev->bus->number) {
437 case 0:
438 switch (PCI_SLOT(dev->devfn)) {
439 case 0x00:
440 rt3883_pci_wr(0x03ff0001,
441 RT3883_PCI_REG_BAR0SETUP_ADDR(0));
442 rt3883_pci_wr(0x03ff0001,
443 RT3883_PCI_REG_BAR0SETUP_ADDR(1));
444
445 rt3883_pci_write_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0,
446 RT3883_MEMORY_BASE);
447 rt3883_pci_read_u32(0, 0x00, 0, PCI_BASE_ADDRESS_0);
448
449 irq = RT3883_CPU_IRQ_PCI;
450 break;
451 case 0x01:
452 rt3883_pci_write_u32(0, 0x01, 0, PCI_IO_BASE,
453 0x00000101);
454 break;
455 case 0x11:
456 irq = RT3883_PCI_IRQ_PCI0;
457 break;
458 case 0x12:
459 irq = RT3883_PCI_IRQ_PCI1;
460 break;
461 }
462 break;
463
464 case 1:
465 irq = RT3883_PCI_IRQ_PCIE;
466 break;
467
468 default:
469 dev_err(&dev->dev, "no IRQ specified\n");
470 return irq;
471 }
472
473 return irq;
474 }
475
476 void __init rt3883_pci_set_plat_dev_init(int (*f)(struct pci_dev *dev))
477 {
478 rt3883_pci_plat_dev_init = f;
479 }
480
481 int pcibios_plat_dev_init(struct pci_dev *dev)
482 {
483 if (rt3883_pci_plat_dev_init)
484 return rt3883_pci_plat_dev_init(dev);
485
486 return 0;
487 }
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