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[package] mac80211: update compat-wireless to 2009-01-29
[openwrt.git] / package / mac80211 / patches / 302-rt2x00-Implement-support-for-rt2800pci.patch
1 From 659988a6bb83536c5d0a01b0b58378cc1856c975 Mon Sep 17 00:00:00 2001
2 From: Ivo van Doorn <IvDoorn@gmail.com>
3 Date: Fri, 23 Jan 2009 17:13:03 +0100
4 Subject: [PATCH] rt2x00: Implement support for rt2800pci
5
6 Add support for the rt2800pci chipset.
7
8 Includes various patches from Mattias, Mark and Felix.
9
10 Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de>
11 Signed-off-by: Mark Asselstine <asselsm@gmail.com>
12 Signed-off-by: Felix Fietkau <nbd@openwrt.org>
13 Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com>
14 ---
15 drivers/net/wireless/rt2x00/Kconfig | 15 +
16 drivers/net/wireless/rt2x00/Makefile | 1 +
17 drivers/net/wireless/rt2x00/rt2800pci.c | 2763 +++++++++++++++++++++++++++++++
18 drivers/net/wireless/rt2x00/rt2800pci.h | 1881 +++++++++++++++++++++
19 drivers/net/wireless/rt2x00/rt2x00.h | 4 +
20 5 files changed, 4664 insertions(+), 0 deletions(-)
21 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.c
22 create mode 100644 drivers/net/wireless/rt2x00/rt2800pci.h
23
24 --- a/drivers/net/wireless/rt2x00/Makefile
25 +++ b/drivers/net/wireless/rt2x00/Makefile
26 @@ -16,5 +16,6 @@ obj-$(CONFIG_RT2X00_LIB_USB) += rt2x00u
27 obj-$(CONFIG_RT2400PCI) += rt2400pci.o
28 obj-$(CONFIG_RT2500PCI) += rt2500pci.o
29 obj-$(CONFIG_RT61PCI) += rt61pci.o
30 +obj-$(CONFIG_RT2800PCI) += rt2800pci.o
31 obj-$(CONFIG_RT2500USB) += rt2500usb.o
32 obj-$(CONFIG_RT73USB) += rt73usb.o
33 --- /dev/null
34 +++ b/drivers/net/wireless/rt2x00/rt2800pci.c
35 @@ -0,0 +1,2763 @@
36 +/*
37 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
38 + <http://rt2x00.serialmonkey.com>
39 +
40 + This program is free software; you can redistribute it and/or modify
41 + it under the terms of the GNU General Public License as published by
42 + the Free Software Foundation; either version 2 of the License, or
43 + (at your option) any later version.
44 +
45 + This program is distributed in the hope that it will be useful,
46 + but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 + GNU General Public License for more details.
49 +
50 + You should have received a copy of the GNU General Public License
51 + along with this program; if not, write to the
52 + Free Software Foundation, Inc.,
53 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
54 + */
55 +
56 +/*
57 + Module: rt2800pci
58 + Abstract: rt2800pci device specific routines.
59 + Supported chipsets: RT2800E & RT2800ED.
60 + */
61 +
62 +#include <linux/crc-ccitt.h>
63 +#include <linux/delay.h>
64 +#include <linux/etherdevice.h>
65 +#include <linux/init.h>
66 +#include <linux/kernel.h>
67 +#include <linux/module.h>
68 +#include <linux/pci.h>
69 +#include <linux/eeprom_93cx6.h>
70 +
71 +#include "rt2x00.h"
72 +#include "rt2x00pci.h"
73 +#include "rt2800pci.h"
74 +
75 +/*
76 + * Allow hardware encryption to be disabled.
77 + */
78 +static int modparam_nohwcrypt = 0;
79 +module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
80 +MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
81 +
82 +/*
83 + * Register access.
84 + * BBP and RF register require indirect register access,
85 + * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
86 + * These indirect registers work with busy bits,
87 + * and we will try maximal REGISTER_BUSY_COUNT times to access
88 + * the register while taking a REGISTER_BUSY_DELAY us delay
89 + * between each attampt. When the busy bit is still set at that time,
90 + * the access attempt is considered to have failed,
91 + * and we will print an error.
92 + */
93 +#define WAIT_FOR_BBP(__dev, __reg) \
94 + rt2x00pci_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
95 +#define WAIT_FOR_RF(__dev, __reg) \
96 + rt2x00pci_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
97 +#define WAIT_FOR_MCU(__dev, __reg) \
98 + rt2x00pci_regbusy_read((__dev), H2M_MAILBOX_CSR, \
99 + H2M_MAILBOX_CSR_OWNER, (__reg))
100 +
101 +static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
102 + const unsigned int word, const u8 value)
103 +{
104 + u32 reg;
105 +
106 + mutex_lock(&rt2x00dev->csr_mutex);
107 +
108 + /*
109 + * Wait until the BBP becomes available, afterwards we
110 + * can safely write the new data into the register.
111 + */
112 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
113 + reg = 0;
114 + rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
115 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
116 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
117 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
118 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
119 +
120 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
121 + }
122 +
123 + mutex_unlock(&rt2x00dev->csr_mutex);
124 +}
125 +
126 +static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
127 + const unsigned int word, u8 *value)
128 +{
129 + u32 reg;
130 +
131 + mutex_lock(&rt2x00dev->csr_mutex);
132 +
133 + /*
134 + * Wait until the BBP becomes available, afterwards we
135 + * can safely write the read request into the register.
136 + * After the data has been written, we wait until hardware
137 + * returns the correct value, if at any time the register
138 + * doesn't become available in time, reg will be 0xffffffff
139 + * which means we return 0xff to the caller.
140 + */
141 + if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
142 + reg = 0;
143 + rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
144 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
145 + rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
146 + rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
147 +
148 + rt2x00pci_register_write(rt2x00dev, BBP_CSR_CFG, reg);
149 +
150 + WAIT_FOR_BBP(rt2x00dev, &reg);
151 + }
152 +
153 + *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
154 +
155 + mutex_unlock(&rt2x00dev->csr_mutex);
156 +}
157 +
158 +static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
159 + const unsigned int word, const u32 value)
160 +{
161 + u32 reg;
162 +
163 + if (!word)
164 + return;
165 +
166 + mutex_lock(&rt2x00dev->csr_mutex);
167 +
168 + /*
169 + * Wait until the RF becomes available, afterwards we
170 + * can safely write the new data into the register.
171 + */
172 + if (WAIT_FOR_RF(rt2x00dev, &reg)) {
173 + reg = 0;
174 + rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
175 + rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
176 + rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
177 + rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
178 +
179 + rt2x00pci_register_write(rt2x00dev, RF_CSR_CFG0, reg);
180 + rt2x00_rf_write(rt2x00dev, word, value);
181 + }
182 +
183 + mutex_unlock(&rt2x00dev->csr_mutex);
184 +}
185 +
186 +static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
187 + const u8 command, const u8 token,
188 + const u8 arg0, const u8 arg1)
189 +{
190 + u32 reg;
191 +
192 + mutex_lock(&rt2x00dev->csr_mutex);
193 +
194 + /*
195 + * Wait until the MCU becomes available, afterwards we
196 + * can safely write the new data into the register.
197 + */
198 + if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
199 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
200 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
201 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
202 + rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
203 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
204 +
205 + reg = 0;
206 + rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
207 + rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
208 + }
209 +
210 + mutex_unlock(&rt2x00dev->csr_mutex);
211 +}
212 +
213 +static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
214 +{
215 + struct rt2x00_dev *rt2x00dev = eeprom->data;
216 + u32 reg;
217 +
218 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
219 +
220 + eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
221 + eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
222 + eeprom->reg_data_clock =
223 + !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
224 + eeprom->reg_chip_select =
225 + !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
226 +}
227 +
228 +static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
229 +{
230 + struct rt2x00_dev *rt2x00dev = eeprom->data;
231 + u32 reg = 0;
232 +
233 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
234 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
235 + rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
236 + !!eeprom->reg_data_clock);
237 + rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
238 + !!eeprom->reg_chip_select);
239 +
240 + rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
241 +}
242 +
243 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
244 +static const struct rt2x00debug rt2800pci_rt2x00debug = {
245 + .owner = THIS_MODULE,
246 + .csr = {
247 + .read = rt2x00pci_register_read,
248 + .write = rt2x00pci_register_write,
249 + .flags = RT2X00DEBUGFS_OFFSET,
250 + .word_base = CSR_REG_BASE,
251 + .word_size = sizeof(u32),
252 + .word_count = CSR_REG_SIZE / sizeof(u32),
253 + },
254 + .eeprom = {
255 + .read = rt2x00_eeprom_read,
256 + .write = rt2x00_eeprom_write,
257 + .word_base = EEPROM_BASE,
258 + .word_size = sizeof(u16),
259 + .word_count = EEPROM_SIZE / sizeof(u16),
260 + },
261 + .bbp = {
262 + .read = rt2800pci_bbp_read,
263 + .write = rt2800pci_bbp_write,
264 + .word_base = BBP_BASE,
265 + .word_size = sizeof(u8),
266 + .word_count = BBP_SIZE / sizeof(u8),
267 + },
268 + .rf = {
269 + .read = rt2x00_rf_read,
270 + .write = rt2800pci_rf_write,
271 + .word_base = RF_BASE,
272 + .word_size = sizeof(u32),
273 + .word_count = RF_SIZE / sizeof(u32),
274 + },
275 +};
276 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
277 +
278 +#ifdef CONFIG_RT2X00_LIB_RFKILL
279 +static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
280 +{
281 + u32 reg;
282 +
283 + rt2x00pci_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
284 + return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
285 +}
286 +#else
287 +#define rt2800pci_rfkill_poll NULL
288 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
289 +
290 +#ifdef CONFIG_RT2X00_LIB_LEDS
291 +static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
292 + enum led_brightness brightness)
293 +{
294 + struct rt2x00_led *led =
295 + container_of(led_cdev, struct rt2x00_led, led_dev);
296 + unsigned int enabled = brightness != LED_OFF;
297 + unsigned int bg_mode =
298 + (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
299 + unsigned int polarity =
300 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
301 + EEPROM_FREQ_LED_POLARITY);
302 + unsigned int ledmode =
303 + rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
304 + EEPROM_FREQ_LED_MODE);
305 +
306 + if (led->type == LED_TYPE_RADIO) {
307 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
308 + enabled ? 0x20 : 0);
309 + } else if (led->type == LED_TYPE_ASSOC) {
310 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
311 + enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
312 + } else if (led->type == LED_TYPE_QUALITY) {
313 + /*
314 + * The brightness is divided into 6 levels (0 - 5),
315 + * The specs tell us the following levels:
316 + * 0, 1 ,3, 7, 15, 31
317 + * to determine the level in a simple way we can simply
318 + * work with bitshifting:
319 + * (1 << level) - 1
320 + */
321 + rt2800pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
322 + (1 << brightness / (LED_FULL / 6)) - 1,
323 + polarity);
324 + }
325 +}
326 +
327 +static int rt2800pci_blink_set(struct led_classdev *led_cdev,
328 + unsigned long *delay_on,
329 + unsigned long *delay_off)
330 +{
331 + struct rt2x00_led *led =
332 + container_of(led_cdev, struct rt2x00_led, led_dev);
333 + u32 reg;
334 +
335 + rt2x00pci_register_read(led->rt2x00dev, LED_CFG, &reg);
336 + rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
337 + rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
338 + rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
339 + rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
340 + rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
341 + rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
342 + rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
343 + rt2x00pci_register_write(led->rt2x00dev, LED_CFG, reg);
344 +
345 + return 0;
346 +}
347 +
348 +static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
349 + struct rt2x00_led *led,
350 + enum led_type type)
351 +{
352 + led->rt2x00dev = rt2x00dev;
353 + led->type = type;
354 + led->led_dev.brightness_set = rt2800pci_brightness_set;
355 + led->led_dev.blink_set = rt2800pci_blink_set;
356 + led->flags = LED_INITIALIZED;
357 +}
358 +#endif /* CONFIG_RT2X00_LIB_LEDS */
359 +
360 +/*
361 + * Configuration handlers.
362 + */
363 +static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
364 + struct rt2x00lib_crypto *crypto,
365 + struct ieee80211_key_conf *key)
366 +{
367 + u32 offset;
368 + u32 reg;
369 +
370 + offset = MAC_WCID_ATTR_ENTRY(crypto->aid);
371 +
372 + reg = 0;
373 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
374 + !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
375 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_PAIRKEY_MODE,
376 + crypto->cipher);
377 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
378 + (crypto->cmd == SET_KEY) ? crypto->bssidx : 0);
379 + rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
380 + rt2x00pci_register_write(rt2x00dev, offset, reg);
381 +}
382 +
383 +static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
384 + struct rt2x00lib_crypto *crypto,
385 + struct ieee80211_key_conf *key)
386 +{
387 + struct hw_key_entry key_entry;
388 + struct rt2x00_field32 field;
389 + u32 offset;
390 + u32 mask;
391 + u32 reg;
392 +
393 + if (crypto->cmd == SET_KEY) {
394 + memcpy(key_entry.key, crypto->key,
395 + sizeof(key_entry.key));
396 + memcpy(key_entry.tx_mic, crypto->tx_mic,
397 + sizeof(key_entry.tx_mic));
398 + memcpy(key_entry.rx_mic, crypto->rx_mic,
399 + sizeof(key_entry.rx_mic));
400 +
401 + offset = SHARED_KEY_ENTRY(key->hw_key_idx);
402 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
403 + &key_entry, sizeof(key_entry));
404 +
405 + /*
406 + * The driver does not support the IV/EIV generation
407 + * in hardware. However it doesn't support the IV/EIV
408 + * inside the ieee80211 frame either, but requires it
409 + * to be provided seperately for the descriptor.
410 + * rt2x00lib will cut the IV/EIV data out of all frames
411 + * given to us by mac80211, but we must tell mac80211
412 + * to generate the IV/EIV data.
413 + */
414 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
415 + }
416 +
417 + /*
418 + * The cipher types are stored over multiple registers
419 + * starting with SHARED_KEY_MODE_BASE each word will have
420 + * 32 bits and contains the cipher types for 2 modes each.
421 + * Using the correct defines correctly will cause overhead,
422 + * so just calculate the correct offset.
423 + */
424 + mask = key->hw_key_idx % 8;
425 + field.bit_offset = (3 * mask);
426 + field.bit_mask = 0x7 << field.bit_offset;
427 +
428 + offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
429 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
430 + rt2x00_set_field32(&reg, field,
431 + (crypto->cmd == SET_KEY) ? crypto->cipher : 0);
432 + rt2x00pci_register_write(rt2x00dev, offset, reg);
433 +
434 + /*
435 + * Update WCID information
436 + */
437 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
438 +
439 + return 0;
440 +}
441 +
442 +static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
443 + struct rt2x00lib_crypto *crypto,
444 + struct ieee80211_key_conf *key)
445 +{
446 + struct hw_key_entry key_entry;
447 + u32 offset;
448 +
449 + /*
450 + * 1 pairwise key is possible per AID, this means that the AID
451 + * equals our hw_key_idx.
452 + */
453 + key->hw_key_idx = crypto->aid;
454 +
455 + if (crypto->cmd == SET_KEY) {
456 + memcpy(key_entry.key, crypto->key,
457 + sizeof(key_entry.key));
458 + memcpy(key_entry.tx_mic, crypto->tx_mic,
459 + sizeof(key_entry.tx_mic));
460 + memcpy(key_entry.rx_mic, crypto->rx_mic,
461 + sizeof(key_entry.rx_mic));
462 +
463 + offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
464 + rt2x00pci_register_multiwrite(rt2x00dev, offset,
465 + &key_entry, sizeof(key_entry));
466 +
467 + /*
468 + * The driver does not support the IV/EIV generation
469 + * in hardware. However it doesn't support the IV/EIV
470 + * inside the ieee80211 frame either, but requires it
471 + * to be provided seperately for the descriptor.
472 + * rt2x00lib will cut the IV/EIV data out of all frames
473 + * given to us by mac80211, but we must tell mac80211
474 + * to generate the IV/EIV data.
475 + */
476 + key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
477 + }
478 +
479 + /*
480 + * Update WCID information
481 + */
482 + rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
483 +
484 + return 0;
485 +}
486 +
487 +static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
488 + const unsigned int filter_flags)
489 +{
490 + u32 reg;
491 +
492 + /*
493 + * Start configuration steps.
494 + * Note that the version error will always be dropped
495 + * and broadcast frames will always be accepted since
496 + * there is no filter for it at this time.
497 + */
498 + rt2x00pci_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
499 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
500 + !(filter_flags & FIF_FCSFAIL));
501 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
502 + !(filter_flags & FIF_PLCPFAIL));
503 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
504 + !(filter_flags & FIF_PROMISC_IN_BSS));
505 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
506 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
507 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
508 + !(filter_flags & FIF_ALLMULTI));
509 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
510 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
511 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
512 + !(filter_flags & FIF_CONTROL));
513 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
514 + !(filter_flags & FIF_CONTROL));
515 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
516 + !(filter_flags & FIF_CONTROL));
517 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
518 + !(filter_flags & FIF_CONTROL));
519 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
520 + !(filter_flags & FIF_CONTROL));
521 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
522 + !(filter_flags & FIF_CONTROL));
523 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
524 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 1);
525 + rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
526 + !(filter_flags & FIF_CONTROL));
527 + rt2x00pci_register_write(rt2x00dev, RX_FILTER_CFG, reg);
528 +}
529 +
530 +static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
531 + struct rt2x00_intf *intf,
532 + struct rt2x00intf_conf *conf,
533 + const unsigned int flags)
534 +{
535 + unsigned int beacon_base;
536 + u32 reg;
537 +
538 + if (flags & CONFIG_UPDATE_TYPE) {
539 + /*
540 + * Clear current synchronisation setup.
541 + * For the Beacon base registers we only need to clear
542 + * the first byte since that byte contains the VALID and OWNER
543 + * bits which (when set to 0) will invalidate the entire beacon.
544 + */
545 + beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
546 + rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
547 +
548 + /*
549 + * Enable synchronisation.
550 + */
551 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
552 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
553 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
554 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
555 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
556 + }
557 +
558 + if (flags & CONFIG_UPDATE_MAC) {
559 + reg = le32_to_cpu(conf->mac[1]);
560 + rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
561 + conf->mac[1] = cpu_to_le32(reg);
562 +
563 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
564 + conf->mac, sizeof(conf->mac));
565 + }
566 +
567 + if (flags & CONFIG_UPDATE_BSSID) {
568 + reg = le32_to_cpu(conf->bssid[1]);
569 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
570 + rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
571 + conf->bssid[1] = cpu_to_le32(reg);
572 +
573 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
574 + conf->bssid, sizeof(conf->bssid));
575 + }
576 +}
577 +
578 +static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
579 + struct rt2x00lib_erp *erp)
580 +{
581 + u32 reg;
582 +
583 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
584 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT,
585 + erp->ack_timeout);
586 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
587 +
588 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
589 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
590 + !!erp->short_preamble);
591 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
592 + !!erp->short_preamble);
593 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
594 +
595 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
596 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
597 + erp->cts_protection ? 2 : 0);
598 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
599 +
600 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE,
601 + erp->basic_rates);
602 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE,
603 + erp->basic_rates >> 32);
604 +
605 + rt2x00pci_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
606 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
607 + rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
608 + rt2x00pci_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
609 +
610 + rt2x00pci_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
611 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
612 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
613 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
614 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
615 + rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
616 + rt2x00pci_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
617 +}
618 +
619 +static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
620 + struct antenna_setup *ant)
621 +{
622 + u16 eeprom;
623 + u8 r1;
624 + u8 r3;
625 +
626 + /*
627 + * FIXME: Use requested antenna configuration.
628 + */
629 +
630 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
631 +
632 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
633 + rt2800pci_bbp_read(rt2x00dev, 3, &r3);
634 +
635 + /*
636 + * Configure the TX antenna.
637 + */
638 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH)) {
639 + case 1:
640 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
641 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
642 + break;
643 + case 2:
644 + rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 16);
645 + break;
646 + case 3:
647 + /* Do nothing */
648 + break;
649 + }
650 +
651 + /*
652 + * Configure the RX antenna.
653 + */
654 + switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
655 + case 1:
656 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
657 + break;
658 + case 2:
659 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
660 + break;
661 + case 3:
662 + rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
663 + break;
664 + }
665 +
666 + rt2800pci_bbp_write(rt2x00dev, 3, r3);
667 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
668 +}
669 +
670 +static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
671 + struct rt2x00lib_conf *libconf)
672 +{
673 + u16 eeprom;
674 + short lna_gain;
675 +
676 + if (libconf->rf.channel <= 14) {
677 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
678 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
679 + } else if (libconf->rf.channel <= 64) {
680 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
681 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
682 + } else if (libconf->rf.channel <= 128) {
683 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
684 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
685 + } else {
686 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
687 + lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
688 + }
689 +
690 + rt2x00dev->lna_gain = lna_gain;
691 +}
692 +
693 +static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
694 + struct rf_channel *rf,
695 + struct channel_info *info)
696 +{
697 + u32 reg;
698 + unsigned int tx_pin;
699 + u16 eeprom;
700 +
701 + tx_pin = 0;
702 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
703 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
704 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
705 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
706 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
707 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
708 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
709 +
710 + rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
711 +
712 + /*
713 + * Determine antenna settings from EEPROM
714 + */
715 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
716 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) == 1) {
717 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
718 + /* Turn off unused PA or LNA when only 1T or 1R */
719 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 0);
720 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 0);
721 + }
722 +
723 + if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 1) {
724 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
725 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
726 + /* Turn off unused PA or LNA when only 1T or 1R */
727 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 0);
728 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 0);
729 + } else if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH) == 2)
730 + rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
731 +
732 + if (rf->channel > 14) {
733 + /*
734 + * When TX power is below 0, we should increase it by 7 to
735 + * make it a positive value (Minumum value is -7).
736 + * However this means that values between 0 and 7 have
737 + * double meaning, and we should set a 7DBm boost flag.
738 + */
739 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
740 + (info->tx_power1 >= 0));
741 +
742 + if (info->tx_power1 < 0)
743 + info->tx_power1 += 7;
744 +
745 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
746 + TXPOWER_A_TO_DEV(info->tx_power1));
747 +
748 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
749 + (info->tx_power2 >= 0));
750 +
751 + if (info->tx_power2 < 0)
752 + info->tx_power2 += 7;
753 +
754 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
755 + TXPOWER_A_TO_DEV(info->tx_power2));
756 +
757 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
758 + } else {
759 + rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
760 + TXPOWER_G_TO_DEV(info->tx_power1));
761 + rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
762 + TXPOWER_G_TO_DEV(info->tx_power2));
763 +
764 + rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
765 + }
766 +
767 + rt2x00_set_field32(&rf->rf4, RF4_BW40,
768 + test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
769 +
770 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
771 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
772 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
773 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
774 +
775 + udelay(200);
776 +
777 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
778 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
779 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
780 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
781 +
782 + udelay(200);
783 +
784 + rt2800pci_rf_write(rt2x00dev, 1, rf->rf1);
785 + rt2800pci_rf_write(rt2x00dev, 2, rf->rf2);
786 + rt2800pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
787 + rt2800pci_rf_write(rt2x00dev, 4, rf->rf4);
788 +
789 + /*
790 + * Change BBP settings
791 + */
792 + rt2800pci_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
793 + rt2800pci_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
794 + rt2800pci_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
795 + rt2800pci_bbp_write(rt2x00dev, 86, 0);
796 +
797 + if (rf->channel <= 14) {
798 + if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
799 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
800 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
801 + } else {
802 + rt2800pci_bbp_write(rt2x00dev, 82, 0x84);
803 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
804 + }
805 +
806 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
807 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 0);
808 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 1);
809 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
810 + } else {
811 + rt2800pci_bbp_write(rt2x00dev, 82, 0xf2);
812 +
813 + if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
814 + rt2800pci_bbp_write(rt2x00dev, 75, 0x46);
815 + else
816 + rt2800pci_bbp_write(rt2x00dev, 75, 0x50);
817 +
818 + rt2x00pci_register_read(rt2x00dev, TX_BAND_CFG, &reg);
819 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_A, 1);
820 + rt2x00_set_field32(&rf->rf3, TX_BAND_CFG_BG, 0);
821 + rt2x00pci_register_write(rt2x00dev, TX_BAND_CFG, reg);
822 + }
823 +
824 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
825 +
826 + msleep(1);
827 +}
828 +
829 +static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
830 + const int txpower)
831 +{
832 + u32 reg;
833 + u32 value = TXPOWER_G_TO_DEV(txpower);
834 + u8 r1;
835 +
836 + rt2800pci_bbp_read(rt2x00dev, 1, &r1);
837 + rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
838 + rt2800pci_bbp_write(rt2x00dev, 1, r1);
839 +
840 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
841 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
842 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
843 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
844 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
845 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
846 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
847 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
848 + rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
849 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
850 +
851 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
852 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
853 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
854 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
855 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
856 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
857 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
858 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
859 + rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
860 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
861 +
862 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
863 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
864 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
865 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
866 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
867 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
868 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
869 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
870 + rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
871 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
872 +
873 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
874 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
875 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
876 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
877 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
878 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
879 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
880 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
881 + rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
882 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
883 +
884 + rt2x00pci_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
885 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
886 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
887 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
888 + rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
889 + rt2x00pci_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
890 +}
891 +
892 +static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
893 + struct rt2x00lib_conf *libconf)
894 +{
895 + u32 reg;
896 +
897 + rt2x00pci_register_read(rt2x00dev, TX_RTY_CFG, &reg);
898 + rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
899 + libconf->conf->short_frame_max_tx_count);
900 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
901 + libconf->conf->long_frame_max_tx_count);
902 + rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
903 + rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
904 + rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
905 + rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
906 + rt2x00pci_register_write(rt2x00dev, TX_RTY_CFG, reg);
907 +}
908 +
909 +static void rt2800pci_config_duration(struct rt2x00_dev *rt2x00dev,
910 + struct rt2x00lib_conf *libconf)
911 +{
912 + u32 reg;
913 +
914 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
915 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
916 + libconf->conf->beacon_int * 16);
917 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
918 +}
919 +
920 +static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
921 + struct rt2x00lib_conf *libconf)
922 +{
923 + enum dev_state state =
924 + (libconf->conf->flags & IEEE80211_CONF_PS) ?
925 + STATE_SLEEP : STATE_AWAKE;
926 + u32 reg;
927 +
928 + if (state == STATE_SLEEP) {
929 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
930 +
931 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
932 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
933 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
934 + libconf->conf->listen_interval - 1);
935 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
936 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
937 +
938 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0);
939 + } else {
940 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
941 +
942 + rt2x00pci_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
943 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
944 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
945 + rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
946 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
947 + }
948 +}
949 +
950 +static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
951 + struct rt2x00lib_conf *libconf,
952 + const unsigned int flags)
953 +{
954 + /* Always recalculate LNA gain before changing configuration */
955 + rt2800pci_config_lna_gain(rt2x00dev, libconf);
956 +
957 + if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
958 + rt2800pci_config_channel(rt2x00dev, &libconf->rf,
959 + &libconf->channel);
960 + if (flags & IEEE80211_CONF_CHANGE_POWER)
961 + rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
962 + if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
963 + rt2800pci_config_retry_limit(rt2x00dev, libconf);
964 + if (flags & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
965 + rt2800pci_config_duration(rt2x00dev, libconf);
966 + if (flags & IEEE80211_CONF_CHANGE_PS)
967 + rt2800pci_config_ps(rt2x00dev, libconf);
968 +}
969 +
970 +/*
971 + * Link tuning
972 + */
973 +static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
974 + struct link_qual *qual)
975 +{
976 + u32 reg;
977 +
978 + /*
979 + * Update FCS error count from register.
980 + */
981 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
982 + qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
983 +
984 + /*
985 + * Update False CCA count from register.
986 + */
987 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
988 + qual->false_cca = rt2x00_get_field32(reg, RX_STA_CNT1_FALSE_CCA);
989 +}
990 +
991 +static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
992 +{
993 + if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
994 + return 0x2e + rt2x00dev->lna_gain;
995 +
996 + if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
997 + return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
998 + else
999 + return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1000 +}
1001 +
1002 +static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1003 + struct link_qual *qual, u8 vgc_level)
1004 +{
1005 + if (qual->vgc_level != vgc_level) {
1006 + rt2800pci_bbp_write(rt2x00dev, 66, vgc_level);
1007 + qual->vgc_level = vgc_level;
1008 + qual->vgc_level_reg = vgc_level;
1009 + }
1010 +}
1011 +
1012 +static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1013 + struct link_qual *qual)
1014 +{
1015 + rt2800pci_set_vgc(rt2x00dev, qual,
1016 + rt2800pci_get_default_vgc(rt2x00dev));
1017 +}
1018 +
1019 +static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1020 + struct link_qual *qual, const u32 count)
1021 +{
1022 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1023 + return;
1024 +
1025 + /*
1026 + * When RSSI is better then -80 increase VGC level with 0x10
1027 + */
1028 + rt2800pci_set_vgc(rt2x00dev, qual,
1029 + rt2800pci_get_default_vgc(rt2x00dev) +
1030 + ((qual->rssi > -80) * 0x10));
1031 +}
1032 +
1033 +/*
1034 + * Firmware functions
1035 + */
1036 +static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1037 +{
1038 + return FIRMWARE_RT2860;
1039 +}
1040 +
1041 +static u16 rt2800pci_get_firmware_crc(const void *data, const size_t len)
1042 +{
1043 + u16 crc;
1044 +
1045 + /*
1046 + * Use the crc ccitt algorithm.
1047 + * This will return the same value as the legacy driver which
1048 + * used bit ordering reversion on the both the firmware bytes
1049 + * before input input as well as on the final output.
1050 + * Obviously using crc ccitt directly is much more efficient.
1051 + * The last 2 bytes in the firmware array are the crc checksum itself,
1052 + * this means that we should never pass those 2 bytes to the crc
1053 + * algorithm.
1054 + */
1055 + crc = crc_ccitt(~0, data, len - 2);
1056 +
1057 + /*
1058 + * There is a small difference between the crc-itu-t + bitrev and
1059 + * the crc-ccitt crc calculation. In the latter method the 2 bytes
1060 + * will be swapped, use swab16 to convert the crc to the correct
1061 + * value.
1062 + */
1063 + return swab16(crc);
1064 +}
1065 +
1066 +static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1067 + const void *data, const size_t len)
1068 +{
1069 + unsigned int i;
1070 + u32 reg;
1071 +
1072 + if (len != 8192) {
1073 + ERROR(rt2x00dev, "Invalid firmware file length (len=%zu)\n", len);
1074 + return -ENOENT;
1075 + }
1076 +
1077 + /*
1078 + * Wait for stable hardware.
1079 + */
1080 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1081 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1082 + if (reg && reg != ~0)
1083 + break;
1084 + msleep(1);
1085 + }
1086 +
1087 + if (i == REGISTER_BUSY_COUNT) {
1088 + ERROR(rt2x00dev, "Unstable hardware.\n");
1089 + return -EBUSY;
1090 + }
1091 +
1092 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1093 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1094 +
1095 + /*
1096 + * Disable DMA, will be reenabled later when enabling
1097 + * the radio.
1098 + */
1099 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1100 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1101 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1102 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1103 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1104 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1105 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1106 +
1107 + /*
1108 + * enable Host program ram write selection
1109 + */
1110 + reg = 0;
1111 + rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1112 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1113 +
1114 + /*
1115 + * Write firmware to device.
1116 + */
1117 + rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1118 + data, len);
1119 +
1120 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1121 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1122 +
1123 + /*
1124 + * Wait for device to stabilize.
1125 + */
1126 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1127 + rt2x00pci_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1128 + if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1129 + break;
1130 + msleep(1);
1131 + }
1132 +
1133 + if (i == REGISTER_BUSY_COUNT) {
1134 + ERROR(rt2x00dev, "PBF system register not ready.\n");
1135 + return -EBUSY;
1136 + }
1137 +
1138 + /*
1139 + * Disable interrupts
1140 + */
1141 + rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1142 +
1143 + /*
1144 + * Initialize BBP R/W access agent
1145 + */
1146 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1147 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1148 +
1149 + return 0;
1150 +}
1151 +
1152 +/*
1153 + * Initialization functions.
1154 + */
1155 +static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1156 +{
1157 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1158 + u32 word;
1159 +
1160 + if (entry->queue->qid == QID_RX) {
1161 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1162 +
1163 + return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1164 + } else {
1165 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1166 +
1167 + return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1168 + }
1169 +}
1170 +
1171 +static void rt2800pci_clear_entry(struct queue_entry *entry)
1172 +{
1173 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1174 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1175 + u32 word;
1176 +
1177 + if (entry->queue->qid == QID_RX) {
1178 + rt2x00_desc_read(entry_priv->desc, 0, &word);
1179 + rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1180 + rt2x00_desc_write(entry_priv->desc, 0, word);
1181 +
1182 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1183 + rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1184 + rt2x00_desc_write(entry_priv->desc, 1, word);
1185 + } else {
1186 + rt2x00_desc_read(entry_priv->desc, 1, &word);
1187 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1188 + rt2x00_desc_write(entry_priv->desc, 1, word);
1189 + }
1190 +}
1191 +
1192 +static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1193 +{
1194 + struct queue_entry_priv_pci *entry_priv;
1195 + u32 reg;
1196 +
1197 + /*
1198 + * Initialize registers.
1199 + */
1200 + entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1201 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1202 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1203 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1204 +
1205 + entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1206 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1207 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1208 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1209 +
1210 + entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1211 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1212 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1213 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1214 +
1215 + entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1216 + rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1217 + rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1218 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1219 +
1220 + entry_priv = rt2x00dev->rx->entries[0].priv_data;
1221 + rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1222 + rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1223 + rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX, 0);
1224 +
1225 + /*
1226 + * Enable global DMA configuration
1227 + */
1228 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1229 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1230 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1231 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1232 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1233 +
1234 + rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1235 +
1236 + return 0;
1237 +}
1238 +
1239 +static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1240 +{
1241 + u32 reg;
1242 + unsigned int i;
1243 +
1244 + rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1245 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1246 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1247 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1248 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1249 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1250 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1251 + rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1252 + rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1253 +
1254 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1255 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1256 +
1257 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1258 +
1259 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1260 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1261 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1262 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1263 +
1264 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1265 +
1266 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1267 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1268 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1269 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1270 + rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1271 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET0, reg);
1272 +
1273 + rt2x00pci_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1274 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1275 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1276 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1277 + rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1278 + rt2x00pci_register_write(rt2x00dev, BCN_OFFSET1, reg);
1279 +
1280 + rt2x00pci_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1281 + rt2x00pci_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1282 +
1283 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1284 +
1285 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1286 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1287 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1288 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1289 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1290 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1291 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1292 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1293 +
1294 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG0, 0x00040a06);
1295 + rt2x00pci_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1296 +
1297 + rt2x00pci_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1298 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1299 + rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1300 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1301 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1302 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1303 + rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1304 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1305 + rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1306 + rt2x00pci_register_write(rt2x00dev, TX_LINK_CFG, reg);
1307 +
1308 + rt2x00pci_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1309 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1310 + rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1311 + rt2x00pci_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1312 +
1313 + rt2x00pci_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1314 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1315 + if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1316 + rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1317 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1318 + else
1319 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1320 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1321 + rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1322 + rt2x00pci_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1323 +
1324 + rt2x00pci_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1325 +
1326 + rt2x00pci_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1327 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1328 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1329 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1330 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1331 + rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1332 + rt2x00pci_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1333 +
1334 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1335 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
1336 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1337 + rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1338 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1339 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1340 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1341 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1342 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1343 + rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1344 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1345 +
1346 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1347 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
1348 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1349 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1350 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1351 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1352 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1353 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1354 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1355 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1356 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1357 +
1358 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1359 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1360 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1361 + rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1362 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1363 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1364 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1365 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1366 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1367 + rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1368 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1369 +
1370 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1371 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1372 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1373 + rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1374 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1375 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1376 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1377 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1378 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1379 + rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1380 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1381 +
1382 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1383 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1384 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1385 + rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1386 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1387 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1388 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1389 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1390 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1391 + rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1392 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1393 +
1394 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1395 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1396 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1397 + rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1398 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1399 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1400 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1401 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1402 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1403 + rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1404 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1405 +
1406 + rt2x00pci_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1407 + rt2x00pci_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1408 +
1409 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1410 + rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1411 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1412 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
1413 +
1414 + rt2x00pci_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1415 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1416 +
1417 + /*
1418 + * ASIC will keep garbage value after boot, clear encryption keys.
1419 + */
1420 + for (i = 0; i < 254; i++) {
1421 + u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1422 + rt2x00pci_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1423 + wcid, sizeof(wcid));
1424 + }
1425 +
1426 + for (i = 0; i < 4; i++)
1427 + rt2x00pci_register_write(rt2x00dev,
1428 + SHARED_KEY_MODE_ENTRY(i), 0);
1429 +
1430 + for (i = 0; i < 256; i++)
1431 + rt2x00pci_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1432 +
1433 + /*
1434 + * Clear all beacons
1435 + * For the Beacon base registers we only need to clear
1436 + * the first byte since that byte contains the VALID and OWNER
1437 + * bits which (when set to 0) will invalidate the entire beacon.
1438 + */
1439 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1440 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1441 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1442 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1443 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1444 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1445 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1446 + rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1447 +
1448 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1449 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1450 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1451 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1452 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1453 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1454 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1455 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1456 + rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1457 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1458 +
1459 + rt2x00pci_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1460 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1461 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1462 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1463 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1464 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1465 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1466 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1467 + rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1468 + rt2x00pci_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1469 +
1470 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1471 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1472 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1473 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 10);
1474 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 11);
1475 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 12);
1476 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 13);
1477 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 14);
1478 + rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 15);
1479 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1480 +
1481 + rt2x00pci_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1482 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1483 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1484 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1485 + rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1486 + rt2x00pci_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1487 +
1488 + /*
1489 + * We must clear the error counters.
1490 + * These registers are cleared on read,
1491 + * so we may pass a useless variable to store the value.
1492 + */
1493 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1494 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1495 + rt2x00pci_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1496 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1497 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1498 + rt2x00pci_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1499 +
1500 + return 0;
1501 +}
1502 +
1503 +static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1504 +{
1505 + unsigned int i;
1506 + u32 reg;
1507 +
1508 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1509 + rt2x00pci_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1510 + if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1511 + return 0;
1512 +
1513 + udelay(REGISTER_BUSY_DELAY);
1514 + }
1515 +
1516 + ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1517 + return -EACCES;
1518 +}
1519 +
1520 +static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1521 +{
1522 + unsigned int i;
1523 + u8 value;
1524 +
1525 + /*
1526 + * BBP was enabled after firmware was loaded,
1527 + * but we need to reactivate it now.
1528 + */
1529 + rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0x00000000);
1530 + rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0x00000000);
1531 + msleep(1);
1532 +
1533 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1534 + rt2800pci_bbp_read(rt2x00dev, 0, &value);
1535 + if ((value != 0xff) && (value != 0x00))
1536 + return 0;
1537 + udelay(REGISTER_BUSY_DELAY);
1538 + }
1539 +
1540 + ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1541 + return -EACCES;
1542 +}
1543 +
1544 +static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1545 +{
1546 + unsigned int i;
1547 + u16 eeprom;
1548 + u8 reg_id;
1549 + u8 value;
1550 +
1551 + if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1552 + rt2800pci_wait_bbp_ready(rt2x00dev)))
1553 + return -EACCES;
1554 +
1555 + rt2800pci_bbp_write(rt2x00dev, 65, 0x2c);
1556 + rt2800pci_bbp_write(rt2x00dev, 66, 0x38);
1557 + rt2800pci_bbp_write(rt2x00dev, 69, 0x12);
1558 + rt2800pci_bbp_write(rt2x00dev, 70, 0x0a);
1559 + rt2800pci_bbp_write(rt2x00dev, 73, 0x10);
1560 + rt2800pci_bbp_write(rt2x00dev, 81, 0x37);
1561 + rt2800pci_bbp_write(rt2x00dev, 82, 0x62);
1562 + rt2800pci_bbp_write(rt2x00dev, 83, 0x6a);
1563 + rt2800pci_bbp_write(rt2x00dev, 84, 0x99);
1564 + rt2800pci_bbp_write(rt2x00dev, 86, 0x00);
1565 + rt2800pci_bbp_write(rt2x00dev, 91, 0x04);
1566 + rt2800pci_bbp_write(rt2x00dev, 92, 0x00);
1567 + rt2800pci_bbp_write(rt2x00dev, 103, 0x00);
1568 + rt2800pci_bbp_write(rt2x00dev, 105, 0x05);
1569 +
1570 + if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1571 + rt2800pci_bbp_write(rt2x00dev, 69, 0x16);
1572 + rt2800pci_bbp_write(rt2x00dev, 73, 0x12);
1573 + }
1574 +
1575 + if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1576 + rt2800pci_bbp_write(rt2x00dev, 84, 0x19);
1577 +
1578 + for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1579 + rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1580 +
1581 + if (eeprom != 0xffff && eeprom != 0x0000) {
1582 + reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1583 + value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1584 + rt2800pci_bbp_write(rt2x00dev, reg_id, value);
1585 + }
1586 + }
1587 +
1588 + return 0;
1589 +}
1590 +
1591 +/*
1592 + * Device state switch handlers.
1593 + */
1594 +static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1595 + enum dev_state state)
1596 +{
1597 + u32 reg;
1598 +
1599 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1600 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1601 + (state == STATE_RADIO_RX_ON) ||
1602 + (state == STATE_RADIO_RX_ON_LINK));
1603 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1604 +}
1605 +
1606 +static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1607 + enum dev_state state)
1608 +{
1609 + int mask = (state == STATE_RADIO_IRQ_ON);
1610 + u32 reg;
1611 +
1612 + /*
1613 + * When interrupts are being enabled, the interrupt registers
1614 + * should clear the register to assure a clean state.
1615 + */
1616 + if (state == STATE_RADIO_IRQ_ON) {
1617 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1618 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1619 + }
1620 +
1621 + rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1622 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1623 + rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1624 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1625 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1626 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1627 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1628 + rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1629 + rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
1630 + rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
1631 + rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
1632 + rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
1633 + rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
1634 + rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
1635 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
1636 + rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
1637 + rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
1638 + rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
1639 + rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
1640 + rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1641 +}
1642 +
1643 +static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
1644 +{
1645 + unsigned int i;
1646 + u32 reg;
1647 +
1648 + for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1649 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1650 + if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
1651 + !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
1652 + return 0;
1653 +
1654 + msleep(1);
1655 + }
1656 +
1657 + ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
1658 + return -EACCES;
1659 +}
1660 +
1661 +static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1662 +{
1663 + u32 reg;
1664 + u16 word;
1665 +
1666 + /*
1667 + * Initialize all registers.
1668 + */
1669 + if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1670 + rt2800pci_init_queues(rt2x00dev) ||
1671 + rt2800pci_init_registers(rt2x00dev) ||
1672 + rt2800pci_wait_wpdma_ready(rt2x00dev) ||
1673 + rt2800pci_init_bbp(rt2x00dev)))
1674 + return -EIO;
1675 +
1676 + /*
1677 + * Send signal to firmware during boot time.
1678 + */
1679 + rt2800pci_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
1680 +
1681 + /*
1682 + * Enable RX.
1683 + */
1684 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1685 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1686 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
1687 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1688 +
1689 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1690 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
1691 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
1692 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
1693 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1694 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1695 +
1696 + rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1697 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
1698 + rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
1699 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1700 +
1701 + /*
1702 + * Initialize LED control
1703 + */
1704 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
1705 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
1706 + word & 0xff, (word >> 8) & 0xff);
1707 +
1708 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
1709 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
1710 + word & 0xff, (word >> 8) & 0xff);
1711 +
1712 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
1713 + rt2800pci_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
1714 + word & 0xff, (word >> 8) & 0xff);
1715 +
1716 + return 0;
1717 +}
1718 +
1719 +static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1720 +{
1721 + u32 reg;
1722 +
1723 + rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1724 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1725 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1726 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1727 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1728 + rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1729 + rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1730 +
1731 + rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
1732 + rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
1733 + rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
1734 +
1735 + rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
1736 +
1737 + /* Wait for DMA, ignore error */
1738 + rt2800pci_wait_wpdma_ready(rt2x00dev);
1739 +}
1740 +
1741 +static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
1742 + enum dev_state state)
1743 +{
1744 + rt2x00pci_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1745 +
1746 + if (state == STATE_AWAKE)
1747 + rt2800pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0);
1748 + else
1749 + rt2800pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
1750 +
1751 + return 0;
1752 +}
1753 +
1754 +static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1755 + enum dev_state state)
1756 +{
1757 + int retval = 0;
1758 +
1759 + switch (state) {
1760 + case STATE_RADIO_ON:
1761 + /*
1762 + * Before the radio can be enabled, the device first has
1763 + * to be woken up. After that it needs a bit of time
1764 + * to be fully awake and the radio can be enabled.
1765 + */
1766 + rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
1767 + msleep(1);
1768 + retval = rt2800pci_enable_radio(rt2x00dev);
1769 + break;
1770 + case STATE_RADIO_OFF:
1771 + /*
1772 + * After the radio has been disablee, the device should
1773 + * be put to sleep for powersaving.
1774 + */
1775 + rt2800pci_disable_radio(rt2x00dev);
1776 + rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
1777 + break;
1778 + case STATE_RADIO_RX_ON:
1779 + case STATE_RADIO_RX_ON_LINK:
1780 + case STATE_RADIO_RX_OFF:
1781 + case STATE_RADIO_RX_OFF_LINK:
1782 + rt2800pci_toggle_rx(rt2x00dev, state);
1783 + break;
1784 + case STATE_RADIO_IRQ_ON:
1785 + case STATE_RADIO_IRQ_OFF:
1786 + rt2800pci_toggle_irq(rt2x00dev, state);
1787 + break;
1788 + case STATE_DEEP_SLEEP:
1789 + case STATE_SLEEP:
1790 + case STATE_STANDBY:
1791 + case STATE_AWAKE:
1792 + retval = rt2800pci_set_state(rt2x00dev, state);
1793 + break;
1794 + default:
1795 + retval = -ENOTSUPP;
1796 + break;
1797 + }
1798 +
1799 + if (unlikely(retval))
1800 + ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1801 + state, retval);
1802 +
1803 + return retval;
1804 +}
1805 +
1806 +/*
1807 + * TX descriptor initialization
1808 + */
1809 +static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1810 + struct sk_buff *skb,
1811 + struct txentry_desc *txdesc)
1812 +{
1813 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1814 + __le32 *txd = skbdesc->desc;
1815 + __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
1816 + u32 word;
1817 +
1818 + /*
1819 + * Initialize TX Info descriptor
1820 + */
1821 + rt2x00_desc_read(txwi, 0, &word);
1822 + rt2x00_set_field32(&word, TXWI_W0_FRAG,
1823 + test_bit(ENTRY_TXD_FIRST_FRAGMENT, &txdesc->flags) ||
1824 + test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1825 + rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
1826 + rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
1827 + rt2x00_set_field32(&word, TXWI_W0_TS,
1828 + test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1829 + rt2x00_set_field32(&word, TXWI_W0_AMPDU,
1830 + test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
1831 + rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
1832 + rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
1833 + rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
1834 + rt2x00_set_field32(&word, TXWI_W0_BW,
1835 + test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
1836 + rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
1837 + test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
1838 + rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
1839 + rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
1840 + rt2x00_desc_write(txwi, 0, word);
1841 +
1842 + rt2x00_desc_read(txwi, 1, &word);
1843 + rt2x00_set_field32(&word, TXWI_W1_ACK,
1844 + test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1845 + rt2x00_set_field32(&word, TXWI_W1_NSEQ,
1846 + test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
1847 + rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
1848 + rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
1849 + skbdesc->entry->entry_idx);
1850 + rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT, skb->len);
1851 + rt2x00_set_field32(&word, TXWI_W1_PACKETID,
1852 + skbdesc->entry->queue->qid);
1853 + rt2x00_desc_write(txwi, 1, word);
1854 +
1855 + if (test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags)) {
1856 + _rt2x00_desc_write(txwi, 2, skbdesc->iv[0]);
1857 + _rt2x00_desc_write(txwi, 3, skbdesc->iv[1]);
1858 + }
1859 +
1860 + /*
1861 + * Initialize TX descriptor
1862 + */
1863 + rt2x00_desc_read(txd, 0, &word);
1864 + rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
1865 + rt2x00_desc_write(txd, 0, word);
1866 +
1867 + rt2x00_desc_read(txd, 1, &word);
1868 + rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
1869 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC1, 1);
1870 + rt2x00_set_field32(&word, TXD_W1_BURST,
1871 + test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1872 + rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
1873 + rt2x00dev->hw->extra_tx_headroom);
1874 + rt2x00_set_field32(&word, TXD_W1_LAST_SEC0,
1875 + !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1876 + rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
1877 + rt2x00_desc_write(txd, 1, word);
1878 +
1879 + rt2x00_desc_read(txd, 2, &word);
1880 + rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
1881 + skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
1882 + rt2x00_desc_write(txd, 2, word);
1883 +
1884 + rt2x00_desc_read(txd, 3, &word);
1885 + rt2x00_set_field32(&word, TXD_W3_WIV, 1);
1886 + rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
1887 + rt2x00_desc_write(txd, 3, word);
1888 +}
1889 +
1890 +/*
1891 + * TX data initialization
1892 + */
1893 +static void rt2800pci_write_beacon(struct queue_entry *entry)
1894 +{
1895 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1896 + struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1897 + unsigned int beacon_base;
1898 + u32 reg;
1899 +
1900 + /*
1901 + * Disable beaconing while we are reloading the beacon data,
1902 + * otherwise we might be sending out invalid data.
1903 + */
1904 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1905 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1906 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1907 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1908 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1909 +
1910 + /*
1911 + * Write entire beacon with descriptor to register.
1912 + */
1913 + beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
1914 + rt2x00pci_register_multiwrite(rt2x00dev,
1915 + beacon_base,
1916 + skbdesc->desc, skbdesc->desc_len);
1917 + rt2x00pci_register_multiwrite(rt2x00dev,
1918 + beacon_base + skbdesc->desc_len,
1919 + entry->skb->data, entry->skb->len);
1920 +
1921 + /*
1922 + * Clean up beacon skb.
1923 + */
1924 + dev_kfree_skb_any(entry->skb);
1925 + entry->skb = NULL;
1926 +}
1927 +
1928 +static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1929 + const enum data_queue_qid queue_idx)
1930 +{
1931 + struct data_queue *queue;
1932 + unsigned int idx, qidx = 0;
1933 + u32 reg;
1934 +
1935 + if (queue_idx == QID_BEACON) {
1936 + rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1937 + if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
1938 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
1939 + rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
1940 + rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
1941 + rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1942 + }
1943 + return;
1944 + }
1945 +
1946 + if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
1947 + return;
1948 +
1949 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1950 + idx = queue->index[Q_INDEX];
1951 +
1952 + if (queue_idx == QID_MGMT)
1953 + qidx = 5;
1954 + else
1955 + qidx = queue_idx;
1956 +
1957 + rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
1958 +}
1959 +
1960 +/*
1961 + * RX control handlers
1962 + */
1963 +static void rt2800pci_fill_rxdone(struct queue_entry *entry,
1964 + struct rxdone_entry_desc *rxdesc)
1965 +{
1966 + struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1967 + struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1968 + __le32 *rxd = entry_priv->desc;
1969 + __le32 *rxwi = (__le32 *)entry->skb->data;
1970 + u32 rxd3;
1971 + u32 rxwi0;
1972 + u32 rxwi1;
1973 + u32 rxwi2;
1974 + u32 rxwi3;
1975 +
1976 + rt2x00_desc_read(rxd, 3, &rxd3);
1977 + rt2x00_desc_read(rxwi, 0, &rxwi0);
1978 + rt2x00_desc_read(rxwi, 1, &rxwi1);
1979 + rt2x00_desc_read(rxwi, 2, &rxwi2);
1980 + rt2x00_desc_read(rxwi, 3, &rxwi3);
1981 +
1982 + if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
1983 + rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1984 +
1985 + if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
1986 + /*
1987 + * Unfortunately we don't know the cipher type used during
1988 + * decryption. This prevents us from correct providing
1989 + * correct statistics through debugfs.
1990 + */
1991 + rxdesc->cipher = CIPHER_NONE;
1992 + rxdesc->cipher_status =
1993 + rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
1994 + }
1995 +
1996 + if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
1997 + /*
1998 + * Hardware has stripped IV/EIV data from 802.11 frame during
1999 + * decryption. Unfortunately the descriptor doesn't contain
2000 + * any fields with the EIV/IV data either, so they can't
2001 + * be restored by rt2x00lib.
2002 + */
2003 + rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2004 +
2005 + if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2006 + rxdesc->flags |= RX_FLAG_DECRYPTED;
2007 + else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2008 + rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2009 + }
2010 +
2011 + if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2012 + rxdesc->dev_flags |= RXDONE_MY_BSS;
2013 +
2014 + if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2015 + rxdesc->flags |= RX_FLAG_SHORT_GI;
2016 +
2017 + if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2018 + rxdesc->flags |= RX_FLAG_40MHZ;
2019 +
2020 + /*
2021 + * Detect RX rate, always use MCS as signal type.
2022 + */
2023 + rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2024 + rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2025 + rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2026 +
2027 + /*
2028 + * Mask of 0x8 bit to remove the short preamble flag.
2029 + */
2030 + if (rxdesc->dev_flags == RATE_MODE_CCK)
2031 + rxdesc->signal &= ~0x8;
2032 +
2033 + rxdesc->rssi =
2034 + (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2035 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1) +
2036 + rt2x00_get_field32(rxwi2, RXWI_W2_RSSI2)) / 3;
2037 +
2038 + rxdesc->noise =
2039 + (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2040 + rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2041 +
2042 + rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2043 +
2044 + /*
2045 + * Remove TXWI descriptor from start of buffer.
2046 + */
2047 + skb_pull(entry->skb, TXWI_DESC_SIZE);
2048 + skb_trim(entry->skb, rxdesc->size);
2049 +}
2050 +
2051 +/*
2052 + * Interrupt functions.
2053 + */
2054 +static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2055 +{
2056 + struct data_queue *queue;
2057 + struct queue_entry *entry;
2058 + struct queue_entry *entry_done;
2059 + struct queue_entry_priv_pci *entry_priv;
2060 + struct txdone_entry_desc txdesc;
2061 + u32 word;
2062 + u32 reg;
2063 + u32 old_reg;
2064 + int type;
2065 + int index;
2066 +
2067 + /*
2068 + * During each loop we will compare the freshly read
2069 + * TX_STA_FIFO register value with the value read from
2070 + * the previous loop. If the 2 values are equal then
2071 + * we should stop processing because the chance it
2072 + * quite big that the device has been unplugged and
2073 + * we risk going into an endless loop.
2074 + */
2075 + old_reg = 0;
2076 +
2077 + while (1) {
2078 + rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2079 + if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2080 + break;
2081 +
2082 + if (old_reg == reg)
2083 + break;
2084 + old_reg = reg;
2085 +
2086 + /*
2087 + * Skip this entry when it contains an invalid
2088 + * queue identication number.
2089 + */
2090 + type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE);
2091 + queue = rt2x00queue_get_queue(rt2x00dev, type);
2092 + if (unlikely(!queue))
2093 + continue;
2094 +
2095 + /*
2096 + * Skip this entry when it contains an invalid
2097 + * index number.
2098 + */
2099 + index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID);
2100 + if (unlikely(index >= queue->limit))
2101 + continue;
2102 +
2103 + entry = &queue->entries[index];
2104 + entry_priv = entry->priv_data;
2105 + rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2106 +
2107 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2108 + while (entry != entry_done) {
2109 + /*
2110 + * Catch up.
2111 + * Just report any entries we missed as failed.
2112 + */
2113 + WARNING(rt2x00dev,
2114 + "TX status report missed for entry %d\n",
2115 + entry_done->entry_idx);
2116 +
2117 + txdesc.flags = 0;
2118 + __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2119 + txdesc.retry = 0;
2120 +
2121 + rt2x00lib_txdone(entry_done, &txdesc);
2122 + entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2123 + }
2124 +
2125 + /*
2126 + * Obtain the status about this packet.
2127 + */
2128 + txdesc.flags = 0;
2129 + if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2130 + __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2131 + else
2132 + __set_bit(TXDONE_FAILURE, &txdesc.flags);
2133 + txdesc.retry = rt2x00_get_field32(word, TXWI_W0_MCS);
2134 +
2135 + rt2x00lib_txdone(entry, &txdesc);
2136 + }
2137 +}
2138 +
2139 +static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2140 +{
2141 + struct rt2x00_dev *rt2x00dev = dev_instance;
2142 + u32 reg;
2143 +
2144 + /* Read status and ACK all interrupts */
2145 + rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2146 + rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2147 +
2148 + if (!reg)
2149 + return IRQ_NONE;
2150 +
2151 + if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2152 + return IRQ_HANDLED;
2153 +
2154 + /*
2155 + * 1 - Rx ring done interrupt.
2156 + */
2157 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2158 + rt2x00pci_rxdone(rt2x00dev);
2159 +
2160 + if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2161 + rt2800pci_txdone(rt2x00dev);
2162 +
2163 + return IRQ_HANDLED;
2164 +}
2165 +
2166 +/*
2167 + * Device probe functions.
2168 + */
2169 +static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2170 +{
2171 + struct eeprom_93cx6 eeprom;
2172 + u32 reg;
2173 + u16 word;
2174 + u8 *mac;
2175 + u8 default_lna_gain;
2176 +
2177 + rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
2178 +
2179 + eeprom.data = rt2x00dev;
2180 + eeprom.register_read = rt2800pci_eepromregister_read;
2181 + eeprom.register_write = rt2800pci_eepromregister_write;
2182 + eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
2183 + PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
2184 + eeprom.reg_data_in = 0;
2185 + eeprom.reg_data_out = 0;
2186 + eeprom.reg_data_clock = 0;
2187 + eeprom.reg_chip_select = 0;
2188 +
2189 + eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
2190 + EEPROM_SIZE / sizeof(u16));
2191 +
2192 + /*
2193 + * Start validation of the data that has been read.
2194 + */
2195 + mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2196 + if (!is_valid_ether_addr(mac)) {
2197 + DECLARE_MAC_BUF(macbuf);
2198 +
2199 + random_ether_addr(mac);
2200 + EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
2201 + }
2202 +
2203 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2204 + if (word == 0xffff) {
2205 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2206 + rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2207 + rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2208 + rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2209 + EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2210 + }
2211 +
2212 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2213 + if (word == 0xffff) {
2214 + rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2215 + rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2216 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2217 + rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2218 + rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2219 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2220 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2221 + rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2222 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2223 + rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2224 + rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2225 + EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2226 + }
2227 +
2228 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2229 + if ((word & 0x00ff) == 0x00ff) {
2230 + rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2231 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2232 + LED_MODE_TXRX_ACTIVITY);
2233 + rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2234 + rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2235 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2236 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2237 + rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2238 + EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2239 + }
2240 +
2241 + /*
2242 + * During the LNA validation we are going to use
2243 + * lna0 as correct value. Note that EEPROM_LNA
2244 + * is never validated.
2245 + */
2246 + rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2247 + default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2248 +
2249 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2250 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2251 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2252 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2253 + rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2254 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2255 +
2256 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2257 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2258 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2259 + if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2260 + rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2261 + rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2262 + default_lna_gain);
2263 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2264 +
2265 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2266 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2267 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2268 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2269 + rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2270 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2271 +
2272 + rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2273 + if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2274 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2275 + if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2276 + rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2277 + rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2278 + default_lna_gain);
2279 + rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2280 +
2281 + return 0;
2282 +}
2283 +
2284 +static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2285 +{
2286 + u32 reg;
2287 + u16 value;
2288 + u16 eeprom;
2289 + u16 device;
2290 +
2291 + /*
2292 + * Read EEPROM word for configuration.
2293 + */
2294 + rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2295 +
2296 + /*
2297 + * Identify RF chipset.
2298 + * To determine the RT chip we have to read the
2299 + * PCI header of the device.
2300 + */
2301 + pci_read_config_word(to_pci_dev(rt2x00dev->dev),
2302 + PCI_CONFIG_HEADER_DEVICE, &device);
2303 + value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2304 + rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
2305 + rt2x00_set_chip(rt2x00dev, device, value, reg);
2306 +
2307 + if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2308 + !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2309 + !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2310 + !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2311 + !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2312 + !rt2x00_rf(&rt2x00dev->chip, RF2020)) {
2313 + ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2314 + return -ENODEV;
2315 + }
2316 +
2317 + /*
2318 + * Read frequency offset and RF programming sequence.
2319 + */
2320 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2321 + rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2322 +
2323 + /*
2324 + * Read external LNA informations.
2325 + */
2326 + rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2327 +
2328 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2329 + __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2330 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2331 + __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2332 +
2333 + /*
2334 + * Detect if this device has an hardware controlled radio.
2335 + */
2336 +#ifdef CONFIG_RT2X00_LIB_RFKILL
2337 + if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2338 + __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2339 +#endif /* CONFIG_RT2X00_LIB_RFKILL */
2340 +
2341 + /*
2342 + * Store led settings, for correct led behaviour.
2343 + */
2344 +#ifdef CONFIG_RT2X00_LIB_LEDS
2345 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2346 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2347 + rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2348 +
2349 + rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2350 +#endif /* CONFIG_RT2X00_LIB_LEDS */
2351 +
2352 + return 0;
2353 +}
2354 +
2355 +/*
2356 + * RF value list for rt2860
2357 + * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2358 + */
2359 +static const struct rf_channel rf_vals[] = {
2360 + { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2361 + { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2362 + { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2363 + { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2364 + { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2365 + { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2366 + { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2367 + { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2368 + { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2369 + { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2370 + { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2371 + { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2372 + { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2373 + { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2374 +
2375 + /* 802.11 UNI / HyperLan 2 */
2376 + { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2377 + { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2378 + { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2379 + { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2380 + { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2381 + { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2382 + { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2383 + { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2384 + { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2385 + { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2386 + { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2387 + { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2388 +
2389 + /* 802.11 HyperLan 2 */
2390 + { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2391 + { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2392 + { 104, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed1a3 },
2393 + { 108, 0x18402ecc, 0x184c0a32, 0x18578a55, 0x180ed193 },
2394 + { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2395 + { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2396 + { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2397 + { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2398 + { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2399 + { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2400 + { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2401 + { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2402 + { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2403 + { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2404 + { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2405 + { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2406 +
2407 + /* 802.11 UNII */
2408 + { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2409 + { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2410 + { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2411 + { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2412 + { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2413 + { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2414 + { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2415 +
2416 + /* 802.11 Japan */
2417 + { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2418 + { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2419 + { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2420 + { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2421 + { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2422 + { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2423 + { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2424 +};
2425 +
2426 +static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2427 +{
2428 + struct hw_mode_spec *spec = &rt2x00dev->spec;
2429 + struct channel_info *info;
2430 + char *tx_power1;
2431 + char *tx_power2;
2432 + unsigned int i;
2433 +
2434 + /*
2435 + * Initialize all hw fields.
2436 + */
2437 + rt2x00dev->hw->flags =
2438 + IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2439 + IEEE80211_HW_SIGNAL_DBM |
2440 + IEEE80211_HW_SUPPORTS_PS |
2441 + IEEE80211_HW_PS_NULLFUNC_STACK;
2442 + rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2443 +
2444 + SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2445 + SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2446 + rt2x00_eeprom_addr(rt2x00dev,
2447 + EEPROM_MAC_ADDR_0));
2448 +
2449 + /*
2450 + * Initialize hw_mode information.
2451 + */
2452 + spec->supported_bands = SUPPORT_BAND_2GHZ;
2453 + spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2454 +
2455 + if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2456 + rt2x00_rf(&rt2x00dev->chip, RF2720)) {
2457 + spec->num_channels = 14;
2458 + spec->channels = rf_vals;
2459 + } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2460 + rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2461 + spec->supported_bands |= SUPPORT_BAND_5GHZ;
2462 + spec->num_channels = ARRAY_SIZE(rf_vals);
2463 + spec->channels = rf_vals;
2464 + }
2465 +
2466 + /*
2467 + * Initialize HT information.
2468 + */
2469 + spec->ht.ht_supported = true;
2470 + spec->ht.cap =
2471 + IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2472 + IEEE80211_HT_CAP_GRN_FLD |
2473 + IEEE80211_HT_CAP_SGI_20 |
2474 + IEEE80211_HT_CAP_SGI_40 |
2475 + IEEE80211_HT_CAP_TX_STBC |
2476 + IEEE80211_HT_CAP_RX_STBC |
2477 + IEEE80211_HT_CAP_PSMP_SUPPORT;
2478 + spec->ht.ampdu_factor = 3;
2479 + spec->ht.ampdu_density = 4;
2480 + spec->ht.mcs.rx_mask[0] = 0xff;
2481 + spec->ht.mcs.rx_mask[1] = 0xff;
2482 + spec->ht.mcs.tx_params =
2483 + IEEE80211_HT_MCS_TX_DEFINED;
2484 +
2485 + /*
2486 + * Create channel information array
2487 + */
2488 + info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2489 + if (!info)
2490 + return -ENOMEM;
2491 +
2492 + spec->channels_info = info;
2493 +
2494 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2495 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2496 +
2497 + for (i = 0; i < 14; i++) {
2498 + info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2499 + info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2500 + }
2501 +
2502 + if (spec->num_channels > 14) {
2503 + tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2504 + tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2505 +
2506 + for (i = 14; i < spec->num_channels; i++) {
2507 + info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2508 + info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2509 + }
2510 + }
2511 +
2512 + return 0;
2513 +}
2514 +
2515 +static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2516 +{
2517 + int retval;
2518 +
2519 + /*
2520 + * Allocate eeprom data.
2521 + */
2522 + retval = rt2800pci_validate_eeprom(rt2x00dev);
2523 + if (retval)
2524 + return retval;
2525 +
2526 + retval = rt2800pci_init_eeprom(rt2x00dev);
2527 + if (retval)
2528 + return retval;
2529 +
2530 + /*
2531 + * Initialize hw specifications.
2532 + */
2533 + retval = rt2800pci_probe_hw_mode(rt2x00dev);
2534 + if (retval)
2535 + return retval;
2536 +
2537 + /*
2538 + * This device requires firmware.
2539 + */
2540 + __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2541 + if (!modparam_nohwcrypt)
2542 + __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
2543 +
2544 + /*
2545 + * Set the rssi offset.
2546 + */
2547 + rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2548 +
2549 + return 0;
2550 +}
2551 +
2552 +/*
2553 + * IEEE80211 stack callback functions.
2554 + */
2555 +static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
2556 +{
2557 + struct rt2x00_dev *rt2x00dev = hw->priv;
2558 + u32 reg;
2559 + bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
2560 +
2561 + rt2x00pci_register_read(rt2x00dev, TX_RTS_CFG, &reg);
2562 + rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
2563 + rt2x00pci_register_write(rt2x00dev, TX_RTS_CFG, reg);
2564 +
2565 + rt2x00pci_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
2566 + rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
2567 + rt2x00pci_register_write(rt2x00dev, CCK_PROT_CFG, reg);
2568 +
2569 + rt2x00pci_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
2570 + rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
2571 + rt2x00pci_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
2572 +
2573 + rt2x00pci_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
2574 + rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
2575 + rt2x00pci_register_write(rt2x00dev, MM20_PROT_CFG, reg);
2576 +
2577 + rt2x00pci_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
2578 + rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
2579 + rt2x00pci_register_write(rt2x00dev, MM40_PROT_CFG, reg);
2580 +
2581 + rt2x00pci_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
2582 + rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
2583 + rt2x00pci_register_write(rt2x00dev, GF20_PROT_CFG, reg);
2584 +
2585 + rt2x00pci_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
2586 + rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
2587 + rt2x00pci_register_write(rt2x00dev, GF40_PROT_CFG, reg);
2588 +
2589 + return 0;
2590 +}
2591 +
2592 +static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
2593 + const struct ieee80211_tx_queue_params *params)
2594 +{
2595 + struct rt2x00_dev *rt2x00dev = hw->priv;
2596 + struct data_queue *queue;
2597 + struct rt2x00_field32 field;
2598 + int retval;
2599 + u32 reg;
2600 + u32 offset;
2601 +
2602 + /*
2603 + * First pass the configuration through rt2x00lib, that will
2604 + * update the queue settings and validate the input. After that
2605 + * we are free to update the registers based on the value
2606 + * in the queue parameter.
2607 + */
2608 + retval = rt2x00mac_conf_tx(hw, queue_idx, params);
2609 + if (retval)
2610 + return retval;
2611 +
2612 + /*
2613 + * We only need to perform additional register initialization
2614 + * for WMM queues/
2615 + */
2616 + if (queue_idx >= 4)
2617 + return 0;
2618 +
2619 + queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2620 +
2621 + /* Update WMM TXOP register */
2622 + offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
2623 + field.bit_offset = (queue_idx & 1) * 16;
2624 + field.bit_mask = 0xffff << field.bit_offset;
2625 +
2626 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2627 + rt2x00_set_field32(&reg, field, queue->txop);
2628 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2629 +
2630 + /* Update WMM registers */
2631 + field.bit_offset = queue_idx * 4;
2632 + field.bit_mask = 0xf << field.bit_offset;
2633 +
2634 + rt2x00pci_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
2635 + rt2x00_set_field32(&reg, field, queue->aifs);
2636 + rt2x00pci_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
2637 +
2638 + rt2x00pci_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
2639 + rt2x00_set_field32(&reg, field, queue->cw_min);
2640 + rt2x00pci_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
2641 +
2642 + rt2x00pci_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
2643 + rt2x00_set_field32(&reg, field, queue->cw_max);
2644 + rt2x00pci_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
2645 +
2646 + /* Update EDCA registers */
2647 + offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
2648 +
2649 + rt2x00pci_register_read(rt2x00dev, offset, &reg);
2650 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
2651 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
2652 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
2653 + rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
2654 + rt2x00pci_register_write(rt2x00dev, offset, reg);
2655 +
2656 + return 0;
2657 +}
2658 +
2659 +static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
2660 +{
2661 + struct rt2x00_dev *rt2x00dev = hw->priv;
2662 + u64 tsf;
2663 + u32 reg;
2664 +
2665 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
2666 + tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
2667 + rt2x00pci_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
2668 + tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
2669 +
2670 + return tsf;
2671 +}
2672 +
2673 +static const struct ieee80211_ops rt2800pci_mac80211_ops = {
2674 + .tx = rt2x00mac_tx,
2675 + .start = rt2x00mac_start,
2676 + .stop = rt2x00mac_stop,
2677 + .add_interface = rt2x00mac_add_interface,
2678 + .remove_interface = rt2x00mac_remove_interface,
2679 + .config = rt2x00mac_config,
2680 + .config_interface = rt2x00mac_config_interface,
2681 + .configure_filter = rt2x00mac_configure_filter,
2682 + .set_key = rt2x00mac_set_key,
2683 + .get_stats = rt2x00mac_get_stats,
2684 + .set_rts_threshold = rt2800pci_set_rts_threshold,
2685 + .bss_info_changed = rt2x00mac_bss_info_changed,
2686 + .conf_tx = rt2800pci_conf_tx,
2687 + .get_tx_stats = rt2x00mac_get_tx_stats,
2688 + .get_tsf = rt2800pci_get_tsf,
2689 +};
2690 +
2691 +static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
2692 + .irq_handler = rt2800pci_interrupt,
2693 + .probe_hw = rt2800pci_probe_hw,
2694 + .get_firmware_name = rt2800pci_get_firmware_name,
2695 + .get_firmware_crc = rt2800pci_get_firmware_crc,
2696 + .load_firmware = rt2800pci_load_firmware,
2697 + .initialize = rt2x00pci_initialize,
2698 + .uninitialize = rt2x00pci_uninitialize,
2699 + .get_entry_state = rt2800pci_get_entry_state,
2700 + .clear_entry = rt2800pci_clear_entry,
2701 + .set_device_state = rt2800pci_set_device_state,
2702 + .rfkill_poll = rt2800pci_rfkill_poll,
2703 + .link_stats = rt2800pci_link_stats,
2704 + .reset_tuner = rt2800pci_reset_tuner,
2705 + .link_tuner = rt2800pci_link_tuner,
2706 + .write_tx_desc = rt2800pci_write_tx_desc,
2707 + .write_tx_data = rt2x00pci_write_tx_data,
2708 + .write_beacon = rt2800pci_write_beacon,
2709 + .kick_tx_queue = rt2800pci_kick_tx_queue,
2710 + .fill_rxdone = rt2800pci_fill_rxdone,
2711 + .config_shared_key = rt2800pci_config_shared_key,
2712 + .config_pairwise_key = rt2800pci_config_pairwise_key,
2713 + .config_filter = rt2800pci_config_filter,
2714 + .config_intf = rt2800pci_config_intf,
2715 + .config_erp = rt2800pci_config_erp,
2716 + .config_ant = rt2800pci_config_ant,
2717 + .config = rt2800pci_config,
2718 +};
2719 +
2720 +static const struct data_queue_desc rt2800pci_queue_rx = {
2721 + .entry_num = RX_ENTRIES,
2722 + .data_size = DATA_FRAME_SIZE,
2723 + .desc_size = RXD_DESC_SIZE,
2724 + .priv_size = sizeof(struct queue_entry_priv_pci),
2725 +};
2726 +
2727 +static const struct data_queue_desc rt2800pci_queue_tx = {
2728 + .entry_num = TX_ENTRIES,
2729 + .data_size = DATA_FRAME_SIZE,
2730 + .desc_size = TXD_DESC_SIZE,
2731 + .priv_size = sizeof(struct queue_entry_priv_pci),
2732 +};
2733 +
2734 +static const struct data_queue_desc rt2800pci_queue_bcn = {
2735 + .entry_num = 8 * BEACON_ENTRIES,
2736 + .data_size = 0, /* No DMA required for beacons */
2737 + .desc_size = TXWI_DESC_SIZE,
2738 + .priv_size = sizeof(struct queue_entry_priv_pci),
2739 +};
2740 +
2741 +static const struct rt2x00_ops rt2800pci_ops = {
2742 + .name = KBUILD_MODNAME,
2743 + .max_sta_intf = 1,
2744 + .max_ap_intf = 8,
2745 + .eeprom_size = EEPROM_SIZE,
2746 + .rf_size = RF_SIZE,
2747 + .tx_queues = NUM_TX_QUEUES,
2748 + .rx = &rt2800pci_queue_rx,
2749 + .tx = &rt2800pci_queue_tx,
2750 + .bcn = &rt2800pci_queue_bcn,
2751 + .lib = &rt2800pci_rt2x00_ops,
2752 + .hw = &rt2800pci_mac80211_ops,
2753 +#ifdef CONFIG_RT2X00_LIB_DEBUGFS
2754 + .debugfs = &rt2800pci_rt2x00debug,
2755 +#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2756 +};
2757 +
2758 +/*
2759 + * RT2800pci module information.
2760 + */
2761 +static struct pci_device_id rt2800pci_device_table[] = {
2762 + { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
2763 + { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
2764 + { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
2765 + { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
2766 + { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
2767 + { 0, }
2768 +};
2769 +
2770 +MODULE_AUTHOR(DRV_PROJECT);
2771 +MODULE_VERSION(DRV_VERSION);
2772 +MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
2773 +MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
2774 +MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
2775 +MODULE_FIRMWARE(FIRMWARE_RT2860);
2776 +MODULE_LICENSE("GPL");
2777 +
2778 +static struct pci_driver rt2800pci_driver = {
2779 + .name = KBUILD_MODNAME,
2780 + .id_table = rt2800pci_device_table,
2781 + .probe = rt2x00pci_probe,
2782 + .remove = __devexit_p(rt2x00pci_remove),
2783 + .suspend = rt2x00pci_suspend,
2784 + .resume = rt2x00pci_resume,
2785 +};
2786 +
2787 +static int __init rt2800pci_init(void)
2788 +{
2789 + return pci_register_driver(&rt2800pci_driver);
2790 +}
2791 +
2792 +static void __exit rt2800pci_exit(void)
2793 +{
2794 + pci_unregister_driver(&rt2800pci_driver);
2795 +}
2796 +
2797 +module_init(rt2800pci_init);
2798 +module_exit(rt2800pci_exit);
2799 --- /dev/null
2800 +++ b/drivers/net/wireless/rt2x00/rt2800pci.h
2801 @@ -0,0 +1,1881 @@
2802 +/*
2803 + Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
2804 + <http://rt2x00.serialmonkey.com>
2805 +
2806 + This program is free software; you can redistribute it and/or modify
2807 + it under the terms of the GNU General Public License as published by
2808 + the Free Software Foundation; either version 2 of the License, or
2809 + (at your option) any later version.
2810 +
2811 + This program is distributed in the hope that it will be useful,
2812 + but WITHOUT ANY WARRANTY; without even the implied warranty of
2813 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2814 + GNU General Public License for more details.
2815 +
2816 + You should have received a copy of the GNU General Public License
2817 + along with this program; if not, write to the
2818 + Free Software Foundation, Inc.,
2819 + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2820 + */
2821 +
2822 +/*
2823 + Module: rt2800pci
2824 + Abstract: Data structures and registers for the rt2800pci module.
2825 + Supported chipsets: RT2800E & RT2800ED.
2826 + */
2827 +
2828 +#ifndef RT2800PCI_H
2829 +#define RT2800PCI_H
2830 +
2831 +/*
2832 + * RF chip defines.
2833 + *
2834 + * RF2820 2.4G 2T3R
2835 + * RF2850 2.4G/5G 2T3R
2836 + * RF2720 2.4G 1T2R
2837 + * RF2750 2.4G/5G 1T2R
2838 + * RF3020 2.4G 1T1R
2839 + * RF2020 2.4G B/G
2840 + */
2841 +#define RF2820 0x0001
2842 +#define RF2850 0x0002
2843 +#define RF2720 0x0003
2844 +#define RF2750 0x0004
2845 +#define RF3020 0x0005
2846 +#define RF2020 0x0006
2847 +
2848 +/*
2849 + * RT2860 version
2850 + */
2851 +#define RT2860C_VERSION 0x28600100
2852 +#define RT2860D_VERSION 0x28600101
2853 +#define RT2880E_VERSION 0x28720200
2854 +#define RT2883_VERSION 0x28830300
2855 +#define RT3070_VERSION 0x30700200
2856 +
2857 +/*
2858 + * Signal information.
2859 + * Defaul offset is required for RSSI <-> dBm conversion.
2860 + */
2861 +#define DEFAULT_RSSI_OFFSET 120 /* FIXME */
2862 +
2863 +/*
2864 + * Register layout information.
2865 + */
2866 +#define CSR_REG_BASE 0x1000
2867 +#define CSR_REG_SIZE 0x0800
2868 +#define EEPROM_BASE 0x0000
2869 +#define EEPROM_SIZE 0x0110
2870 +#define BBP_BASE 0x0000
2871 +#define BBP_SIZE 0x0080
2872 +#define RF_BASE 0x0000
2873 +#define RF_SIZE 0x0014
2874 +
2875 +/*
2876 + * Number of TX queues.
2877 + */
2878 +#define NUM_TX_QUEUES 4
2879 +
2880 +/*
2881 + * PCI registers.
2882 + */
2883 +
2884 +/*
2885 + * PCI Configuration Header
2886 + */
2887 +#define PCI_CONFIG_HEADER_VENDOR 0x0000
2888 +#define PCI_CONFIG_HEADER_DEVICE 0x0002
2889 +
2890 +/*
2891 + * E2PROM_CSR: EEPROM control register.
2892 + * RELOAD: Write 1 to reload eeprom content.
2893 + * TYPE_93C46: 1: 93c46, 0:93c66.
2894 + * LOAD_STATUS: 1:loading, 0:done.
2895 + */
2896 +#define E2PROM_CSR 0x0004
2897 +#define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
2898 +#define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
2899 +#define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
2900 +#define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
2901 +#define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
2902 +#define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
2903 +#define E2PROM_CSR_RELOAD FIELD32(0x00000080)
2904 +
2905 +/*
2906 + * HOST-MCU shared memory
2907 + */
2908 +#define HOST_CMD_CSR 0x0404
2909 +#define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
2910 +
2911 +/*
2912 + * INT_SOURCE_CSR: Interrupt source register.
2913 + * Write one to clear corresponding bit.
2914 + * TX_FIFO_STATUS: FIFO Statistics is full, sw should read 0x171c
2915 + */
2916 +#define INT_SOURCE_CSR 0x0200
2917 +#define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
2918 +#define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
2919 +#define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
2920 +#define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2921 +#define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2922 +#define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2923 +#define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2924 +#define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2925 +#define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2926 +#define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
2927 +#define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
2928 +#define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
2929 +#define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
2930 +#define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2931 +#define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2932 +#define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
2933 +#define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
2934 +#define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
2935 +
2936 +/*
2937 + * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
2938 + */
2939 +#define INT_MASK_CSR 0x0204
2940 +#define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
2941 +#define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
2942 +#define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
2943 +#define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
2944 +#define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
2945 +#define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
2946 +#define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
2947 +#define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
2948 +#define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
2949 +#define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
2950 +#define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
2951 +#define INT_MASK_CSR_TBTT FIELD32(0x00000800)
2952 +#define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
2953 +#define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
2954 +#define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
2955 +#define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
2956 +#define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
2957 +#define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
2958 +
2959 +/*
2960 + * WPDMA_GLO_CFG
2961 + */
2962 +#define WPDMA_GLO_CFG 0x0208
2963 +#define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
2964 +#define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
2965 +#define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
2966 +#define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
2967 +#define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
2968 +#define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
2969 +#define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
2970 +#define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
2971 +#define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
2972 +
2973 +/*
2974 + * WPDMA_RST_IDX
2975 + */
2976 +#define WPDMA_RST_IDX 0x020c
2977 +#define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
2978 +#define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
2979 +#define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
2980 +#define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
2981 +#define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
2982 +#define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
2983 +#define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
2984 +
2985 +/*
2986 + * DELAY_INT_CFG
2987 + */
2988 +#define DELAY_INT_CFG 0x0210
2989 +#define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
2990 +#define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
2991 +#define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
2992 +#define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
2993 +#define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
2994 +#define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
2995 +
2996 +/*
2997 + * WMM_AIFSN_CFG: Aifsn for each EDCA AC
2998 + * AIFSN0: AC_BE
2999 + * AIFSN1: AC_BK
3000 + * AIFSN1: AC_VI
3001 + * AIFSN1: AC_VO
3002 + */
3003 +#define WMM_AIFSN_CFG 0x0214
3004 +#define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
3005 +#define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
3006 +#define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
3007 +#define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
3008 +
3009 +/*
3010 + * WMM_CWMIN_CSR: CWmin for each EDCA AC
3011 + * CWMIN0: AC_BE
3012 + * CWMIN1: AC_BK
3013 + * CWMIN1: AC_VI
3014 + * CWMIN1: AC_VO
3015 + */
3016 +#define WMM_CWMIN_CFG 0x0218
3017 +#define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
3018 +#define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
3019 +#define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
3020 +#define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
3021 +
3022 +/*
3023 + * WMM_CWMAX_CSR: CWmax for each EDCA AC
3024 + * CWMAX0: AC_BE
3025 + * CWMAX1: AC_BK
3026 + * CWMAX1: AC_VI
3027 + * CWMAX1: AC_VO
3028 + */
3029 +#define WMM_CWMAX_CFG 0x021c
3030 +#define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
3031 +#define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
3032 +#define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
3033 +#define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
3034 +
3035 +/*
3036 + * AC_TXOP0: AC_BK/AC_BE TXOP register
3037 + * AC0TXOP: AC_BK in unit of 32us
3038 + * AC1TXOP: AC_BE in unit of 32us
3039 + */
3040 +#define WMM_TXOP0_CFG 0x0220
3041 +#define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
3042 +#define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
3043 +
3044 +/*
3045 + * AC_TXOP1: AC_VO/AC_VI TXOP register
3046 + * AC2TXOP: AC_VI in unit of 32us
3047 + * AC3TXOP: AC_VO in unit of 32us
3048 + */
3049 +#define WMM_TXOP1_CFG 0x0224
3050 +#define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
3051 +#define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
3052 +
3053 +/*
3054 + * RINGREG_DIFF
3055 + */
3056 +#define RINGREG_DIFF 0x0010
3057 +
3058 +/*
3059 + * GPIO_CTRL_CFG:
3060 + */
3061 +#define GPIO_CTRL_CFG 0x0228
3062 +#define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
3063 +#define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
3064 +#define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
3065 +#define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
3066 +#define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
3067 +#define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
3068 +#define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
3069 +#define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
3070 +#define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
3071 +
3072 +/*
3073 + * MCU_CMD_CFG
3074 + */
3075 +#define MCU_CMD_CFG 0x022c
3076 +
3077 +/*
3078 + * AC_BK register offsets
3079 + */
3080 +#define TX_BASE_PTR0 0x0230
3081 +#define TX_MAX_CNT0 0x0234
3082 +#define TX_CTX_IDX0 0x0238
3083 +#define TX_DTX_IDX0 0x023c
3084 +
3085 +/*
3086 + * AC_BE register offsets
3087 + */
3088 +#define TX_BASE_PTR1 0x0240
3089 +#define TX_MAX_CNT1 0x0244
3090 +#define TX_CTX_IDX1 0x0248
3091 +#define TX_DTX_IDX1 0x024c
3092 +
3093 +/*
3094 + * AC_VI register offsets
3095 + */
3096 +#define TX_BASE_PTR2 0x0250
3097 +#define TX_MAX_CNT2 0x0254
3098 +#define TX_CTX_IDX2 0x0258
3099 +#define TX_DTX_IDX2 0x025c
3100 +
3101 +/*
3102 + * AC_VO register offsets
3103 + */
3104 +#define TX_BASE_PTR3 0x0260
3105 +#define TX_MAX_CNT3 0x0264
3106 +#define TX_CTX_IDX3 0x0268
3107 +#define TX_DTX_IDX3 0x026c
3108 +
3109 +/*
3110 + * HCCA register offsets
3111 + */
3112 +#define TX_BASE_PTR4 0x0270
3113 +#define TX_MAX_CNT4 0x0274
3114 +#define TX_CTX_IDX4 0x0278
3115 +#define TX_DTX_IDX4 0x027c
3116 +
3117 +/*
3118 + * MGMT register offsets
3119 + */
3120 +#define TX_BASE_PTR5 0x0280
3121 +#define TX_MAX_CNT5 0x0284
3122 +#define TX_CTX_IDX5 0x0288
3123 +#define TX_DTX_IDX5 0x028c
3124 +
3125 +/*
3126 + * Queue register offset macros
3127 + */
3128 +#define TX_QUEUE_REG_OFFSET 0x10
3129 +#define TX_BASE_PTR(__x) TX_BASE_PTR0 + ((__x) * TX_QUEUE_REG_OFFSET)
3130 +#define TX_MAX_CNT(__x) TX_MAX_CNT0 + ((__x) * TX_QUEUE_REG_OFFSET)
3131 +#define TX_CTX_IDX(__x) TX_CTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3132 +#define TX_DTX_IDX(__x) TX_DTX_IDX0 + ((__x) * TX_QUEUE_REG_OFFSET)
3133 +
3134 +/*
3135 + * RX register offsets
3136 + */
3137 +#define RX_BASE_PTR 0x0290
3138 +#define RX_MAX_CNT 0x0294
3139 +#define RX_CRX_IDX 0x0298
3140 +#define RX_DRX_IDX 0x029c
3141 +
3142 +/*
3143 + * PBF_SYS_CTRL
3144 + * HOST_RAM_WRITE: enable Host program ram write selection
3145 + */
3146 +#define PBF_SYS_CTRL 0x0400
3147 +#define PBF_SYS_CTRL_READY FIELD32(0x00000080)
3148 +#define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
3149 +
3150 +/*
3151 + * PBF registers
3152 + * Most are for debug. Driver doesn't touch PBF register.
3153 + */
3154 +#define PBF_CFG 0x0408
3155 +#define PBF_MAX_PCNT 0x040c
3156 +#define PBF_CTRL 0x0410
3157 +#define PBF_INT_STA 0x0414
3158 +#define PBF_INT_ENA 0x0418
3159 +
3160 +/*
3161 + * BCN_OFFSET0:
3162 + */
3163 +#define BCN_OFFSET0 0x042c
3164 +#define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
3165 +#define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
3166 +#define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
3167 +#define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
3168 +
3169 +/*
3170 + * BCN_OFFSET1:
3171 + */
3172 +#define BCN_OFFSET1 0x0430
3173 +#define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
3174 +#define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
3175 +#define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
3176 +#define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
3177 +
3178 +/*
3179 + * PBF registers
3180 + * Most are for debug. Driver doesn't touch PBF register.
3181 + */
3182 +#define TXRXQ_PCNT 0x0438
3183 +#define PBF_DBG 0x043c
3184 +
3185 +/*
3186 + * MAC Control/Status Registers(CSR).
3187 + * Some values are set in TU, whereas 1 TU == 1024 us.
3188 + */
3189 +
3190 +/*
3191 + * MAC_CSR0: ASIC revision number.
3192 + * ASIC_REV: 0
3193 + * ASIC_VER: 2860
3194 + */
3195 +#define MAC_CSR0 0x1000
3196 +#define MAC_CSR0_ASIC_REV FIELD32(0x0000ffff)
3197 +#define MAC_CSR0_ASIC_VER FIELD32(0xffff0000)
3198 +
3199 +/*
3200 + * MAC_SYS_CTRL:
3201 + */
3202 +#define MAC_SYS_CTRL 0x1004
3203 +#define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
3204 +#define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
3205 +#define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
3206 +#define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
3207 +#define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
3208 +#define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
3209 +#define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
3210 +#define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
3211 +
3212 +/*
3213 + * MAC_ADDR_DW0: STA MAC register 0
3214 + */
3215 +#define MAC_ADDR_DW0 0x1008
3216 +#define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
3217 +#define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
3218 +#define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
3219 +#define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
3220 +
3221 +/*
3222 + * MAC_ADDR_DW1: STA MAC register 1
3223 + * UNICAST_TO_ME_MASK:
3224 + * Used to mask off bits from byte 5 of the MAC address
3225 + * to determine the UNICAST_TO_ME bit for RX frames.
3226 + * The full mask is complemented by BSS_ID_MASK:
3227 + * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
3228 + */
3229 +#define MAC_ADDR_DW1 0x100c
3230 +#define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
3231 +#define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
3232 +#define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
3233 +
3234 +/*
3235 + * MAC_BSSID_DW0: BSSID register 0
3236 + */
3237 +#define MAC_BSSID_DW0 0x1010
3238 +#define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
3239 +#define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
3240 +#define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
3241 +#define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
3242 +
3243 +/*
3244 + * MAC_BSSID_DW1: BSSID register 1
3245 + * BSS_ID_MASK:
3246 + * 0: 1-BSSID mode (BSS index = 0)
3247 + * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
3248 + * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
3249 + * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
3250 + * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
3251 + * BSSID. This will make sure that those bits will be ignored
3252 + * when determining the MY_BSS of RX frames.
3253 + */
3254 +#define MAC_BSSID_DW1 0x1014
3255 +#define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
3256 +#define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
3257 +#define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
3258 +#define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
3259 +
3260 +/*
3261 + * MAX_LEN_CFG: Maximum frame length register.
3262 + * MAX_MPDU: rt2860b max 16k bytes
3263 + * MAX_PSDU: Maximum PSDU length
3264 + * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
3265 + */
3266 +#define MAX_LEN_CFG 0x1018
3267 +#define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
3268 +#define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
3269 +#define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
3270 +#define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
3271 +
3272 +/*
3273 + * BBP_CSR_CFG: BBP serial control register
3274 + * VALUE: Register value to program into BBP
3275 + * REG_NUM: Selected BBP register
3276 + * READ_CONTROL: 0 write BBP, 1 read BBP
3277 + * BUSY: ASIC is busy executing BBP commands
3278 + * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
3279 + * BBP_RW_MODE: 0 serial, 1 paralell
3280 + */
3281 +#define BBP_CSR_CFG 0x101c
3282 +#define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
3283 +#define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
3284 +#define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
3285 +#define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
3286 +#define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
3287 +#define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
3288 +
3289 +/*
3290 + * RF_CSR_CFG0: RF control register
3291 + * REGID_AND_VALUE: Register value to program into RF
3292 + * BITWIDTH: Selected RF register
3293 + * STANDBYMODE: 0 high when standby, 1 low when standby
3294 + * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
3295 + * BUSY: ASIC is busy executing RF commands
3296 + */
3297 +#define RF_CSR_CFG0 0x1020
3298 +#define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
3299 +#define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
3300 +#define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
3301 +#define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
3302 +#define RF_CSR_CFG0_SEL FIELD32(0x40000000)
3303 +#define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
3304 +
3305 +/*
3306 + * RF_CSR_CFG1: RF control register
3307 + * REGID_AND_VALUE: Register value to program into RF
3308 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3309 + * 0: 3 system clock cycle (37.5usec)
3310 + * 1: 5 system clock cycle (62.5usec)
3311 + */
3312 +#define RF_CSR_CFG1 0x1024
3313 +#define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
3314 +#define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
3315 +
3316 +/*
3317 + * RF_CSR_CFG2: RF control register
3318 + * VALUE: Register value to program into RF
3319 + * RFGAP: Gap between BB_CONTROL_RF and RF_LE
3320 + * 0: 3 system clock cycle (37.5usec)
3321 + * 1: 5 system clock cycle (62.5usec)
3322 + */
3323 +#define RF_CSR_CFG2 0x1028
3324 +#define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
3325 +
3326 +/*
3327 + * LED_CFG: LED control
3328 + * color LED's:
3329 + * 0: off
3330 + * 1: blinking upon TX2
3331 + * 2: periodic slow blinking
3332 + * 3: always on
3333 + * LED polarity:
3334 + * 0: active low
3335 + * 1: active high
3336 + */
3337 +#define LED_CFG 0x102c
3338 +#define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
3339 +#define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
3340 +#define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
3341 +#define LED_CFG_R_LED_MODE FIELD32(0x03000000)
3342 +#define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
3343 +#define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
3344 +#define LED_CFG_LED_POLAR FIELD32(0x40000000)
3345 +
3346 +/*
3347 + * XIFS_TIME_CFG: MAC timing
3348 + * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
3349 + * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
3350 + * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
3351 + * when MAC doesn't reference BBP signal BBRXEND
3352 + * EIFS: unit 1us
3353 + * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
3354 + *
3355 + */
3356 +#define XIFS_TIME_CFG 0x1100
3357 +#define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
3358 +#define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
3359 +#define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
3360 +#define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
3361 +#define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
3362 +
3363 +/*
3364 + * BKOFF_SLOT_CFG:
3365 + */
3366 +#define BKOFF_SLOT_CFG 0x1104
3367 +#define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
3368 +#define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
3369 +
3370 +/*
3371 + * NAV_TIME_CFG:
3372 + */
3373 +#define NAV_TIME_CFG 0x1108
3374 +#define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
3375 +#define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
3376 +#define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
3377 +#define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
3378 +
3379 +/*
3380 + * CH_TIME_CFG: count as channel busy
3381 + */
3382 +#define CH_TIME_CFG 0x110c
3383 +
3384 +/*
3385 + * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
3386 + */
3387 +#define PBF_LIFE_TIMER 0x1110
3388 +
3389 +/*
3390 + * BCN_TIME_CFG:
3391 + * BEACON_INTERVAL: in unit of 1/16 TU
3392 + * TSF_TICKING: Enable TSF auto counting
3393 + * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
3394 + * BEACON_GEN: Enable beacon generator
3395 + */
3396 +#define BCN_TIME_CFG 0x1114
3397 +#define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
3398 +#define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
3399 +#define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
3400 +#define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
3401 +#define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
3402 +#define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
3403 +
3404 +/*
3405 + * TBTT_SYNC_CFG:
3406 + */
3407 +#define TBTT_SYNC_CFG 0x1118
3408 +
3409 +/*
3410 + * TSF_TIMER_DW0: Local lsb TSF timer, read-only
3411 + */
3412 +#define TSF_TIMER_DW0 0x111c
3413 +#define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
3414 +
3415 +/*
3416 + * TSF_TIMER_DW1: Local msb TSF timer, read-only
3417 + */
3418 +#define TSF_TIMER_DW1 0x1120
3419 +#define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
3420 +
3421 +/*
3422 + * TBTT_TIMER: TImer remains till next TBTT, read-only
3423 + */
3424 +#define TBTT_TIMER 0x1124
3425 +
3426 +/*
3427 + * INT_TIMER_CFG:
3428 + */
3429 +#define INT_TIMER_CFG 0x1128
3430 +
3431 +/*
3432 + * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
3433 + */
3434 +#define INT_TIMER_EN 0x112c
3435 +
3436 +/*
3437 + * CH_IDLE_STA: channel idle time
3438 + */
3439 +#define CH_IDLE_STA 0x1130
3440 +
3441 +/*
3442 + * CH_BUSY_STA: channel busy time
3443 + */
3444 +#define CH_BUSY_STA 0x1134
3445 +
3446 +/*
3447 + * MAC_STATUS_CFG:
3448 + * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
3449 + * if 1 or higher one of the 2 registers is busy.
3450 + */
3451 +#define MAC_STATUS_CFG 0x1200
3452 +#define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
3453 +
3454 +/*
3455 + * PWR_PIN_CFG:
3456 + */
3457 +#define PWR_PIN_CFG 0x1204
3458 +
3459 +/*
3460 + * AUTOWAKEUP_CFG: Manual power control / status register
3461 + * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
3462 + * AUTOWAKE: 0:sleep, 1:awake
3463 + */
3464 +#define AUTOWAKEUP_CFG 0x1208
3465 +#define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
3466 +#define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
3467 +#define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
3468 +
3469 +/*
3470 + * EDCA_AC0_CFG:
3471 + */
3472 +#define EDCA_AC0_CFG 0x1300
3473 +#define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
3474 +#define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
3475 +#define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
3476 +#define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
3477 +
3478 +/*
3479 + * EDCA_AC1_CFG:
3480 + */
3481 +#define EDCA_AC1_CFG 0x1304
3482 +#define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
3483 +#define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
3484 +#define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
3485 +#define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
3486 +
3487 +/*
3488 + * EDCA_AC2_CFG:
3489 + */
3490 +#define EDCA_AC2_CFG 0x1308
3491 +#define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
3492 +#define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
3493 +#define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
3494 +#define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
3495 +
3496 +/*
3497 + * EDCA_AC3_CFG:
3498 + */
3499 +#define EDCA_AC3_CFG 0x130c
3500 +#define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
3501 +#define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
3502 +#define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
3503 +#define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
3504 +
3505 +/*
3506 + * EDCA_TID_AC_MAP:
3507 + */
3508 +#define EDCA_TID_AC_MAP 0x1310
3509 +
3510 +/*
3511 + * TX_PWR_CFG_0:
3512 + */
3513 +#define TX_PWR_CFG_0 0x1314
3514 +#define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
3515 +#define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
3516 +#define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
3517 +#define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
3518 +#define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
3519 +#define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
3520 +#define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
3521 +#define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
3522 +
3523 +/*
3524 + * TX_PWR_CFG_1:
3525 + */
3526 +#define TX_PWR_CFG_1 0x1318
3527 +#define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
3528 +#define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
3529 +#define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
3530 +#define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
3531 +#define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
3532 +#define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
3533 +#define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
3534 +#define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
3535 +
3536 +/*
3537 + * TX_PWR_CFG_2:
3538 + */
3539 +#define TX_PWR_CFG_2 0x131c
3540 +#define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
3541 +#define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
3542 +#define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
3543 +#define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
3544 +#define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
3545 +#define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
3546 +#define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
3547 +#define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
3548 +
3549 +/*
3550 + * TX_PWR_CFG_3:
3551 + */
3552 +#define TX_PWR_CFG_3 0x1320
3553 +#define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
3554 +#define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
3555 +#define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
3556 +#define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
3557 +#define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
3558 +#define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
3559 +#define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
3560 +#define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
3561 +
3562 +/*
3563 + * TX_PWR_CFG_4:
3564 + */
3565 +#define TX_PWR_CFG_4 0x1324
3566 +#define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
3567 +#define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
3568 +#define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
3569 +#define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
3570 +
3571 +/*
3572 + * TX_PIN_CFG:
3573 + */
3574 +#define TX_PIN_CFG 0x1328
3575 +#define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
3576 +#define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
3577 +#define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
3578 +#define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
3579 +#define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
3580 +#define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
3581 +#define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
3582 +#define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
3583 +#define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
3584 +#define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
3585 +#define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
3586 +#define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
3587 +#define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
3588 +#define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
3589 +#define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
3590 +#define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
3591 +#define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
3592 +#define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
3593 +#define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
3594 +#define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
3595 +
3596 +/*
3597 + * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
3598 + */
3599 +#define TX_BAND_CFG 0x132c
3600 +#define TX_BAND_CFG_A FIELD32(0x00000002)
3601 +#define TX_BAND_CFG_BG FIELD32(0x00000004)
3602 +
3603 +/*
3604 + * TX_SW_CFG0:
3605 + */
3606 +#define TX_SW_CFG0 0x1330
3607 +
3608 +/*
3609 + * TX_SW_CFG1:
3610 + */
3611 +#define TX_SW_CFG1 0x1334
3612 +
3613 +/*
3614 + * TX_SW_CFG2:
3615 + */
3616 +#define TX_SW_CFG2 0x1338
3617 +
3618 +/*
3619 + * TXOP_THRES_CFG:
3620 + */
3621 +#define TXOP_THRES_CFG 0x133c
3622 +
3623 +/*
3624 + * TXOP_CTRL_CFG:
3625 + */
3626 +#define TXOP_CTRL_CFG 0x1340
3627 +
3628 +/*
3629 + * TX_RTS_CFG:
3630 + * RTS_THRES: unit:byte
3631 + * RTS_FBK_EN: enable rts rate fallback
3632 + */
3633 +#define TX_RTS_CFG 0x1344
3634 +#define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
3635 +#define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
3636 +#define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
3637 +
3638 +/*
3639 + * TX_TIMEOUT_CFG:
3640 + * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
3641 + * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
3642 + * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
3643 + * it is recommended that:
3644 + * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
3645 + */
3646 +#define TX_TIMEOUT_CFG 0x1348
3647 +#define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
3648 +#define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
3649 +#define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
3650 +
3651 +/*
3652 + * TX_RTY_CFG:
3653 + * SHORT_RTY_LIMIT: short retry limit
3654 + * LONG_RTY_LIMIT: long retry limit
3655 + * LONG_RTY_THRE: Long retry threshoold
3656 + * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
3657 + * 0:expired by retry limit, 1: expired by mpdu life timer
3658 + * AGG_RTY_MODE: Aggregate MPDU retry mode
3659 + * 0:expired by retry limit, 1: expired by mpdu life timer
3660 + * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
3661 + */
3662 +#define TX_RTY_CFG 0x134c
3663 +#define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
3664 +#define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
3665 +#define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
3666 +#define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
3667 +#define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
3668 +#define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
3669 +
3670 +/*
3671 + * TX_LINK_CFG:
3672 + * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
3673 + * MFB_ENABLE: TX apply remote MFB 1:enable
3674 + * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
3675 + * 0: not apply remote remote unsolicit (MFS=7)
3676 + * TX_MRQ_EN: MCS request TX enable
3677 + * TX_RDG_EN: RDG TX enable
3678 + * TX_CF_ACK_EN: Piggyback CF-ACK enable
3679 + * REMOTE_MFB: remote MCS feedback
3680 + * REMOTE_MFS: remote MCS feedback sequence number
3681 + */
3682 +#define TX_LINK_CFG 0x1350
3683 +#define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
3684 +#define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
3685 +#define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
3686 +#define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
3687 +#define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
3688 +#define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
3689 +#define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
3690 +#define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
3691 +
3692 +/*
3693 + * HT_FBK_CFG0:
3694 + */
3695 +#define HT_FBK_CFG0 0x1354
3696 +#define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
3697 +#define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
3698 +#define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
3699 +#define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
3700 +#define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
3701 +#define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
3702 +#define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
3703 +#define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
3704 +
3705 +/*
3706 + * HT_FBK_CFG1:
3707 + */
3708 +#define HT_FBK_CFG1 0x1358
3709 +#define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
3710 +#define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
3711 +#define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
3712 +#define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
3713 +#define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
3714 +#define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
3715 +#define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
3716 +#define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
3717 +
3718 +/*
3719 + * LG_FBK_CFG0:
3720 + */
3721 +#define LG_FBK_CFG0 0x135c
3722 +#define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
3723 +#define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
3724 +#define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
3725 +#define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
3726 +#define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
3727 +#define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
3728 +#define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
3729 +#define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
3730 +
3731 +/*
3732 + * LG_FBK_CFG1:
3733 + */
3734 +#define LG_FBK_CFG1 0x1360
3735 +#define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
3736 +#define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
3737 +#define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
3738 +#define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
3739 +
3740 +/*
3741 + * CCK_PROT_CFG: CCK Protection
3742 + * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
3743 + * PROTECT_CTRL: Protection control frame type for CCK TX
3744 + * 0:none, 1:RTS/CTS, 2:CTS-to-self
3745 + * PROTECT_NAV: TXOP protection type for CCK TX
3746 + * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
3747 + * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
3748 + * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
3749 + * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
3750 + * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
3751 + * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
3752 + * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
3753 + * RTS_TH_EN: RTS threshold enable on CCK TX
3754 + */
3755 +#define CCK_PROT_CFG 0x1364
3756 +#define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3757 +#define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3758 +#define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3759 +#define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3760 +#define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3761 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3762 +#define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3763 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3764 +#define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3765 +#define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3766 +
3767 +/*
3768 + * OFDM_PROT_CFG: OFDM Protection
3769 + */
3770 +#define OFDM_PROT_CFG 0x1368
3771 +#define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3772 +#define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3773 +#define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3774 +#define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3775 +#define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3776 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3777 +#define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3778 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3779 +#define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3780 +#define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3781 +
3782 +/*
3783 + * MM20_PROT_CFG: MM20 Protection
3784 + */
3785 +#define MM20_PROT_CFG 0x136c
3786 +#define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3787 +#define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3788 +#define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3789 +#define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3790 +#define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3791 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3792 +#define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3793 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3794 +#define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3795 +#define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3796 +
3797 +/*
3798 + * MM40_PROT_CFG: MM40 Protection
3799 + */
3800 +#define MM40_PROT_CFG 0x1370
3801 +#define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3802 +#define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3803 +#define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3804 +#define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3805 +#define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3806 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3807 +#define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3808 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3809 +#define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3810 +#define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3811 +
3812 +/*
3813 + * GF20_PROT_CFG: GF20 Protection
3814 + */
3815 +#define GF20_PROT_CFG 0x1374
3816 +#define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3817 +#define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3818 +#define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3819 +#define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3820 +#define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3821 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3822 +#define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3823 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3824 +#define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3825 +#define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3826 +
3827 +/*
3828 + * GF40_PROT_CFG: GF40 Protection
3829 + */
3830 +#define GF40_PROT_CFG 0x1378
3831 +#define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
3832 +#define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
3833 +#define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
3834 +#define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
3835 +#define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
3836 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
3837 +#define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
3838 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
3839 +#define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
3840 +#define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
3841 +
3842 +/*
3843 + * EXP_CTS_TIME:
3844 + */
3845 +#define EXP_CTS_TIME 0x137c
3846 +
3847 +/*
3848 + * EXP_ACK_TIME:
3849 + */
3850 +#define EXP_ACK_TIME 0x1380
3851 +
3852 +/*
3853 + * RX_FILTER_CFG: RX configuration register.
3854 + */
3855 +#define RX_FILTER_CFG 0x1400
3856 +#define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
3857 +#define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
3858 +#define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
3859 +#define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
3860 +#define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
3861 +#define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
3862 +#define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
3863 +#define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
3864 +#define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
3865 +#define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
3866 +#define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
3867 +#define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
3868 +#define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
3869 +#define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
3870 +#define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
3871 +#define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
3872 +#define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
3873 +
3874 +/*
3875 + * AUTO_RSP_CFG:
3876 + * AUTORESPONDER: 0: disable, 1: enable
3877 + * BAC_ACK_POLICY: 0:long, 1:short preamble
3878 + * CTS_40_MMODE: Response CTS 40MHz duplicate mode
3879 + * CTS_40_MREF: Response CTS 40MHz duplicate mode
3880 + * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
3881 + * DUAL_CTS_EN: Power bit value in control frame
3882 + * ACK_CTS_PSM_BIT:Power bit value in control frame
3883 + */
3884 +#define AUTO_RSP_CFG 0x1404
3885 +#define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
3886 +#define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
3887 +#define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
3888 +#define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
3889 +#define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
3890 +#define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
3891 +#define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
3892 +
3893 +/*
3894 + * LEGACY_BASIC_RATE:
3895 + */
3896 +#define LEGACY_BASIC_RATE 0x1408
3897 +
3898 +/*
3899 + * HT_BASIC_RATE:
3900 + */
3901 +#define HT_BASIC_RATE 0x140c
3902 +
3903 +/*
3904 + * HT_CTRL_CFG:
3905 + */
3906 +#define HT_CTRL_CFG 0x1410
3907 +
3908 +/*
3909 + * SIFS_COST_CFG:
3910 + */
3911 +#define SIFS_COST_CFG 0x1414
3912 +
3913 +/*
3914 + * RX_PARSER_CFG:
3915 + * Set NAV for all received frames
3916 + */
3917 +#define RX_PARSER_CFG 0x1418
3918 +
3919 +/*
3920 + * TX_SEC_CNT0:
3921 + */
3922 +#define TX_SEC_CNT0 0x1500
3923 +
3924 +/*
3925 + * RX_SEC_CNT0:
3926 + */
3927 +#define RX_SEC_CNT0 0x1504
3928 +
3929 +/*
3930 + * CCMP_FC_MUTE:
3931 + */
3932 +#define CCMP_FC_MUTE 0x1508
3933 +
3934 +/*
3935 + * TXOP_HLDR_ADDR0:
3936 + */
3937 +#define TXOP_HLDR_ADDR0 0x1600
3938 +
3939 +/*
3940 + * TXOP_HLDR_ADDR1:
3941 + */
3942 +#define TXOP_HLDR_ADDR1 0x1604
3943 +
3944 +/*
3945 + * TXOP_HLDR_ET:
3946 + */
3947 +#define TXOP_HLDR_ET 0x1608
3948 +
3949 +/*
3950 + * QOS_CFPOLL_RA_DW0:
3951 + */
3952 +#define QOS_CFPOLL_RA_DW0 0x160c
3953 +
3954 +/*
3955 + * QOS_CFPOLL_RA_DW1:
3956 + */
3957 +#define QOS_CFPOLL_RA_DW1 0x1610
3958 +
3959 +/*
3960 + * QOS_CFPOLL_QC:
3961 + */
3962 +#define QOS_CFPOLL_QC 0x1614
3963 +
3964 +/*
3965 + * RX_STA_CNT0: RX PLCP error count & RX CRC error count
3966 + */
3967 +#define RX_STA_CNT0 0x1700
3968 +#define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
3969 +#define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
3970 +
3971 +/*
3972 + * RX_STA_CNT1: RX False CCA count & RX LONG frame count
3973 + */
3974 +#define RX_STA_CNT1 0x1704
3975 +#define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
3976 +#define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
3977 +
3978 +/*
3979 + * RX_STA_CNT2:
3980 + */
3981 +#define RX_STA_CNT2 0x1708
3982 +#define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
3983 +#define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
3984 +
3985 +/*
3986 + * TX_STA_CNT0: TX Beacon count
3987 + */
3988 +#define TX_STA_CNT0 0x170c
3989 +#define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
3990 +#define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
3991 +
3992 +/*
3993 + * TX_STA_CNT1: TX tx count
3994 + */
3995 +#define TX_STA_CNT1 0x1710
3996 +#define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
3997 +#define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
3998 +
3999 +/*
4000 + * TX_STA_CNT2: TX tx count
4001 + */
4002 +#define TX_STA_CNT2 0x1714
4003 +#define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
4004 +#define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
4005 +
4006 +/*
4007 + * TX_STA_FIFO: TX Result for specific PID status fifo register
4008 + */
4009 +#define TX_STA_FIFO 0x1718
4010 +#define TX_STA_FIFO_VALID FIELD32(0x00000001)
4011 +#define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
4012 +#define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
4013 +#define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
4014 +#define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
4015 +#define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
4016 +#define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
4017 +
4018 +/*
4019 + * TX_AGG_CNT: Debug counter
4020 + */
4021 +#define TX_AGG_CNT 0x171c
4022 +#define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
4023 +#define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
4024 +
4025 +/*
4026 + * TX_AGG_CNT0:
4027 + */
4028 +#define TX_AGG_CNT0 0x1720
4029 +#define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
4030 +#define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
4031 +
4032 +/*
4033 + * TX_AGG_CNT1:
4034 + */
4035 +#define TX_AGG_CNT1 0x1724
4036 +#define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
4037 +#define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
4038 +
4039 +/*
4040 + * TX_AGG_CNT2:
4041 + */
4042 +#define TX_AGG_CNT2 0x1728
4043 +#define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
4044 +#define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
4045 +
4046 +/*
4047 + * TX_AGG_CNT3:
4048 + */
4049 +#define TX_AGG_CNT3 0x172c
4050 +#define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
4051 +#define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
4052 +
4053 +/*
4054 + * TX_AGG_CNT4:
4055 + */
4056 +#define TX_AGG_CNT4 0x1730
4057 +#define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
4058 +#define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
4059 +
4060 +/*
4061 + * TX_AGG_CNT5:
4062 + */
4063 +#define TX_AGG_CNT5 0x1734
4064 +#define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
4065 +#define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
4066 +
4067 +/*
4068 + * TX_AGG_CNT6:
4069 + */
4070 +#define TX_AGG_CNT6 0x1738
4071 +#define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
4072 +#define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
4073 +
4074 +/*
4075 + * TX_AGG_CNT7:
4076 + */
4077 +#define TX_AGG_CNT7 0x173c
4078 +#define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
4079 +#define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
4080 +
4081 +/*
4082 + * MPDU_DENSITY_CNT:
4083 + * TX_ZERO_DEL: TX zero length delimiter count
4084 + * RX_ZERO_DEL: RX zero length delimiter count
4085 + */
4086 +#define MPDU_DENSITY_CNT 0x1740
4087 +#define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
4088 +#define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
4089 +
4090 +/*
4091 + * Security key table memory, base address = 0x1800
4092 + */
4093 +struct hw_pairwise_ta_entry {
4094 + u8 address[6];
4095 + u8 reserved[2];
4096 +} __attribute__ ((packed));
4097 +
4098 +struct wcid_entry {
4099 + u8 rx_ba_bitmat7;
4100 + u8 rx_ba_bitmat0;
4101 + u8 mac[6];
4102 +} __attribute__ ((packed));
4103 +
4104 +struct hw_key_entry {
4105 + u8 key[16];
4106 + u8 tx_mic[8];
4107 + u8 rx_mic[8];
4108 +} __attribute__ ((packed));
4109 +
4110 +/*
4111 + * Security key table memory.
4112 + * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
4113 + * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
4114 + * PAIRWISE_IVEIV_TABLE_BASE: 8-byte * 256-entry
4115 + * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
4116 + * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
4117 + * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
4118 + * SHARED_KEY_MODE_BASE: 32-byte * 16-entry
4119 + */
4120 +#define MAC_WCID_BASE 0x1800
4121 +#define PAIRWISE_KEY_TABLE_BASE 0x4000
4122 +#define PAIRWISE_IVEIV_TABLE_BASE 0x6000
4123 +#define MAC_IVEIV_TABLE_BASE 0x6000
4124 +#define MAC_WCID_ATTRIBUTE_BASE 0x6800
4125 +#define SHARED_KEY_TABLE_BASE 0x6c00
4126 +#define SHARED_KEY_MODE_BASE 0x7000
4127 +
4128 +#define SHARED_KEY_ENTRY(__idx) \
4129 + ( SHARED_KEY_TABLE_BASE + \
4130 + ((__idx) * sizeof(struct hw_key_entry)) )
4131 +#define SHARED_KEY_MODE_ENTRY(__idx) \
4132 + ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
4133 +#define PAIRWISE_KEY_ENTRY(__idx) \
4134 + ( PAIRWISE_KEY_TABLE_BASE + \
4135 + ((__idx) * sizeof(struct hw_key_entry)) )
4136 +
4137 +#define MAC_WCID_ENTRY(__idx) \
4138 + ( MAC_WCID_BASE + (2 * sizeof(u32) * (__idx)) )
4139 +#define MAC_WCID_ATTR_ENTRY(__idx) \
4140 + ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
4141 +
4142 +/*
4143 + * MAC_WCID_ATTRIBUTE:
4144 + * KEYTAB: 0: shared key table, 1: pairwise key table
4145 + * BSS_IDX: multipleBSS index for the WCID
4146 + */
4147 +#define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
4148 +#define MAC_WCID_ATTRIBUTE_PAIRKEY_MODE FIELD32(0x0000000e)
4149 +#define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
4150 +#define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
4151 +
4152 +/*
4153 + * SHARED_KEY_MODE:
4154 + */
4155 +#define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
4156 +#define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
4157 +#define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
4158 +#define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
4159 +#define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
4160 +#define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
4161 +#define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
4162 +#define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
4163 +
4164 +/*
4165 + * HOST-MCU communication
4166 + */
4167 +
4168 +/*
4169 + * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
4170 + */
4171 +#define H2M_MAILBOX_CSR 0x7010
4172 +#define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
4173 +#define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
4174 +#define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
4175 +#define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
4176 +
4177 +/*
4178 + * H2M_MAILBOX_CID:
4179 + */
4180 +#define H2M_MAILBOX_CID 0x7014
4181 +
4182 +/*
4183 + * H2M_MAILBOX_STATUS:
4184 + */
4185 +#define H2M_MAILBOX_STATUS 0x701c
4186 +
4187 +/*
4188 + * H2M_INT_SRC:
4189 + */
4190 +#define H2M_INT_SRC 0x7024
4191 +
4192 +/*
4193 + * H2M_BBP_AGENT:
4194 + */
4195 +#define H2M_BBP_AGENT 0x7028
4196 +
4197 +/*
4198 + * MCU_LEDCS: LED control for MCU Mailbox.
4199 + */
4200 +#define MCU_LEDCS_LED_MODE FIELD8(0x1f)
4201 +#define MCU_LEDCS_POLARITY FIELD8(0x01)
4202 +
4203 +/*
4204 + * HW_CS_CTS_BASE:
4205 + * Carrier-sense CTS frame base address.
4206 + * It's where mac stores carrier-sense frame for carrier-sense function.
4207 + */
4208 +#define HW_CS_CTS_BASE 0x7700
4209 +
4210 +/*
4211 + * HW_DFS_CTS_BASE:
4212 + * FS CTS frame base address. It's where mac stores CTS frame for DFS.
4213 + */
4214 +#define HW_DFS_CTS_BASE 0x7780
4215 +
4216 +/*
4217 + * TXRX control registers - base address 0x3000
4218 + */
4219 +
4220 +/*
4221 + * TXRX_CSR1:
4222 + * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
4223 + */
4224 +#define TXRX_CSR1 0x77d0
4225 +
4226 +/*
4227 + * HW_DEBUG_SETTING_BASE:
4228 + * since NULL frame won't be that long (256 byte)
4229 + * We steal 16 tail bytes to save debugging settings
4230 + */
4231 +#define HW_DEBUG_SETTING_BASE 0x77f0
4232 +#define HW_DEBUG_SETTING_BASE2 0x7770
4233 +
4234 +/*
4235 + * HW_BEACON_BASE
4236 + * In order to support maximum 8 MBSS and its maximum length
4237 + * is 512 bytes for each beacon
4238 + * Three section discontinue memory segments will be used.
4239 + * 1. The original region for BCN 0~3
4240 + * 2. Extract memory from FCE table for BCN 4~5
4241 + * 3. Extract memory from Pair-wise key table for BCN 6~7
4242 + * It occupied those memory of wcid 238~253 for BCN 6
4243 + * and wcid 222~237 for BCN 7
4244 + *
4245 + * IMPORTANT NOTE: Not sure why legacy driver does this,
4246 + * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
4247 + */
4248 +#define HW_BEACON_BASE0 0x7800
4249 +#define HW_BEACON_BASE1 0x7a00
4250 +#define HW_BEACON_BASE2 0x7c00
4251 +#define HW_BEACON_BASE3 0x7e00
4252 +#define HW_BEACON_BASE4 0x7200
4253 +#define HW_BEACON_BASE5 0x7400
4254 +#define HW_BEACON_BASE6 0x5dc0
4255 +#define HW_BEACON_BASE7 0x5bc0
4256 +
4257 +#define HW_BEACON_OFFSET(__index) \
4258 + ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
4259 + (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
4260 + (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
4261 +
4262 +/*
4263 + * 8051 firmware image.
4264 + */
4265 +#define FIRMWARE_RT2860 "rt2860.bin"
4266 +#define FIRMWARE_IMAGE_BASE 0x2000
4267 +
4268 +/*
4269 + * BBP registers.
4270 + * The wordsize of the BBP is 8 bits.
4271 + */
4272 +
4273 +/*
4274 + * BBP 1: TX Antenna
4275 + */
4276 +#define BBP1_TX_POWER FIELD8(0x07)
4277 +#define BBP1_TX_ANTENNA FIELD8(0x18)
4278 +
4279 +/*
4280 + * BBP 3: RX Antenna
4281 + */
4282 +#define BBP3_RX_ANTENNA FIELD8(0x18)
4283 +
4284 +/*
4285 + * RF registers
4286 + */
4287 +
4288 +/*
4289 + * RF 2
4290 + */
4291 +#define RF2_ANTENNA_RX2 FIELD32(0x00000040)
4292 +#define RF2_ANTENNA_TX1 FIELD32(0x00004000)
4293 +#define RF2_ANTENNA_RX1 FIELD32(0x00020000)
4294 +
4295 +/*
4296 + * RF 3
4297 + */
4298 +#define RF3_TXPOWER_G FIELD32(0x00003e00)
4299 +#define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
4300 +#define RF3_TXPOWER_A FIELD32(0x00003c00)
4301 +
4302 +/*
4303 + * RF 4
4304 + */
4305 +#define RF4_TXPOWER_G FIELD32(0x000007c0)
4306 +#define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
4307 +#define RF4_TXPOWER_A FIELD32(0x00000780)
4308 +#define RF4_FREQ_OFFSET FIELD32(0x001f8000)
4309 +#define RF4_BW40 FIELD32(0x00200000)
4310 +
4311 +/*
4312 + * EEPROM content.
4313 + * The wordsize of the EEPROM is 16 bits.
4314 + */
4315 +
4316 +/*
4317 + * EEPROM Version
4318 + */
4319 +#define EEPROM_VERSION 0x0001
4320 +#define EEPROM_VERSION_FAE FIELD16(0x00ff)
4321 +#define EEPROM_VERSION_VERSION FIELD16(0xff00)
4322 +
4323 +/*
4324 + * HW MAC address.
4325 + */
4326 +#define EEPROM_MAC_ADDR_0 0x0002
4327 +#define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
4328 +#define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
4329 +#define EEPROM_MAC_ADDR_1 0x0003
4330 +#define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
4331 +#define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
4332 +#define EEPROM_MAC_ADDR_2 0x0004
4333 +#define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
4334 +#define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
4335 +
4336 +/*
4337 + * EEPROM ANTENNA config
4338 + * RXPATH: 1: 1R, 2: 2R, 3: 3R
4339 + * TXPATH: 1: 1T, 2: 2T
4340 + */
4341 +#define EEPROM_ANTENNA 0x001a
4342 +#define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
4343 +#define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
4344 +#define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
4345 +
4346 +/*
4347 + * EEPROM NIC config
4348 + * CARDBUS_ACCEL: 0 - enable, 1 - disable
4349 + */
4350 +#define EEPROM_NIC 0x001b
4351 +#define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
4352 +#define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
4353 +#define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
4354 +#define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
4355 +#define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
4356 +#define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
4357 +#define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
4358 +#define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
4359 +#define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
4360 +#define EEPROM_NIC_BW40M_A FIELD16(0x0200)
4361 +
4362 +/*
4363 + * EEPROM frequency
4364 + */
4365 +#define EEPROM_FREQ 0x001d
4366 +#define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
4367 +#define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
4368 +#define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
4369 +
4370 +/*
4371 + * EEPROM LED
4372 + * POLARITY_RDY_G: Polarity RDY_G setting.
4373 + * POLARITY_RDY_A: Polarity RDY_A setting.
4374 + * POLARITY_ACT: Polarity ACT setting.
4375 + * POLARITY_GPIO_0: Polarity GPIO0 setting.
4376 + * POLARITY_GPIO_1: Polarity GPIO1 setting.
4377 + * POLARITY_GPIO_2: Polarity GPIO2 setting.
4378 + * POLARITY_GPIO_3: Polarity GPIO3 setting.
4379 + * POLARITY_GPIO_4: Polarity GPIO4 setting.
4380 + * LED_MODE: Led mode.
4381 + */
4382 +#define EEPROM_LED1 0x001e
4383 +#define EEPROM_LED2 0x001f
4384 +#define EEPROM_LED3 0x0020
4385 +#define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
4386 +#define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
4387 +#define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
4388 +#define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
4389 +#define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
4390 +#define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
4391 +#define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
4392 +#define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
4393 +#define EEPROM_LED_LED_MODE FIELD16(0x1f00)
4394 +
4395 +/*
4396 + * EEPROM LNA
4397 + */
4398 +#define EEPROM_LNA 0x0022
4399 +#define EEPROM_LNA_BG FIELD16(0x00ff)
4400 +#define EEPROM_LNA_A0 FIELD16(0xff00)
4401 +
4402 +/*
4403 + * EEPROM RSSI BG offset
4404 + */
4405 +#define EEPROM_RSSI_BG 0x0023
4406 +#define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
4407 +#define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
4408 +
4409 +/*
4410 + * EEPROM RSSI BG2 offset
4411 + */
4412 +#define EEPROM_RSSI_BG2 0x0024
4413 +#define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
4414 +#define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
4415 +
4416 +/*
4417 + * EEPROM RSSI A offset
4418 + */
4419 +#define EEPROM_RSSI_A 0x0025
4420 +#define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
4421 +#define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
4422 +
4423 +/*
4424 + * EEPROM RSSI A2 offset
4425 + */
4426 +#define EEPROM_RSSI_A2 0x0026
4427 +#define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
4428 +#define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
4429 +
4430 +/*
4431 + * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
4432 + * This is delta in 40MHZ.
4433 + * VALUE: Tx Power dalta value (MAX=4)
4434 + * TYPE: 1: Plus the delta value, 0: minus the delta value
4435 + * TXPOWER: Enable:
4436 + */
4437 +#define EEPROM_TXPOWER_DELTA 0x0028
4438 +#define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
4439 +#define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
4440 +#define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
4441 +
4442 +/*
4443 + * EEPROM TXPOWER 802.11G
4444 + */
4445 +#define EEPROM_TXPOWER_BG1 0x0029
4446 +#define EEPROM_TXPOWER_BG2 0x0030
4447 +#define EEPROM_TXPOWER_BG_SIZE 7
4448 +#define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
4449 +#define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
4450 +
4451 +/*
4452 + * EEPROM TXPOWER 802.11A
4453 + */
4454 +#define EEPROM_TXPOWER_A1 0x003c
4455 +#define EEPROM_TXPOWER_A2 0x0053
4456 +#define EEPROM_TXPOWER_A_SIZE 6
4457 +#define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
4458 +#define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
4459 +
4460 +/*
4461 + * EEPROM TXpower byrate: 20MHZ power
4462 + */
4463 +#define EEPROM_TXPOWER_BYRATE 0x006f
4464 +
4465 +/*
4466 + * EEPROM BBP.
4467 + */
4468 +#define EEPROM_BBP_START 0x0078
4469 +#define EEPROM_BBP_SIZE 16
4470 +#define EEPROM_BBP_VALUE FIELD16(0x00ff)
4471 +#define EEPROM_BBP_REG_ID FIELD16(0xff00)
4472 +
4473 +/*
4474 + * MCU mailbox commands.
4475 + */
4476 +#define MCU_SLEEP 0x30
4477 +#define MCU_WAKEUP 0x31
4478 +#define MCU_LED 0x50
4479 +#define MCU_LED_STRENGTH 0x51
4480 +#define MCU_LED_1 0x52
4481 +#define MCU_LED_2 0x53
4482 +#define MCU_LED_3 0x54
4483 +#define MCU_RADAR 0x60
4484 +#define MCU_BOOT_SIGNAL 0x72
4485 +
4486 +/*
4487 + * DMA descriptor defines.
4488 + */
4489 +#define TXD_DESC_SIZE ( 4 * sizeof(__le32) )
4490 +#define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4491 +#define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
4492 +#define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
4493 +
4494 +/*
4495 + * TX descriptor format for TX, PRIO and Beacon Ring.
4496 + */
4497 +
4498 +/*
4499 + * Word0
4500 + */
4501 +#define TXD_W0_SD_PTR0 FIELD32(0xffffffff)
4502 +
4503 +/*
4504 + * Word1
4505 + */
4506 +#define TXD_W1_SD_LEN1 FIELD32(0x00003fff)
4507 +#define TXD_W1_LAST_SEC1 FIELD32(0x00004000)
4508 +#define TXD_W1_BURST FIELD32(0x00008000)
4509 +#define TXD_W1_SD_LEN0 FIELD32(0x3fff0000)
4510 +#define TXD_W1_LAST_SEC0 FIELD32(0x40000000)
4511 +#define TXD_W1_DMA_DONE FIELD32(0x80000000)
4512 +
4513 +/*
4514 + * Word2
4515 + */
4516 +#define TXD_W2_SD_PTR1 FIELD32(0xffffffff)
4517 +
4518 +/*
4519 + * Word3
4520 + * WIV: Wireless Info Valid. 1: Driver filled WI, 0: DMA needs to copy WI
4521 + * QSEL: Select on-chip FIFO ID for 2nd-stage output scheduler.
4522 + * 0:MGMT, 1:HCCA 2:EDCA
4523 + */
4524 +#define TXD_W3_WIV FIELD32(0x01000000)
4525 +#define TXD_W3_QSEL FIELD32(0x06000000)
4526 +#define TXD_W3_TCO FIELD32(0x20000000)
4527 +#define TXD_W3_UCO FIELD32(0x40000000)
4528 +#define TXD_W3_ICO FIELD32(0x80000000)
4529 +
4530 +/*
4531 + * TX WI structure
4532 + */
4533 +
4534 +/*
4535 + * Word0
4536 + * FRAG: 1 To inform TKIP engine this is a fragment.
4537 + * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
4538 + * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
4539 + * BW: Channel bandwidth 20MHz or 40 MHz
4540 + * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
4541 + */
4542 +#define TXWI_W0_FRAG FIELD32(0x00000001)
4543 +#define TXWI_W0_MIMO_PS FIELD32(0x00000002)
4544 +#define TXWI_W0_CF_ACK FIELD32(0x00000004)
4545 +#define TXWI_W0_TS FIELD32(0x00000008)
4546 +#define TXWI_W0_AMPDU FIELD32(0x00000010)
4547 +#define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
4548 +#define TXWI_W0_TX_OP FIELD32(0x00000300)
4549 +#define TXWI_W0_MCS FIELD32(0x007f0000)
4550 +#define TXWI_W0_BW FIELD32(0x00800000)
4551 +#define TXWI_W0_SHORT_GI FIELD32(0x01000000)
4552 +#define TXWI_W0_STBC FIELD32(0x06000000)
4553 +#define TXWI_W0_IFS FIELD32(0x08000000)
4554 +#define TXWI_W0_PHYMODE FIELD32(0xc0000000)
4555 +
4556 +/*
4557 + * Word1
4558 + */
4559 +#define TXWI_W1_ACK FIELD32(0x00000001)
4560 +#define TXWI_W1_NSEQ FIELD32(0x00000002)
4561 +#define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
4562 +#define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
4563 +#define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4564 +#define TXWI_W1_PACKETID FIELD32(0xf0000000)
4565 +
4566 +/*
4567 + * Word2
4568 + */
4569 +#define TXWI_W2_IV FIELD32(0xffffffff)
4570 +
4571 +/*
4572 + * Word3
4573 + */
4574 +#define TXWI_W3_EIV FIELD32(0xffffffff)
4575 +
4576 +/*
4577 + * RX descriptor format for RX Ring.
4578 + */
4579 +
4580 +/*
4581 + * Word0
4582 + */
4583 +#define RXD_W0_SDP0 FIELD32(0xffffffff)
4584 +
4585 +/*
4586 + * Word1
4587 + */
4588 +#define RXD_W1_SDL1 FIELD32(0x00003fff)
4589 +#define RXD_W1_SDL0 FIELD32(0x3fff0000)
4590 +#define RXD_W1_LS0 FIELD32(0x40000000)
4591 +#define RXD_W1_DMA_DONE FIELD32(0x80000000)
4592 +
4593 +/*
4594 + * Word2
4595 + */
4596 +#define RXD_W2_SDP1 FIELD32(0xffffffff)
4597 +
4598 +/*
4599 + * Word3
4600 + * AMSDU: RX with 802.3 header, not 802.11 header.
4601 + * DECRYPTED: This frame is being decrypted.
4602 + */
4603 +#define RXD_W3_BA FIELD32(0x00000001)
4604 +#define RXD_W3_DATA FIELD32(0x00000002)
4605 +#define RXD_W3_NULLDATA FIELD32(0x00000004)
4606 +#define RXD_W3_FRAG FIELD32(0x00000008)
4607 +#define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
4608 +#define RXD_W3_MULTICAST FIELD32(0x00000020)
4609 +#define RXD_W3_BROADCAST FIELD32(0x00000040)
4610 +#define RXD_W3_MY_BSS FIELD32(0x00000080)
4611 +#define RXD_W3_CRC_ERROR FIELD32(0x00000100)
4612 +#define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
4613 +#define RXD_W3_AMSDU FIELD32(0x00000800)
4614 +#define RXD_W3_HTC FIELD32(0x00001000)
4615 +#define RXD_W3_RSSI FIELD32(0x00002000)
4616 +#define RXD_W3_L2PAD FIELD32(0x00004000)
4617 +#define RXD_W3_AMPDU FIELD32(0x00008000)
4618 +#define RXD_W3_DECRYPTED FIELD32(0x00010000)
4619 +#define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
4620 +#define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
4621 +
4622 +/*
4623 + * RX WI structure
4624 + */
4625 +
4626 +/*
4627 + * Word0
4628 + */
4629 +#define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
4630 +#define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
4631 +#define RXWI_W0_BSSID FIELD32(0x00001c00)
4632 +#define RXWI_W0_UDF FIELD32(0x0000e000)
4633 +#define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
4634 +#define RXWI_W0_TID FIELD32(0xf0000000)
4635 +
4636 +/*
4637 + * Word1
4638 + */
4639 +#define RXWI_W1_FRAG FIELD32(0x0000000f)
4640 +#define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
4641 +#define RXWI_W1_MCS FIELD32(0x007f0000)
4642 +#define RXWI_W1_BW FIELD32(0x00800000)
4643 +#define RXWI_W1_SHORT_GI FIELD32(0x01000000)
4644 +#define RXWI_W1_STBC FIELD32(0x06000000)
4645 +#define RXWI_W1_PHYMODE FIELD32(0xc0000000)
4646 +
4647 +/*
4648 + * Word2
4649 + */
4650 +#define RXWI_W2_RSSI0 FIELD32(0x000000ff)
4651 +#define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
4652 +#define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
4653 +
4654 +/*
4655 + * Word3
4656 + */
4657 +#define RXWI_W3_SNR0 FIELD32(0x000000ff)
4658 +#define RXWI_W3_SNR1 FIELD32(0x0000ff00)
4659 +
4660 +/*
4661 + * Macro's for converting txpower from EEPROM to mac80211 value
4662 + * and from mac80211 value to register value.
4663 + */
4664 +#define MIN_G_TXPOWER 0
4665 +#define MIN_A_TXPOWER -7
4666 +#define MAX_G_TXPOWER 31
4667 +#define MAX_A_TXPOWER 15
4668 +#define DEFAULT_TXPOWER 5
4669 +
4670 +#define TXPOWER_G_FROM_DEV(__txpower) \
4671 + ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4672 +
4673 +#define TXPOWER_G_TO_DEV(__txpower) \
4674 + clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
4675 +
4676 +#define TXPOWER_A_FROM_DEV(__txpower) \
4677 + ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
4678 +
4679 +#define TXPOWER_A_TO_DEV(__txpower) \
4680 + clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
4681 +
4682 +#endif /* RT2800PCI_H */
4683 --- a/drivers/net/wireless/rt2x00/rt2x00.h
4684 +++ b/drivers/net/wireless/rt2x00/rt2x00.h
4685 @@ -139,6 +139,10 @@ struct rt2x00_chip {
4686 #define RT2561 0x0302
4687 #define RT2661 0x0401
4688 #define RT2571 0x1300
4689 +#define RT2860 0x0601 /* 2.4GHz PCI/CB */
4690 +#define RT2860D 0x0681 /* 2.4GHz, 5GHz PCI/CB */
4691 +#define RT2890 0x0701 /* 2.4GHz PCIe */
4692 +#define RT2890D 0x0781 /* 2.4GHz, 5GHz PCIe */
4693
4694 u16 rf;
4695 u32 rev;
Personal OpenWRT clone
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