target/linux/coldfire/patches/045-m547x_8x_fec_dma.patch

   1 From b778a60aba67d29857fc7016c8c2f2d87a23de1f Mon Sep 17 00:00:00 2001
   2 From: Kurt Mahan <kmahan@freescale.com>
   3 Date: Sun, 9 Mar 2008 22:14:05 -0600
   4 Subject: [PATCH] Add DMA and FEC.
   5
   6 LTIBName: m547x-8x-fec-dma
   7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
   8 ---
   9  arch/m68k/Kconfig            |    9 +
  10  arch/m68k/coldfire/Makefile  |    2 +
  11  arch/m68k/coldfire/dma.c     |  537 +++++++++
  12  drivers/Makefile             |    2 +
  13  drivers/dma/MCD_dma.h        |  408 +++++++
  14  drivers/dma/MCD_dmaApi.c     |  968 +++++++++++++++++
  15  drivers/dma/MCD_progCheck.h  |   33 +
  16  drivers/dma/MCD_tasks.c      | 2452 ++++++++++++++++++++++++++++++++++++++++++
  17  drivers/dma/MCD_tasksInit.c  |  284 +++++
  18  drivers/dma/MCD_tasksInit.h  |   73 ++
  19  drivers/dma/Makefile         |    2 +
  20  drivers/net/Kconfig          |    2 +
  21  drivers/net/Makefile         |    2 +
  22  drivers/net/fec/Kconfig      |   25 +
  23  drivers/net/fec/Makefile     |    7 +
  24  drivers/net/fec/fec.c        | 1375 +++++++++++++++++++++++
  25  drivers/net/fec/fec.h        |  162 +++
  26  drivers/net/fec/ks8721.c     |  125 +++
  27  drivers/net/fec/ks8721.h     |   21 +
  28  include/asm-m68k/MCD_dma.h   |  408 +++++++
  29  include/asm-m68k/coldfire.h  |    1 +
  30  include/asm-m68k/dma.h       |  106 ++-
  31  include/asm-m68k/m5485dma.h  |   97 ++
  32  include/asm-m68k/m5485sram.h |   12 +
  33  24 files changed, 7112 insertions(+), 1 deletions(-)
  34  create mode 100644 arch/m68k/coldfire/dma.c
  35  create mode 100644 drivers/dma/MCD_dma.h
  36  create mode 100644 drivers/dma/MCD_dmaApi.c
  37  create mode 100644 drivers/dma/MCD_progCheck.h
  38  create mode 100644 drivers/dma/MCD_tasks.c
  39  create mode 100644 drivers/dma/MCD_tasksInit.c
  40  create mode 100644 drivers/dma/MCD_tasksInit.h
  41  create mode 100644 drivers/net/fec/Kconfig
  42  create mode 100644 drivers/net/fec/Makefile
  43  create mode 100755 drivers/net/fec/fec.c
  44  create mode 100755 drivers/net/fec/fec.h
  45  create mode 100644 drivers/net/fec/ks8721.c
  46  create mode 100644 drivers/net/fec/ks8721.h
  47  create mode 100644 include/asm-m68k/MCD_dma.h
  48  create mode 100644 include/asm-m68k/m5485dma.h
  49  create mode 100644 include/asm-m68k/m5485sram.h
  50
  51 --- a/arch/m68k/Kconfig
  52 +++ b/arch/m68k/Kconfig
  53 @@ -141,6 +141,15 @@ config CFV4E
  54         select MMU_CFV4E if MMU
  55         default y
  56
  57 +config MCD_DMA
  58 +       bool "ColdFire MCD DMA support"
  59 +       depends on CFV4E
  60 +       default y
  61 +       help
  62 +         This enables support for the ColdFire 547x/548x family
  63 +         multichannel DMA support.  Many drivers need it.
  64 +         If you want it, say Y
  65 +
  66  config AMIGA
  67         bool "Amiga support"
  68         depends on !MMU_SUN3
  69 --- a/arch/m68k/coldfire/Makefile
  70 +++ b/arch/m68k/coldfire/Makefile
  71 @@ -10,3 +10,5 @@ endif
  72
  73  obj-$(CONFIG_PCI)      += pci.o mcf5445x-pci.o iomap.o
  74  obj-$(CONFIG_M54455)   += mcf5445x-devices.o
  75 +
  76 +obj-$(CONFIG_MCD_DMA)  += dma.o
  77 --- /dev/null
  78 +++ b/arch/m68k/coldfire/dma.c
  79 @@ -0,0 +1,537 @@
  80 +#include <linux/kernel.h>
  81 +#include <linux/sched.h>
  82 +#include <linux/mm.h>
  83 +#include <linux/init.h>
  84 +#include <linux/interrupt.h>
  85 +#include <asm/io.h>
  86 +#include <asm/irq.h>
  87 +#include <asm/dma.h>
  88 +#include <asm/coldfire.h>
  89 +#include <asm/m5485sram.h>
  90 +#include <asm/mcfsim.h>
  91 +
  92 +
  93 +
  94 +void dma_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs);
  95 +
  96 +/*
  97 + * This global keeps track of which initiators have been
  98 + * used of the available assignments.  Initiators 0-15 are
  99 + * hardwired.  Initiators 16-31 are multiplexed and controlled
 100 + * via the Initiatior Mux Control Registe (IMCR).  The
 101 + * assigned requestor is stored with the associated initiator
 102 + * number.
 103 + */
 104 +static int used_reqs[32] = {
 105 +       DMA_ALWAYS, DMA_DSPI_RX, DMA_DSPI_TX, DMA_DREQ0,
 106 +       DMA_PSC0_RX, DMA_PSC0_TX, DMA_USBEP0, DMA_USBEP1,
 107 +       DMA_USBEP2, DMA_USBEP3, DMA_PCI_TX, DMA_PCI_RX,
 108 +       DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
 109 +       0, 0, 0, 0,
 110 +       0, 0, 0, 0,
 111 +       0, 0, 0, 0,
 112 +       0, 0, 0, 0
 113 +};
 114 +
 115 +/*
 116 + * This global keeps track of which channels have been assigned
 117 + * to tasks.  This methology assumes that no single initiator
 118 + * will be tied to more than one task/channel
 119 + */
 120 +static char used_channel[16] = {
 121 +       -1, -1, -1, -1, -1, -1, -1, -1,
 122 +       -1, -1, -1, -1, -1, -1, -1, -1
 123 +};
 124 +
 125 +unsigned int connected_channel[16] = {
 126 +       0, 0, 0, 0, 0, 0, 0, 0,
 127 +       0, 0, 0, 0, 0, 0, 0, 0
 128 +};
 129 +
 130 +/********************************************************************/
 131 +/*
 132 + * Attempt to enable the provided Initiator in the Initiator
 133 + * Mux Control Register
 134 + *
 135 + * Parameters:
 136 + *  initiator   Initiator identifier
 137 + *
 138 + * Return Value:
 139 + *  1   if unable to make the assignment
 140 + *  0   successful
 141 + */
 142 +int
 143 +dma_set_initiator(int initiator)
 144 +{
 145 +       switch (initiator) {    /*
 146 +                                * These initiators are always active
 147 +                                */
 148 +       case DMA_ALWAYS:
 149 +       case DMA_DSPI_RX:
 150 +       case DMA_DSPI_TX:
 151 +       case DMA_DREQ0:
 152 +       case DMA_PSC0_RX:
 153 +       case DMA_PSC0_TX:
 154 +       case DMA_USBEP0:
 155 +       case DMA_USBEP1:
 156 +       case DMA_USBEP2:
 157 +       case DMA_USBEP3:
 158 +       case DMA_PCI_TX:
 159 +       case DMA_PCI_RX:
 160 +       case DMA_PSC1_RX:
 161 +       case DMA_PSC1_TX:
 162 +       case DMA_I2C_RX:
 163 +       case DMA_I2C_TX:
 164 +               break;
 165 +
 166 +       case DMA_FEC0_RX:
 167 +               MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC16(3))
 168 +                   | MCF_DMA_IMCR_SRC16_FEC0RX;
 169 +               used_reqs[16] = DMA_FEC0_RX;
 170 +               break;
 171 +
 172 +       case DMA_FEC0_TX:
 173 +               MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC17(3))
 174 +                   | MCF_DMA_IMCR_SRC17_FEC0TX;
 175 +               used_reqs[17] = DMA_FEC0_TX;
 176 +               break;
 177 +
 178 +       case DMA_FEC1_RX:
 179 +               MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC20(3))
 180 +                   | MCF_DMA_IMCR_SRC20_FEC1RX;
 181 +               used_reqs[20] = DMA_FEC1_RX;
 182 +               break;
 183 +
 184 +       case DMA_FEC1_TX:
 185 +               if (used_reqs[21] == 0) {
 186 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
 187 +                           | MCF_DMA_IMCR_SRC21_FEC1TX;
 188 +                       used_reqs[21] = DMA_FEC1_TX;
 189 +               } else if (used_reqs[25] == 0) {
 190 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
 191 +                           | MCF_DMA_IMCR_SRC25_FEC1TX;
 192 +                       used_reqs[25] = DMA_FEC1_TX;
 193 +               } else if (used_reqs[31] == 0) {
 194 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
 195 +                           | MCF_DMA_IMCR_SRC31_FEC1TX;
 196 +                       used_reqs[31] = DMA_FEC1_TX;
 197 +               } else          /* No empty slots */
 198 +                       return 1;
 199 +               break;
 200 +
 201 +       case DMA_DREQ1:
 202 +               if (used_reqs[29] == 0) {
 203 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
 204 +                           | MCF_DMA_IMCR_SRC29_DREQ1;
 205 +                       used_reqs[29] = DMA_DREQ1;
 206 +               } else if (used_reqs[21] == 0) {
 207 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC21(3))
 208 +                           | MCF_DMA_IMCR_SRC21_DREQ1;
 209 +                       used_reqs[21] = DMA_DREQ1;
 210 +               } else          /* No empty slots */
 211 +                       return 1;
 212 +               break;
 213 +
 214 +       case DMA_CTM0:
 215 +               if (used_reqs[24] == 0) {
 216 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC24(3))
 217 +                           | MCF_DMA_IMCR_SRC24_CTM0;
 218 +                       used_reqs[24] = DMA_CTM0;
 219 +               } else          /* No empty slots */
 220 +                       return 1;
 221 +               break;
 222 +
 223 +       case DMA_CTM1:
 224 +               if (used_reqs[25] == 0) {
 225 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC25(3))
 226 +                           | MCF_DMA_IMCR_SRC25_CTM1;
 227 +                       used_reqs[25] = DMA_CTM1;
 228 +               } else          /* No empty slots */
 229 +                       return 1;
 230 +               break;
 231 +
 232 +       case DMA_CTM2:
 233 +               if (used_reqs[26] == 0) {
 234 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
 235 +                           | MCF_DMA_IMCR_SRC26_CTM2;
 236 +                       used_reqs[26] = DMA_CTM2;
 237 +               } else          /* No empty slots */
 238 +                       return 1;
 239 +               break;
 240 +
 241 +       case DMA_CTM3:
 242 +               if (used_reqs[27] == 0) {
 243 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
 244 +                           | MCF_DMA_IMCR_SRC27_CTM3;
 245 +                       used_reqs[27] = DMA_CTM3;
 246 +               } else          /* No empty slots */
 247 +                       return 1;
 248 +               break;
 249 +
 250 +       case DMA_CTM4:
 251 +               if (used_reqs[28] == 0) {
 252 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
 253 +                           | MCF_DMA_IMCR_SRC28_CTM4;
 254 +                       used_reqs[28] = DMA_CTM4;
 255 +               } else          /* No empty slots */
 256 +                       return 1;
 257 +               break;
 258 +
 259 +       case DMA_CTM5:
 260 +               if (used_reqs[29] == 0) {
 261 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
 262 +                           | MCF_DMA_IMCR_SRC29_CTM5;
 263 +                       used_reqs[29] = DMA_CTM5;
 264 +               } else          /* No empty slots */
 265 +                       return 1;
 266 +               break;
 267 +
 268 +       case DMA_CTM6:
 269 +               if (used_reqs[30] == 0) {
 270 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
 271 +                           | MCF_DMA_IMCR_SRC30_CTM6;
 272 +                       used_reqs[30] = DMA_CTM6;
 273 +               } else          /* No empty slots */
 274 +                       return 1;
 275 +               break;
 276 +
 277 +       case DMA_CTM7:
 278 +               if (used_reqs[31] == 0) {
 279 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
 280 +                           | MCF_DMA_IMCR_SRC31_CTM7;
 281 +                       used_reqs[31] = DMA_CTM7;
 282 +               } else          /* No empty slots */
 283 +                       return 1;
 284 +               break;
 285 +
 286 +       case DMA_USBEP4:
 287 +               if (used_reqs[26] == 0) {
 288 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC26(3))
 289 +                           | MCF_DMA_IMCR_SRC26_USBEP4;
 290 +                       used_reqs[26] = DMA_USBEP4;
 291 +               } else          /* No empty slots */
 292 +                       return 1;
 293 +               break;
 294 +
 295 +       case DMA_USBEP5:
 296 +               if (used_reqs[27] == 0) {
 297 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC27(3))
 298 +                           | MCF_DMA_IMCR_SRC27_USBEP5;
 299 +                       used_reqs[27] = DMA_USBEP5;
 300 +               } else          /* No empty slots */
 301 +                       return 1;
 302 +               break;
 303 +
 304 +       case DMA_USBEP6:
 305 +               if (used_reqs[28] == 0) {
 306 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
 307 +                           | MCF_DMA_IMCR_SRC28_USBEP6;
 308 +                       used_reqs[28] = DMA_USBEP6;
 309 +               } else          /* No empty slots */
 310 +                       return 1;
 311 +               break;
 312 +
 313 +       case DMA_PSC2_RX:
 314 +               if (used_reqs[28] == 0) {
 315 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC28(3))
 316 +                           | MCF_DMA_IMCR_SRC28_PSC2RX;
 317 +                       used_reqs[28] = DMA_PSC2_RX;
 318 +               } else          /* No empty slots */
 319 +                       return 1;
 320 +               break;
 321 +
 322 +       case DMA_PSC2_TX:
 323 +               if (used_reqs[29] == 0) {
 324 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC29(3))
 325 +                           | MCF_DMA_IMCR_SRC29_PSC2TX;
 326 +                       used_reqs[29] = DMA_PSC2_TX;
 327 +               } else          /* No empty slots */
 328 +                       return 1;
 329 +               break;
 330 +
 331 +       case DMA_PSC3_RX:
 332 +               if (used_reqs[30] == 0) {
 333 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC30(3))
 334 +                           | MCF_DMA_IMCR_SRC30_PSC3RX;
 335 +                       used_reqs[30] = DMA_PSC3_RX;
 336 +               } else          /* No empty slots */
 337 +                       return 1;
 338 +               break;
 339 +
 340 +       case DMA_PSC3_TX:
 341 +               if (used_reqs[31] == 0) {
 342 +                       MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_SRC31(3))
 343 +                           | MCF_DMA_IMCR_SRC31_PSC3TX;
 344 +                       used_reqs[31] = DMA_PSC3_TX;
 345 +               } else          /* No empty slots */
 346 +                       return 1;
 347 +               break;
 348 +
 349 +       default:
 350 +               return 1;
 351 +       }
 352 +       return 0;
 353 +}
 354 +
 355 +/********************************************************************/
 356 +/*
 357 + * Return the initiator number for the given requestor
 358 + *
 359 + * Parameters:
 360 + *  requestor   Initiator/Requestor identifier
 361 + *
 362 + * Return Value:
 363 + *  The initiator number (0-31) if initiator has been assigned
 364 + *  0 (always initiator) otherwise
 365 + */
 366 +unsigned int
 367 +dma_get_initiator(int requestor)
 368 +{
 369 +       u32 i;
 370 +
 371 +       for (i = 0; i < sizeof (used_reqs); ++i) {
 372 +               if (used_reqs[i] == requestor)
 373 +                       return i;
 374 +       }
 375 +       return 0;
 376 +}
 377 +
 378 +/********************************************************************/
 379 +/*
 380 + * Remove the given initiator from the active list
 381 + *
 382 + * Parameters:
 383 + *  requestor   Initiator/Requestor identifier
 384 + */
 385 +void
 386 +dma_remove_initiator(int requestor)
 387 +{
 388 +       u32 i;
 389 +
 390 +       for (i = 0; i < sizeof (used_reqs); ++i) {
 391 +               if (used_reqs[i] == requestor) {
 392 +                       used_reqs[i] = -1;
 393 +                       break;
 394 +               }
 395 +       }
 396 +}
 397 +
 398 +/********************************************************************/
 399 +/*
 400 + * Attempt to find an available channel for FEC and mark is as used
 401 + *
 402 + * Parameters:
 403 + *  requestor   Initiator/Requestor identifier
 404 + *
 405 + * Return Value:
 406 + *  First available channel (from 0 to 5) or -1 if they are all occupied
 407 + */
 408 +int
 409 +dma_set_channel_fec(int requestor)
 410 +{
 411 +       u32 i, t;
 412 +
 413 +#ifdef CONFIG_FEC_548x_ENABLE_FEC2
 414 +       t = 4;
 415 +#else
 416 +       t = 2;
 417 +#endif
 418 +
 419 +
 420 +
 421 +       for (i = 0; i < t ; ++i)
 422 +               if (used_channel[i] == -1) {
 423 +                       used_channel[i] = requestor;
 424 +                       return i;
 425 +               }
 426 +       /* All channels taken */
 427 +       return -1;
 428 +}
 429 +
 430 +/********************************************************************/
 431 +/*
 432 + * Attempt to find an available channel and mark is as used
 433 + *
 434 + * Parameters:
 435 + *  requestor   Initiator/Requestor identifier
 436 + *
 437 + * Return Value:
 438 + *  First available channel (from 6 to 15) or -1 if they are all occupied
 439 + */
 440 +int
 441 +dma_set_channel(int requestor)
 442 +{
 443 +       u32 i;
 444 +#ifdef CONFIG_NET_FEC2
 445 +       i = 4;
 446 +#else
 447 +       i = 2;
 448 +#endif
 449 +
 450 +       for (; i < 16; ++i)
 451 +               if (used_channel[i] == -1) {
 452 +                       used_channel[i] = requestor;
 453 +                       return i;
 454 +               }
 455 +
 456 +       /* All channels taken */
 457 +       return -1;
 458 +}
 459 +
 460 +/********************************************************************/
 461 +/*
 462 + * Return the channel being initiated by the given requestor
 463 + *
 464 + * Parameters:
 465 + *  requestor   Initiator/Requestor identifier
 466 + */
 467 +int
 468 +dma_get_channel(int requestor)
 469 +{
 470 +       u32 i;
 471 +
 472 +       for (i = 0; i < sizeof (used_channel); ++i) {
 473 +               if (used_channel[i] == requestor)
 474 +                       return i;
 475 +       }
 476 +       return -1;
 477 +}
 478 +
 479 +/********************************************************************/
 480 +/*
 481 + * Connects a channel with reference on your data
 482 + *
 483 + * Parameters:
 484 + *  channel   channel number
 485 + *  reference addres of your data
 486 +  */
 487 +int
 488 +dma_connect(int channel, int address)
 489 +{
 490 +       if ((channel < 16) && (channel >= 0))
 491 +               connected_channel[channel] = address;
 492 +       else
 493 +               return -1;
 494 +       return 0;
 495 +}
 496 +
 497 +/********************************************************************/
 498 +/*
 499 + * Disconnects a channel with reference on your data
 500 + *
 501 + * Parameters:
 502 + *  channel   channel number
 503 +*/
 504 +int
 505 +dma_disconnect(int channel)
 506 +{
 507 +       if ((channel < 16) && (channel >= 0))
 508 +               connected_channel[channel] = 0;
 509 +       else
 510 +               return -1;
 511 +       return 0;
 512 +}
 513 +
 514 +/********************************************************************/
 515 +/*
 516 + * Remove the channel being initiated by the given requestor from
 517 + * the active list
 518 + *
 519 + * Parameters:
 520 + *  requestor   Initiator/Requestor identifier
 521 + */
 522 +void
 523 +dma_remove_channel(int requestor)
 524 +{
 525 +       u32 i;
 526 +
 527 +       for (i = 0; i < sizeof (used_channel); ++i) {
 528 +               if (used_channel[i] == requestor) {
 529 +                       used_channel[i] = -1;
 530 +                       break;
 531 +               }
 532 +       }
 533 +}
 534 +
 535 +/********************************************************************/
 536 +/*
 537 + * This is the catch-all interrupt handler for the mult-channel DMA
 538 + */
 539 +volatile u8 dma_iflag[16];
 540 +u32 tx = 0;
 541 +
 542 +void
 543 +dma_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
 544 +{
 545 +       u32 i, interrupts/*, mask, temp*/;
 546 +
 547 +       /*
 548 +        * Determine which interrupt(s) triggered by AND'ing the
 549 +        * pending interrupts with those that aren't masked.
 550 +        */
 551 +/*     mask = MCF_DMA_DIMR;
 552 +       MCF_DMA_DIMR = 0xffffffff;
 553 +*/
 554 +       interrupts = MCF_DMA_DIPR;
 555 +       MCF_DMA_DIPR |= interrupts;
 556 +//     temp = interrupts;
 557 +
 558 +       //MCF_DMA_DIPR = interrupts;
 559 +       for (i = 0; i < 16; ++i, interrupts >>= 1)
 560 +               if (interrupts & 0x1)
 561 +                       if (connected_channel[i] != 0)
 562 +                               ((void (*)(void)) (connected_channel[i])) ();
 563 +
 564 +/*     MCF_DMA_DIPR |= temp;
 565 +       MCF_DMA_DIMR = mask;*/
 566 +}
 567 +
 568 +void
 569 +dma_remove_channel_by_number(int channel)
 570 +{
 571 +       if (channel < sizeof (used_channel) && channel >= 0)
 572 +               used_channel[channel] = -1;
 573 +}
 574 +
 575 +int __devinit
 576 +dma_init()
 577 +{
 578 +       int result;
 579 +       char *dma_version_str;
 580 +
 581 +       MCD_getVersion(&dma_version_str);
 582 +       printk("Initialize %s\n", dma_version_str);
 583 +
 584 +       if (request_irq
 585 +           (64 + ISC_DMA,
 586 +            dma_interrupt_handler,
 587 +            IRQF_DISABLED,
 588 +            "MCD-DMA",
 589 +            NULL)) {
 590 +               printk("Cannot allocate the DMA IRQ(48)\n");
 591 +               return 1;
 592 +       }
 593 +
 594 +       MCF_DMA_DIMR = 0;
 595 +       MCF_DMA_DIPR = 0xFFFFFFFF;
 596 +
 597 +       MCF_ICR(ISC_DMA) = ILP_DMA;
 598 +#if 0
 599 +// JKM
 600 +       enable_irq( 64 + ISC_DMA );
 601 +#endif
 602 +
 603 +       result =
 604 +           MCD_initDma((dmaRegs *) (MCF_MBAR + 0x8000),
 605 +                       (void *) SYS_SRAM_DMA_START, MCD_RELOC_TASKS);
 606 +       if (result != MCD_OK) {
 607 +               printk("Cannot perform DMA initialization\n");
 608 +               free_irq(64 + ISC_DMA, NULL);
 609 +               return 1;
 610 +       }
 611 +
 612 +       return 0;
 613 +}
 614 +
 615 +device_initcall(dma_init);
 616 +
 617 --- a/drivers/Makefile
 618 +++ b/drivers/Makefile
 619 @@ -93,3 +93,5 @@ obj-$(CONFIG_PPC_PS3)         += ps3/
 620  obj-$(CONFIG_OF)               += of/
 621  obj-$(CONFIG_SSB)              += ssb/
 622  obj-$(CONFIG_VIRTIO)           += virtio/
 623 +
 624 +obj-$(CONFIG_MCD_DMA)          += dma/
 625 --- /dev/null
 626 +++ b/drivers/dma/MCD_dma.h
 627 @@ -0,0 +1,408 @@
 628 +/*********************************************************************
 629 + *
 630 + * Copyright (C) 2004  Motorola, Inc.
 631 + *  MOTOROLA, INC. All Rights Reserved.
 632 + *  You are hereby granted a copyright license to use
 633 + *  the SOFTWARE so long as this entire notice is
 634 + *  retained without alteration in any modified and/or redistributed
 635 + *  versions, and that such modified versions are clearly identified
 636 + *  as such. No licenses are granted by implication, estoppel or
 637 + *  otherwise under any patents or trademarks of Motorola, Inc. This
 638 + *  software is provided on an "AS IS" basis and without warranty.
 639 + *
 640 + *  To the maximum extent permitted by applicable law, MOTOROLA
 641 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
 642 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 643 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
 644 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
 645 + *  ACCOMPANYING WRITTEN MATERIALS.
 646 + *
 647 + *  To the maximum extent permitted by applicable law, IN NO EVENT
 648 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
 649 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
 650 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 651 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
 652 + *
 653 + *  Motorola assumes no responsibility for the maintenance and support
 654 + *  of this software
 655 + ********************************************************************/
 656 +
 657 +/*
 658 + * File:        MCD_dma.h
 659 + * Purpose:     Main header file for multi-channel DMA API.
 660 + *
 661 + * Notes:
 662 + *
 663 + * Modifications:
 664 + */
 665 +#ifndef _MCD_API_H
 666 +#define _MCD_API_H
 667 +
 668 +#include <asm/types.h>
 669 +
 670 +/*
 671 + * Turn Execution Unit tasks ON (#define) or OFF (#undef)
 672 + */
 673 +#undef MCD_INCLUDE_EU
 674 +
 675 +/*
 676 + * Number of DMA channels
 677 + */
 678 +#define NCHANNELS 16
 679 +
 680 +/*
 681 + * Total number of variants
 682 + */
 683 +#ifdef MCD_INCLUDE_EU
 684 +#define NUMOFVARIANTS   6
 685 +#else
 686 +#define NUMOFVARIANTS   4
 687 +#endif
 688 +
 689 +/*
 690 + * Define sizes of the various tables
 691 + */
 692 +#define TASK_TABLE_SIZE     (NCHANNELS*32)
 693 +#define VAR_TAB_SIZE        (128)
 694 +#define CONTEXT_SAVE_SIZE   (128)
 695 +#define FUNCDESC_TAB_SIZE   (256)
 696 +
 697 +#ifdef MCD_INCLUDE_EU
 698 +#define FUNCDESC_TAB_NUM    16
 699 +#else
 700 +#define FUNCDESC_TAB_NUM    1
 701 +#endif
 702 +
 703 +
 704 +#ifndef DEFINESONLY
 705 +
 706 +/*
 707 + * Portability typedefs
 708 + */
 709 + /*
 710 +#ifndef s32
 711 +typedef int s32;
 712 +#endif
 713 +#ifndef u32
 714 +typedef unsigned int u32;
 715 +#endif
 716 +#ifndef s16
 717 +typedef short s16;
 718 +#endif
 719 +#ifndef u16
 720 +typedef unsigned short u16;
 721 +#endif
 722 +#ifndef s8
 723 +typedef char s8;
 724 +#endif
 725 +#ifndef u8
 726 +typedef unsigned char u8;
 727 +#endif
 728 +*/
 729 +/*
 730 + * These structures represent the internal registers of the
 731 + * multi-channel DMA
 732 + */
 733 +struct dmaRegs_s {
 734 +   u32 taskbar;         /* task table base address register */
 735 +   u32 currPtr;
 736 +   u32 endPtr;
 737 +   u32 varTablePtr;
 738 +   u16 dma_rsvd0;
 739 +   u16 ptdControl;      /* ptd control */
 740 +   u32 intPending;      /* interrupt pending register */
 741 +   u32 intMask;         /* interrupt mask register */
 742 +   u16 taskControl[16]; /* task control registers */
 743 +   u8  priority[32];    /* priority registers */
 744 +   u32 initiatorMux;    /* initiator mux control */
 745 +   u32 taskSize0;       /* task size control register 0. */
 746 +   u32 taskSize1;       /* task size control register 1. */
 747 +   u32 dma_rsvd1;       /* reserved */
 748 +   u32 dma_rsvd2;       /* reserved */
 749 +   u32 debugComp1;      /* debug comparator 1 */
 750 +   u32 debugComp2;      /* debug comparator 2 */
 751 +   u32 debugControl;    /* debug control */
 752 +   u32 debugStatus;     /* debug status */
 753 +   u32 ptdDebug;        /* priority task decode debug */
 754 +   u32 dma_rsvd3[31];   /* reserved */
 755 +};
 756 +typedef volatile struct dmaRegs_s dmaRegs;
 757 +
 758 +#endif
 759 +
 760 +/*
 761 + * PTD contrl reg bits
 762 + */
 763 +#define PTD_CTL_TSK_PRI         0x8000
 764 +#define PTD_CTL_COMM_PREFETCH   0x0001
 765 +
 766 +/*
 767 + * Task Control reg bits and field masks
 768 + */
 769 +#define TASK_CTL_EN             0x8000
 770 +#define TASK_CTL_VALID          0x4000
 771 +#define TASK_CTL_ALWAYS         0x2000
 772 +#define TASK_CTL_INIT_MASK      0x1f00
 773 +#define TASK_CTL_ASTRT          0x0080
 774 +#define TASK_CTL_HIPRITSKEN     0x0040
 775 +#define TASK_CTL_HLDINITNUM     0x0020
 776 +#define TASK_CTL_ASTSKNUM_MASK  0x000f
 777 +
 778 +/*
 779 + * Priority reg bits and field masks
 780 + */
 781 +#define PRIORITY_HLD            0x80
 782 +#define PRIORITY_PRI_MASK       0x07
 783 +
 784 +/*
 785 + * Debug Control reg bits and field masks
 786 + */
 787 +#define DBG_CTL_BLOCK_TASKS_MASK    0xffff0000
 788 +#define DBG_CTL_AUTO_ARM            0x00008000
 789 +#define DBG_CTL_BREAK               0x00004000
 790 +#define DBG_CTL_COMP1_TYP_MASK      0x00003800
 791 +#define DBG_CTL_COMP2_TYP_MASK      0x00000070
 792 +#define DBG_CTL_EXT_BREAK           0x00000004
 793 +#define DBG_CTL_INT_BREAK           0x00000002
 794 +
 795 +/*
 796 + * PTD Debug reg selector addresses
 797 + * This reg must be written with a value to show the contents of
 798 + * one of the desired internal register.
 799 + */
 800 +#define PTD_DBG_REQ             0x00 /* shows the state of 31 initiators */
 801 +#define PTD_DBG_TSK_VLD_INIT    0x01 /* shows which 16 tasks are valid and
 802 +                                        have initiators asserted */
 803 +
 804 +
 805 +/*
 806 + * General return values
 807 + */
 808 +#define MCD_OK                   0
 809 +#define MCD_ERROR               -1
 810 +#define MCD_TABLE_UNALIGNED     -2
 811 +#define MCD_CHANNEL_INVALID     -3
 812 +
 813 +/*
 814 + * MCD_initDma input flags
 815 + */
 816 +#define MCD_RELOC_TASKS         0x00000001
 817 +#define MCD_NO_RELOC_TASKS      0x00000000
 818 +#define MCD_COMM_PREFETCH_EN    0x00000002  /* Commbus Prefetching - MCF547x/548x ONLY */
 819 +
 820 +/*
 821 + * MCD_dmaStatus Status Values for each channel
 822 + */
 823 +#define MCD_NO_DMA  1 /* No DMA has been requested since reset */
 824 +#define MCD_IDLE    2 /* DMA active, but the initiator is currently inactive */
 825 +#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
 826 +#define MCD_PAUSED  4 /* DMA active but it is currently paused */
 827 +#define MCD_HALTED  5 /* the most recent DMA has been killed with MCD_killTask() */
 828 +#define MCD_DONE    6 /* the most recent DMA has completed. */
 829 +
 830 +
 831 +/*
 832 + * MCD_startDma parameter defines
 833 + */
 834 +
 835 +/*
 836 + * Constants for the funcDesc parameter
 837 + */
 838 +/* Byte swapping: */
 839 +#define MCD_NO_BYTE_SWAP    0x00045670  /* to disable byte swapping. */
 840 +#define MCD_BYTE_REVERSE    0x00076540  /* to reverse the bytes of each u32 of the DMAed data. */
 841 +#define MCD_U16_REVERSE     0x00067450  /* to reverse the 16-bit halves of
 842 +                                           each 32-bit data value being DMAed.*/
 843 +#define MCD_U16_BYTE_REVERSE    0x00054760 /* to reverse the byte halves of each
 844 +                                            16-bit half of each 32-bit data value DMAed */
 845 +#define MCD_NO_BIT_REV  0x00000000  /* do not reverse the bits of each byte DMAed. */
 846 +#define MCD_BIT_REV     0x00088880  /* reverse the bits of each byte DMAed */
 847 +/* CRCing: */
 848 +#define MCD_CRC16       0xc0100000  /* to perform CRC-16 on DMAed data. */
 849 +#define MCD_CRCCCITT    0xc0200000  /* to perform CRC-CCITT on DMAed data. */
 850 +#define MCD_CRC32       0xc0300000  /* to perform CRC-32 on DMAed data. */
 851 +#define MCD_CSUMINET    0xc0400000  /* to perform internet checksums on DMAed data.*/
 852 +#define MCD_NO_CSUM     0xa0000000  /* to perform no checksumming. */
 853 +
 854 +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
 855 +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
 856 +
 857 +/*
 858 + * Constants for the flags parameter
 859 + */
 860 +#define MCD_TT_FLAGS_RL   0x00000001 /* Read line */
 861 +#define MCD_TT_FLAGS_CW   0x00000002 /* Combine Writes */
 862 +#define MCD_TT_FLAGS_SP   0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY  */
 863 +#define MCD_TT_FLAGS_MASK 0x000000ff
 864 +#define MCD_TT_FLAGS_DEF  (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
 865 +
 866 +#define MCD_SINGLE_DMA  0x00000100 /* Unchained DMA */
 867 +#define MCD_CHAIN_DMA              /* TBD */
 868 +#define MCD_EU_DMA                 /* TBD */
 869 +#define MCD_FECTX_DMA   0x00001000 /* FEC TX ring DMA */
 870 +#define MCD_FECRX_DMA   0x00002000 /* FEC RX ring DMA */
 871 +
 872 +
 873 +/* these flags are valid for MCD_startDma and the chained buffer descriptors */
 874 +#define MCD_BUF_READY   0x80000000 /* indicates that this buffer is now under the DMA's control */
 875 +#define MCD_WRAP        0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
 876 +#define MCD_INTERRUPT   0x10000000 /* to generate an interrupt after completion of the DMA. */
 877 +#define MCD_END_FRAME   0x08000000 /* tell the DMA to end the frame when transferring
 878 +                                      last byte of data in buffer */
 879 +#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
 880 +                                      prior to performing the DMA. */
 881 +
 882 +/* Defines for the FEC buffer descriptor control/status word*/
 883 +#define MCD_FEC_BUF_READY   0x8000
 884 +#define MCD_FEC_WRAP        0x2000
 885 +#define MCD_FEC_INTERRUPT   0x1000
 886 +#define MCD_FEC_END_FRAME   0x0800
 887 +
 888 +
 889 +/*
 890 + * Defines for general intuitiveness
 891 + */
 892 +
 893 +#define MCD_TRUE  1
 894 +#define MCD_FALSE 0
 895 +
 896 +/*
 897 + * Three different cases for destination and source.
 898 + */
 899 +#define MINUS1          -1
 900 +#define ZERO            0
 901 +#define PLUS1           1
 902 +
 903 +#ifndef DEFINESONLY
 904 +
 905 +/* Task Table Entry struct*/
 906 +typedef struct {
 907 +    u32 TDTstart;   /* task descriptor table start */
 908 +    u32 TDTend;     /* task descriptor table end */
 909 +    u32 varTab;     /* variable table start */
 910 +    u32 FDTandFlags;    /* function descriptor table start and flags */
 911 +    volatile u32 descAddrAndStatus;
 912 +    volatile u32 modifiedVarTab;
 913 +    u32 contextSaveSpace;   /* context save space start */
 914 +    u32 literalBases;
 915 +} TaskTableEntry;
 916 +
 917 +
 918 +/* Chained buffer descriptor */
 919 +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
 920 +struct MCD_bufDesc_struct {
 921 +   u32 flags;         /* flags describing the DMA */
 922 +   u32 csumResult;    /* checksum from checksumming performed since last checksum reset */
 923 +   s8  *srcAddr;      /* the address to move data from */
 924 +   s8  *destAddr;     /* the address to move data to */
 925 +   s8  *lastDestAddr; /* the last address written to */
 926 +   u32 dmaSize;       /* the number of bytes to transfer independent of the transfer size */
 927 +   MCD_bufDesc *next; /* next buffer descriptor in chain */
 928 +   u32 info;          /* private information about this descriptor;  DMA does not affect it */
 929 +};
 930 +
 931 +/* Progress Query struct */
 932 +typedef volatile struct MCD_XferProg_struct {
 933 +   s8 *lastSrcAddr;         /* the most-recent or last, post-increment source address */
 934 +   s8 *lastDestAddr;        /* the most-recent or last, post-increment destination address */
 935 +   u32  dmaSize;            /* the amount of data transferred for the current buffer */
 936 +   MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
 937 +} MCD_XferProg;
 938 +
 939 +
 940 +/* FEC buffer descriptor */
 941 +typedef volatile struct MCD_bufDescFec_struct {
 942 +    u16 statCtrl;
 943 +    u16 length;
 944 +    u32 dataPointer;
 945 +} MCD_bufDescFec;
 946 +
 947 +
 948 +/*************************************************************************/
 949 +/*
 950 + * API function Prototypes  - see MCD_dmaApi.c for further notes
 951 + */
 952 +
 953 +/*
 954 + * MCD_startDma starts a particular kind of DMA .
 955 + */
 956 +int MCD_startDma (
 957 +   int channel,   /* the channel on which to run the DMA */
 958 +   s8  *srcAddr,  /* the address to move data from, or buffer-descriptor address */
 959 +   s16 srcIncr,   /* the amount to increment the source address per transfer */
 960 +   s8  *destAddr, /* the address to move data to */
 961 +   s16 destIncr,  /* the amount to increment the destination address per transfer */
 962 +   u32 dmaSize,   /* the number of bytes to transfer independent of the transfer size */
 963 +   u32 xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
 964 +   u32 initiator, /* what device initiates the DMA */
 965 +   int priority,  /* priority of the DMA */
 966 +   u32 flags,     /* flags describing the DMA */
 967 +   u32 funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
 968 +);
 969 +
 970 +/*
 971 + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
 972 + * registers, relocating and creating the appropriate task structures, and
 973 + * setting up some global settings
 974 + */
 975 +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
 976 +
 977 +/*
 978 + * MCD_dmaStatus() returns the status of the DMA on the requested channel.
 979 + */
 980 +int MCD_dmaStatus (int channel);
 981 +
 982 +/*
 983 + * MCD_XferProgrQuery() returns progress of DMA on requested channel
 984 + */
 985 +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
 986 +
 987 +/*
 988 + * MCD_killDma() halts the DMA on the requested channel, without any
 989 + * intention of resuming the DMA.
 990 + */
 991 +int MCD_killDma (int channel);
 992 +
 993 +/*
 994 + * MCD_continDma() continues a DMA which as stopped due to encountering an
 995 + * unready buffer descriptor.
 996 + */
 997 +int MCD_continDma (int channel);
 998 +
 999 +/*
1000 + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
1001 + * running on that channel).
1002 + */
1003 +int MCD_pauseDma (int channel);
1004 +
1005 +/*
1006 + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
1007 + * running on that channel).
1008 + */
1009 +int MCD_resumeDma (int channel);
1010 +
1011 +/*
1012 + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
1013 + */
1014 +int MCD_csumQuery (int channel, u32 *csum);
1015 +
1016 +/*
1017 + * MCD_getCodeSize provides the packed size required by the microcoded task
1018 + * and structures.
1019 + */
1020 +int MCD_getCodeSize(void);
1021 +
1022 +/*
1023 + * MCD_getVersion provides a pointer to a version string and returns a
1024 + * version number.
1025 + */
1026 +int MCD_getVersion(char **longVersion);
1027 +
1028 +/* macro for setting a location in the variable table */
1029 +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
1030 +   /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
1031 +      so I'm avoiding surrounding it with "do {} while(0)" */
1032 +
1033 +#endif  /* DEFINESONLY */
1034 +
1035 +#endif /* _MCD_API_H */
1036 --- /dev/null
1037 +++ b/drivers/dma/MCD_dmaApi.c
1038 @@ -0,0 +1,968 @@
1039 +/*********************************************************************
1040 + *
1041 + * Copyright (C) 2004  Motorola, Inc.
1042 + *  MOTOROLA, INC. All Rights Reserved.
1043 + *  You are hereby granted a copyright license to use
1044 + *  the SOFTWARE so long as this entire notice is
1045 + *  retained without alteration in any modified and/or redistributed
1046 + *  versions, and that such modified versions are clearly identified
1047 + *  as such. No licenses are granted by implication, estoppel or
1048 + *  otherwise under any patents or trademarks of Motorola, Inc. This
1049 + *  software is provided on an "AS IS" basis and without warranty.
1050 + *
1051 + *  To the maximum extent permitted by applicable law, MOTOROLA
1052 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
1053 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
1054 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
1055 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
1056 + *  ACCOMPANYING WRITTEN MATERIALS.
1057 + *
1058 + *  To the maximum extent permitted by applicable law, IN NO EVENT
1059 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
1060 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
1061 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
1062 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
1063 + *
1064 + *  Motorola assumes no responsibility for the maintenance and support
1065 + *  of this software
1066 + ********************************************************************/
1067 +
1068 +/*
1069 + * File:        MCD_dmaApi.c
1070 + * Purpose:     Main C file for multi-channel DMA API.
1071 + *
1072 + * Notes:
1073 + *
1074 + *
1075 + * Modifications:
1076 + *
1077 + *
1078 + */
1079 +#include <asm/types.h>
1080 +#include <asm/MCD_dma.h>
1081 +#include <asm/virtconvert.h>
1082 +#include "MCD_tasksInit.h"
1083 +#include "MCD_progCheck.h"
1084 +
1085 +/********************************************************************/
1086 +/*
1087 + * This is an API-internal pointer to the DMA's registers
1088 + */
1089 +dmaRegs *MCD_dmaBar;
1090 +
1091 +/*
1092 + * These are the real and model task tables as generated by the
1093 + * build process
1094 + */
1095 +extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
1096 +extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
1097 +
1098 +/*
1099 + * However, this (usually) gets relocated to on-chip SRAM, at which
1100 + * point we access them as these tables
1101 + */
1102 +volatile TaskTableEntry *MCD_taskTable;
1103 +TaskTableEntry *MCD_modelTaskTable;
1104 +
1105 +
1106 +/*
1107 + * MCD_chStatus[] is an array of status indicators for remembering
1108 + * whether a DMA has ever been attempted on each channel, pausing
1109 + * status, etc.
1110 + */
1111 +static int MCD_chStatus[NCHANNELS] =
1112 +{
1113 +    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
1114 +    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
1115 +    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
1116 +    MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
1117 +};
1118 +
1119 +/*
1120 + * Prototypes for local functions
1121 + */
1122 +static void MCD_memcpy (int *dest, int *src, u32 size);
1123 +static void MCD_resmActions (int channel);
1124 +
1125 +/*
1126 + * Buffer descriptors used for storage of progress info for single Dmas
1127 + * Also used as storage for the DMA for CRCs for single DMAs
1128 + * Otherwise, the DMA does not parse these buffer descriptors
1129 + */
1130 +#ifdef MCD_INCLUDE_EU
1131 +extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
1132 +#else
1133 +MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
1134 +#endif
1135 +MCD_bufDesc *MCD_relocBuffDesc;
1136 +
1137 +
1138 +/*
1139 + * Defines for the debug control register's functions
1140 + */
1141 +#define DBG_CTL_COMP1_TASK  (0x00002000) /* have comparator 1 look for a task # */
1142 +#define DBG_CTL_ENABLE      (DBG_CTL_AUTO_ARM    | \
1143 +                             DBG_CTL_BREAK       | \
1144 +                             DBG_CTL_INT_BREAK   | \
1145 +                             DBG_CTL_COMP1_TASK)
1146 +#define DBG_CTL_DISABLE     (DBG_CTL_AUTO_ARM    | \
1147 +                             DBG_CTL_INT_BREAK   | \
1148 +                             DBG_CTL_COMP1_TASK)
1149 +#define DBG_KILL_ALL_STAT   (0xFFFFFFFF)
1150 +
1151 +/*
1152 + * Offset to context save area where progress info is stored
1153 + */
1154 +#define CSAVE_OFFSET        10
1155 +
1156 +/*
1157 + * Defines for Byte Swapping
1158 + */
1159 +#define MCD_BYTE_SWAP_KILLER    0xFFF8888F
1160 +#define MCD_NO_BYTE_SWAP_ATALL  0x00040000
1161 +
1162 +/*
1163 + * Execution Unit Identifiers
1164 + */
1165 +#define MAC  0  /* legacy - not used */
1166 +#define LUAC 1  /* legacy - not used */
1167 +#define CRC  2  /* legacy - not used */
1168 +#define LURC 3  /* Logic Unit with CRC */
1169 +
1170 +/*
1171 + * Task Identifiers
1172 + */
1173 +#define TASK_CHAINNOEU  0
1174 +#define TASK_SINGLENOEU 1
1175 +#ifdef MCD_INCLUDE_EU
1176 +#define TASK_CHAINEU    2
1177 +#define TASK_SINGLEEU   3
1178 +#define TASK_FECRX      4
1179 +#define TASK_FECTX      5
1180 +#else
1181 +#define TASK_CHAINEU    0
1182 +#define TASK_SINGLEEU   1
1183 +#define TASK_FECRX      2
1184 +#define TASK_FECTX      3
1185 +#endif
1186 +
1187 +/*
1188 + * Structure to remember which variant is on which channel
1189 + * TBD- need this?
1190 + */
1191 +typedef struct MCD_remVariants_struct MCD_remVariant;
1192 +struct MCD_remVariants_struct
1193 +{
1194 +   int remDestRsdIncr[NCHANNELS];  /* -1,0,1 */
1195 +   int remSrcRsdIncr[NCHANNELS];   /* -1,0,1 */
1196 +   s16 remDestIncr[NCHANNELS];     /* DestIncr */
1197 +   s16 remSrcIncr[NCHANNELS];      /* srcIncr */
1198 +   u32 remXferSize[NCHANNELS];     /* xferSize */
1199 +};
1200 +
1201 +/*
1202 + * Structure to remember the startDma parameters for each channel
1203 + */
1204 +MCD_remVariant MCD_remVariants;
1205 +/********************************************************************/
1206 +/*
1207 + * Function: MCD_initDma
1208 + * Purpose:  Initializes the DMA API by setting up a pointer to the DMA
1209 + *           registers, relocating and creating the appropriate task
1210 + *           structures, and setting up some global settings
1211 + * Arguments:
1212 + *  dmaBarAddr    - pointer to the multichannel DMA registers
1213 + *  taskTableDest - location to move DMA task code and structs to
1214 + *  flags         - operational parameters
1215 + * Return Value:
1216 + *  MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
1217 + *  MCD_OK otherwise
1218 + */
1219 +extern u32 MCD_funcDescTab0[];
1220 +
1221 +int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
1222 +{
1223 +    int i;
1224 +    TaskTableEntry *entryPtr;
1225 +
1226 +    /* setup the local pointer to register set */
1227 +    MCD_dmaBar = dmaBarAddr;
1228 +
1229 +    /* do we need to move/create a task table */
1230 +    if ((flags & MCD_RELOC_TASKS) != 0)
1231 +    {
1232 +        int fixedSize;
1233 +        u32 *fixedPtr;
1234 +        /*int *tablePtr = taskTableDest;TBD*/
1235 +        int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
1236 +        int taskDescTabsOffset;
1237 +        int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
1238 +        int taskDescTabSize;
1239 +
1240 +        int i;
1241 +
1242 +        /* check if physical address is aligned on 512 byte boundary */
1243 +        if (((u32)taskTableDest & 0x000001ff) != 0)
1244 +            return(MCD_TABLE_UNALIGNED);
1245 +
1246 +        MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
1247 +
1248 +        /*
1249 +         * Create a task table:
1250 +         * - compute aligned base offsets for variable tables and
1251 +         *   function descriptor tables, then
1252 +         * - loop through the task table and setup the pointers
1253 +         * - copy over model task table with the the actual task descriptor
1254 +         *   tables
1255 +         */
1256 +
1257 +        taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
1258 +        /* align variable tables to size */
1259 +        varTabsOffset = taskTableSize + (u32)taskTableDest;
1260 +        if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
1261 +            varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
1262 +        /* align function descriptor tables */
1263 +        varTabsSize = NCHANNELS * VAR_TAB_SIZE;
1264 +        funcDescTabsOffset = varTabsOffset + varTabsSize;
1265 +
1266 +        if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
1267 +            funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) &
1268 +            (~FUNCDESC_TAB_SIZE);
1269 +
1270 +        funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
1271 +        contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
1272 +        contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
1273 +        fixedSize = taskTableSize + varTabsSize + funcDescTabsSize +
1274 +                    contextSavesSize;
1275 +
1276 +        /* zero the thing out */
1277 +        fixedPtr = (u32 *)taskTableDest;
1278 +        for (i = 0;i<(fixedSize/4);i++)
1279 +            fixedPtr[i] = 0;
1280 +
1281 +        entryPtr = (TaskTableEntry*)MCD_taskTable;
1282 +        /* set up fixed pointers */
1283 +        for (i = 0; i < NCHANNELS; i++)
1284 +        {
1285 +            entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */
1286 +            entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF;
1287 +            entryPtr[i].contextSaveSpace = (u32)contextSavesOffset;
1288 +            varTabsOffset += VAR_TAB_SIZE;
1289 +#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
1290 +            funcDescTabsOffset += FUNCDESC_TAB_SIZE;
1291 +#endif
1292 +            contextSavesOffset += CONTEXT_SAVE_SIZE;
1293 +        }
1294 +        /* copy over the function descriptor table */
1295 +        for ( i = 0; i < FUNCDESC_TAB_NUM; i++)
1296 +        {
1297 +            MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
1298 +                       (void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
1299 +        }
1300 +
1301 +        /* copy model task table to where the context saves stuff leaves off*/
1302 +        MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset;
1303 +
1304 +        MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc,
1305 +                    NUMOFVARIANTS * sizeof(TaskTableEntry));
1306 +
1307 +        entryPtr = MCD_modelTaskTable; /* point to local version of
1308 +                                                            model task table */
1309 +        taskDescTabsOffset = (u32)MCD_modelTaskTable +
1310 +                            (NUMOFVARIANTS * sizeof(TaskTableEntry));
1311 +
1312 +        /* copy actual task code and update TDT ptrs in local model task table */
1313 +        for (i = 0; i < NUMOFVARIANTS; i++)
1314 +        {
1315 +            taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
1316 +            MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize);
1317 +            entryPtr[i].TDTstart = (u32)taskDescTabsOffset;
1318 +            taskDescTabsOffset += taskDescTabSize;
1319 +            entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
1320 +        }
1321 +#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
1322 +                         where they are since DMA might write to them */
1323 +        MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
1324 +#else /* DMA does not touch them so they can be wherever and we don't need to
1325 +         waste SRAM on them */
1326 +        MCD_relocBuffDesc = MCD_singleBufDescs;
1327 +#endif
1328 +    }
1329 +    else
1330 +    {
1331 +        /* point the would-be relocated task tables and the
1332 +        buffer descriptors to the ones the linker generated */
1333 +
1334 +        if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0)
1335 +            return(MCD_TABLE_UNALIGNED);
1336 +
1337 +        /* need to add code to make sure that every thing else is aligned properly TBD*/
1338 +        /* this is problematic if we init more than once or after running tasks,
1339 +            need to add variable to see if we have aleady init'd */
1340 +        entryPtr = MCD_realTaskTableSrc;
1341 +        for (i = 0; i < NCHANNELS; i++)
1342 +        {
1343 +            if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
1344 +                ((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
1345 +                return(MCD_TABLE_UNALIGNED);
1346 +        }
1347 +
1348 +        MCD_taskTable = MCD_realTaskTableSrc;
1349 +        MCD_modelTaskTable = MCD_modelTaskTableSrc;
1350 +        MCD_relocBuffDesc = MCD_singleBufDescs;
1351 +    }
1352 +
1353 +
1354 +    /* Make all channels as totally inactive, and remember them as such: */
1355 +
1356 +    MCD_dmaBar->taskbar = (u32) MCD_taskTable;
1357 +    for (i = 0;  i < NCHANNELS;  i++)
1358 +    {
1359 +        MCD_dmaBar->taskControl[i] = 0x0;
1360 +        MCD_chStatus[i] = MCD_NO_DMA;
1361 +    }
1362 +
1363 +   /* Set up pausing mechanism to inactive state: */
1364 +    MCD_dmaBar->debugComp1 = 0;  /* no particular values yet for either comparator registers */
1365 +    MCD_dmaBar->debugComp2 = 0;
1366 +    MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
1367 +    MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
1368 +
1369 +    /* enable or disable commbus prefetch, really need an ifdef or
1370 +       something to keep from trying to set this in the 8220 */
1371 +    if ((flags & MCD_COMM_PREFETCH_EN) != 0)
1372 +        MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
1373 +    else
1374 +        MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
1375 +
1376 +    return(MCD_OK);
1377 +}
1378 +/*********************** End of MCD_initDma() ***********************/
1379 +
1380 +/********************************************************************/
1381 +/* Function:   MCD_dmaStatus
1382 + * Purpose:    Returns the status of the DMA on the requested channel
1383 + * Arguments:  channel - channel number
1384 + * Returns:    Predefined status indicators
1385 + */
1386 +int MCD_dmaStatus (int channel)
1387 +{
1388 +    u16 tcrValue;
1389 +
1390 +    if((channel < 0) || (channel >= NCHANNELS))
1391 +        return(MCD_CHANNEL_INVALID);
1392 +
1393 +    tcrValue = MCD_dmaBar->taskControl[channel];
1394 +    if ((tcrValue & TASK_CTL_EN) == 0)
1395 +    {  /* nothing running */
1396 +        /* if last reported with task enabled */
1397 +        if (   MCD_chStatus[channel] == MCD_RUNNING
1398 +            || MCD_chStatus[channel] == MCD_IDLE)
1399 +            MCD_chStatus[channel] = MCD_DONE;
1400 +    }
1401 +    else /* something is running */
1402 +    {
1403 +        /* There are three possibilities: paused, running or idle. */
1404 +        if (   MCD_chStatus[channel] == MCD_RUNNING
1405 +            || MCD_chStatus[channel] == MCD_IDLE)
1406 +        {
1407 +            MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
1408 +            /* This register is selected to know which initiator is
1409 +            actually asserted. */
1410 +            if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 )
1411 +                MCD_chStatus[channel] = MCD_RUNNING;
1412 +            else
1413 +                MCD_chStatus[channel] = MCD_IDLE;
1414 +        /* do not change the status if it is already paused. */
1415 +        }
1416 +    }
1417 +    return MCD_chStatus[channel];
1418 +}
1419 +/******************** End of MCD_dmaStatus() ************************/
1420 +
1421 +/********************************************************************/
1422 +/* Function:    MCD_startDma
1423 + * Ppurpose:    Starts a particular kind of DMA
1424 + * Arguments:   see below
1425 + * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
1426 + */
1427 +
1428 +int MCD_startDma (
1429 +    int  channel,   /* the channel on which to run the DMA */
1430 +    s8   *srcAddr,  /* the address to move data from, or physical buffer-descriptor address */
1431 +    s16  srcIncr,   /* the amount to increment the source address per transfer */
1432 +    s8   *destAddr, /* the address to move data to */
1433 +    s16  destIncr,  /* the amount to increment the destination address per transfer */
1434 +    u32  dmaSize,   /* the number of bytes to transfer independent of the transfer size */
1435 +    u32  xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
1436 +    u32  initiator, /* what device initiates the DMA */
1437 +    int  priority,  /* priority of the DMA */
1438 +    u32  flags,     /* flags describing the DMA */
1439 +    u32  funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
1440 +#ifdef MCD_NEED_ADDR_TRANS
1441 +    s8   *srcAddrVirt /* virtual buffer descriptor address TBD*/
1442 +#endif
1443 +)
1444 +{
1445 +    int srcRsdIncr, destRsdIncr;
1446 +    int *cSave;
1447 +    short xferSizeIncr;
1448 +    int tcrCount = 0;
1449 +#ifdef MCD_INCLUDE_EU
1450 +    u32 *realFuncArray;
1451 +#endif
1452 +
1453 +    if((channel < 0) || (channel >= NCHANNELS))
1454 +        return(MCD_CHANNEL_INVALID);
1455 +
1456 +    /* tbd - need to determine the proper response to a bad funcDesc when not
1457 +       including EU functions, for now, assign a benign funcDesc, but maybe
1458 +       should return an error */
1459 +#ifndef MCD_INCLUDE_EU
1460 +    funcDesc = MCD_FUNC_NOEU1;
1461 +#endif
1462 +
1463 +#ifdef MCD_DEBUG
1464 +printf("startDma:Setting up params\n");
1465 +#endif
1466 +   /* Set us up for task-wise priority.  We don't technically need to do this on every start, but
1467 +      since the register involved is in the same longword as other registers that users are in control
1468 +      of, setting it more than once is probably preferable.  That since the documentation doesn't seem
1469 +      to be completely consistent about the nature of the PTD control register. */
1470 +    MCD_dmaBar->ptdControl |= (u16) 0x8000;
1471 +#if 1 /* Not sure what we need to keep here rtm TBD */
1472 +    /* Calculate additional parameters to the regular DMA calls. */
1473 +    srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
1474 +    destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
1475 +
1476 +    xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
1477 +
1478 +    /* Remember for each channel which variant is running. */
1479 +    MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
1480 +    MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
1481 +    MCD_remVariants.remDestIncr[channel] = destIncr;
1482 +    MCD_remVariants.remSrcIncr[channel] = srcIncr;
1483 +    MCD_remVariants.remXferSize[channel] = xferSize;
1484 +#endif
1485 +
1486 +    cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD;
1487 +
1488 +#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
1489 +    realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
1490 +    /* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
1491 +    realFuncArray[(LURC*16)] = xferSize == 4 ?
1492 +                                 funcDesc : xferSize == 2 ?
1493 +                                     funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
1494 +    realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
1495 +#endif
1496 +   /* Write the initiator field in the TCR, and also set the initiator-hold
1497 +      bit.  Note that,due to a hardware quirk, this could collide with an
1498 +      MDE access to the initiator-register file, so we have to verify that the write
1499 +      reads back correctly. */
1500 +
1501 +    MCD_dmaBar->taskControl[channel] =
1502 +        (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
1503 +
1504 +    while(((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
1505 +          ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) &&
1506 +            (tcrCount < 1000))
1507 +    {
1508 +        tcrCount++;
1509 +        /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/
1510 +        MCD_dmaBar->taskControl[channel] =
1511 +            (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
1512 +    }
1513 +
1514 +    MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK;
1515 +    /* should be albe to handle this stuff with only one write to ts reg - tbd */
1516 +    if (channel < 8 && channel >= 0)
1517 +    {
1518 +        MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4);
1519 +        MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2);
1520 +        MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4);
1521 +    }
1522 +    else
1523 +    {
1524 +        MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4);
1525 +        MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2);
1526 +        MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4);
1527 +    }
1528 +
1529 +    /* setup task table flags/options which mostly control the line buffers */
1530 +    MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
1531 +    MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
1532 +
1533 +    if (flags & MCD_FECTX_DMA)
1534 +    {
1535 +        /* TDTStart and TDTEnd */
1536 +        MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart;
1537 +        MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
1538 +        MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
1539 +    }
1540 +    else if (flags & MCD_FECRX_DMA)
1541 +    {
1542 +        /* TDTStart and TDTEnd */
1543 +        MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart;
1544 +        MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
1545 +        MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
1546 +    }
1547 +    else if(flags & MCD_SINGLE_DMA)
1548 +    {
1549 +        /* this buffer descriptor is used for storing off initial parameters for later
1550 +           progress query calculation and for the DMA to write the resulting checksum
1551 +           The DMA does not use this to determine how to operate, that info is passed
1552 +           with the init routine*/
1553 +        MCD_relocBuffDesc[channel].srcAddr = srcAddr;
1554 +        MCD_relocBuffDesc[channel].destAddr = destAddr;
1555 +        MCD_relocBuffDesc[channel].lastDestAddr = destAddr;  /* definitely not its final value */
1556 +        MCD_relocBuffDesc[channel].dmaSize = dmaSize;
1557 +        MCD_relocBuffDesc[channel].flags = 0;       /* not used */
1558 +        MCD_relocBuffDesc[channel].csumResult = 0;  /* not used */
1559 +        MCD_relocBuffDesc[channel].next = 0;        /* not used */
1560 +
1561 +        /* Initialize the progress-querying stuff to show no progress:*/
1562 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
1563 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
1564 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
1565 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
1566 +                                             (u32) &(MCD_relocBuffDesc[channel]);
1567 +        /* tbd - need to keep the user from trying to call the EU routine
1568 +           when MCD_INCLUDE_EU is not defined */
1569 +        if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
1570 +        {
1571 +           /* TDTStart and TDTEnd */
1572 +           MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
1573 +           MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
1574 +           MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize, dmaSize,
1575 +                                xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
1576 +                                MCD_taskTable, channel);
1577 +        }
1578 +        else
1579 +        {
1580 +           /* TDTStart and TDTEnd */
1581 +           MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
1582 +           MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
1583 +           MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize, dmaSize,
1584 +                              xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
1585 +                              MCD_taskTable, channel);
1586 +        }
1587 +    }
1588 +    else
1589 +    { /* chained DMAS */
1590 +        /* Initialize the progress-querying stuff to show no progress:*/
1591 +#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
1592 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
1593 +          = (int)((MCD_bufDesc*) phys_to_virt(srcAddr))->srcAddr;
1594 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
1595 +          = (int)((MCD_bufDesc*) phys_to_virt(srcAddr))->destAddr;
1596 +#else /* if using address translation, need the virtual addr of the first buffdesc */
1597 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
1598 +          = (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
1599 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
1600 +          = (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
1601 +#endif
1602 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
1603 +        ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
1604 +
1605 +        if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
1606 +        {
1607 +          /*TDTStart and TDTEnd*/
1608 +          MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
1609 +          MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
1610 +          MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize,
1611 +                                    xferSizeIncr, cSave, MCD_taskTable, channel);
1612 +        }
1613 +        else
1614 +        {
1615 +          /*TDTStart and TDTEnd*/
1616 +          MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
1617 +          MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend;
1618 +          MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize,
1619 +                                 xferSizeIncr, cSave, MCD_taskTable, channel);
1620 +        }
1621 +    }
1622 +    MCD_chStatus[channel] = MCD_IDLE;
1623 +    return(MCD_OK);
1624 +}
1625 +
1626 +/************************ End of MCD_startDma() *********************/
1627 +
1628 +/********************************************************************/
1629 +/* Function:    MCD_XferProgrQuery
1630 + * Purpose:     Returns progress of DMA on requested channel
1631 + * Arguments:   channel - channel to retrieve progress for
1632 + *              progRep - pointer to user supplied MCD_XferProg struct
1633 + * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
1634 + *
1635 + * Notes:
1636 + *  MCD_XferProgrQuery() upon completing or after aborting a DMA, or
1637 + *  while the DMA is in progress, this function returns the first
1638 + *  DMA-destination address not (or not yet) used in the DMA. When
1639 + *  encountering a non-ready buffer descriptor, the information for
1640 + *  the last completed descriptor is returned.
1641 + *
1642 + *  MCD_XferProgQuery() has to avoid the possibility of getting
1643 + *  partially-updated information in the event that we should happen
1644 + *  to query DMA progress just as the DMA is updating it. It does that
1645 + *  by taking advantage of the fact context is not saved frequently for
1646 + *  the most part. We therefore read it at least twice until we get the
1647 + *  same information twice in a row.
1648 + *
1649 + *  Because a small, but not insignificant, amount of time is required
1650 + *  to write out the progress-query information, especially upon
1651 + *  completion of the DMA, it would be wise to guarantee some time lag
1652 + *  between successive readings of the progress-query information.
1653 + */
1654 +
1655 +/*
1656 + * How many iterations of the loop below to execute to stabilize values
1657 + */
1658 +#define STABTIME 0
1659 +
1660 +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
1661 +{
1662 +    MCD_XferProg prevRep;
1663 +    int again;  /* true if we are to try again to get consistent results */
1664 +    int i;  /* used as a time-waste counter */
1665 +    int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
1666 +    int numIterations; /* number of iterations */
1667 +    int bytesNotXfered; /* bytes that did not get xfered. */
1668 +    s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
1669 +    int subModVal, addModVal; /* Mode values to added and subtracted from the
1670 +                                final destAddr */
1671 +
1672 +    if((channel < 0) || (channel >= NCHANNELS))
1673 +        return(MCD_CHANNEL_INVALID);
1674 +
1675 +    /* Read a trial value for the progress-reporting values*/
1676 +    prevRep.lastSrcAddr =
1677 +          (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
1678 +    prevRep.lastDestAddr =
1679 +          (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
1680 +    prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
1681 +    prevRep.currBufDesc =
1682 +          (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
1683 +    /* Repeatedly reread those values until they match previous values: */
1684 +    do {
1685 +        /* Waste a little bit of time to ensure stability: */
1686 +        for (i = 0;  i < STABTIME;  i++)
1687 +            i += i >> 2;  /* make sure this loop does something so that it doesn't get optimized out */
1688 +        /* Check them again: */
1689 +        progRep->lastSrcAddr =
1690 +            (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
1691 +        progRep->lastDestAddr =
1692 +            (s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
1693 +        progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
1694 +        progRep->currBufDesc =
1695 +            (MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
1696 +       /* See if they match: */
1697 +       if (   prevRep.lastSrcAddr != progRep->lastSrcAddr
1698 +           || prevRep.lastDestAddr != progRep->lastDestAddr
1699 +           || prevRep.dmaSize != progRep->dmaSize
1700 +           || prevRep.currBufDesc != progRep->currBufDesc)
1701 +       {
1702 +          /* If they don't match, remember previous values and try again:*/
1703 +          prevRep.lastSrcAddr = progRep->lastSrcAddr;
1704 +          prevRep.lastDestAddr = progRep->lastDestAddr;
1705 +          prevRep.dmaSize = progRep->dmaSize;
1706 +          prevRep.currBufDesc = progRep->currBufDesc;
1707 +          again = MCD_TRUE;
1708 +       }
1709 +       else
1710 +          again = MCD_FALSE;
1711 +    } while (again == MCD_TRUE);
1712 +
1713 +
1714 +    /* Update the dCount, srcAddr and destAddr */
1715 +    /* To calculate dmaCount, we consider destination address. C
1716 +       overs M1,P1,Z for destination */
1717 +    switch(MCD_remVariants.remDestRsdIncr[channel]) {
1718 +        case MINUS1:
1719 +           subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
1720 +           addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
1721 +           LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
1722 +           LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
1723 +           destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
1724 +           bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) *
1725 +                            ( MCD_remVariants.remDestIncr[channel]
1726 +                            + MCD_remVariants.remXferSize[channel]);
1727 +           progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal;
1728 +           break;
1729 +        case ZERO:
1730 +           progRep->lastDestAddr = progRep->currBufDesc->destAddr;
1731 +           break;
1732 +        case PLUS1:
1733 +           /* This value has to be subtracted from the final calculated dCount. */
1734 +           subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
1735 +           /* These bytes are already in lastDestAddr. */
1736 +            addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
1737 +            LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
1738 +            LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
1739 +            destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
1740 +            numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel];
1741 +            bytesNotXfered =  numIterations *
1742 +                ( MCD_remVariants.remDestIncr[channel]
1743 +                  - MCD_remVariants.remXferSize[channel]);
1744 +           progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
1745 +           break;
1746 +        default:
1747 +           break;
1748 +    }
1749 +
1750 +    /* This covers M1,P1,Z for source */
1751 +    switch(MCD_remVariants.remSrcRsdIncr[channel]) {
1752 +        case MINUS1:
1753 +            progRep->lastSrcAddr =
1754 +                progRep->currBufDesc->srcAddr +
1755 +                 ( MCD_remVariants.remSrcIncr[channel] *
1756 +                   (progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
1757 +            break;
1758 +        case ZERO:
1759 +            progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
1760 +            break;
1761 +       case PLUS1:
1762 +            progRep->lastSrcAddr =
1763 +                progRep->currBufDesc->srcAddr +
1764 +                 ( MCD_remVariants.remSrcIncr[channel] *
1765 +                   (progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
1766 +          break;
1767 +       default: break;
1768 +    }
1769 +
1770 +    return(MCD_OK);
1771 +}
1772 +/******************* End of MCD_XferProgrQuery() ********************/
1773 +
1774 +/********************************************************************/
1775 +/* MCD_resmActions() does the majority of the actions of a DMA resume.
1776 + * It is called from MCD_killDma() and MCD_resumeDma().  It has to be
1777 + * a separate function because the kill function has to negate the task
1778 + * enable before resuming it, but the resume function has to do nothing
1779 + * if there is no DMA on that channel (i.e., if the enable bit is 0).
1780 + */
1781 +static void MCD_resmActions (int channel)
1782 +{
1783 +   MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
1784 +   MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
1785 +   MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know
1786 +                                        which initiator is actually asserted. */
1787 +   if((MCD_dmaBar->ptdDebug >> channel ) & 0x1)
1788 +       MCD_chStatus[channel] = MCD_RUNNING;
1789 +   else
1790 +       MCD_chStatus[channel] = MCD_IDLE;
1791 +}
1792 +/********************* End of MCD_resmActions() *********************/
1793 +
1794 +/********************************************************************/
1795 +/* Function:    MCD_killDma
1796 + * Purpose:     Halt the DMA on the requested channel, without any
1797 + *              intention of resuming the DMA.
1798 + * Arguments:   channel - requested channel
1799 + * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
1800 + *
1801 + * Notes:
1802 + *  A DMA may be killed from any state, including paused state, and it
1803 + *  always goes to the MCD_HALTED state even if it is killed while in
1804 + *  the MCD_NO_DMA or MCD_IDLE states.
1805 + */
1806 +int MCD_killDma (int channel)
1807 +{
1808 +   /* MCD_XferProg progRep; */
1809 +
1810 +    if((channel < 0) || (channel >= NCHANNELS))
1811 +        return(MCD_CHANNEL_INVALID);
1812 +
1813 +    MCD_dmaBar->taskControl[channel] = 0x0;
1814 +    MCD_resumeDma (channel);
1815 +    /*
1816 +     * This must be after the write to the TCR so that the task doesn't
1817 +     * start up again momentarily, and before the status assignment so
1818 +     * as to override whatever MCD_resumeDma() may do to the channel
1819 +     * status.
1820 +     */
1821 +    MCD_chStatus[channel] = MCD_HALTED;
1822 +
1823 +    /*
1824 +     * Update the current buffer descriptor's lastDestAddr field
1825 +     *
1826 +     * MCD_XferProgrQuery (channel, &progRep);
1827 +     * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
1828 +     */
1829 +    return(MCD_OK);
1830 +}
1831 +/************************ End of MCD_killDma() **********************/
1832 +
1833 +/********************************************************************/
1834 +/* Function:    MCD_continDma
1835 + * Purpose:     Continue a DMA which as stopped due to encountering an
1836 + *              unready buffer descriptor.
1837 + * Arguments:   channel - channel to continue the DMA on
1838 + * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
1839 + *
1840 + * Notes:
1841 + *  This routine does not check to see if there is a task which can
1842 + *  be continued. Also this routine should not be used with single DMAs.
1843 + */
1844 +int MCD_continDma (int channel)
1845 +{
1846 +    if((channel < 0) || (channel >= NCHANNELS))
1847 +        return(MCD_CHANNEL_INVALID);
1848 +
1849 +    MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
1850 +    MCD_chStatus[channel] = MCD_RUNNING;
1851 +
1852 +    return(MCD_OK);
1853 +}
1854 +/********************** End of MCD_continDma() **********************/
1855 +
1856 +/*********************************************************************
1857 + * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
1858 + * to freeze a task and resume it.  We freeze a task by breakpointing
1859 + * on the stated task.  That is, not any specific place in the task,
1860 + * but any time that task executes.  In particular, when that task
1861 + * executes, we want to freeze that task and only that task.
1862 + *
1863 + * The bits of the debug control register influence interrupts vs.
1864 + * breakpoints as follows:
1865 + * - Bits 14 and 0 enable or disable debug functions.  If enabled, you
1866 + *   will get the interrupt but you may or may not get a breakpoint.
1867 + * - Bits 2 and 1 decide whether you also get a breakpoint in addition
1868 + *   to an interrupt.
1869 + *
1870 + * The debug unit can do these actions in response to either internally
1871 + * detected breakpoint conditions from the comparators, or in response
1872 + * to the external breakpoint pin, or both.
1873 + * - Bits 14 and 1 perform the above-described functions for
1874 + *   internally-generated conditions, i.e., the debug comparators.
1875 + * - Bits 0 and 2 perform the above-described functions for external
1876 + *   conditions, i.e., the breakpoint external pin.
1877 + *
1878 + * Note that, although you "always" get the interrupt when you turn
1879 + * the debug functions, the interrupt can nevertheless, if desired, be
1880 + * masked by the corresponding bit in the PTD's IMR. Note also that
1881 + * this means that bits 14 and 0 must enable debug functions before
1882 + * bits 1 and 2, respectively, have any effect.
1883 + *
1884 + * NOTE: It's extremely important to not pause more than one DMA channel
1885 + *  at a time.
1886 + ********************************************************************/
1887 +
1888 +/********************************************************************/
1889 +/* Function:    MCD_pauseDma
1890 + * Purpose:     Pauses the DMA on a given channel (if any DMA is running
1891 + *              on that channel).
1892 + * Arguments:   channel
1893 + * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
1894 + */
1895 +int MCD_pauseDma (int channel)
1896 +{
1897 +    /* MCD_XferProg progRep; */
1898 +
1899 +    if((channel < 0) || (channel >= NCHANNELS))
1900 +        return(MCD_CHANNEL_INVALID);
1901 +
1902 +    if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
1903 +    {
1904 +        MCD_dmaBar->debugComp1 = channel;
1905 +        MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
1906 +        MCD_chStatus[channel] = MCD_PAUSED;
1907 +
1908 +        /*
1909 +         * Update the current buffer descriptor's lastDestAddr field
1910 +         *
1911 +         * MCD_XferProgrQuery (channel, &progRep);
1912 +         * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
1913 +         */
1914 +    }
1915 +    return(MCD_OK);
1916 +}
1917 +/************************* End of MCD_pauseDma() ********************/
1918 +
1919 +/********************************************************************/
1920 +/* Function:    MCD_resumeDma
1921 + * Purpose:     Resumes the DMA on a given channel (if any DMA is
1922 + *              running on that channel).
1923 + * Arguments:   channel - channel on which to resume DMA
1924 + * Returns:     MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
1925 + */
1926 +int MCD_resumeDma (int channel)
1927 +{
1928 +    if((channel < 0) || (channel >= NCHANNELS))
1929 +        return(MCD_CHANNEL_INVALID);
1930 +
1931 +    if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
1932 +        MCD_resmActions (channel);
1933 +
1934 +    return(MCD_OK);
1935 +}
1936 +/************************ End of MCD_resumeDma() ********************/
1937 +
1938 +/********************************************************************/
1939 +/* Function:    MCD_csumQuery
1940 + * Purpose:     Provide the checksum after performing a non-chained DMA
1941 + * Arguments:   channel - channel to report on
1942 + *              csum - pointer to where to write the checksum/CRC
1943 + * Returns:     MCD_ERROR if the channel is invalid, else MCD_OK
1944 + *
1945 + * Notes:
1946 + *
1947 + */
1948 +int MCD_csumQuery (int channel, u32 *csum)
1949 +{
1950 +#ifdef MCD_INCLUDE_EU
1951 +    if((channel < 0) || (channel >= NCHANNELS))
1952 +        return(MCD_CHANNEL_INVALID);
1953 +
1954 +    *csum = MCD_relocBuffDesc[channel].csumResult;
1955 +    return(MCD_OK);
1956 +#else
1957 +    return(MCD_ERROR);
1958 +#endif
1959 +}
1960 +/*********************** End of MCD_resumeDma() *********************/
1961 +
1962 +/********************************************************************/
1963 +/* Function:    MCD_getCodeSize
1964 + * Purpose:     Provide the size requirements of the microcoded tasks
1965 + * Returns:     Size in bytes
1966 + */
1967 +int MCD_getCodeSize(void)
1968 +{
1969 +#ifdef MCD_INCLUDE_EU
1970 +    return(0x2b5c);
1971 +#else
1972 +    return(0x173c);
1973 +#endif
1974 +}
1975 +/********************** End of MCD_getCodeSize() ********************/
1976 +
1977 +/********************************************************************/
1978 +/* Function:    MCD_getVersion
1979 + * Purpose:     Provide the version string and number
1980 + * Arguments:   longVersion - user supplied pointer to a pointer to a char
1981 + *                    which points to the version string
1982 + * Returns:     Version number and version string (by reference)
1983 + */
1984 +char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
1985 +#define MCD_REV_MAJOR   0x00
1986 +#define MCD_REV_MINOR   0x03
1987 +
1988 +int MCD_getVersion(char **longVersion)
1989 +{
1990 +    *longVersion = MCD_versionString;
1991 +    return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
1992 +}
1993 +/********************** End of MCD_getVersion() *********************/
1994 +
1995 +/********************************************************************/
1996 +/* Private version of memcpy()
1997 + * Note that everything this is used for is longword-aligned.
1998 + */
1999 +static void MCD_memcpy (int *dest, int *src, u32 size)
2000 +{
2001 +    u32 i;
2002 +
2003 +    for (i = 0;  i < size;  i += sizeof(int), dest++, src++)
2004 +        *dest = *src;
2005 +}
2006 +/********************************************************************/
2007 --- /dev/null
2008 +++ b/drivers/dma/MCD_progCheck.h
2009 @@ -0,0 +1,33 @@
2010 +/*********************************************************************
2011 + *
2012 + * Copyright (C) 2004  Motorola, Inc.
2013 + *  MOTOROLA, INC. All Rights Reserved.
2014 + *  You are hereby granted a copyright license to use
2015 + *  the SOFTWARE so long as this entire notice is
2016 + *  retained without alteration in any modified and/or redistributed
2017 + *  versions, and that such modified versions are clearly identified
2018 + *  as such. No licenses are granted by implication, estoppel or
2019 + *  otherwise under any patents or trademarks of Motorola, Inc. This
2020 + *  software is provided on an "AS IS" basis and without warranty.
2021 + *
2022 + *  To the maximum extent permitted by applicable law, MOTOROLA
2023 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
2024 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
2025 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
2026 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
2027 + *  ACCOMPANYING WRITTEN MATERIALS.
2028 + *
2029 + *  To the maximum extent permitted by applicable law, IN NO EVENT
2030 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
2031 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
2032 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
2033 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
2034 + *
2035 + *  Motorola assumes no responsibility for the maintenance and support
2036 + *  of this software
2037 + ********************************************************************/
2038 + /* This file is autogenerated. Do not change */
2039 +#define CURRBD 4
2040 +#define DCOUNT 6
2041 +#define DESTPTR 5
2042 +#define SRCPTR 7
2043 --- /dev/null
2044 +++ b/drivers/dma/MCD_tasks.c
2045 @@ -0,0 +1,2452 @@
2046 +/*********************************************************************
2047 + *
2048 + * Copyright (C) 2004  Motorola, Inc.
2049 + *  MOTOROLA, INC. All Rights Reserved.
2050 + *  You are hereby granted a copyright license to use
2051 + *  the SOFTWARE so long as this entire notice is
2052 + *  retained without alteration in any modified and/or redistributed
2053 + *  versions, and that such modified versions are clearly identified
2054 + *  as such. No licenses are granted by implication, estoppel or
2055 + *  otherwise under any patents or trademarks of Motorola, Inc. This
2056 + *  software is provided on an "AS IS" basis and without warranty.
2057 + *
2058 + *  To the maximum extent permitted by applicable law, MOTOROLA
2059 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
2060 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
2061 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
2062 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
2063 + *  ACCOMPANYING WRITTEN MATERIALS.
2064 + *
2065 + *  To the maximum extent permitted by applicable law, IN NO EVENT
2066 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
2067 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
2068 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
2069 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
2070 + *
2071 + *  Motorola assumes no responsibility for the maintenance and support
2072 + *  of this software
2073 + ********************************************************************/
2074 +/*
2075 + * File:        MCD_tasks.c
2076 + * Purpose:     Contains task code and structures for Multi-channel DMA
2077 + *
2078 + * Notes:
2079 + *
2080 + *
2081 + * Modifications:
2082 + *
2083 + *
2084 + */
2085 +
2086 +#include <asm/MCD_dma.h>
2087 +
2088 +u32 MCD_varTab0[];
2089 +u32 MCD_varTab1[];
2090 +u32 MCD_varTab2[];
2091 +u32 MCD_varTab3[];
2092 +u32 MCD_varTab4[];
2093 +u32 MCD_varTab5[];
2094 +u32 MCD_varTab6[];
2095 +u32 MCD_varTab7[];
2096 +u32 MCD_varTab8[];
2097 +u32 MCD_varTab9[];
2098 +u32 MCD_varTab10[];
2099 +u32 MCD_varTab11[];
2100 +u32 MCD_varTab12[];
2101 +u32 MCD_varTab13[];
2102 +u32 MCD_varTab14[];
2103 +u32 MCD_varTab15[];
2104 +
2105 +u32 MCD_funcDescTab0[];
2106 +#ifdef MCD_INCLUDE_EU
2107 +u32 MCD_funcDescTab1[];
2108 +u32 MCD_funcDescTab2[];
2109 +u32 MCD_funcDescTab3[];
2110 +u32 MCD_funcDescTab4[];
2111 +u32 MCD_funcDescTab5[];
2112 +u32 MCD_funcDescTab6[];
2113 +u32 MCD_funcDescTab7[];
2114 +u32 MCD_funcDescTab8[];
2115 +u32 MCD_funcDescTab9[];
2116 +u32 MCD_funcDescTab10[];
2117 +u32 MCD_funcDescTab11[];
2118 +u32 MCD_funcDescTab12[];
2119 +u32 MCD_funcDescTab13[];
2120 +u32 MCD_funcDescTab14[];
2121 +u32 MCD_funcDescTab15[];
2122 +#endif
2123 +
2124 +u32 MCD_contextSave0[];
2125 +u32 MCD_contextSave1[];
2126 +u32 MCD_contextSave2[];
2127 +u32 MCD_contextSave3[];
2128 +u32 MCD_contextSave4[];
2129 +u32 MCD_contextSave5[];
2130 +u32 MCD_contextSave6[];
2131 +u32 MCD_contextSave7[];
2132 +u32 MCD_contextSave8[];
2133 +u32 MCD_contextSave9[];
2134 +u32 MCD_contextSave10[];
2135 +u32 MCD_contextSave11[];
2136 +u32 MCD_contextSave12[];
2137 +u32 MCD_contextSave13[];
2138 +u32 MCD_contextSave14[];
2139 +u32 MCD_contextSave15[];
2140 +
2141 +u32 MCD_realTaskTableSrc[] =
2142 +{
2143 +    0x00000000,
2144 +    0x00000000,
2145 +    (u32)MCD_varTab0,   /* Task 0 Variable Table */
2146 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2147 +    0x00000000,
2148 +    0x00000000,
2149 +    (u32)MCD_contextSave0,  /* Task 0 context save space */
2150 +    0x00000000,
2151 +    0x00000000,
2152 +    0x00000000,
2153 +    (u32)MCD_varTab1,   /* Task 1 Variable Table */
2154 +#ifdef MCD_INCLUDE_EU
2155 +    (u32)MCD_funcDescTab1,  /* Task 1 Function Descriptor Table & Flags */
2156 +#else
2157 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2158 +#endif
2159 +    0x00000000,
2160 +    0x00000000,
2161 +    (u32)MCD_contextSave1,  /* Task 1 context save space */
2162 +    0x00000000,
2163 +    0x00000000,
2164 +    0x00000000,
2165 +    (u32)MCD_varTab2,   /* Task 2 Variable Table */
2166 +#ifdef MCD_INCLUDE_EU
2167 +    (u32)MCD_funcDescTab2,  /* Task 2 Function Descriptor Table & Flags */
2168 +#else
2169 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2170 +#endif
2171 +    0x00000000,
2172 +    0x00000000,
2173 +    (u32)MCD_contextSave2,  /* Task 2 context save space */
2174 +    0x00000000,
2175 +    0x00000000,
2176 +    0x00000000,
2177 +    (u32)MCD_varTab3,   /* Task 3 Variable Table */
2178 +#ifdef MCD_INCLUDE_EU
2179 +    (u32)MCD_funcDescTab3,  /* Task 3 Function Descriptor Table & Flags */
2180 +#else
2181 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2182 +#endif
2183 +    0x00000000,
2184 +    0x00000000,
2185 +    (u32)MCD_contextSave3,  /* Task 3 context save space */
2186 +    0x00000000,
2187 +    0x00000000,
2188 +    0x00000000,
2189 +    (u32)MCD_varTab4,   /* Task 4 Variable Table */
2190 +#ifdef MCD_INCLUDE_EU
2191 +    (u32)MCD_funcDescTab4,  /* Task 4 Function Descriptor Table & Flags */
2192 +#else
2193 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2194 +#endif
2195 +    0x00000000,
2196 +    0x00000000,
2197 +    (u32)MCD_contextSave4,  /* Task 4 context save space */
2198 +    0x00000000,
2199 +    0x00000000,
2200 +    0x00000000,
2201 +    (u32)MCD_varTab5,   /* Task 5 Variable Table */
2202 +#ifdef MCD_INCLUDE_EU
2203 +    (u32)MCD_funcDescTab5,  /* Task 5 Function Descriptor Table & Flags */
2204 +#else
2205 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2206 +#endif
2207 +    0x00000000,
2208 +    0x00000000,
2209 +    (u32)MCD_contextSave5,  /* Task 5 context save space */
2210 +    0x00000000,
2211 +    0x00000000,
2212 +    0x00000000,
2213 +    (u32)MCD_varTab6,   /* Task 6 Variable Table */
2214 +#ifdef MCD_INCLUDE_EU
2215 +    (u32)MCD_funcDescTab6,  /* Task 6 Function Descriptor Table & Flags */
2216 +#else
2217 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2218 +#endif
2219 +    0x00000000,
2220 +    0x00000000,
2221 +    (u32)MCD_contextSave6,  /* Task 6 context save space */
2222 +    0x00000000,
2223 +    0x00000000,
2224 +    0x00000000,
2225 +    (u32)MCD_varTab7,   /* Task 7 Variable Table */
2226 +#ifdef MCD_INCLUDE_EU
2227 +    (u32)MCD_funcDescTab7,  /* Task 7 Function Descriptor Table & Flags */
2228 +#else
2229 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2230 +#endif
2231 +    0x00000000,
2232 +    0x00000000,
2233 +    (u32)MCD_contextSave7,  /* Task 7 context save space */
2234 +    0x00000000,
2235 +    0x00000000,
2236 +    0x00000000,
2237 +    (u32)MCD_varTab8,   /* Task 8 Variable Table */
2238 +#ifdef MCD_INCLUDE_EU
2239 +    (u32)MCD_funcDescTab8,  /* Task 8 Function Descriptor Table & Flags */
2240 +#else
2241 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2242 +#endif
2243 +    0x00000000,
2244 +    0x00000000,
2245 +    (u32)MCD_contextSave8,  /* Task 8 context save space */
2246 +    0x00000000,
2247 +    0x00000000,
2248 +    0x00000000,
2249 +    (u32)MCD_varTab9,   /* Task 9 Variable Table */
2250 +#ifdef MCD_INCLUDE_EU
2251 +    (u32)MCD_funcDescTab9,  /* Task 9 Function Descriptor Table & Flags */
2252 +#else
2253 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2254 +#endif
2255 +    0x00000000,
2256 +    0x00000000,
2257 +    (u32)MCD_contextSave9,  /* Task 9 context save space */
2258 +    0x00000000,
2259 +    0x00000000,
2260 +    0x00000000,
2261 +    (u32)MCD_varTab10,  /* Task 10 Variable Table */
2262 +#ifdef MCD_INCLUDE_EU
2263 +    (u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
2264 +#else
2265 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2266 +#endif
2267 +    0x00000000,
2268 +    0x00000000,
2269 +    (u32)MCD_contextSave10, /* Task 10 context save space */
2270 +    0x00000000,
2271 +    0x00000000,
2272 +    0x00000000,
2273 +    (u32)MCD_varTab11,  /* Task 11 Variable Table */
2274 +#ifdef MCD_INCLUDE_EU
2275 +    (u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
2276 +#else
2277 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2278 +#endif
2279 +    0x00000000,
2280 +    0x00000000,
2281 +    (u32)MCD_contextSave11, /* Task 11 context save space */
2282 +    0x00000000,
2283 +    0x00000000,
2284 +    0x00000000,
2285 +    (u32)MCD_varTab12,  /* Task 12 Variable Table */
2286 +#ifdef MCD_INCLUDE_EU
2287 +    (u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
2288 +#else
2289 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2290 +#endif
2291 +    0x00000000,
2292 +    0x00000000,
2293 +    (u32)MCD_contextSave12, /* Task 12 context save space */
2294 +    0x00000000,
2295 +    0x00000000,
2296 +    0x00000000,
2297 +    (u32)MCD_varTab13,  /* Task 13 Variable Table */
2298 +#ifdef MCD_INCLUDE_EU
2299 +    (u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
2300 +#else
2301 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2302 +#endif
2303 +    0x00000000,
2304 +    0x00000000,
2305 +    (u32)MCD_contextSave13, /* Task 13 context save space */
2306 +    0x00000000,
2307 +    0x00000000,
2308 +    0x00000000,
2309 +    (u32)MCD_varTab14,  /* Task 14 Variable Table */
2310 +#ifdef MCD_INCLUDE_EU
2311 +    (u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
2312 +#else
2313 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2314 +#endif
2315 +    0x00000000,
2316 +    0x00000000,
2317 +    (u32)MCD_contextSave14, /* Task 14 context save space */
2318 +    0x00000000,
2319 +    0x00000000,
2320 +    0x00000000,
2321 +    (u32)MCD_varTab15,  /* Task 15 Variable Table */
2322 +#ifdef MCD_INCLUDE_EU
2323 +    (u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
2324 +#else
2325 +    (u32)MCD_funcDescTab0,  /* Task 0 Function Descriptor Table & Flags */
2326 +#endif
2327 +    0x00000000,
2328 +    0x00000000,
2329 +    (u32)MCD_contextSave15, /* Task 15 context save space */
2330 +    0x00000000,
2331 +};
2332 +
2333 +
2334 +u32 MCD_varTab0[] =
2335 +{   /* Task 0 Variable Table */
2336 +    0x00000000, /* var[0] */
2337 +    0x00000000, /* var[1] */
2338 +    0x00000000, /* var[2] */
2339 +    0x00000000, /* var[3] */
2340 +    0x00000000, /* var[4] */
2341 +    0x00000000, /* var[5] */
2342 +    0x00000000, /* var[6] */
2343 +    0x00000000, /* var[7] */
2344 +    0x00000000, /* var[8] */
2345 +    0x00000000, /* var[9] */
2346 +    0x00000000, /* var[10] */
2347 +    0x00000000, /* var[11] */
2348 +    0x00000000, /* var[12] */
2349 +    0x00000000, /* var[13] */
2350 +    0x00000000, /* var[14] */
2351 +    0x00000000, /* var[15] */
2352 +    0x00000000, /* var[16] */
2353 +    0x00000000, /* var[17] */
2354 +    0x00000000, /* var[18] */
2355 +    0x00000000, /* var[19] */
2356 +    0x00000000, /* var[20] */
2357 +    0x00000000, /* var[21] */
2358 +    0x00000000, /* var[22] */
2359 +    0x00000000, /* var[23] */
2360 +    0xe0000000, /* inc[0] */
2361 +    0x20000000, /* inc[1] */
2362 +    0x2000ffff, /* inc[2] */
2363 +    0x00000000, /* inc[3] */
2364 +    0x00000000, /* inc[4] */
2365 +    0x00000000, /* inc[5] */
2366 +    0x00000000, /* inc[6] */
2367 +    0x00000000, /* inc[7] */
2368 +};
2369 +
2370 +
2371 +u32 MCD_varTab1[] =
2372 +{   /* Task 1 Variable Table */
2373 +    0x00000000, /* var[0] */
2374 +    0x00000000, /* var[1] */
2375 +    0x00000000, /* var[2] */
2376 +    0x00000000, /* var[3] */
2377 +    0x00000000, /* var[4] */
2378 +    0x00000000, /* var[5] */
2379 +    0x00000000, /* var[6] */
2380 +    0x00000000, /* var[7] */
2381 +    0x00000000, /* var[8] */
2382 +    0x00000000, /* var[9] */
2383 +    0x00000000, /* var[10] */
2384 +    0x00000000, /* var[11] */
2385 +    0x00000000, /* var[12] */
2386 +    0x00000000, /* var[13] */
2387 +    0x00000000, /* var[14] */
2388 +    0x00000000, /* var[15] */
2389 +    0x00000000, /* var[16] */
2390 +    0x00000000, /* var[17] */
2391 +    0x00000000, /* var[18] */
2392 +    0x00000000, /* var[19] */
2393 +    0x00000000, /* var[20] */
2394 +    0x00000000, /* var[21] */
2395 +    0x00000000, /* var[22] */
2396 +    0x00000000, /* var[23] */
2397 +    0xe0000000, /* inc[0] */
2398 +    0x20000000, /* inc[1] */
2399 +    0x2000ffff, /* inc[2] */
2400 +    0x00000000, /* inc[3] */
2401 +    0x00000000, /* inc[4] */
2402 +    0x00000000, /* inc[5] */
2403 +    0x00000000, /* inc[6] */
2404 +    0x00000000, /* inc[7] */
2405 +};
2406 +
2407 +u32 MCD_varTab2[]=
2408 +{   /* Task 2 Variable Table */
2409 +    0x00000000, /* var[0] */
2410 +    0x00000000, /* var[1] */
2411 +    0x00000000, /* var[2] */
2412 +    0x00000000, /* var[3] */
2413 +    0x00000000, /* var[4] */
2414 +    0x00000000, /* var[5] */
2415 +    0x00000000, /* var[6] */
2416 +    0x00000000, /* var[7] */
2417 +    0x00000000, /* var[8] */
2418 +    0x00000000, /* var[9] */
2419 +    0x00000000, /* var[10] */
2420 +    0x00000000, /* var[11] */
2421 +    0x00000000, /* var[12] */
2422 +    0x00000000, /* var[13] */
2423 +    0x00000000, /* var[14] */
2424 +    0x00000000, /* var[15] */
2425 +    0x00000000, /* var[16] */
2426 +    0x00000000, /* var[17] */
2427 +    0x00000000, /* var[18] */
2428 +    0x00000000, /* var[19] */
2429 +    0x00000000, /* var[20] */
2430 +    0x00000000, /* var[21] */
2431 +    0x00000000, /* var[22] */
2432 +    0x00000000, /* var[23] */
2433 +    0xe0000000, /* inc[0] */
2434 +    0x20000000, /* inc[1] */
2435 +    0x2000ffff, /* inc[2] */
2436 +    0x00000000, /* inc[3] */
2437 +    0x00000000, /* inc[4] */
2438 +    0x00000000, /* inc[5] */
2439 +    0x00000000, /* inc[6] */
2440 +    0x00000000, /* inc[7] */
2441 +};
2442 +
2443 +u32 MCD_varTab3[]=
2444 +{   /* Task 3 Variable Table */
2445 +    0x00000000, /* var[0] */
2446 +    0x00000000, /* var[1] */
2447 +    0x00000000, /* var[2] */
2448 +    0x00000000, /* var[3] */
2449 +    0x00000000, /* var[4] */
2450 +    0x00000000, /* var[5] */
2451 +    0x00000000, /* var[6] */
2452 +    0x00000000, /* var[7] */
2453 +    0x00000000, /* var[8] */
2454 +    0x00000000, /* var[9] */
2455 +    0x00000000, /* var[10] */
2456 +    0x00000000, /* var[11] */
2457 +    0x00000000, /* var[12] */
2458 +    0x00000000, /* var[13] */
2459 +    0x00000000, /* var[14] */
2460 +    0x00000000, /* var[15] */
2461 +    0x00000000, /* var[16] */
2462 +    0x00000000, /* var[17] */
2463 +    0x00000000, /* var[18] */
2464 +    0x00000000, /* var[19] */
2465 +    0x00000000, /* var[20] */
2466 +    0x00000000, /* var[21] */
2467 +    0x00000000, /* var[22] */
2468 +    0x00000000, /* var[23] */
2469 +    0xe0000000, /* inc[0] */
2470 +    0x20000000, /* inc[1] */
2471 +    0x2000ffff, /* inc[2] */
2472 +    0x00000000, /* inc[3] */
2473 +    0x00000000, /* inc[4] */
2474 +    0x00000000, /* inc[5] */
2475 +    0x00000000, /* inc[6] */
2476 +    0x00000000, /* inc[7] */
2477 +};
2478 +
2479 +u32 MCD_varTab4[]=
2480 +{   /* Task 4 Variable Table */
2481 +    0x00000000, /* var[0] */
2482 +    0x00000000, /* var[1] */
2483 +    0x00000000, /* var[2] */
2484 +    0x00000000, /* var[3] */
2485 +    0x00000000, /* var[4] */
2486 +    0x00000000, /* var[5] */
2487 +    0x00000000, /* var[6] */
2488 +    0x00000000, /* var[7] */
2489 +    0x00000000, /* var[8] */
2490 +    0x00000000, /* var[9] */
2491 +    0x00000000, /* var[10] */
2492 +    0x00000000, /* var[11] */
2493 +    0x00000000, /* var[12] */
2494 +    0x00000000, /* var[13] */
2495 +    0x00000000, /* var[14] */
2496 +    0x00000000, /* var[15] */
2497 +    0x00000000, /* var[16] */
2498 +    0x00000000, /* var[17] */
2499 +    0x00000000, /* var[18] */
2500 +    0x00000000, /* var[19] */
2501 +    0x00000000, /* var[20] */
2502 +    0x00000000, /* var[21] */
2503 +    0x00000000, /* var[22] */
2504 +    0x00000000, /* var[23] */
2505 +    0xe0000000, /* inc[0] */
2506 +    0x20000000, /* inc[1] */
2507 +    0x2000ffff, /* inc[2] */
2508 +    0x00000000, /* inc[3] */
2509 +    0x00000000, /* inc[4] */
2510 +    0x00000000, /* inc[5] */
2511 +    0x00000000, /* inc[6] */
2512 +    0x00000000, /* inc[7] */
2513 +};
2514 +
2515 +u32 MCD_varTab5[]=
2516 +{   /* Task 5 Variable Table */
2517 +    0x00000000, /* var[0] */
2518 +    0x00000000, /* var[1] */
2519 +    0x00000000, /* var[2] */
2520 +    0x00000000, /* var[3] */
2521 +    0x00000000, /* var[4] */
2522 +    0x00000000, /* var[5] */
2523 +    0x00000000, /* var[6] */
2524 +    0x00000000, /* var[7] */
2525 +    0x00000000, /* var[8] */
2526 +    0x00000000, /* var[9] */
2527 +    0x00000000, /* var[10] */
2528 +    0x00000000, /* var[11] */
2529 +    0x00000000, /* var[12] */
2530 +    0x00000000, /* var[13] */
2531 +    0x00000000, /* var[14] */
2532 +    0x00000000, /* var[15] */
2533 +    0x00000000, /* var[16] */
2534 +    0x00000000, /* var[17] */
2535 +    0x00000000, /* var[18] */
2536 +    0x00000000, /* var[19] */
2537 +    0x00000000, /* var[20] */
2538 +    0x00000000, /* var[21] */
2539 +    0x00000000, /* var[22] */
2540 +    0x00000000, /* var[23] */
2541 +    0xe0000000, /* inc[0] */
2542 +    0x20000000, /* inc[1] */
2543 +    0x2000ffff, /* inc[2] */
2544 +    0x00000000, /* inc[3] */
2545 +    0x00000000, /* inc[4] */
2546 +    0x00000000, /* inc[5] */
2547 +    0x00000000, /* inc[6] */
2548 +    0x00000000, /* inc[7] */
2549 +};
2550 +
2551 +u32 MCD_varTab6[]=
2552 +{   /* Task 6 Variable Table */
2553 +    0x00000000, /* var[0] */
2554 +    0x00000000, /* var[1] */
2555 +    0x00000000, /* var[2] */
2556 +    0x00000000, /* var[3] */
2557 +    0x00000000, /* var[4] */
2558 +    0x00000000, /* var[5] */
2559 +    0x00000000, /* var[6] */
2560 +    0x00000000, /* var[7] */
2561 +    0x00000000, /* var[8] */
2562 +    0x00000000, /* var[9] */
2563 +    0x00000000, /* var[10] */
2564 +    0x00000000, /* var[11] */
2565 +    0x00000000, /* var[12] */
2566 +    0x00000000, /* var[13] */
2567 +    0x00000000, /* var[14] */
2568 +    0x00000000, /* var[15] */
2569 +    0x00000000, /* var[16] */
2570 +    0x00000000, /* var[17] */
2571 +    0x00000000, /* var[18] */
2572 +    0x00000000, /* var[19] */
2573 +    0x00000000, /* var[20] */
2574 +    0x00000000, /* var[21] */
2575 +    0x00000000, /* var[22] */
2576 +    0x00000000, /* var[23] */
2577 +    0xe0000000, /* inc[0] */
2578 +    0x20000000, /* inc[1] */
2579 +    0x2000ffff, /* inc[2] */
2580 +    0x00000000, /* inc[3] */
2581 +    0x00000000, /* inc[4] */
2582 +    0x00000000, /* inc[5] */
2583 +    0x00000000, /* inc[6] */
2584 +    0x00000000, /* inc[7] */
2585 +};
2586 +
2587 +u32 MCD_varTab7[]=
2588 +{   /* Task 7 Variable Table */
2589 +    0x00000000, /* var[0] */
2590 +    0x00000000, /* var[1] */
2591 +    0x00000000, /* var[2] */
2592 +    0x00000000, /* var[3] */
2593 +    0x00000000, /* var[4] */
2594 +    0x00000000, /* var[5] */
2595 +    0x00000000, /* var[6] */
2596 +    0x00000000, /* var[7] */
2597 +    0x00000000, /* var[8] */
2598 +    0x00000000, /* var[9] */
2599 +    0x00000000, /* var[10] */
2600 +    0x00000000, /* var[11] */
2601 +    0x00000000, /* var[12] */
2602 +    0x00000000, /* var[13] */
2603 +    0x00000000, /* var[14] */
2604 +    0x00000000, /* var[15] */
2605 +    0x00000000, /* var[16] */
2606 +    0x00000000, /* var[17] */
2607 +    0x00000000, /* var[18] */
2608 +    0x00000000, /* var[19] */
2609 +    0x00000000, /* var[20] */
2610 +    0x00000000, /* var[21] */
2611 +    0x00000000, /* var[22] */
2612 +    0x00000000, /* var[23] */
2613 +    0xe0000000, /* inc[0] */
2614 +    0x20000000, /* inc[1] */
2615 +    0x2000ffff, /* inc[2] */
2616 +    0x00000000, /* inc[3] */
2617 +    0x00000000, /* inc[4] */
2618 +    0x00000000, /* inc[5] */
2619 +    0x00000000, /* inc[6] */
2620 +    0x00000000, /* inc[7] */
2621 +};
2622 +
2623 +u32 MCD_varTab8[]=
2624 +{   /* Task 8 Variable Table */
2625 +    0x00000000, /* var[0] */
2626 +    0x00000000, /* var[1] */
2627 +    0x00000000, /* var[2] */
2628 +    0x00000000, /* var[3] */
2629 +    0x00000000, /* var[4] */
2630 +    0x00000000, /* var[5] */
2631 +    0x00000000, /* var[6] */
2632 +    0x00000000, /* var[7] */
2633 +    0x00000000, /* var[8] */
2634 +    0x00000000, /* var[9] */
2635 +    0x00000000, /* var[10] */
2636 +    0x00000000, /* var[11] */
2637 +    0x00000000, /* var[12] */
2638 +    0x00000000, /* var[13] */
2639 +    0x00000000, /* var[14] */
2640 +    0x00000000, /* var[15] */
2641 +    0x00000000, /* var[16] */
2642 +    0x00000000, /* var[17] */
2643 +    0x00000000, /* var[18] */
2644 +    0x00000000, /* var[19] */
2645 +    0x00000000, /* var[20] */
2646 +    0x00000000, /* var[21] */
2647 +    0x00000000, /* var[22] */
2648 +    0x00000000, /* var[23] */
2649 +    0xe0000000, /* inc[0] */
2650 +    0x20000000, /* inc[1] */
2651 +    0x2000ffff, /* inc[2] */
2652 +    0x00000000, /* inc[3] */
2653 +    0x00000000, /* inc[4] */
2654 +    0x00000000, /* inc[5] */
2655 +    0x00000000, /* inc[6] */
2656 +    0x00000000, /* inc[7] */
2657 +};
2658 +
2659 +u32 MCD_varTab9[]=
2660 +{   /* Task 9 Variable Table */
2661 +    0x00000000, /* var[0] */
2662 +    0x00000000, /* var[1] */
2663 +    0x00000000, /* var[2] */
2664 +    0x00000000, /* var[3] */
2665 +    0x00000000, /* var[4] */
2666 +    0x00000000, /* var[5] */
2667 +    0x00000000, /* var[6] */
2668 +    0x00000000, /* var[7] */
2669 +    0x00000000, /* var[8] */
2670 +    0x00000000, /* var[9] */
2671 +    0x00000000, /* var[10] */
2672 +    0x00000000, /* var[11] */
2673 +    0x00000000, /* var[12] */
2674 +    0x00000000, /* var[13] */
2675 +    0x00000000, /* var[14] */
2676 +    0x00000000, /* var[15] */
2677 +    0x00000000, /* var[16] */
2678 +    0x00000000, /* var[17] */
2679 +    0x00000000, /* var[18] */
2680 +    0x00000000, /* var[19] */
2681 +    0x00000000, /* var[20] */
2682 +    0x00000000, /* var[21] */
2683 +    0x00000000, /* var[22] */
2684 +    0x00000000, /* var[23] */
2685 +    0xe0000000, /* inc[0] */
2686 +    0x20000000, /* inc[1] */
2687 +    0x2000ffff, /* inc[2] */
2688 +    0x00000000, /* inc[3] */
2689 +    0x00000000, /* inc[4] */
2690 +    0x00000000, /* inc[5] */
2691 +    0x00000000, /* inc[6] */
2692 +    0x00000000, /* inc[7] */
2693 +};
2694 +
2695 +u32 MCD_varTab10[]=
2696 +{   /* Task 10 Variable Table */
2697 +    0x00000000, /* var[0] */
2698 +    0x00000000, /* var[1] */
2699 +    0x00000000, /* var[2] */
2700 +    0x00000000, /* var[3] */
2701 +    0x00000000, /* var[4] */
2702 +    0x00000000, /* var[5] */
2703 +    0x00000000, /* var[6] */
2704 +    0x00000000, /* var[7] */
2705 +    0x00000000, /* var[8] */
2706 +    0x00000000, /* var[9] */
2707 +    0x00000000, /* var[10] */
2708 +    0x00000000, /* var[11] */
2709 +    0x00000000, /* var[12] */
2710 +    0x00000000, /* var[13] */
2711 +    0x00000000, /* var[14] */
2712 +    0x00000000, /* var[15] */
2713 +    0x00000000, /* var[16] */
2714 +    0x00000000, /* var[17] */
2715 +    0x00000000, /* var[18] */
2716 +    0x00000000, /* var[19] */
2717 +    0x00000000, /* var[20] */
2718 +    0x00000000, /* var[21] */
2719 +    0x00000000, /* var[22] */
2720 +    0x00000000, /* var[23] */
2721 +    0xe0000000, /* inc[0] */
2722 +    0x20000000, /* inc[1] */
2723 +    0x2000ffff, /* inc[2] */
2724 +    0x00000000, /* inc[3] */
2725 +    0x00000000, /* inc[4] */
2726 +    0x00000000, /* inc[5] */
2727 +    0x00000000, /* inc[6] */
2728 +    0x00000000, /* inc[7] */
2729 +};
2730 +
2731 +u32 MCD_varTab11[]=
2732 +{   /* Task 11 Variable Table */
2733 +    0x00000000, /* var[0] */
2734 +    0x00000000, /* var[1] */
2735 +    0x00000000, /* var[2] */
2736 +    0x00000000, /* var[3] */
2737 +    0x00000000, /* var[4] */
2738 +    0x00000000, /* var[5] */
2739 +    0x00000000, /* var[6] */
2740 +    0x00000000, /* var[7] */
2741 +    0x00000000, /* var[8] */
2742 +    0x00000000, /* var[9] */
2743 +    0x00000000, /* var[10] */
2744 +    0x00000000, /* var[11] */
2745 +    0x00000000, /* var[12] */
2746 +    0x00000000, /* var[13] */
2747 +    0x00000000, /* var[14] */
2748 +    0x00000000, /* var[15] */
2749 +    0x00000000, /* var[16] */
2750 +    0x00000000, /* var[17] */
2751 +    0x00000000, /* var[18] */
2752 +    0x00000000, /* var[19] */
2753 +    0x00000000, /* var[20] */
2754 +    0x00000000, /* var[21] */
2755 +    0x00000000, /* var[22] */
2756 +    0x00000000, /* var[23] */
2757 +    0xe0000000, /* inc[0] */
2758 +    0x20000000, /* inc[1] */
2759 +    0x2000ffff, /* inc[2] */
2760 +    0x00000000, /* inc[3] */
2761 +    0x00000000, /* inc[4] */
2762 +    0x00000000, /* inc[5] */
2763 +    0x00000000, /* inc[6] */
2764 +    0x00000000, /* inc[7] */
2765 +};
2766 +
2767 +u32 MCD_varTab12[]=
2768 +{   /* Task 12 Variable Table */
2769 +    0x00000000, /* var[0] */
2770 +    0x00000000, /* var[1] */
2771 +    0x00000000, /* var[2] */
2772 +    0x00000000, /* var[3] */
2773 +    0x00000000, /* var[4] */
2774 +    0x00000000, /* var[5] */
2775 +    0x00000000, /* var[6] */
2776 +    0x00000000, /* var[7] */
2777 +    0x00000000, /* var[8] */
2778 +    0x00000000, /* var[9] */
2779 +    0x00000000, /* var[10] */
2780 +    0x00000000, /* var[11] */
2781 +    0x00000000, /* var[12] */
2782 +    0x00000000, /* var[13] */
2783 +    0x00000000, /* var[14] */
2784 +    0x00000000, /* var[15] */
2785 +    0x00000000, /* var[16] */
2786 +    0x00000000, /* var[17] */
2787 +    0x00000000, /* var[18] */
2788 +    0x00000000, /* var[19] */
2789 +    0x00000000, /* var[20] */
2790 +    0x00000000, /* var[21] */
2791 +    0x00000000, /* var[22] */
2792 +    0x00000000, /* var[23] */
2793 +    0xe0000000, /* inc[0] */
2794 +    0x20000000, /* inc[1] */
2795 +    0x2000ffff, /* inc[2] */
2796 +    0x00000000, /* inc[3] */
2797 +    0x00000000, /* inc[4] */
2798 +    0x00000000, /* inc[5] */
2799 +    0x00000000, /* inc[6] */
2800 +    0x00000000, /* inc[7] */
2801 +};
2802 +
2803 +u32 MCD_varTab13[]=
2804 +{   /* Task 13 Variable Table */
2805 +    0x00000000, /* var[0] */
2806 +    0x00000000, /* var[1] */
2807 +    0x00000000, /* var[2] */
2808 +    0x00000000, /* var[3] */
2809 +    0x00000000, /* var[4] */
2810 +    0x00000000, /* var[5] */
2811 +    0x00000000, /* var[6] */
2812 +    0x00000000, /* var[7] */
2813 +    0x00000000, /* var[8] */
2814 +    0x00000000, /* var[9] */
2815 +    0x00000000, /* var[10] */
2816 +    0x00000000, /* var[11] */
2817 +    0x00000000, /* var[12] */
2818 +    0x00000000, /* var[13] */
2819 +    0x00000000, /* var[14] */
2820 +    0x00000000, /* var[15] */
2821 +    0x00000000, /* var[16] */
2822 +    0x00000000, /* var[17] */
2823 +    0x00000000, /* var[18] */
2824 +    0x00000000, /* var[19] */
2825 +    0x00000000, /* var[20] */
2826 +    0x00000000, /* var[21] */
2827 +    0x00000000, /* var[22] */
2828 +    0x00000000, /* var[23] */
2829 +    0xe0000000, /* inc[0] */
2830 +    0x20000000, /* inc[1] */
2831 +    0x2000ffff, /* inc[2] */
2832 +    0x00000000, /* inc[3] */
2833 +    0x00000000, /* inc[4] */
2834 +    0x00000000, /* inc[5] */
2835 +    0x00000000, /* inc[6] */
2836 +    0x00000000, /* inc[7] */
2837 +};
2838 +
2839 +u32 MCD_varTab14[]=
2840 +{   /* Task 14 Variable Table */
2841 +    0x00000000, /* var[0] */
2842 +    0x00000000, /* var[1] */
2843 +    0x00000000, /* var[2] */
2844 +    0x00000000, /* var[3] */
2845 +    0x00000000, /* var[4] */
2846 +    0x00000000, /* var[5] */
2847 +    0x00000000, /* var[6] */
2848 +    0x00000000, /* var[7] */
2849 +    0x00000000, /* var[8] */
2850 +    0x00000000, /* var[9] */
2851 +    0x00000000, /* var[10] */
2852 +    0x00000000, /* var[11] */
2853 +    0x00000000, /* var[12] */
2854 +    0x00000000, /* var[13] */
2855 +    0x00000000, /* var[14] */
2856 +    0x00000000, /* var[15] */
2857 +    0x00000000, /* var[16] */
2858 +    0x00000000, /* var[17] */
2859 +    0x00000000, /* var[18] */
2860 +    0x00000000, /* var[19] */
2861 +    0x00000000, /* var[20] */
2862 +    0x00000000, /* var[21] */
2863 +    0x00000000, /* var[22] */
2864 +    0x00000000, /* var[23] */
2865 +    0xe0000000, /* inc[0] */
2866 +    0x20000000, /* inc[1] */
2867 +    0x2000ffff, /* inc[2] */
2868 +    0x00000000, /* inc[3] */
2869 +    0x00000000, /* inc[4] */
2870 +    0x00000000, /* inc[5] */
2871 +    0x00000000, /* inc[6] */
2872 +    0x00000000, /* inc[7] */
2873 +};
2874 +
2875 +u32 MCD_varTab15[]=
2876 +{   /* Task 15 Variable Table */
2877 +    0x00000000, /* var[0] */
2878 +    0x00000000, /* var[1] */
2879 +    0x00000000, /* var[2] */
2880 +    0x00000000, /* var[3] */
2881 +    0x00000000, /* var[4] */
2882 +    0x00000000, /* var[5] */
2883 +    0x00000000, /* var[6] */
2884 +    0x00000000, /* var[7] */
2885 +    0x00000000, /* var[8] */
2886 +    0x00000000, /* var[9] */
2887 +    0x00000000, /* var[10] */
2888 +    0x00000000, /* var[11] */
2889 +    0x00000000, /* var[12] */
2890 +    0x00000000, /* var[13] */
2891 +    0x00000000, /* var[14] */
2892 +    0x00000000, /* var[15] */
2893 +    0x00000000, /* var[16] */
2894 +    0x00000000, /* var[17] */
2895 +    0x00000000, /* var[18] */
2896 +    0x00000000, /* var[19] */
2897 +    0x00000000, /* var[20] */
2898 +    0x00000000, /* var[21] */
2899 +    0x00000000, /* var[22] */
2900 +    0x00000000, /* var[23] */
2901 +    0xe0000000, /* inc[0] */
2902 +    0x20000000, /* inc[1] */
2903 +    0x2000ffff, /* inc[2] */
2904 +    0x00000000, /* inc[3] */
2905 +    0x00000000, /* inc[4] */
2906 +    0x00000000, /* inc[5] */
2907 +    0x00000000, /* inc[6] */
2908 +    0x00000000, /* inc[7] */
2909 +};
2910 +
2911 +u32 MCD_funcDescTab0[]=
2912 +{   /* Task 0 Function Descriptor Table */
2913 +    0x00000000,
2914 +    0x00000000,
2915 +    0x00000000,
2916 +    0x00000000,
2917 +    0x00000000,
2918 +    0x00000000,
2919 +    0x00000000,
2920 +    0x00000000,
2921 +    0x00000000,
2922 +    0x00000000,
2923 +    0x00000000,
2924 +    0x00000000,
2925 +    0x00000000,
2926 +    0x00000000,
2927 +    0x00000000,
2928 +    0x00000000,
2929 +    0x00000000,
2930 +    0x00000000,
2931 +    0x00000000,
2932 +    0x00000000,
2933 +    0x00000000,
2934 +    0x00000000,
2935 +    0x00000000,
2936 +    0x00000000,
2937 +    0x00000000,
2938 +    0x00000000,
2939 +    0x00000000,
2940 +    0x00000000,
2941 +    0x00000000,
2942 +    0x00000000,
2943 +    0x00000000,
2944 +    0x00000000,
2945 +    0x00000000,
2946 +    0x00000000,
2947 +    0x00000000,
2948 +    0x00000000,
2949 +    0x00000000,
2950 +    0x00000000,
2951 +    0x00000000,
2952 +    0x00000000,
2953 +    0x00000000,
2954 +    0x00000000,
2955 +    0x00000000,
2956 +    0x00000000,
2957 +    0x00000000,
2958 +    0x00000000,
2959 +    0x00000000,
2960 +    0x00000000,
2961 +    0xa0045670, /* mainFunc(), EU# 3 */
2962 +    0xa0000000, /* rsduFunc(), EU# 3 */
2963 +    0xa0000000, /* crcAccumVal(), EU# 3 */
2964 +    0x20000000, /* setCrcAccum(), EU# 3 */
2965 +    0x21800000, /* and(), EU# 3 */
2966 +    0x21e00000, /* or(), EU# 3 */
2967 +    0x20400000, /* add(), EU# 3 */
2968 +    0x20500000, /* sub(), EU# 3 */
2969 +    0x205a0000, /* andNot(), EU# 3 */
2970 +    0x202fa000, /* andReadyBit(), EU# 3 */
2971 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
2972 +    0x202ea000, /* andWrapBit(), EU# 3 */
2973 +    0x202da000, /* andEndFrameBit(), EU# 3 */
2974 +    0x202e2000, /* andInterruptBit(), EU# 3 */
2975 +    0x202f2000, /* andLoopBit(), EU# 3 */
2976 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
2977 +};
2978 +
2979 +#ifdef MCD_INCLUDE_EU
2980 +u32 MCD_funcDescTab1[]=
2981 +{   /* Task 1 Function Descriptor Table */
2982 +    0x00000000,
2983 +    0x00000000,
2984 +    0x00000000,
2985 +    0x00000000,
2986 +    0x00000000,
2987 +    0x00000000,
2988 +    0x00000000,
2989 +    0x00000000,
2990 +    0x00000000,
2991 +    0x00000000,
2992 +    0x00000000,
2993 +    0x00000000,
2994 +    0x00000000,
2995 +    0x00000000,
2996 +    0x00000000,
2997 +    0x00000000,
2998 +    0x00000000,
2999 +    0x00000000,
3000 +    0x00000000,
3001 +    0x00000000,
3002 +    0x00000000,
3003 +    0x00000000,
3004 +    0x00000000,
3005 +    0x00000000,
3006 +    0x00000000,
3007 +    0x00000000,
3008 +    0x00000000,
3009 +    0x00000000,
3010 +    0x00000000,
3011 +    0x00000000,
3012 +    0x00000000,
3013 +    0x00000000,
3014 +    0x00000000,
3015 +    0x00000000,
3016 +    0x00000000,
3017 +    0x00000000,
3018 +    0x00000000,
3019 +    0x00000000,
3020 +    0x00000000,
3021 +    0x00000000,
3022 +    0x00000000,
3023 +    0x00000000,
3024 +    0x00000000,
3025 +    0x00000000,
3026 +    0x00000000,
3027 +    0x00000000,
3028 +    0x00000000,
3029 +    0x00000000,
3030 +    0xa0045670, /* mainFunc(), EU# 3 */
3031 +    0xa0000000, /* rsduFunc(), EU# 3 */
3032 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3033 +    0x20000000, /* setCrcAccum(), EU# 3 */
3034 +    0x21800000, /* and(), EU# 3 */
3035 +    0x21e00000, /* or(), EU# 3 */
3036 +    0x20400000, /* add(), EU# 3 */
3037 +    0x20500000, /* sub(), EU# 3 */
3038 +    0x205a0000, /* andNot(), EU# 3 */
3039 +    0x202fa000, /* andReadyBit(), EU# 3 */
3040 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3041 +    0x202ea000, /* andWrapBit(), EU# 3 */
3042 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3043 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3044 +    0x202f2000, /* andLoopBit(), EU# 3 */
3045 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3046 +};
3047 +
3048 +u32 MCD_funcDescTab2[]=
3049 +{   /* Task 2 Function Descriptor Table */
3050 +    0x00000000,
3051 +    0x00000000,
3052 +    0x00000000,
3053 +    0x00000000,
3054 +    0x00000000,
3055 +    0x00000000,
3056 +    0x00000000,
3057 +    0x00000000,
3058 +    0x00000000,
3059 +    0x00000000,
3060 +    0x00000000,
3061 +    0x00000000,
3062 +    0x00000000,
3063 +    0x00000000,
3064 +    0x00000000,
3065 +    0x00000000,
3066 +    0x00000000,
3067 +    0x00000000,
3068 +    0x00000000,
3069 +    0x00000000,
3070 +    0x00000000,
3071 +    0x00000000,
3072 +    0x00000000,
3073 +    0x00000000,
3074 +    0x00000000,
3075 +    0x00000000,
3076 +    0x00000000,
3077 +    0x00000000,
3078 +    0x00000000,
3079 +    0x00000000,
3080 +    0x00000000,
3081 +    0x00000000,
3082 +    0x00000000,
3083 +    0x00000000,
3084 +    0x00000000,
3085 +    0x00000000,
3086 +    0x00000000,
3087 +    0x00000000,
3088 +    0x00000000,
3089 +    0x00000000,
3090 +    0x00000000,
3091 +    0x00000000,
3092 +    0x00000000,
3093 +    0x00000000,
3094 +    0x00000000,
3095 +    0x00000000,
3096 +    0x00000000,
3097 +    0x00000000,
3098 +    0xa0045670, /* mainFunc(), EU# 3 */
3099 +    0xa0000000, /* rsduFunc(), EU# 3 */
3100 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3101 +    0x20000000, /* setCrcAccum(), EU# 3 */
3102 +    0x21800000, /* and(), EU# 3 */
3103 +    0x21e00000, /* or(), EU# 3 */
3104 +    0x20400000, /* add(), EU# 3 */
3105 +    0x20500000, /* sub(), EU# 3 */
3106 +    0x205a0000, /* andNot(), EU# 3 */
3107 +    0x202fa000, /* andReadyBit(), EU# 3 */
3108 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3109 +    0x202ea000, /* andWrapBit(), EU# 3 */
3110 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3111 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3112 +    0x202f2000, /* andLoopBit(), EU# 3 */
3113 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3114 +};
3115 +
3116 +u32 MCD_funcDescTab3[]=
3117 +{   /* Task 3 Function Descriptor Table */
3118 +    0x00000000,
3119 +    0x00000000,
3120 +    0x00000000,
3121 +    0x00000000,
3122 +    0x00000000,
3123 +    0x00000000,
3124 +    0x00000000,
3125 +    0x00000000,
3126 +    0x00000000,
3127 +    0x00000000,
3128 +    0x00000000,
3129 +    0x00000000,
3130 +    0x00000000,
3131 +    0x00000000,
3132 +    0x00000000,
3133 +    0x00000000,
3134 +    0x00000000,
3135 +    0x00000000,
3136 +    0x00000000,
3137 +    0x00000000,
3138 +    0x00000000,
3139 +    0x00000000,
3140 +    0x00000000,
3141 +    0x00000000,
3142 +    0x00000000,
3143 +    0x00000000,
3144 +    0x00000000,
3145 +    0x00000000,
3146 +    0x00000000,
3147 +    0x00000000,
3148 +    0x00000000,
3149 +    0x00000000,
3150 +    0x00000000,
3151 +    0x00000000,
3152 +    0x00000000,
3153 +    0x00000000,
3154 +    0x00000000,
3155 +    0x00000000,
3156 +    0x00000000,
3157 +    0x00000000,
3158 +    0x00000000,
3159 +    0x00000000,
3160 +    0x00000000,
3161 +    0x00000000,
3162 +    0x00000000,
3163 +    0x00000000,
3164 +    0x00000000,
3165 +    0x00000000,
3166 +    0xa0045670, /* mainFunc(), EU# 3 */
3167 +    0xa0000000, /* rsduFunc(), EU# 3 */
3168 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3169 +    0x20000000, /* setCrcAccum(), EU# 3 */
3170 +    0x21800000, /* and(), EU# 3 */
3171 +    0x21e00000, /* or(), EU# 3 */
3172 +    0x20400000, /* add(), EU# 3 */
3173 +    0x20500000, /* sub(), EU# 3 */
3174 +    0x205a0000, /* andNot(), EU# 3 */
3175 +    0x202fa000, /* andReadyBit(), EU# 3 */
3176 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3177 +    0x202ea000, /* andWrapBit(), EU# 3 */
3178 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3179 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3180 +    0x202f2000, /* andLoopBit(), EU# 3 */
3181 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3182 +};
3183 +
3184 +u32 MCD_funcDescTab4[]=
3185 +{   /* Task 4 Function Descriptor Table */
3186 +    0x00000000,
3187 +    0x00000000,
3188 +    0x00000000,
3189 +    0x00000000,
3190 +    0x00000000,
3191 +    0x00000000,
3192 +    0x00000000,
3193 +    0x00000000,
3194 +    0x00000000,
3195 +    0x00000000,
3196 +    0x00000000,
3197 +    0x00000000,
3198 +    0x00000000,
3199 +    0x00000000,
3200 +    0x00000000,
3201 +    0x00000000,
3202 +    0x00000000,
3203 +    0x00000000,
3204 +    0x00000000,
3205 +    0x00000000,
3206 +    0x00000000,
3207 +    0x00000000,
3208 +    0x00000000,
3209 +    0x00000000,
3210 +    0x00000000,
3211 +    0x00000000,
3212 +    0x00000000,
3213 +    0x00000000,
3214 +    0x00000000,
3215 +    0x00000000,
3216 +    0x00000000,
3217 +    0x00000000,
3218 +    0x00000000,
3219 +    0x00000000,
3220 +    0x00000000,
3221 +    0x00000000,
3222 +    0x00000000,
3223 +    0x00000000,
3224 +    0x00000000,
3225 +    0x00000000,
3226 +    0x00000000,
3227 +    0x00000000,
3228 +    0x00000000,
3229 +    0x00000000,
3230 +    0x00000000,
3231 +    0x00000000,
3232 +    0x00000000,
3233 +    0x00000000,
3234 +    0xa0045670, /* mainFunc(), EU# 3 */
3235 +    0xa0000000, /* rsduFunc(), EU# 3 */
3236 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3237 +    0x20000000, /* setCrcAccum(), EU# 3 */
3238 +    0x21800000, /* and(), EU# 3 */
3239 +    0x21e00000, /* or(), EU# 3 */
3240 +    0x20400000, /* add(), EU# 3 */
3241 +    0x20500000, /* sub(), EU# 3 */
3242 +    0x205a0000, /* andNot(), EU# 3 */
3243 +    0x202fa000, /* andReadyBit(), EU# 3 */
3244 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3245 +    0x202ea000, /* andWrapBit(), EU# 3 */
3246 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3247 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3248 +    0x202f2000, /* andLoopBit(), EU# 3 */
3249 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3250 +};
3251 +
3252 +u32 MCD_funcDescTab5[]=
3253 +{   /* Task 5 Function Descriptor Table */
3254 +    0x00000000,
3255 +    0x00000000,
3256 +    0x00000000,
3257 +    0x00000000,
3258 +    0x00000000,
3259 +    0x00000000,
3260 +    0x00000000,
3261 +    0x00000000,
3262 +    0x00000000,
3263 +    0x00000000,
3264 +    0x00000000,
3265 +    0x00000000,
3266 +    0x00000000,
3267 +    0x00000000,
3268 +    0x00000000,
3269 +    0x00000000,
3270 +    0x00000000,
3271 +    0x00000000,
3272 +    0x00000000,
3273 +    0x00000000,
3274 +    0x00000000,
3275 +    0x00000000,
3276 +    0x00000000,
3277 +    0x00000000,
3278 +    0x00000000,
3279 +    0x00000000,
3280 +    0x00000000,
3281 +    0x00000000,
3282 +    0x00000000,
3283 +    0x00000000,
3284 +    0x00000000,
3285 +    0x00000000,
3286 +    0x00000000,
3287 +    0x00000000,
3288 +    0x00000000,
3289 +    0x00000000,
3290 +    0x00000000,
3291 +    0x00000000,
3292 +    0x00000000,
3293 +    0x00000000,
3294 +    0x00000000,
3295 +    0x00000000,
3296 +    0x00000000,
3297 +    0x00000000,
3298 +    0x00000000,
3299 +    0x00000000,
3300 +    0x00000000,
3301 +    0x00000000,
3302 +    0xa0045670, /* mainFunc(), EU# 3 */
3303 +    0xa0000000, /* rsduFunc(), EU# 3 */
3304 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3305 +    0x20000000, /* setCrcAccum(), EU# 3 */
3306 +    0x21800000, /* and(), EU# 3 */
3307 +    0x21e00000, /* or(), EU# 3 */
3308 +    0x20400000, /* add(), EU# 3 */
3309 +    0x20500000, /* sub(), EU# 3 */
3310 +    0x205a0000, /* andNot(), EU# 3 */
3311 +    0x202fa000, /* andReadyBit(), EU# 3 */
3312 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3313 +    0x202ea000, /* andWrapBit(), EU# 3 */
3314 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3315 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3316 +    0x202f2000, /* andLoopBit(), EU# 3 */
3317 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3318 +};
3319 +
3320 +u32 MCD_funcDescTab6[]=
3321 +{   /* Task 6 Function Descriptor Table */
3322 +    0x00000000,
3323 +    0x00000000,
3324 +    0x00000000,
3325 +    0x00000000,
3326 +    0x00000000,
3327 +    0x00000000,
3328 +    0x00000000,
3329 +    0x00000000,
3330 +    0x00000000,
3331 +    0x00000000,
3332 +    0x00000000,
3333 +    0x00000000,
3334 +    0x00000000,
3335 +    0x00000000,
3336 +    0x00000000,
3337 +    0x00000000,
3338 +    0x00000000,
3339 +    0x00000000,
3340 +    0x00000000,
3341 +    0x00000000,
3342 +    0x00000000,
3343 +    0x00000000,
3344 +    0x00000000,
3345 +    0x00000000,
3346 +    0x00000000,
3347 +    0x00000000,
3348 +    0x00000000,
3349 +    0x00000000,
3350 +    0x00000000,
3351 +    0x00000000,
3352 +    0x00000000,
3353 +    0x00000000,
3354 +    0x00000000,
3355 +    0x00000000,
3356 +    0x00000000,
3357 +    0x00000000,
3358 +    0x00000000,
3359 +    0x00000000,
3360 +    0x00000000,
3361 +    0x00000000,
3362 +    0x00000000,
3363 +    0x00000000,
3364 +    0x00000000,
3365 +    0x00000000,
3366 +    0x00000000,
3367 +    0x00000000,
3368 +    0x00000000,
3369 +    0x00000000,
3370 +    0xa0045670, /* mainFunc(), EU# 3 */
3371 +    0xa0000000, /* rsduFunc(), EU# 3 */
3372 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3373 +    0x20000000, /* setCrcAccum(), EU# 3 */
3374 +    0x21800000, /* and(), EU# 3 */
3375 +    0x21e00000, /* or(), EU# 3 */
3376 +    0x20400000, /* add(), EU# 3 */
3377 +    0x20500000, /* sub(), EU# 3 */
3378 +    0x205a0000, /* andNot(), EU# 3 */
3379 +    0x202fa000, /* andReadyBit(), EU# 3 */
3380 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3381 +    0x202ea000, /* andWrapBit(), EU# 3 */
3382 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3383 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3384 +    0x202f2000, /* andLoopBit(), EU# 3 */
3385 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3386 +};
3387 +
3388 +u32 MCD_funcDescTab7[]=
3389 +{   /* Task 7 Function Descriptor Table */
3390 +    0x00000000,
3391 +    0x00000000,
3392 +    0x00000000,
3393 +    0x00000000,
3394 +    0x00000000,
3395 +    0x00000000,
3396 +    0x00000000,
3397 +    0x00000000,
3398 +    0x00000000,
3399 +    0x00000000,
3400 +    0x00000000,
3401 +    0x00000000,
3402 +    0x00000000,
3403 +    0x00000000,
3404 +    0x00000000,
3405 +    0x00000000,
3406 +    0x00000000,
3407 +    0x00000000,
3408 +    0x00000000,
3409 +    0x00000000,
3410 +    0x00000000,
3411 +    0x00000000,
3412 +    0x00000000,
3413 +    0x00000000,
3414 +    0x00000000,
3415 +    0x00000000,
3416 +    0x00000000,
3417 +    0x00000000,
3418 +    0x00000000,
3419 +    0x00000000,
3420 +    0x00000000,
3421 +    0x00000000,
3422 +    0x00000000,
3423 +    0x00000000,
3424 +    0x00000000,
3425 +    0x00000000,
3426 +    0x00000000,
3427 +    0x00000000,
3428 +    0x00000000,
3429 +    0x00000000,
3430 +    0x00000000,
3431 +    0x00000000,
3432 +    0x00000000,
3433 +    0x00000000,
3434 +    0x00000000,
3435 +    0x00000000,
3436 +    0x00000000,
3437 +    0x00000000,
3438 +    0xa0045670, /* mainFunc(), EU# 3 */
3439 +    0xa0000000, /* rsduFunc(), EU# 3 */
3440 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3441 +    0x20000000, /* setCrcAccum(), EU# 3 */
3442 +    0x21800000, /* and(), EU# 3 */
3443 +    0x21e00000, /* or(), EU# 3 */
3444 +    0x20400000, /* add(), EU# 3 */
3445 +    0x20500000, /* sub(), EU# 3 */
3446 +    0x205a0000, /* andNot(), EU# 3 */
3447 +    0x202fa000, /* andReadyBit(), EU# 3 */
3448 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3449 +    0x202ea000, /* andWrapBit(), EU# 3 */
3450 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3451 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3452 +    0x202f2000, /* andLoopBit(), EU# 3 */
3453 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3454 +};
3455 +
3456 +u32 MCD_funcDescTab8[]=
3457 +{   /* Task 8 Function Descriptor Table */
3458 +    0x00000000,
3459 +    0x00000000,
3460 +    0x00000000,
3461 +    0x00000000,
3462 +    0x00000000,
3463 +    0x00000000,
3464 +    0x00000000,
3465 +    0x00000000,
3466 +    0x00000000,
3467 +    0x00000000,
3468 +    0x00000000,
3469 +    0x00000000,
3470 +    0x00000000,
3471 +    0x00000000,
3472 +    0x00000000,
3473 +    0x00000000,
3474 +    0x00000000,
3475 +    0x00000000,
3476 +    0x00000000,
3477 +    0x00000000,
3478 +    0x00000000,
3479 +    0x00000000,
3480 +    0x00000000,
3481 +    0x00000000,
3482 +    0x00000000,
3483 +    0x00000000,
3484 +    0x00000000,
3485 +    0x00000000,
3486 +    0x00000000,
3487 +    0x00000000,
3488 +    0x00000000,
3489 +    0x00000000,
3490 +    0x00000000,
3491 +    0x00000000,
3492 +    0x00000000,
3493 +    0x00000000,
3494 +    0x00000000,
3495 +    0x00000000,
3496 +    0x00000000,
3497 +    0x00000000,
3498 +    0x00000000,
3499 +    0x00000000,
3500 +    0x00000000,
3501 +    0x00000000,
3502 +    0x00000000,
3503 +    0x00000000,
3504 +    0x00000000,
3505 +    0x00000000,
3506 +    0xa0045670, /* mainFunc(), EU# 3 */
3507 +    0xa0000000, /* rsduFunc(), EU# 3 */
3508 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3509 +    0x20000000, /* setCrcAccum(), EU# 3 */
3510 +    0x21800000, /* and(), EU# 3 */
3511 +    0x21e00000, /* or(), EU# 3 */
3512 +    0x20400000, /* add(), EU# 3 */
3513 +    0x20500000, /* sub(), EU# 3 */
3514 +    0x205a0000, /* andNot(), EU# 3 */
3515 +    0x202fa000, /* andReadyBit(), EU# 3 */
3516 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3517 +    0x202ea000, /* andWrapBit(), EU# 3 */
3518 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3519 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3520 +    0x202f2000, /* andLoopBit(), EU# 3 */
3521 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3522 +};
3523 +
3524 +u32 MCD_funcDescTab9[]=
3525 +{   /* Task 9 Function Descriptor Table */
3526 +    0x00000000,
3527 +    0x00000000,
3528 +    0x00000000,
3529 +    0x00000000,
3530 +    0x00000000,
3531 +    0x00000000,
3532 +    0x00000000,
3533 +    0x00000000,
3534 +    0x00000000,
3535 +    0x00000000,
3536 +    0x00000000,
3537 +    0x00000000,
3538 +    0x00000000,
3539 +    0x00000000,
3540 +    0x00000000,
3541 +    0x00000000,
3542 +    0x00000000,
3543 +    0x00000000,
3544 +    0x00000000,
3545 +    0x00000000,
3546 +    0x00000000,
3547 +    0x00000000,
3548 +    0x00000000,
3549 +    0x00000000,
3550 +    0x00000000,
3551 +    0x00000000,
3552 +    0x00000000,
3553 +    0x00000000,
3554 +    0x00000000,
3555 +    0x00000000,
3556 +    0x00000000,
3557 +    0x00000000,
3558 +    0x00000000,
3559 +    0x00000000,
3560 +    0x00000000,
3561 +    0x00000000,
3562 +    0x00000000,
3563 +    0x00000000,
3564 +    0x00000000,
3565 +    0x00000000,
3566 +    0x00000000,
3567 +    0x00000000,
3568 +    0x00000000,
3569 +    0x00000000,
3570 +    0x00000000,
3571 +    0x00000000,
3572 +    0x00000000,
3573 +    0x00000000,
3574 +    0xa0045670, /* mainFunc(), EU# 3 */
3575 +    0xa0000000, /* rsduFunc(), EU# 3 */
3576 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3577 +    0x20000000, /* setCrcAccum(), EU# 3 */
3578 +    0x21800000, /* and(), EU# 3 */
3579 +    0x21e00000, /* or(), EU# 3 */
3580 +    0x20400000, /* add(), EU# 3 */
3581 +    0x20500000, /* sub(), EU# 3 */
3582 +    0x205a0000, /* andNot(), EU# 3 */
3583 +    0x202fa000, /* andReadyBit(), EU# 3 */
3584 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3585 +    0x202ea000, /* andWrapBit(), EU# 3 */
3586 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3587 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3588 +    0x202f2000, /* andLoopBit(), EU# 3 */
3589 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3590 +};
3591 +
3592 +u32 MCD_funcDescTab10[]=
3593 +{   /* Task 10 Function Descriptor Table */
3594 +    0x00000000,
3595 +    0x00000000,
3596 +    0x00000000,
3597 +    0x00000000,
3598 +    0x00000000,
3599 +    0x00000000,
3600 +    0x00000000,
3601 +    0x00000000,
3602 +    0x00000000,
3603 +    0x00000000,
3604 +    0x00000000,
3605 +    0x00000000,
3606 +    0x00000000,
3607 +    0x00000000,
3608 +    0x00000000,
3609 +    0x00000000,
3610 +    0x00000000,
3611 +    0x00000000,
3612 +    0x00000000,
3613 +    0x00000000,
3614 +    0x00000000,
3615 +    0x00000000,
3616 +    0x00000000,
3617 +    0x00000000,
3618 +    0x00000000,
3619 +    0x00000000,
3620 +    0x00000000,
3621 +    0x00000000,
3622 +    0x00000000,
3623 +    0x00000000,
3624 +    0x00000000,
3625 +    0x00000000,
3626 +    0x00000000,
3627 +    0x00000000,
3628 +    0x00000000,
3629 +    0x00000000,
3630 +    0x00000000,
3631 +    0x00000000,
3632 +    0x00000000,
3633 +    0x00000000,
3634 +    0x00000000,
3635 +    0x00000000,
3636 +    0x00000000,
3637 +    0x00000000,
3638 +    0x00000000,
3639 +    0x00000000,
3640 +    0x00000000,
3641 +    0x00000000,
3642 +    0xa0045670, /* mainFunc(), EU# 3 */
3643 +    0xa0000000, /* rsduFunc(), EU# 3 */
3644 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3645 +    0x20000000, /* setCrcAccum(), EU# 3 */
3646 +    0x21800000, /* and(), EU# 3 */
3647 +    0x21e00000, /* or(), EU# 3 */
3648 +    0x20400000, /* add(), EU# 3 */
3649 +    0x20500000, /* sub(), EU# 3 */
3650 +    0x205a0000, /* andNot(), EU# 3 */
3651 +    0x202fa000, /* andReadyBit(), EU# 3 */
3652 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3653 +    0x202ea000, /* andWrapBit(), EU# 3 */
3654 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3655 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3656 +    0x202f2000, /* andLoopBit(), EU# 3 */
3657 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3658 +};
3659 +
3660 +u32 MCD_funcDescTab11[]=
3661 +{   /* Task 11 Function Descriptor Table */
3662 +    0x00000000,
3663 +    0x00000000,
3664 +    0x00000000,
3665 +    0x00000000,
3666 +    0x00000000,
3667 +    0x00000000,
3668 +    0x00000000,
3669 +    0x00000000,
3670 +    0x00000000,
3671 +    0x00000000,
3672 +    0x00000000,
3673 +    0x00000000,
3674 +    0x00000000,
3675 +    0x00000000,
3676 +    0x00000000,
3677 +    0x00000000,
3678 +    0x00000000,
3679 +    0x00000000,
3680 +    0x00000000,
3681 +    0x00000000,
3682 +    0x00000000,
3683 +    0x00000000,
3684 +    0x00000000,
3685 +    0x00000000,
3686 +    0x00000000,
3687 +    0x00000000,
3688 +    0x00000000,
3689 +    0x00000000,
3690 +    0x00000000,
3691 +    0x00000000,
3692 +    0x00000000,
3693 +    0x00000000,
3694 +    0x00000000,
3695 +    0x00000000,
3696 +    0x00000000,
3697 +    0x00000000,
3698 +    0x00000000,
3699 +    0x00000000,
3700 +    0x00000000,
3701 +    0x00000000,
3702 +    0x00000000,
3703 +    0x00000000,
3704 +    0x00000000,
3705 +    0x00000000,
3706 +    0x00000000,
3707 +    0x00000000,
3708 +    0x00000000,
3709 +    0x00000000,
3710 +    0xa0045670, /* mainFunc(), EU# 3 */
3711 +    0xa0000000, /* rsduFunc(), EU# 3 */
3712 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3713 +    0x20000000, /* setCrcAccum(), EU# 3 */
3714 +    0x21800000, /* and(), EU# 3 */
3715 +    0x21e00000, /* or(), EU# 3 */
3716 +    0x20400000, /* add(), EU# 3 */
3717 +    0x20500000, /* sub(), EU# 3 */
3718 +    0x205a0000, /* andNot(), EU# 3 */
3719 +    0x202fa000, /* andReadyBit(), EU# 3 */
3720 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3721 +    0x202ea000, /* andWrapBit(), EU# 3 */
3722 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3723 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3724 +    0x202f2000, /* andLoopBit(), EU# 3 */
3725 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3726 +};
3727 +
3728 +u32 MCD_funcDescTab12[]=
3729 +{   /* Task 12 Function Descriptor Table */
3730 +    0x00000000,
3731 +    0x00000000,
3732 +    0x00000000,
3733 +    0x00000000,
3734 +    0x00000000,
3735 +    0x00000000,
3736 +    0x00000000,
3737 +    0x00000000,
3738 +    0x00000000,
3739 +    0x00000000,
3740 +    0x00000000,
3741 +    0x00000000,
3742 +    0x00000000,
3743 +    0x00000000,
3744 +    0x00000000,
3745 +    0x00000000,
3746 +    0x00000000,
3747 +    0x00000000,
3748 +    0x00000000,
3749 +    0x00000000,
3750 +    0x00000000,
3751 +    0x00000000,
3752 +    0x00000000,
3753 +    0x00000000,
3754 +    0x00000000,
3755 +    0x00000000,
3756 +    0x00000000,
3757 +    0x00000000,
3758 +    0x00000000,
3759 +    0x00000000,
3760 +    0x00000000,
3761 +    0x00000000,
3762 +    0x00000000,
3763 +    0x00000000,
3764 +    0x00000000,
3765 +    0x00000000,
3766 +    0x00000000,
3767 +    0x00000000,
3768 +    0x00000000,
3769 +    0x00000000,
3770 +    0x00000000,
3771 +    0x00000000,
3772 +    0x00000000,
3773 +    0x00000000,
3774 +    0x00000000,
3775 +    0x00000000,
3776 +    0x00000000,
3777 +    0x00000000,
3778 +    0xa0045670, /* mainFunc(), EU# 3 */
3779 +    0xa0000000, /* rsduFunc(), EU# 3 */
3780 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3781 +    0x20000000, /* setCrcAccum(), EU# 3 */
3782 +    0x21800000, /* and(), EU# 3 */
3783 +    0x21e00000, /* or(), EU# 3 */
3784 +    0x20400000, /* add(), EU# 3 */
3785 +    0x20500000, /* sub(), EU# 3 */
3786 +    0x205a0000, /* andNot(), EU# 3 */
3787 +    0x202fa000, /* andReadyBit(), EU# 3 */
3788 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3789 +    0x202ea000, /* andWrapBit(), EU# 3 */
3790 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3791 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3792 +    0x202f2000, /* andLoopBit(), EU# 3 */
3793 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3794 +};
3795 +
3796 +u32 MCD_funcDescTab13[]=
3797 +{   /* Task 13 Function Descriptor Table */
3798 +    0x00000000,
3799 +    0x00000000,
3800 +    0x00000000,
3801 +    0x00000000,
3802 +    0x00000000,
3803 +    0x00000000,
3804 +    0x00000000,
3805 +    0x00000000,
3806 +    0x00000000,
3807 +    0x00000000,
3808 +    0x00000000,
3809 +    0x00000000,
3810 +    0x00000000,
3811 +    0x00000000,
3812 +    0x00000000,
3813 +    0x00000000,
3814 +    0x00000000,
3815 +    0x00000000,
3816 +    0x00000000,
3817 +    0x00000000,
3818 +    0x00000000,
3819 +    0x00000000,
3820 +    0x00000000,
3821 +    0x00000000,
3822 +    0x00000000,
3823 +    0x00000000,
3824 +    0x00000000,
3825 +    0x00000000,
3826 +    0x00000000,
3827 +    0x00000000,
3828 +    0x00000000,
3829 +    0x00000000,
3830 +    0x00000000,
3831 +    0x00000000,
3832 +    0x00000000,
3833 +    0x00000000,
3834 +    0x00000000,
3835 +    0x00000000,
3836 +    0x00000000,
3837 +    0x00000000,
3838 +    0x00000000,
3839 +    0x00000000,
3840 +    0x00000000,
3841 +    0x00000000,
3842 +    0x00000000,
3843 +    0x00000000,
3844 +    0x00000000,
3845 +    0x00000000,
3846 +    0xa0045670, /* mainFunc(), EU# 3 */
3847 +    0xa0000000, /* rsduFunc(), EU# 3 */
3848 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3849 +    0x20000000, /* setCrcAccum(), EU# 3 */
3850 +    0x21800000, /* and(), EU# 3 */
3851 +    0x21e00000, /* or(), EU# 3 */
3852 +    0x20400000, /* add(), EU# 3 */
3853 +    0x20500000, /* sub(), EU# 3 */
3854 +    0x205a0000, /* andNot(), EU# 3 */
3855 +    0x202fa000, /* andReadyBit(), EU# 3 */
3856 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3857 +    0x202ea000, /* andWrapBit(), EU# 3 */
3858 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3859 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3860 +    0x202f2000, /* andLoopBit(), EU# 3 */
3861 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3862 +};
3863 +
3864 +u32 MCD_funcDescTab14[]=
3865 +{   /* Task 14 Function Descriptor Table */
3866 +    0x00000000,
3867 +    0x00000000,
3868 +    0x00000000,
3869 +    0x00000000,
3870 +    0x00000000,
3871 +    0x00000000,
3872 +    0x00000000,
3873 +    0x00000000,
3874 +    0x00000000,
3875 +    0x00000000,
3876 +    0x00000000,
3877 +    0x00000000,
3878 +    0x00000000,
3879 +    0x00000000,
3880 +    0x00000000,
3881 +    0x00000000,
3882 +    0x00000000,
3883 +    0x00000000,
3884 +    0x00000000,
3885 +    0x00000000,
3886 +    0x00000000,
3887 +    0x00000000,
3888 +    0x00000000,
3889 +    0x00000000,
3890 +    0x00000000,
3891 +    0x00000000,
3892 +    0x00000000,
3893 +    0x00000000,
3894 +    0x00000000,
3895 +    0x00000000,
3896 +    0x00000000,
3897 +    0x00000000,
3898 +    0x00000000,
3899 +    0x00000000,
3900 +    0x00000000,
3901 +    0x00000000,
3902 +    0x00000000,
3903 +    0x00000000,
3904 +    0x00000000,
3905 +    0x00000000,
3906 +    0x00000000,
3907 +    0x00000000,
3908 +    0x00000000,
3909 +    0x00000000,
3910 +    0x00000000,
3911 +    0x00000000,
3912 +    0x00000000,
3913 +    0x00000000,
3914 +    0xa0045670, /* mainFunc(), EU# 3 */
3915 +    0xa0000000, /* rsduFunc(), EU# 3 */
3916 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3917 +    0x20000000, /* setCrcAccum(), EU# 3 */
3918 +    0x21800000, /* and(), EU# 3 */
3919 +    0x21e00000, /* or(), EU# 3 */
3920 +    0x20400000, /* add(), EU# 3 */
3921 +    0x20500000, /* sub(), EU# 3 */
3922 +    0x205a0000, /* andNot(), EU# 3 */
3923 +    0x202fa000, /* andReadyBit(), EU# 3 */
3924 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3925 +    0x202ea000, /* andWrapBit(), EU# 3 */
3926 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3927 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3928 +    0x202f2000, /* andLoopBit(), EU# 3 */
3929 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3930 +};
3931 +
3932 +u32 MCD_funcDescTab15[]=
3933 +{   /* Task 15 Function Descriptor Table */
3934 +    0x00000000,
3935 +    0x00000000,
3936 +    0x00000000,
3937 +    0x00000000,
3938 +    0x00000000,
3939 +    0x00000000,
3940 +    0x00000000,
3941 +    0x00000000,
3942 +    0x00000000,
3943 +    0x00000000,
3944 +    0x00000000,
3945 +    0x00000000,
3946 +    0x00000000,
3947 +    0x00000000,
3948 +    0x00000000,
3949 +    0x00000000,
3950 +    0x00000000,
3951 +    0x00000000,
3952 +    0x00000000,
3953 +    0x00000000,
3954 +    0x00000000,
3955 +    0x00000000,
3956 +    0x00000000,
3957 +    0x00000000,
3958 +    0x00000000,
3959 +    0x00000000,
3960 +    0x00000000,
3961 +    0x00000000,
3962 +    0x00000000,
3963 +    0x00000000,
3964 +    0x00000000,
3965 +    0x00000000,
3966 +    0x00000000,
3967 +    0x00000000,
3968 +    0x00000000,
3969 +    0x00000000,
3970 +    0x00000000,
3971 +    0x00000000,
3972 +    0x00000000,
3973 +    0x00000000,
3974 +    0x00000000,
3975 +    0x00000000,
3976 +    0x00000000,
3977 +    0x00000000,
3978 +    0x00000000,
3979 +    0x00000000,
3980 +    0x00000000,
3981 +    0x00000000,
3982 +    0xa0045670, /* mainFunc(), EU# 3 */
3983 +    0xa0000000, /* rsduFunc(), EU# 3 */
3984 +    0xa0000000, /* crcAccumVal(), EU# 3 */
3985 +    0x20000000, /* setCrcAccum(), EU# 3 */
3986 +    0x21800000, /* and(), EU# 3 */
3987 +    0x21e00000, /* or(), EU# 3 */
3988 +    0x20400000, /* add(), EU# 3 */
3989 +    0x20500000, /* sub(), EU# 3 */
3990 +    0x205a0000, /* andNot(), EU# 3 */
3991 +    0x202fa000, /* andReadyBit(), EU# 3 */
3992 +    0x202f9000, /* andNotReadyBit(), EU# 3 */
3993 +    0x202ea000, /* andWrapBit(), EU# 3 */
3994 +    0x202da000, /* andEndFrameBit(), EU# 3 */
3995 +    0x202e2000, /* andInterruptBit(), EU# 3 */
3996 +    0x202f2000, /* andLoopBit(), EU# 3 */
3997 +    0x2020a000, /* andCrcRestartBit(), EU# 3 */
3998 +};
3999 +#endif /*MCD_INCLUDE_EU*/
4000 +
4001 +u32 MCD_contextSave0[128];  /* Task 0 context save space */
4002 +u32 MCD_contextSave1[128];  /* Task 1 context save space */
4003 +u32 MCD_contextSave2[128];  /* Task 2 context save space */
4004 +u32 MCD_contextSave3[128];  /* Task 3 context save space */
4005 +u32 MCD_contextSave4[128];  /* Task 4 context save space */
4006 +u32 MCD_contextSave5[128];  /* Task 5 context save space */
4007 +u32 MCD_contextSave6[128];  /* Task 6 context save space */
4008 +u32 MCD_contextSave7[128];  /* Task 7 context save space */
4009 +u32 MCD_contextSave8[128];  /* Task 8 context save space */
4010 +u32 MCD_contextSave9[128];  /* Task 9 context save space */
4011 +u32 MCD_contextSave10[128]; /* Task 10 context save space */
4012 +u32 MCD_contextSave11[128]; /* Task 11 context save space */
4013 +u32 MCD_contextSave12[128]; /* Task 12 context save space */
4014 +u32 MCD_contextSave13[128]; /* Task 13 context save space */
4015 +u32 MCD_contextSave14[128]; /* Task 14 context save space */
4016 +u32 MCD_contextSave15[128]; /* Task 15 context save space */
4017 +
4018 +/* Task Descriptor Tables - the guts */
4019 +u32 MCD_ChainNoEu_TDT[];
4020 +u32 MCD_SingleNoEu_TDT[];
4021 +#ifdef MCD_INCLUDE_EU
4022 +u32 MCD_ChainEu_TDT[];
4023 +u32 MCD_SingleEu_TDT[];
4024 +#endif
4025 +u32 MCD_ENetRcv_TDT[];
4026 +u32 MCD_ENetXmit_TDT[];
4027 +
4028 +u32 MCD_modelTaskTableSrc[]=
4029 +{
4030 +    (u32)MCD_ChainNoEu_TDT,
4031 +    (u32)&((u8*)MCD_ChainNoEu_TDT)[0x00000178],
4032 +    0x00000000,
4033 +    0x00000000,
4034 +    0x00000000,
4035 +    0x00000000,
4036 +    0x00000000,
4037 +    0x00000000,
4038 +    (u32)MCD_SingleNoEu_TDT,
4039 +    (u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4],
4040 +    0x00000000,
4041 +    0x00000000,
4042 +    0x00000000,
4043 +    0x00000000,
4044 +    0x00000000,
4045 +    0x00000000,
4046 +#ifdef MCD_INCLUDE_EU
4047 +    (u32)MCD_ChainEu_TDT,
4048 +    (u32)&((u8*)MCD_ChainEu_TDT)[0x00000180],
4049 +    0x00000000,
4050 +    0x00000000,
4051 +    0x00000000,
4052 +    0x00000000,
4053 +    0x00000000,
4054 +    0x00000000,
4055 +    (u32)MCD_SingleEu_TDT,
4056 +    (u32)&((u8*)MCD_SingleEu_TDT)[0x000000dc],
4057 +    0x00000000,
4058 +    0x00000000,
4059 +    0x00000000,
4060 +    0x00000000,
4061 +    0x00000000,
4062 +    0x00000000,
4063 +#endif
4064 +    (u32)MCD_ENetRcv_TDT,
4065 +    (u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009C],
4066 +    0x00000000,
4067 +    0x00000000,
4068 +    0x00000000,
4069 +    0x00000000,
4070 +    0x00000000,
4071 +    0x00000000,
4072 +    (u32)MCD_ENetXmit_TDT,
4073 +    (u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0],
4074 +    0x00000000,
4075 +    0x00000000,
4076 +    0x00000000,
4077 +    0x00000000,
4078 +    0x00000000,
4079 +    0x00000000,
4080 +};
4081 +
4082 +u32 MCD_ChainNoEu_TDT[]=
4083 +{
4084 +    0x80004000, /* 0000(:370):  LCDEXT: idx0 = 0x00000000; ; */
4085 +    0x8118801b, /* 0004(:370):  LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
4086 +    0xb8ca0018, /* 0008(:371):    LCD: idx2 = *(idx1 + var20); idx2 once var0; idx2 += inc3 */
4087 +    0x10004b10, /* 000C(:372):      DRD1A: var18 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4088 +    0x7000000c, /* 0010(:373):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4089 +    0x024cf89f, /* 0014(:373):      DRD2B1: var9 = EU3(); EU3(idx2)  */
4090 +    0x60000009, /* 0018(:374):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT init=0 WS=0 RS=0 */
4091 +    0x080cf89f, /* 001C(:374):      DRD2B1: idx0 = EU3(); EU3(idx2)  */
4092 +    0x000001f8, /* 0020(:0):    NOP */
4093 +    0x98180524, /* 0024(:378):  LCD: idx0 = idx0; idx0 != var20; idx0 += inc4 */
4094 +    0x8118801b, /* 0028(:380):    LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
4095 +    0xf8ca001a, /* 002C(:381):      LCDEXT: idx2 = *(idx1 + var20 + 8); idx2 once var0; idx2 += inc3 */
4096 +    0xb8ca601b, /* 0030(:382):      LCD: idx3 = *(idx1 + var20 + 12); ; idx3 += inc3 */
4097 +    0x10004310, /* 0034(:384):        DRD1A: var16 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4098 +    0x00001718, /* 0038(:385):        DRD1A: var5 = idx3; FN=0 init=0 WS=0 RS=0 */
4099 +    0xb8ca001d, /* 003C(:387):      LCD: idx2 = *(idx1 + var20 + 20); idx2 once var0; idx2 += inc3 */
4100 +    0x10001f10, /* 0040(:388):        DRD1A: var7 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4101 +    0x60000007, /* 0044(:389):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */
4102 +    0x020cf893, /* 0048(:389):        DRD2B1: var8 = EU3(); EU3(idx2,var19)  */
4103 +    0x98ca001c, /* 004C(:391):      LCD: idx2 = idx1 + var20 + 4; idx2 once var0; idx2 += inc3 */
4104 +    0x00000710, /* 0050(:392):        DRD1A: var1 = idx2; FN=0 init=0 WS=0 RS=0 */
4105 +    0x98ca8018, /* 0054(:393):      LCD: idx2 = idx1 + var21; idx2 once var0; idx2 += inc3 */
4106 +    0x10002b10, /* 0058(:394):        DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4107 +    0x0000c828, /* 005C(:395):        DRD1A: *idx2 = var5; FN=0 init=0 WS=0 RS=0 */
4108 +    0x000001f8, /* 0060(:0):      NOP */
4109 +    0xc14ae018, /* 0064(:399):    LCDEXT: idx1 = var2 + var21; ; idx1 += inc3 */
4110 +    0xc004a51d, /* 0068(:399):    LCDEXT: idx2 = var0, idx3 = var9; idx3 == var20; idx2 += inc3, idx3 += inc5 */
4111 +    0x811a601b, /* 006C(:400):    LCD: idx4 = var2; ; idx4 += inc3 */
4112 +    0xc28a21c2, /* 0070(:403):      LCDEXT: idx5 = var5, idx6 = var20; idx6 < var7; idx5 += inc0, idx6 += inc2 */
4113 +    0x881be009, /* 0074(:403):      LCD: idx7 = var16; ; idx7 += inc1 */
4114 +    0x03fed7b8, /* 0078(:406):        DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */
4115 +    0xda9b001b, /* 007C(:408):      LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4116 +    0x9b9be01b, /* 0080(:408):      LCD: idx7 = idx7; ; idx7 += inc3 */
4117 +    0x1000cb20, /* 0084(:409):        DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
4118 +    0x70000006, /* 0088(:410):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4119 +    0x088cf896, /* 008C(:410):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4120 +    0x1000cb28, /* 0090(:411):        DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4121 +    0x70000006, /* 0094(:412):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4122 +    0x088cf896, /* 0098(:412):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4123 +    0x1000cb30, /* 009C(:413):        DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4124 +    0x70000006, /* 00A0(:414):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4125 +    0x088cf896, /* 00A4(:414):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4126 +    0x1000cb38, /* 00A8(:415):        DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
4127 +    0x0000c728, /* 00AC(:416):        DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
4128 +    0x000001f8, /* 00B0(:0):      NOP */
4129 +    0xc14ae018, /* 00B4(:420):    LCDEXT: idx1 = var2 + var21; ; idx1 += inc3 */
4130 +    0xc004a5dd, /* 00B8(:420):    LCDEXT: idx2 = var0, idx3 = var9; idx3 == var23; idx2 += inc3, idx3 += inc5 */
4131 +    0x811a601b, /* 00BC(:421):    LCD: idx4 = var2; ; idx4 += inc3 */
4132 +    0xda9b001b, /* 00C0(:424):      LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4133 +    0x9b9be01b, /* 00C4(:424):      LCD: idx7 = idx7; ; idx7 += inc3 */
4134 +    0x0000d3a0, /* 00C8(:425):        DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
4135 +    0xc28a21c2, /* 00CC(:427):      LCDEXT: idx5 = var5, idx6 = var20; idx6 < var7; idx5 += inc0, idx6 += inc2 */
4136 +    0x881be009, /* 00D0(:427):      LCD: idx7 = var16; ; idx7 += inc1 */
4137 +    0x0bfed7b8, /* 00D4(:430):        DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */
4138 +    0xda9b001b, /* 00D8(:432):      LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4139 +    0x9b9be01b, /* 00DC(:432):      LCD: idx7 = idx7; ; idx7 += inc3 */
4140 +    0x1000cb20, /* 00E0(:433):        DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
4141 +    0x70000006, /* 00E4(:434):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4142 +    0x088cf896, /* 00E8(:434):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4143 +    0x1000cb28, /* 00EC(:435):        DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4144 +    0x70000006, /* 00F0(:436):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4145 +    0x088cf896, /* 00F4(:436):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4146 +    0x1000cb30, /* 00F8(:437):        DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4147 +    0x70000006, /* 00FC(:438):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4148 +    0x088cf896, /* 0100(:438):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4149 +    0x1000cb38, /* 0104(:439):        DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
4150 +    0x0000c728, /* 0108(:440):        DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
4151 +    0x000001f8, /* 010C(:0):      NOP */
4152 +    0x8118801b, /* 0110(:444):    LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
4153 +    0x8a19001b, /* 0114(:446):      LCD: idx2 = var20; idx2 once var0; idx2 += inc3 */
4154 +    0x6000000e, /* 0118(:447):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */
4155 +    0x088cf49f, /* 011C(:447):        DRD2B1: idx2 = EU3(); EU3(var18)  */
4156 +    0xd9190536, /* 0120(:448):      LCDEXT: idx2 = idx2; idx2 == var20; idx2 += inc6 */
4157 +    0x98ca0018, /* 0124(:448):      LCD: idx3 = idx1 + var20; idx3 once var0; idx3 += inc3 */
4158 +    0x6000000a, /* 0128(:450):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
4159 +    0x0cccfcdf, /* 012C(:450):        DRD2B1: *idx3 = EU3(); EU3(*idx3)  */
4160 +    0x000001f8, /* 0130(:0):      NOP */
4161 +    0xa14a001e, /* 0134(:453):    LCD: idx1 = *(var2 + var20 + 24); idx1 once var0; idx1 += inc3 */
4162 +    0x10000b08, /* 0138(:454):      DRD1A: var2 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
4163 +    0x10002c90, /* 013C(:455):      DRD1A: var11 = var18; FN=0 MORE init=0 WS=0 RS=0 */
4164 +    0xb8ca0018, /* 0140(:456):      LCD: idx2 = *(idx1 + var20); idx2 once var0; idx2 += inc3 */
4165 +    0x10004b10, /* 0144(:457):        DRD1A: var18 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4166 +    0x70000009, /* 0148(:458):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT MORE init=0 WS=0 RS=0 */
4167 +    0x080cf89f, /* 014C(:458):        DRD2B1: idx0 = EU3(); EU3(idx2)  */
4168 +    0x6000000c, /* 0150(:459):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT init=0 WS=0 RS=0 */
4169 +    0x024cf89f, /* 0154(:459):        DRD2B1: var9 = EU3(); EU3(idx2)  */
4170 +    0x000001f8, /* 0158(:0):      NOP */
4171 +    0x8a18801b, /* 015C(:465):    LCD: idx1 = var20; idx1 once var0; idx1 += inc3 */
4172 +    0x7000000d, /* 0160(:466):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
4173 +    0x084cf2df, /* 0164(:466):      DRD2B1: idx1 = EU3(); EU3(var11)  */
4174 +    0xd899053f, /* 0168(:467):      LCDEXT: idx2 = idx1; idx2 > var20; idx2 += inc7 */
4175 +    0x8019801b, /* 016C(:467):      LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */
4176 +    0x040001f8, /* 0170(:468):        DRD1A: FN=0 INT init=0 WS=0 RS=0 */
4177 +    0x000001f8, /* 0174(:0):      NOP */
4178 +    0x000001f8, /* 0178(:0):    NOP */
4179 +};
4180 +u32 MCD_SingleNoEu_TDT[]=
4181 +{
4182 +    0x8318001b, /* 0000(:646):  LCD: idx0 = var6; idx0 once var0; idx0 += inc3 */
4183 +    0x7000000c, /* 0004(:647):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4184 +    0x080cf81f, /* 0008(:647):    DRD2B1: idx0 = EU3(); EU3(idx0)  */
4185 +    0x8318801b, /* 000C(:648):    LCD: idx1 = var6; idx1 once var0; idx1 += inc3 */
4186 +    0x6000000d, /* 0010(:649):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */
4187 +    0x084cf85f, /* 0014(:649):      DRD2B1: idx1 = EU3(); EU3(idx1)  */
4188 +    0x000001f8, /* 0018(:0):    NOP */
4189 +    0x8498001b, /* 001C(:653):  LCD: idx0 = var9; idx0 once var0; idx0 += inc3 */
4190 +    0x7000000c, /* 0020(:654):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4191 +    0x020cf81f, /* 0024(:654):    DRD2B1: var8 = EU3(); EU3(idx0)  */
4192 +    0x6000000d, /* 0028(:655):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */
4193 +    0x028cf81f, /* 002C(:655):    DRD2B1: var10 = EU3(); EU3(idx0)  */
4194 +    0xc404601b, /* 0030(:658):  LCDEXT: idx0 = var8, idx1 = var8; ; idx0 += inc3, idx1 += inc3 */
4195 +    0xc00423dc, /* 0034(:658):  LCDEXT: idx2 = var0, idx3 = var8; idx3 == var15; idx2 += inc3, idx3 += inc4 */
4196 +    0x809a601b, /* 0038(:659):  LCD: idx4 = var1; ; idx4 += inc3 */
4197 +    0xc207a182, /* 003C(:662):    LCDEXT: idx5 = var4, idx6 = var15; idx6 < var6; idx5 += inc0, idx6 += inc2 */
4198 +    0x869be009, /* 0040(:662):    LCD: idx7 = var13; ; idx7 += inc1 */
4199 +    0x03fed7b8, /* 0044(:665):      DRD1A: *idx7; FN=0 init=31 WS=3 RS=3 */
4200 +    0xda9b001b, /* 0048(:667):    LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4201 +    0x9b9be01b, /* 004C(:667):    LCD: idx7 = idx7; ; idx7 += inc3 */
4202 +    0x70000006, /* 0050(:669):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4203 +    0x088cf890, /* 0054(:669):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4204 +    0x1000cb28, /* 0058(:670):      DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4205 +    0x70000006, /* 005C(:671):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4206 +    0x088cf890, /* 0060(:671):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4207 +    0x1000cb30, /* 0064(:672):      DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4208 +    0x70000006, /* 0068(:673):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4209 +    0x088cf890, /* 006C(:673):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4210 +    0x0000cb38, /* 0070(:674):      DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
4211 +    0x000001f8, /* 0074(:0):    NOP */
4212 +    0xc404601b, /* 0078(:678):  LCDEXT: idx0 = var8, idx1 = var8; ; idx0 += inc3, idx1 += inc3 */
4213 +    0xc004245c, /* 007C(:678):  LCDEXT: idx2 = var0, idx3 = var8; idx3 == var17; idx2 += inc3, idx3 += inc4 */
4214 +    0x809a601b, /* 0080(:679):  LCD: idx4 = var1; ; idx4 += inc3 */
4215 +    0xda9b001b, /* 0084(:682):    LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4216 +    0x9b9be01b, /* 0088(:682):    LCD: idx7 = idx7; ; idx7 += inc3 */
4217 +    0x0000d3a0, /* 008C(:683):      DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
4218 +    0xc207a182, /* 0090(:685):    LCDEXT: idx5 = var4, idx6 = var15; idx6 < var6; idx5 += inc0, idx6 += inc2 */
4219 +    0x869be009, /* 0094(:685):    LCD: idx7 = var13; ; idx7 += inc1 */
4220 +    0x0bfed7b8, /* 0098(:688):      DRD1A: *idx7; FN=0 TFD init=31 WS=3 RS=3 */
4221 +    0xda9b001b, /* 009C(:690):    LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4222 +    0x9b9be01b, /* 00A0(:690):    LCD: idx7 = idx7; ; idx7 += inc3 */
4223 +    0x70000006, /* 00A4(:692):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4224 +    0x088cf890, /* 00A8(:692):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4225 +    0x1000cb28, /* 00AC(:693):      DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4226 +    0x70000006, /* 00B0(:694):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4227 +    0x088cf890, /* 00B4(:694):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4228 +    0x1000cb30, /* 00B8(:695):      DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4229 +    0x70000006, /* 00BC(:696):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4230 +    0x088cf890, /* 00C0(:696):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4231 +    0x0000cb38, /* 00C4(:697):      DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
4232 +    0x000001f8, /* 00C8(:0):    NOP */
4233 +    0xc51803ed, /* 00CC(:701):  LCDEXT: idx0 = var10; idx0 > var15; idx0 += inc5 */
4234 +    0x8018801b, /* 00D0(:701):  LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */
4235 +    0x040001f8, /* 00D4(:702):    DRD1A: FN=0 INT init=0 WS=0 RS=0 */
4236 +};
4237 +#ifdef MCD_INCLUDE_EU
4238 +u32 MCD_ChainEu_TDT[]=
4239 +{
4240 +    0x80004000, /* 0000(:928):  LCDEXT: idx0 = 0x00000000; ; */
4241 +    0x8118801b, /* 0004(:928):  LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
4242 +    0xb8ca0018, /* 0008(:929):    LCD: idx2 = *(idx1 + var20); idx2 once var0; idx2 += inc3 */
4243 +    0x10004b10, /* 000C(:930):      DRD1A: var18 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4244 +    0x7000000c, /* 0010(:931):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4245 +    0x024cf89f, /* 0014(:931):      DRD2B1: var9 = EU3(); EU3(idx2)  */
4246 +    0x60000009, /* 0018(:932):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT init=0 WS=0 RS=0 */
4247 +    0x080cf89f, /* 001C(:932):      DRD2B1: idx0 = EU3(); EU3(idx2)  */
4248 +    0x000001f8, /* 0020(:0):    NOP */
4249 +    0x98180524, /* 0024(:936):  LCD: idx0 = idx0; idx0 != var20; idx0 += inc4 */
4250 +    0x8118801b, /* 0028(:938):    LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
4251 +    0xf8ca001a, /* 002C(:939):      LCDEXT: idx2 = *(idx1 + var20 + 8); idx2 once var0; idx2 += inc3 */
4252 +    0xb8ca601b, /* 0030(:940):      LCD: idx3 = *(idx1 + var20 + 12); ; idx3 += inc3 */
4253 +    0x10004310, /* 0034(:942):        DRD1A: var16 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4254 +    0x00001718, /* 0038(:943):        DRD1A: var5 = idx3; FN=0 init=0 WS=0 RS=0 */
4255 +    0xb8ca001d, /* 003C(:945):      LCD: idx2 = *(idx1 + var20 + 20); idx2 once var0; idx2 += inc3 */
4256 +    0x10001f10, /* 0040(:946):        DRD1A: var7 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4257 +    0x60000007, /* 0044(:947):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=7 EXT init=0 WS=0 RS=0 */
4258 +    0x020cf893, /* 0048(:947):        DRD2B1: var8 = EU3(); EU3(idx2,var19)  */
4259 +    0x98ca001c, /* 004C(:949):      LCD: idx2 = idx1 + var20 + 4; idx2 once var0; idx2 += inc3 */
4260 +    0x00000710, /* 0050(:950):        DRD1A: var1 = idx2; FN=0 init=0 WS=0 RS=0 */
4261 +    0x98ca8018, /* 0054(:951):      LCD: idx2 = idx1 + var21; idx2 once var0; idx2 += inc3 */
4262 +    0x10002b10, /* 0058(:952):        DRD1A: var10 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4263 +    0x0000c828, /* 005C(:953):        DRD1A: *idx2 = var5; FN=0 init=0 WS=0 RS=0 */
4264 +    0x000001f8, /* 0060(:0):      NOP */
4265 +    0xc14ae018, /* 0064(:957):    LCDEXT: idx1 = var2 + var21; ; idx1 += inc3 */
4266 +    0xc004a51d, /* 0068(:957):    LCDEXT: idx2 = var0, idx3 = var9; idx3 == var20; idx2 += inc3, idx3 += inc5 */
4267 +    0x811a601b, /* 006C(:958):    LCD: idx4 = var2; ; idx4 += inc3 */
4268 +    0xc28a21c2, /* 0070(:961):      LCDEXT: idx5 = var5, idx6 = var20; idx6 < var7; idx5 += inc0, idx6 += inc2 */
4269 +    0x881be009, /* 0074(:961):      LCD: idx7 = var16; ; idx7 += inc1 */
4270 +    0x63fe0000, /* 0078(:964):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */
4271 +    0x0d4cfddf, /* 007C(:964):        DRD2B1: *idx5 = EU3(); EU3(*idx7)  */
4272 +    0xda9b001b, /* 0080(:966):      LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4273 +    0x9b9be01b, /* 0084(:966):      LCD: idx7 = idx7; ; idx7 += inc3 */
4274 +    0x1000cb20, /* 0088(:967):        DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
4275 +    0x70000006, /* 008C(:968):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4276 +    0x088cf896, /* 0090(:968):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4277 +    0x1000cb28, /* 0094(:969):        DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4278 +    0x70000006, /* 0098(:970):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4279 +    0x088cf896, /* 009C(:970):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4280 +    0x1000cb30, /* 00A0(:971):        DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4281 +    0x70000006, /* 00A4(:972):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4282 +    0x088cf896, /* 00A8(:972):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4283 +    0x1000cb38, /* 00AC(:973):        DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
4284 +    0x0000c728, /* 00B0(:974):        DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
4285 +    0x000001f8, /* 00B4(:0):      NOP */
4286 +    0xc14ae018, /* 00B8(:978):    LCDEXT: idx1 = var2 + var21; ; idx1 += inc3 */
4287 +    0xc004a5dd, /* 00BC(:978):    LCDEXT: idx2 = var0, idx3 = var9; idx3 == var23; idx2 += inc3, idx3 += inc5 */
4288 +    0x811a601b, /* 00C0(:979):    LCD: idx4 = var2; ; idx4 += inc3 */
4289 +    0xda9b001b, /* 00C4(:982):      LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4290 +    0x9b9be01b, /* 00C8(:982):      LCD: idx7 = idx7; ; idx7 += inc3 */
4291 +    0x0000d3a0, /* 00CC(:983):        DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
4292 +    0xc28a21c2, /* 00D0(:985):      LCDEXT: idx5 = var5, idx6 = var20; idx6 < var7; idx5 += inc0, idx6 += inc2 */
4293 +    0x881be009, /* 00D4(:985):      LCD: idx7 = var16; ; idx7 += inc1 */
4294 +    0x6bfe0000, /* 00D8(:988):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */
4295 +    0x0d4cfddf, /* 00DC(:988):        DRD2B1: *idx5 = EU3(); EU3(*idx7)  */
4296 +    0xda9b001b, /* 00E0(:990):      LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4297 +    0x9b9be01b, /* 00E4(:990):      LCD: idx7 = idx7; ; idx7 += inc3 */
4298 +    0x1000cb20, /* 00E8(:991):        DRD1A: *idx2 = idx4; FN=0 MORE init=0 WS=0 RS=0 */
4299 +    0x70000006, /* 00EC(:992):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4300 +    0x088cf896, /* 00F0(:992):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4301 +    0x1000cb28, /* 00F4(:993):        DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4302 +    0x70000006, /* 00F8(:994):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4303 +    0x088cf896, /* 00FC(:994):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4304 +    0x1000cb30, /* 0100(:995):        DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4305 +    0x70000006, /* 0104(:996):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4306 +    0x088cf896, /* 0108(:996):        DRD2B1: idx2 = EU3(); EU3(idx2,var22)  */
4307 +    0x1000cb38, /* 010C(:997):        DRD1A: *idx2 = idx7; FN=0 MORE init=0 WS=0 RS=0 */
4308 +    0x0000c728, /* 0110(:998):        DRD1A: *idx1 = idx5; FN=0 init=0 WS=0 RS=0 */
4309 +    0x000001f8, /* 0114(:0):      NOP */
4310 +    0x8118801b, /* 0118(:1002):    LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
4311 +    0x8a19001b, /* 011C(:1004):      LCD: idx2 = var20; idx2 once var0; idx2 += inc3 */
4312 +    0x6000000e, /* 0120(:1005):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=14 EXT init=0 WS=0 RS=0 */
4313 +    0x088cf49f, /* 0124(:1005):        DRD2B1: idx2 = EU3(); EU3(var18)  */
4314 +    0xd9190536, /* 0128(:1006):      LCDEXT: idx2 = idx2; idx2 == var20; idx2 += inc6 */
4315 +    0x98ca0018, /* 012C(:1006):      LCD: idx3 = idx1 + var20; idx3 once var0; idx3 += inc3 */
4316 +    0x6000000a, /* 0130(:1008):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
4317 +    0x0cccfcdf, /* 0134(:1008):        DRD2B1: *idx3 = EU3(); EU3(*idx3)  */
4318 +    0x000001f8, /* 0138(:0):      NOP */
4319 +    0xa14a001e, /* 013C(:1011):    LCD: idx1 = *(var2 + var20 + 24); idx1 once var0; idx1 += inc3 */
4320 +    0x10000b08, /* 0140(:1012):      DRD1A: var2 = idx1; FN=0 MORE init=0 WS=0 RS=0 */
4321 +    0x10002c90, /* 0144(:1013):      DRD1A: var11 = var18; FN=0 MORE init=0 WS=0 RS=0 */
4322 +    0xb8ca0018, /* 0148(:1014):      LCD: idx2 = *(idx1 + var20); idx2 once var0; idx2 += inc3 */
4323 +    0x10004b10, /* 014C(:1015):        DRD1A: var18 = idx2; FN=0 MORE init=0 WS=0 RS=0 */
4324 +    0x70000009, /* 0150(:1016):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT MORE init=0 WS=0 RS=0 */
4325 +    0x080cf89f, /* 0154(:1016):        DRD2B1: idx0 = EU3(); EU3(idx2)  */
4326 +    0x6000000c, /* 0158(:1017):        DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT init=0 WS=0 RS=0 */
4327 +    0x024cf89f, /* 015C(:1017):        DRD2B1: var9 = EU3(); EU3(idx2)  */
4328 +    0x000001f8, /* 0160(:0):      NOP */
4329 +    0x8a18801b, /* 0164(:1023):    LCD: idx1 = var20; idx1 once var0; idx1 += inc3 */
4330 +    0x7000000d, /* 0168(:1024):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
4331 +    0x084cf2df, /* 016C(:1024):      DRD2B1: idx1 = EU3(); EU3(var11)  */
4332 +    0xd899053f, /* 0170(:1025):      LCDEXT: idx2 = idx1; idx2 > var20; idx2 += inc7 */
4333 +    0x8019801b, /* 0174(:1025):      LCD: idx3 = var0; idx3 once var0; idx3 += inc3 */
4334 +    0x040001f8, /* 0178(:1026):        DRD1A: FN=0 INT init=0 WS=0 RS=0 */
4335 +    0x000001f8, /* 017C(:0):      NOP */
4336 +    0x000001f8, /* 0180(:0):    NOP */
4337 +};
4338 +u32 MCD_SingleEu_TDT[]=
4339 +{
4340 +    0x8318001b, /* 0000(:1204):  LCD: idx0 = var6; idx0 once var0; idx0 += inc3 */
4341 +    0x7000000c, /* 0004(:1205):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4342 +    0x080cf81f, /* 0008(:1205):    DRD2B1: idx0 = EU3(); EU3(idx0)  */
4343 +    0x8318801b, /* 000C(:1206):    LCD: idx1 = var6; idx1 once var0; idx1 += inc3 */
4344 +    0x6000000d, /* 0010(:1207):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */
4345 +    0x084cf85f, /* 0014(:1207):      DRD2B1: idx1 = EU3(); EU3(idx1)  */
4346 +    0x000001f8, /* 0018(:0):    NOP */
4347 +    0x8498001b, /* 001C(:1211):  LCD: idx0 = var9; idx0 once var0; idx0 += inc3 */
4348 +    0x7000000c, /* 0020(:1212):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4349 +    0x020cf81f, /* 0024(:1212):    DRD2B1: var8 = EU3(); EU3(idx0)  */
4350 +    0x6000000d, /* 0028(:1213):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT init=0 WS=0 RS=0 */
4351 +    0x028cf81f, /* 002C(:1213):    DRD2B1: var10 = EU3(); EU3(idx0)  */
4352 +    0xc404601b, /* 0030(:1216):  LCDEXT: idx0 = var8, idx1 = var8; ; idx0 += inc3, idx1 += inc3 */
4353 +    0xc00423dc, /* 0034(:1216):  LCDEXT: idx2 = var0, idx3 = var8; idx3 == var15; idx2 += inc3, idx3 += inc4 */
4354 +    0x809a601b, /* 0038(:1217):  LCD: idx4 = var1; ; idx4 += inc3 */
4355 +    0xc207a182, /* 003C(:1220):    LCDEXT: idx5 = var4, idx6 = var15; idx6 < var6; idx5 += inc0, idx6 += inc2 */
4356 +    0x869be009, /* 0040(:1220):    LCD: idx7 = var13; ; idx7 += inc1 */
4357 +    0x63fe0000, /* 0044(:1223):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 EXT init=31 WS=3 RS=3 */
4358 +    0x0d4cfddf, /* 0048(:1223):      DRD2B1: *idx5 = EU3(); EU3(*idx7)  */
4359 +    0xda9b001b, /* 004C(:1225):    LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4360 +    0x9b9be01b, /* 0050(:1225):    LCD: idx7 = idx7; ; idx7 += inc3 */
4361 +    0x70000006, /* 0054(:1227):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4362 +    0x088cf890, /* 0058(:1227):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4363 +    0x1000cb28, /* 005C(:1228):      DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4364 +    0x70000006, /* 0060(:1229):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4365 +    0x088cf890, /* 0064(:1229):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4366 +    0x1000cb30, /* 0068(:1230):      DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4367 +    0x70000006, /* 006C(:1231):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4368 +    0x088cf890, /* 0070(:1231):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4369 +    0x0000cb38, /* 0074(:1232):      DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
4370 +    0x000001f8, /* 0078(:0):    NOP */
4371 +    0xc404601b, /* 007C(:1236):  LCDEXT: idx0 = var8, idx1 = var8; ; idx0 += inc3, idx1 += inc3 */
4372 +    0xc004245c, /* 0080(:1236):  LCDEXT: idx2 = var0, idx3 = var8; idx3 == var17; idx2 += inc3, idx3 += inc4 */
4373 +    0x809a601b, /* 0084(:1237):  LCD: idx4 = var1; ; idx4 += inc3 */
4374 +    0xda9b001b, /* 0088(:1240):    LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4375 +    0x9b9be01b, /* 008C(:1240):    LCD: idx7 = idx7; ; idx7 += inc3 */
4376 +    0x0000d3a0, /* 0090(:1241):      DRD1A: *idx4; FN=0 init=0 WS=0 RS=0 */
4377 +    0xc207a182, /* 0094(:1243):    LCDEXT: idx5 = var4, idx6 = var15; idx6 < var6; idx5 += inc0, idx6 += inc2 */
4378 +    0x869be009, /* 0098(:1243):    LCD: idx7 = var13; ; idx7 += inc1 */
4379 +    0x6bfe0000, /* 009C(:1246):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=0 TFD EXT init=31 WS=3 RS=3 */
4380 +    0x0d4cfddf, /* 00A0(:1246):      DRD2B1: *idx5 = EU3(); EU3(*idx7)  */
4381 +    0xda9b001b, /* 00A4(:1248):    LCDEXT: idx5 = idx5, idx6 = idx6; idx5 once var0; idx5 += inc3, idx6 += inc3 */
4382 +    0x9b9be01b, /* 00A8(:1248):    LCD: idx7 = idx7; ; idx7 += inc3 */
4383 +    0x70000006, /* 00AC(:1250):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4384 +    0x088cf890, /* 00B0(:1250):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4385 +    0x1000cb28, /* 00B4(:1251):      DRD1A: *idx2 = idx5; FN=0 MORE init=0 WS=0 RS=0 */
4386 +    0x70000006, /* 00B8(:1252):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4387 +    0x088cf890, /* 00BC(:1252):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4388 +    0x1000cb30, /* 00C0(:1253):      DRD1A: *idx2 = idx6; FN=0 MORE init=0 WS=0 RS=0 */
4389 +    0x70000006, /* 00C4(:1254):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=6 EXT MORE init=0 WS=0 RS=0 */
4390 +    0x088cf890, /* 00C8(:1254):      DRD2B1: idx2 = EU3(); EU3(idx2,var16)  */
4391 +    0x0000cb38, /* 00CC(:1255):      DRD1A: *idx2 = idx7; FN=0 init=0 WS=0 RS=0 */
4392 +    0x000001f8, /* 00D0(:0):    NOP */
4393 +    0xc51803ed, /* 00D4(:1259):  LCDEXT: idx0 = var10; idx0 > var15; idx0 += inc5 */
4394 +    0x8018801b, /* 00D8(:1259):  LCD: idx1 = var0; idx1 once var0; idx1 += inc3 */
4395 +    0x040001f8, /* 00DC(:1260):    DRD1A: FN=0 INT init=0 WS=0 RS=0 */
4396 +};
4397 +#endif
4398 +u32 MCD_ENetRcv_TDT[]=
4399 +{
4400 +    0x80004000, /* 0000(:1334):  LCDEXT: idx0 = 0x00000000; ; */
4401 +    0x82188000, /* 0004(:1334):  LCD: idx1 = var4; idx1 once var0; idx1 += inc0 */
4402 +    0x10000788, /* 0008(:1335):    DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
4403 +    0x60000009, /* 000C(:1336):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT init=0 WS=0 RS=0 */
4404 +    0x080cf05f, /* 0010(:1336):    DRD2B1: idx0 = EU3(); EU3(var1)  */
4405 +    0x98180249, /* 0014(:1339):  LCD: idx0 = idx0; idx0 != var9; idx0 += inc1 */
4406 +    0x82448004, /* 0018(:1341):    LCD: idx1 = var4 + var9 + 4; idx1 once var0; idx1 += inc0 */
4407 +    0x7000000d, /* 001C(:1342):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
4408 +    0x014cf05f, /* 0020(:1342):      DRD2B1: var5 = EU3(); EU3(var1)  */
4409 +    0x7000000b, /* 0024(:1343):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT MORE init=0 WS=0 RS=0 */
4410 +    0x020cf05f, /* 0028(:1343):      DRD2B1: var8 = EU3(); EU3(var1)  */
4411 +    0x70000004, /* 002C(:1344):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
4412 +    0x018cf04a, /* 0030(:1344):      DRD2B1: var6 = EU3(); EU3(var1,var10)  */
4413 +    0x70000004, /* 0034(:1345):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
4414 +    0x004cf04b, /* 0038(:1345):      DRD2B1: var1 = EU3(); EU3(var1,var11)  */
4415 +    0x00000b88, /* 003C(:1348):      DRD1A: var2 = *idx1; FN=0 init=0 WS=0 RS=0 */
4416 +    0xc4838190, /* 0040(:1351):    LCDEXT: idx1 = var9, idx2 = var7; idx1 < var6; idx1 += inc2, idx2 += inc0 */
4417 +    0x8119e012, /* 0044(:1351):    LCD: idx3 = var2; ; idx3 += inc2 */
4418 +    0x03e0cf90, /* 0048(:1354):      DRD1A: *idx3 = *idx2; FN=0 init=31 WS=0 RS=0 */
4419 +    0x81188000, /* 004C(:1357):    LCD: idx1 = var2; idx1 once var0; idx1 += inc0 */
4420 +    0x000ac788, /* 0050(:1358):      DRD1A: *idx1 = *idx1; FN=0 init=0 WS=1 RS=1 */
4421 +    0xc4838000, /* 0054(:1360):    LCDEXT: idx1 = var9, idx2 = var7; idx1 once var0; idx1 += inc0, idx2 += inc0 */
4422 +    0x8219e000, /* 0058(:1360):    LCD: idx3 = var4; ; idx3 += inc0 */
4423 +    0x70000004, /* 005C(:1368):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
4424 +    0x084cfc8c, /* 0060(:1368):      DRD2B1: idx1 = EU3(); EU3(*idx2,var12)  */
4425 +    0x60000005, /* 0064(:1371):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=5 EXT init=0 WS=0 RS=0 */
4426 +    0x0cccf841, /* 0068(:1371):      DRD2B1: *idx3 = EU3(); EU3(idx1,var1)  */
4427 +    0x82468000, /* 006C(:1377):    LCD: idx1 = var4 + var13; idx1 once var0; idx1 += inc0 */
4428 +    0xc419025b, /* 0070(:1379):      LCDEXT: idx2 = var8; idx2 > var9; idx2 += inc3 */
4429 +    0x80198000, /* 0074(:1379):      LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */
4430 +    0x00008400, /* 0078(:1380):        DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */
4431 +    0x00001308, /* 007C(:1381):      DRD1A: var4 = idx1; FN=0 init=0 WS=0 RS=0 */
4432 +    0x82188000, /* 0080(:1384):    LCD: idx1 = var4; idx1 once var0; idx1 += inc0 */
4433 +    0x10000788, /* 0084(:1385):      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
4434 +    0x60000009, /* 0088(:1386):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT init=0 WS=0 RS=0 */
4435 +    0x080cf05f, /* 008C(:1386):      DRD2B1: idx0 = EU3(); EU3(var1)  */
4436 +    0xc2988249, /* 0090(:1389):    LCDEXT: idx1 = var5; idx1 != var9; idx1 += inc1 */
4437 +    0x80190000, /* 0094(:1389):    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
4438 +    0x040001f8, /* 0098(:1390):      DRD1A: FN=0 INT init=0 WS=0 RS=0 */
4439 +    0x000001f8, /* 009C(:0):    NOP */
4440 +};
4441 +u32 MCD_ENetXmit_TDT[]=
4442 +{
4443 +    0x80004000, /* 0000(:1465):  LCDEXT: idx0 = 0x00000000; ; */
4444 +    0x81988000, /* 0004(:1465):  LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
4445 +    0x10000788, /* 0008(:1466):    DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
4446 +    0x60000009, /* 000C(:1467):    DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT init=0 WS=0 RS=0 */
4447 +    0x080cf05f, /* 0010(:1467):    DRD2B1: idx0 = EU3(); EU3(var1)  */
4448 +    0x98180309, /* 0014(:1470):  LCD: idx0 = idx0; idx0 != var12; idx0 += inc1 */
4449 +    0x80004003, /* 0018(:1472):    LCDEXT: idx1 = 0x00000003; ; */
4450 +    0x81c60004, /* 001C(:1472):    LCD: idx2 = var3 + var12 + 4; idx2 once var0; idx2 += inc0 */
4451 +    0x7000000d, /* 0020(:1473):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
4452 +    0x014cf05f, /* 0024(:1473):      DRD2B1: var5 = EU3(); EU3(var1)  */
4453 +    0x7000000b, /* 0028(:1474):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=11 EXT MORE init=0 WS=0 RS=0 */
4454 +    0x028cf05f, /* 002C(:1474):      DRD2B1: var10 = EU3(); EU3(var1)  */
4455 +    0x7000000c, /* 0030(:1475):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=12 EXT MORE init=0 WS=0 RS=0 */
4456 +    0x018cf05f, /* 0034(:1475):      DRD2B1: var6 = EU3(); EU3(var1)  */
4457 +    0x70000004, /* 0038(:1476):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT MORE init=0 WS=0 RS=0 */
4458 +    0x01ccf04d, /* 003C(:1476):      DRD2B1: var7 = EU3(); EU3(var1,var13)  */
4459 +    0x10000b90, /* 0040(:1477):      DRD1A: var2 = *idx2; FN=0 MORE init=0 WS=0 RS=0 */
4460 +    0x60000004, /* 0044(:1478):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=4 EXT init=0 WS=0 RS=0 */
4461 +    0x020cf0a1, /* 0048(:1478):      DRD2B1: var8 = EU3(); EU3(var2,idx1)  */
4462 +    0xc3188312, /* 004C(:1481):    LCDEXT: idx1 = var6; idx1 > var12; idx1 += inc2 */
4463 +    0x83c70000, /* 0050(:1481):    LCD: idx2 = var7 + var14; idx2 once var0; idx2 += inc0 */
4464 +    0x00001f10, /* 0054(:1482):      DRD1A: var7 = idx2; FN=0 init=0 WS=0 RS=0 */
4465 +    0xc583a3c3, /* 0058(:1484):    LCDEXT: idx1 = var11, idx2 = var7; idx2 >= var15; idx1 += inc0, idx2 += inc3 */
4466 +    0x81042325, /* 005C(:1484):    LCD: idx3 = var2, idx4 = var8; idx4 == var12; idx3 += inc4, idx4 += inc5 */
4467 +    0x03e0c798, /* 0060(:1489):      DRD1A: *idx1 = *idx3; FN=0 init=31 WS=0 RS=0 */
4468 +    0xd8990000, /* 0064(:1492):    LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
4469 +    0x9999e000, /* 0068(:1492):    LCD: idx3 = idx3; ; idx3 += inc0 */
4470 +    0x000acf98, /* 006C(:1493):      DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */
4471 +    0xd8992306, /* 0070(:1495):    LCDEXT: idx1 = idx1, idx2 = idx2; idx2 > var12; idx1 += inc0, idx2 += inc6 */
4472 +    0x9999e03f, /* 0074(:1495):    LCD: idx3 = idx3; ; idx3 += inc7 */
4473 +    0x03eac798, /* 0078(:1498):      DRD1A: *idx1 = *idx3; FN=0 init=31 WS=1 RS=1 */
4474 +    0xd8990000, /* 007C(:1501):    LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
4475 +    0x9999e000, /* 0080(:1501):    LCD: idx3 = idx3; ; idx3 += inc0 */
4476 +    0x000acf98, /* 0084(:1502):      DRD1A: *idx3 = *idx3; FN=0 init=0 WS=1 RS=1 */
4477 +    0xd8990000, /* 0088(:1504):    LCDEXT: idx1 = idx1, idx2 = idx2; idx1 once var0; idx1 += inc0, idx2 += inc0 */
4478 +    0x99832302, /* 008C(:1504):    LCD: idx3 = idx3, idx4 = var6; idx4 > var12; idx3 += inc0, idx4 += inc2 */
4479 +    0x0beac798, /* 0090(:1507):      DRD1A: *idx1 = *idx3; FN=0 TFD init=31 WS=1 RS=1 */
4480 +    0x81988000, /* 0094(:1509):    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
4481 +    0x6000000a, /* 0098(:1510):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=10 EXT init=0 WS=0 RS=0 */
4482 +    0x0c4cfc5f, /* 009C(:1510):      DRD2B1: *idx1 = EU3(); EU3(*idx1)  */
4483 +    0x81c80000, /* 00A0(:1512):    LCD: idx1 = var3 + var16; idx1 once var0; idx1 += inc0 */
4484 +    0xc5190312, /* 00A4(:1514):      LCDEXT: idx2 = var10; idx2 > var12; idx2 += inc2 */
4485 +    0x80198000, /* 00A8(:1514):      LCD: idx3 = var0; idx3 once var0; idx3 += inc0 */
4486 +    0x00008400, /* 00AC(:1515):        DRD1A: idx1 = var0; FN=0 init=0 WS=0 RS=0 */
4487 +    0x00000f08, /* 00B0(:1516):      DRD1A: var3 = idx1; FN=0 init=0 WS=0 RS=0 */
4488 +    0x81988000, /* 00B4(:1519):    LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
4489 +    0x10000788, /* 00B8(:1520):      DRD1A: var1 = *idx1; FN=0 MORE init=0 WS=0 RS=0 */
4490 +    0x60000009, /* 00BC(:1521):      DRD2A: EU0=0 EU1=0 EU2=0 EU3=9 EXT init=0 WS=0 RS=0 */
4491 +    0x080cf05f, /* 00C0(:1521):      DRD2B1: idx0 = EU3(); EU3(var1)  */
4492 +    0xc2988309, /* 00C4(:1524):    LCDEXT: idx1 = var5; idx1 != var12; idx1 += inc1 */
4493 +    0x80190000, /* 00C8(:1524):    LCD: idx2 = var0; idx2 once var0; idx2 += inc0 */
4494 +    0x040001f8, /* 00CC(:1525):      DRD1A: FN=0 INT init=0 WS=0 RS=0 */
4495 +    0x000001f8, /* 00D0(:0):    NOP */
4496 +};
4497 +
4498 --- /dev/null
4499 +++ b/drivers/dma/MCD_tasksInit.c
4500 @@ -0,0 +1,284 @@
4501 +/*********************************************************************
4502 + *
4503 + * Copyright (C) 2004  Motorola, Inc.
4504 + *     MOTOROLA, INC. All Rights Reserved.
4505 + *  You are hereby granted a copyright license to use
4506 + *  the SOFTWARE so long as this entire notice is
4507 + *  retained without alteration in any modified and/or redistributed
4508 + *  versions, and that such modified versions are clearly identified
4509 + *  as such. No licenses are granted by implication, estoppel or
4510 + *  otherwise under any patents or trademarks of Motorola, Inc. This
4511 + *  software is provided on an "AS IS" basis and without warranty.
4512 + *
4513 + *  To the maximum extent permitted by applicable law, MOTOROLA
4514 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
4515 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
4516 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
4517 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
4518 + *  ACCOMPANYING WRITTEN MATERIALS.
4519 + *
4520 + *  To the maximum extent permitted by applicable law, IN NO EVENT
4521 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
4522 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
4523 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
4524 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4525 + *
4526 + *  Motorola assumes no responsibility for the maintenance and support
4527 + *  of this software
4528 + ********************************************************************/
4529 +/*
4530 + * Do not edit!
4531 + */
4532 + /*
4533 + * File:               MCD_tasksInit.c
4534 + * Purpose:            Function for initialize variable tables of different
4535 + *              types of tasks.
4536 + *
4537 + * Notes:
4538 + *
4539 + *
4540 + * Modifications:
4541 + *
4542 + *
4543 + */
4544 +
4545 +#include <asm/MCD_dma.h>
4546 +
4547 +extern dmaRegs *MCD_dmaBar;
4548 +
4549 +/*
4550 + * Task 0
4551 + */
4552 +
4553 +void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
4554 +{
4555 +
4556 +       MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
4557 +       MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
4558 +       MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
4559 +       MCD_SET_VAR(taskTable+channel, 19, (u32)xferSize);      /* var[19] */
4560 +       MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));      /* inc[2] */
4561 +       MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
4562 +       MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000);     /* var[1] */
4563 +       MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000);     /* var[3] */
4564 +       MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000);     /* var[4] */
4565 +       MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000);     /* var[5] */
4566 +       MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000);     /* var[6] */
4567 +       MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000);     /* var[7] */
4568 +       MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000);     /* var[8] */
4569 +       MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000);     /* var[9] */
4570 +       MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
4571 +       MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000);    /* var[11] */
4572 +       MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
4573 +       MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000);    /* var[13] */
4574 +       MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000000);    /* var[14] */
4575 +       MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000000);    /* var[15] */
4576 +       MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000000);    /* var[16] */
4577 +       MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000000);    /* var[17] */
4578 +       MCD_SET_VAR(taskTable+channel, 18, (u32)0x00000000);    /* var[18] */
4579 +       MCD_SET_VAR(taskTable+channel, 20, (u32)0x00000000);    /* var[20] */
4580 +       MCD_SET_VAR(taskTable+channel, 21, (u32)0x00000010);    /* var[21] */
4581 +       MCD_SET_VAR(taskTable+channel, 22, (u32)0x00000004);    /* var[22] */
4582 +       MCD_SET_VAR(taskTable+channel, 23, (u32)0x00000080);    /* var[23] */
4583 +       MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
4584 +       MCD_SET_VAR(taskTable+channel, 28, (u32)0x60000000);    /* inc[4] */
4585 +       MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001);    /* inc[5] */
4586 +       MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000000);    /* inc[6] */
4587 +       MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000);    /* inc[7] */
4588 +
4589 +    /* Set the task's Enable bit in its Task Control Register */
4590 +    MCD_dmaBar->taskControl[channel] |= (u16)0x8000; /* add a MACRO HERE TBD*/
4591 +
4592 +
4593 +}
4594 +
4595 +
4596 +/*
4597 + * Task 1
4598 + */
4599 +
4600 +void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, int dmaSizeMXferSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
4601 +{
4602 +
4603 +       MCD_SET_VAR(taskTable+channel, 13, (u32)srcAddr);       /* var[13] */
4604 +       MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
4605 +       MCD_SET_VAR(taskTable+channel, 4, (u32)destAddr);       /* var[4] */
4606 +       MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
4607 +       MCD_SET_VAR(taskTable+channel, 6, (u32)dmaSize);        /* var[6] */
4608 +       MCD_SET_VAR(taskTable+channel, 7, (u32)dmaSizeMXferSize);       /* var[7] */
4609 +       MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));      /* inc[2] */
4610 +       MCD_SET_VAR(taskTable+channel, 9, (u32)flags);  /* var[9] */
4611 +       MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
4612 +       MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
4613 +       MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000);     /* var[2] */
4614 +       MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000);     /* var[3] */
4615 +       MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000);     /* var[5] */
4616 +       MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000);     /* var[8] */
4617 +       MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
4618 +       MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000);    /* var[11] */
4619 +       MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
4620 +       MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000000);    /* var[14] */
4621 +       MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000000);    /* var[15] */
4622 +       MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000004);    /* var[16] */
4623 +       MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000080);    /* var[17] */
4624 +       MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
4625 +       MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001);    /* inc[4] */
4626 +       MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000);    /* inc[5] */
4627 +
4628 +
4629 +    /* enable the task */
4630 +    MCD_dmaBar->taskControl[channel] |= (u16)0x8000; /* add a MACRO HERE TBD*/
4631 +}
4632 +
4633 +
4634 +/*
4635 + * Task 2
4636 + */
4637 +
4638 +void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
4639 +{
4640 +
4641 +       MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
4642 +       MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
4643 +       MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
4644 +       MCD_SET_VAR(taskTable+channel, 19, (u32)xferSize);      /* var[19] */
4645 +       MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));      /* inc[2] */
4646 +       MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
4647 +       MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000);     /* var[1] */
4648 +       MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000);     /* var[3] */
4649 +       MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000);     /* var[4] */
4650 +       MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000);     /* var[5] */
4651 +       MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000);     /* var[6] */
4652 +       MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000);     /* var[7] */
4653 +       MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000);     /* var[8] */
4654 +       MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000);     /* var[9] */
4655 +       MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
4656 +       MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000);    /* var[11] */
4657 +       MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
4658 +       MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000);    /* var[13] */
4659 +       MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000000);    /* var[14] */
4660 +       MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000000);    /* var[15] */
4661 +       MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000000);    /* var[16] */
4662 +       MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000000);    /* var[17] */
4663 +       MCD_SET_VAR(taskTable+channel, 18, (u32)0x00000000);    /* var[18] */
4664 +       MCD_SET_VAR(taskTable+channel, 20, (u32)0x00000000);    /* var[20] */
4665 +       MCD_SET_VAR(taskTable+channel, 21, (u32)0x00000010);    /* var[21] */
4666 +       MCD_SET_VAR(taskTable+channel, 22, (u32)0x00000004);    /* var[22] */
4667 +       MCD_SET_VAR(taskTable+channel, 23, (u32)0x00000080);    /* var[23] */
4668 +       MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
4669 +       MCD_SET_VAR(taskTable+channel, 28, (u32)0x60000000);    /* inc[4] */
4670 +       MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001);    /* inc[5] */
4671 +       MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000000);    /* inc[6] */
4672 +       MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000);    /* inc[7] */
4673 +
4674 +    /*enable the task*/
4675 +    MCD_dmaBar->taskControl[channel] |= (u16)0x8000; /* add a MACRO HERE TBD*/
4676 +}
4677 +
4678 +
4679 +/*
4680 + * Task 3
4681 + */
4682 +
4683 +void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, int dmaSizeMXferSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
4684 +{
4685 +
4686 +       MCD_SET_VAR(taskTable+channel, 13, (u32)srcAddr);       /* var[13] */
4687 +       MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr));   /* inc[1] */
4688 +       MCD_SET_VAR(taskTable+channel, 4, (u32)destAddr);       /* var[4] */
4689 +       MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr));  /* inc[0] */
4690 +       MCD_SET_VAR(taskTable+channel, 6, (u32)dmaSize);        /* var[6] */
4691 +       MCD_SET_VAR(taskTable+channel, 7, (u32)dmaSizeMXferSize);       /* var[7] */
4692 +       MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr));      /* inc[2] */
4693 +       MCD_SET_VAR(taskTable+channel, 9, (u32)flags);  /* var[9] */
4694 +       MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
4695 +       MCD_SET_VAR(taskTable+channel, 0, (u32)cSave);  /* var[0] */
4696 +       MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000);     /* var[2] */
4697 +       MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000);     /* var[3] */
4698 +       MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000);     /* var[5] */
4699 +       MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000);     /* var[8] */
4700 +       MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
4701 +       MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000);    /* var[11] */
4702 +       MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
4703 +       MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000000);    /* var[14] */
4704 +       MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000000);    /* var[15] */
4705 +       MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000004);    /* var[16] */
4706 +       MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000080);    /* var[17] */
4707 +       MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000);    /* inc[3] */
4708 +       MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001);    /* inc[4] */
4709 +       MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000);    /* inc[5] */
4710 +
4711 +    /*enable the task*/
4712 +    MCD_dmaBar->taskControl[channel] |= (u16)0x8000; /* add a MACRO HERE TBD*/
4713 +
4714 +}
4715 +
4716 +
4717 +/*
4718 + * Task 4
4719 + */
4720 +
4721 +void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
4722 +{
4723 +
4724 +       MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
4725 +       MCD_SET_VAR(taskTable+channel, 4, (u32)currBD); /* var[4] */
4726 +       MCD_SET_VAR(taskTable+channel, 7, (u32)rcvFifoPtr);     /* var[7] */
4727 +       MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000);     /* var[1] */
4728 +       MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000);     /* var[2] */
4729 +       MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000);     /* var[3] */
4730 +       MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000);     /* var[5] */
4731 +       MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000);     /* var[6] */
4732 +       MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000);     /* var[8] */
4733 +       MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000);     /* var[9] */
4734 +       MCD_SET_VAR(taskTable+channel, 10, (u32)0x0000ffff);    /* var[10] */
4735 +       MCD_SET_VAR(taskTable+channel, 11, (u32)0x30000000);    /* var[11] */
4736 +       MCD_SET_VAR(taskTable+channel, 12, (u32)0x0fffffff);    /* var[12] */
4737 +       MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000008);    /* var[13] */
4738 +       MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000);    /* inc[0] */
4739 +       MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000);    /* inc[1] */
4740 +       MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004);    /* inc[2] */
4741 +       MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000);    /* inc[3] */
4742 +    /*enable the task*/
4743 +    MCD_dmaBar->taskControl[channel] |= (u16)0x8000; /* add a MACRO HERE TBD*/
4744 +
4745 +}
4746 +
4747 +
4748 +/*
4749 + * Task 5
4750 + */
4751 +
4752 +void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
4753 +{
4754 +
4755 +       MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
4756 +       MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
4757 +       MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr);   /* var[11] */
4758 +       MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000);     /* var[1] */
4759 +       MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000);     /* var[2] */
4760 +       MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000);     /* var[4] */
4761 +       MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000);     /* var[5] */
4762 +       MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000);     /* var[6] */
4763 +       MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000);     /* var[7] */
4764 +       MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000);     /* var[8] */
4765 +       MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000);     /* var[9] */
4766 +       MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000);    /* var[10] */
4767 +       MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000);    /* var[12] */
4768 +       MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff);    /* var[13] */
4769 +       MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff);    /* var[14] */
4770 +       MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004);    /* var[15] */
4771 +       MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008);    /* var[16] */
4772 +       MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000);    /* inc[0] */
4773 +       MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000);    /* inc[1] */
4774 +       MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000);    /* inc[2] */
4775 +       MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc);    /* inc[3] */
4776 +       MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004);    /* inc[4] */
4777 +       MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000);    /* inc[5] */
4778 +       MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff);    /* inc[6] */
4779 +       MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001);    /* inc[7] */
4780 +
4781 +    /*enable the task*/
4782 +    MCD_dmaBar->taskControl[channel] |= (u16)0x8000; /* add a MACRO HERE TBD*/
4783 +
4784 +}
4785 --- /dev/null
4786 +++ b/drivers/dma/MCD_tasksInit.h
4787 @@ -0,0 +1,73 @@
4788 +/*********************************************************************
4789 + *
4790 + * Copyright (C) 2004  Motorola, Inc.
4791 + *  MOTOROLA, INC. All Rights Reserved.
4792 + *  You are hereby granted a copyright license to use
4793 + *  the SOFTWARE so long as this entire notice is
4794 + *  retained without alteration in any modified and/or redistributed
4795 + *  versions, and that such modified versions are clearly identified
4796 + *  as such. No licenses are granted by implication, estoppel or
4797 + *  otherwise under any patents or trademarks of Motorola, Inc. This
4798 + *  software is provided on an "AS IS" basis and without warranty.
4799 + *
4800 + *  To the maximum extent permitted by applicable law, MOTOROLA
4801 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
4802 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
4803 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
4804 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
4805 + *  ACCOMPANYING WRITTEN MATERIALS.
4806 + *
4807 + *  To the maximum extent permitted by applicable law, IN NO EVENT
4808 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
4809 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
4810 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
4811 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
4812 + *
4813 + *  Motorola assumes no responsibility for the maintenance and support
4814 + *  of this software
4815 + ********************************************************************/
4816 +#ifndef MCD_TSK_INIT_H
4817 +#define MCD_TSK_INIT_H 1
4818 +
4819 +/*
4820 + * Do not edit!
4821 + */
4822 +
4823 +
4824 +
4825 +/*
4826 + * Task 0
4827 + */
4828 +void  MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
4829 +
4830 +
4831 +/*
4832 + * Task 1
4833 + */
4834 +void  MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, int dmaSizeMXferSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
4835 +
4836 +
4837 +/*
4838 + * Task 2
4839 + */
4840 +void  MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
4841 +
4842 +
4843 +/*
4844 + * Task 3
4845 + */
4846 +void  MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, int dmaSizeMXferSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
4847 +
4848 +
4849 +/*
4850 + * Task 4
4851 + */
4852 +void  MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
4853 +
4854 +
4855 +/*
4856 + * Task 5
4857 + */
4858 +void  MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
4859 +
4860 +#endif  /* MCD_TSK_INIT_H */
4861 --- a/drivers/dma/Makefile
4862 +++ b/drivers/dma/Makefile
4863 @@ -4,3 +4,5 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
4864  ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
4865  obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
4866  obj-$(CONFIG_FSL_DMA) += fsldma.o
4867 +obj-$(CONFIG_MCD_DMA) += mcddma.o
4868 +mcddma-objs := MCD_dmaApi.o MCD_tasks.o MCD_tasksInit.o
4869 --- a/drivers/net/Kconfig
4870 +++ b/drivers/net/Kconfig
4871 @@ -351,6 +351,8 @@ config MACB
4872
4873  source "drivers/net/arm/Kconfig"
4874
4875 +source "drivers/net/fec/Kconfig"
4876 +
4877  config AX88796
4878         tristate "ASIX AX88796 NE2000 clone support"
4879         depends on ARM || MIPS || SUPERH
4880 --- a/drivers/net/Makefile
4881 +++ b/drivers/net/Makefile
4882 @@ -226,6 +226,8 @@ obj-$(CONFIG_ENC28J60) += enc28j60.o
4883
4884  obj-$(CONFIG_MACB) += macb.o
4885
4886 +obj-$(CONFIG_FEC_548x) += fec/
4887 +
4888  obj-$(CONFIG_ARM) += arm/
4889  obj-$(CONFIG_DEV_APPLETALK) += appletalk/
4890  obj-$(CONFIG_TR) += tokenring/
4891 --- /dev/null
4892 +++ b/drivers/net/fec/Kconfig
4893 @@ -0,0 +1,25 @@
4894 +config FEC_548x
4895 +       tristate "MCF547x/MCF548x Fast Ethernet Controller support"
4896 +       depends on M547X_8X
4897 +       help
4898 +         The MCF547x and MCF548x have a built-in Fast Ethernet Controller.
4899 +         Saying Y here will include support for this device in the kernel.
4900 +
4901 +         To compile this driver as a module, choose M here: the module
4902 +         will be called fecm.
4903 +
4904 +config FEC_548x_AUTO_NEGOTIATION
4905 +       bool "Enable Auto-Negotiation"
4906 +       depends on FEC_548x
4907 +       help
4908 +         This option enables the FEC to automatically detect the
4909 +         half/full duplex mode and the network speed at initialization
4910 +         If you want this, say Y.
4911 +
4912 +config FEC_548x_ENABLE_FEC2
4913 +       bool "Enable the second FEC"
4914 +       depends on FEC_548x
4915 +       help
4916 +         This enables the second FEC on the 547x/548x. If you want to use
4917 +         it, say Y.
4918 +
4919 --- /dev/null
4920 +++ b/drivers/net/fec/Makefile
4921 @@ -0,0 +1,7 @@
4922 +#
4923 +# Makefile for the FEC ethernet driver
4924 +#
4925 +
4926 +obj-$(CONFIG_FEC_548x) += fecm.o
4927 +
4928 +fecm-objs := fec.o ks8721.o
4929 --- /dev/null
4930 +++ b/drivers/net/fec/fec.c
4931 @@ -0,0 +1,1375 @@
4932 +/*
4933 + * Performance and stability improvements: (C) Copyright 2008,
4934 + *      Daniel Krueger, SYSTEC electronic GmbH
4935 + *
4936 + * Code crunched to get it to work on 2.6.24 -- FEC cleanup coming
4937 + * soon -- Kurt Mahan
4938 + *
4939 + */
4940 +#include <linux/module.h>
4941 +#include <linux/kernel.h>
4942 +#include <linux/string.h>
4943 +#include <linux/ptrace.h>
4944 +#include <linux/errno.h>
4945 +#include <linux/ioport.h>
4946 +#include <linux/slab.h>
4947 +#include <linux/interrupt.h>
4948 +#include <linux/pci.h>
4949 +#include <linux/init.h>
4950 +#include <linux/delay.h>
4951 +#include <linux/netdevice.h>
4952 +#include <linux/etherdevice.h>
4953 +#include <linux/skbuff.h>
4954 +#include <linux/spinlock.h>
4955 +#include <linux/workqueue.h>
4956 +#include <linux/bitops.h>
4957 +
4958 +#include <asm/coldfire.h>
4959 +#include <asm/mcfsim.h>
4960 +
4961 +#include <asm/dma.h>
4962 +#include <asm/MCD_dma.h>
4963 +#include <asm/m5485sram.h>
4964 +#include <asm/virtconvert.h>
4965 +#include <asm/irq.h>
4966 +
4967 +#include "fec.h"
4968 +#include "ks8721.h"
4969 +
4970 +#ifdef CONFIG_FEC_548x_ENABLE_FEC2
4971 +#define        FEC_MAX_PORTS   2
4972 +#define        FEC_2
4973 +#else
4974 +#define        FEC_MAX_PORTS   1
4975 +#undef FEC_2
4976 +#endif
4977 +
4978 +#define VERSION "0.13"
4979 +MODULE_DESCRIPTION( "DMA Fast Ethernet Controller driver ver " VERSION);
4980 +
4981 +// Private structure
4982 +struct fec_priv {
4983 +       struct net_device *netdev;              /* owning net device */
4984 +       void* fecpriv_txbuf[FEC_TX_BUF_NUMBER]; //Array of transmission buffers
4985 +       MCD_bufDescFec *fecpriv_txdesc; // Array of transmission descriptors
4986 +       volatile unsigned int fecpriv_current_tx;       // Inex of the transmission descriptor that is used by DMA
4987 +       volatile unsigned int fecpriv_next_tx;  // Inex of the transmission descriptor that can be used for new data
4988 +       unsigned int fecpriv_current_rx;        // Index of the reception descriptor that is used by DMA
4989 +       MCD_bufDescFec *fecpriv_rxdesc;         // Array of reception descriptors
4990 +//     unsigned char *fecpriv_rxbuf;           // Address of reception buffers
4991 +       struct sk_buff *askb_rx[FEC_RX_BUF_NUMBER]; // Array of reception skb structure pointers
4992 +       unsigned int fecpriv_initiator_rx;      // Reception DMA initiator
4993 +       unsigned int fecpriv_initiator_tx;      // Transmission DMA initiator
4994 +       int fecpriv_fec_rx_channel;     // DMA reception channel
4995 +       int fecpriv_fec_tx_channel;     // DMA transmission channel
4996 +       int fecpriv_rx_requestor;       // DMA reception requestor
4997 +       int fecpriv_tx_requestor;       // DMA transmission requestor
4998 +       void *fecpriv_interrupt_fec_rx_handler; // DMA reception handler
4999 +       void *fecpriv_interrupt_fec_tx_handler; // DMA transmission handler
5000 +       unsigned char *fecpriv_mac_addr;        // Private copy of FEC address
5001 +       struct net_device_stats fecpriv_stat;   // Pointer to the statistical information
5002 +       spinlock_t fecpriv_lock;
5003 +       int fecpriv_rxflag;
5004 +       struct tasklet_struct fecpriv_tasklet_reinit;
5005 +       int index;
5006 +};
5007 +
5008 +struct net_device *fec_dev[FEC_MAX_PORTS];
5009 +
5010 +// FEC functions
5011 +int __init fec_init(void);
5012 +struct net_device_stats *fec_get_stat(struct net_device *dev);
5013 +
5014 +int fec_open(struct net_device *dev);
5015 +int fec_close(struct net_device *nd);
5016 +int fec_tx(struct sk_buff *skb, struct net_device *dev);
5017 +void fec_set_multicast_list(struct net_device *nd);
5018 +int fec_set_mac_address(struct net_device *dev, void *p);
5019 +void fec_tx_timeout(struct net_device *dev);
5020 +void fec_interrupt_fec_tx_handler(struct net_device *dev);
5021 +void fec_interrupt_fec_rx_handler(struct net_device *dev);
5022 +irqreturn_t fec_interrupt_handler(int irq, void *dev_id);
5023 +void fec_interrupt_fec_tx_handler_fec0(void);
5024 +void fec_interrupt_fec_rx_handler_fec0(void);
5025 +void fec_interrupt_fec_reinit(unsigned long data);
5026 +
5027 +unsigned char fec_mac_addr_fec0[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x50 };   // Default address of FEC0
5028 +
5029 +#ifdef   FEC_2
5030 +unsigned char fec_mac_addr_fec1[6] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x51 };   // Default address of FEC1
5031 +#endif
5032 +
5033 +#ifndef MODULE
5034 +int fec_str_to_mac( char *str_mac, unsigned char* addr);
5035 +int __init fec_mac_setup0 (char *s);
5036 +#endif
5037 +
5038 +
5039 +#ifdef   FEC_2
5040 +void fec_interrupt_fec_tx_handler_fec1(void);
5041 +void fec_interrupt_fec_rx_handler_fec1(void);
5042 +
5043 +#ifndef MODULE
5044 +int __init fec_mac_setup1 (char *s);
5045 +#endif
5046 +
5047 +#endif
5048 +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int *data);
5049 +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int data);
5050 +
5051 +module_init(fec_init);
5052 +/* module_exit(fec_cleanup); */
5053 +__setup("mac0=", fec_mac_setup0);
5054 +
5055 +#ifdef   FEC_2
5056 +__setup("mac1=", fec_mac_setup1);
5057 +#endif
5058 +
5059 +/*
5060 + * Initialize a FEC device
5061 + */
5062 +int fec_enet_init(struct net_device *dev)
5063 +{
5064 +       static int index = 0;
5065 +       struct fec_priv *fp = netdev_priv(dev);
5066 +       int i;
5067 +
5068 +       fp->index = index;
5069 +       fp->netdev = dev;
5070 +       fec_dev[ index ] = dev;
5071 +printk(KERN_INFO "FEI: index=%d\n", index);
5072 +
5073 +       if (index == 0) {
5074 +               /* disable fec0 */
5075 +               FEC_ECR(FEC_BASE_ADDR_FEC0) = FEC_ECR_DISABLE;
5076 +
5077 +               /* setup the interrupt handler */
5078 +               dev->irq = 64 + ISC_FEC0;
5079 +
5080 +               if (request_irq(dev->irq, fec_interrupt_handler,
5081 +                               IRQF_DISABLED, "ColdFire FEC 0", dev)) {
5082 +                       dev->irq = 0;
5083 +                       printk("Cannot allocate FEC0 IRQ\n");
5084 +               } else {
5085 +                       /* interrupt priority and level */
5086 +                       MCF_ICR(ISC_FEC0) = ILP_FEC0;
5087 +               }
5088 +
5089 +               /* fec base address */
5090 +               dev->base_addr = FEC_BASE_ADDR_FEC0;
5091 +
5092 +               /* requestor numbers */
5093 +               fp->fecpriv_rx_requestor = DMA_FEC0_RX;
5094 +               fp->fecpriv_tx_requestor = DMA_FEC0_TX;
5095 +
5096 +               /* fec0 handlers */
5097 +               fp->fecpriv_interrupt_fec_rx_handler = fec_interrupt_fec_rx_handler_fec0;
5098 +               fp->fecpriv_interrupt_fec_tx_handler = fec_interrupt_fec_tx_handler_fec0;
5099 +
5100 +               /* tx descriptors */
5101 +               fp->fecpriv_txdesc = (void*)FEC_TX_DESC_FEC0;
5102 +
5103 +               /* rx descriptors */
5104 +               fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC0;
5105 +
5106 +printk(KERN_INFO "FEI: txdesc=0x%p  rxdesc=0x%p\n", fp->fecpriv_txdesc, fp->fecpriv_rxdesc);
5107 +
5108 +               /* mac addr */
5109 +               fp->fecpriv_mac_addr = fec_mac_addr_fec0;
5110 +       }
5111 +       else {
5112 +               /* disable fec1 */
5113 +               FEC_ECR(FEC_BASE_ADDR_FEC1) = FEC_ECR_DISABLE;
5114 +#ifdef FEC_2
5115 +               /* setup the interrupt handler */
5116 +               dev->irq = 64 + ISC_FEC1;
5117 +
5118 +               if (request_irq(dev->irq, fec_interrupt_handler,
5119 +                               IRQF_DISABLED, "ColdFire FEC 1", dev)) {
5120 +                       dev->irq = 0;
5121 +                       printk("Cannot allocate FEC1 IRQ\n");
5122 +               } else {
5123 +                       /* interrupt priority and level */
5124 +                       MCF_ICR(ISC_FEC1) = ILP_FEC1;
5125 +               }
5126 +
5127 +               /* fec base address */
5128 +               dev->base_addr = FEC_BASE_ADDR_FEC1;
5129 +
5130 +               /* requestor numbers */
5131 +               fp->fecpriv_rx_requestor = DMA_FEC1_RX;
5132 +               fp->fecpriv_tx_requestor = DMA_FEC1_TX;
5133 +
5134 +               /* fec1 handlers */
5135 +               fp->fecpriv_interrupt_fec_rx_handler = fec_interrupt_fec_rx_handler_fec1;
5136 +               fp->fecpriv_interrupt_fec_tx_handler = fec_interrupt_fec_tx_handler_fec1;
5137 +
5138 +               /* tx descriptors */
5139 +               fp->fecpriv_txdesc = (void*)FEC_TX_DESC_FEC1;
5140 +
5141 +               /* rx descriptors */
5142 +               fp->fecpriv_rxdesc = (void*)FEC_RX_DESC_FEC1;
5143 +
5144 +               /* mac addr */
5145 +               fp->fecpriv_mac_addr = fec_mac_addr_fec1;
5146 +#endif
5147 +       }
5148 +
5149 +printk(KERN_INFO "FEI: index=%d base_addr=0x%lx\n", index, dev->base_addr);
5150 +
5151 +       /* clear MIB */
5152 +       memset((void *) (dev->base_addr + 0x200), 0, FEC_MIB_LEN);
5153 +
5154 +       /* clear the statistics structure */
5155 +       memset((void *) &(fp->fecpriv_stat), 0,
5156 +              sizeof(struct net_device_stats));
5157 +
5158 +       /* grab the FEC initiators */
5159 +       dma_set_initiator(fp->fecpriv_tx_requestor);
5160 +       fp->fecpriv_initiator_tx = dma_get_initiator(fp->fecpriv_tx_requestor);
5161 +       dma_set_initiator(fp->fecpriv_rx_requestor);
5162 +       fp->fecpriv_initiator_rx = dma_get_initiator(fp->fecpriv_rx_requestor);
5163 +
5164 +       /* reset the DMA channels */
5165 +       fp->fecpriv_fec_rx_channel = -1;
5166 +       fp->fecpriv_fec_tx_channel = -1;
5167 +
5168 +       for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
5169 +               fp->askb_rx[i] = NULL;
5170 +
5171 +       /* initialize the pointers to the socket buffers */
5172 +       for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
5173 +               fp->fecpriv_txbuf[i] = NULL;
5174 +
5175 +       ether_setup(dev);
5176 +
5177 +       dev->open = fec_open;
5178 +       dev->stop = fec_close;
5179 +       dev->hard_start_xmit = fec_tx;
5180 +       dev->get_stats = fec_get_stat;
5181 +       dev->set_multicast_list = fec_set_multicast_list;
5182 +       dev->set_mac_address = fec_set_mac_address;
5183 +       dev->tx_timeout = fec_tx_timeout;
5184 +       dev->watchdog_timeo = FEC_TX_TIMEOUT * HZ;
5185 +
5186 +       memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN);
5187 +
5188 +       spin_lock_init(&fp->fecpriv_lock);
5189 +
5190 +       // Initialize FEC/I2C/IRQ Pin Assignment Register
5191 +       FEC_GPIO_PAR_FECI2CIRQ &= 0xF;
5192 +       FEC_GPIO_PAR_FECI2CIRQ |= FEC_FECI2CIRQ;
5193 +
5194 +       index++;
5195 +       return 0;
5196 +}
5197 +
5198 +/*
5199 + * Module Initialization
5200 + */
5201 +int __init fec_init(void)
5202 +{
5203 +       struct net_device *dev;
5204 +       int i;
5205 +       int err;
5206 +       DECLARE_MAC_BUF(mac);
5207 +
5208 +       printk(KERN_INFO "FEC ENET (DMA) Version .00\n");
5209 +
5210 +
5211 +       for (i = 0; i < FEC_MAX_PORTS; i++) {
5212 +               dev = alloc_etherdev(sizeof(struct fec_priv));
5213 +               if (!dev)
5214 +                       return -ENOMEM;
5215 +               err = fec_enet_init(dev);
5216 +               if (err) {
5217 +                       free_netdev(dev);
5218 +                       continue;
5219 +               }
5220 +               if (register_netdev(dev) != 0) {
5221 +                       free_netdev(dev);
5222 +                       return -EIO;
5223 +               }
5224 +
5225 +               printk(KERN_INFO "%s: ethernet %s\n",
5226 +                      dev->name, print_mac(mac, dev->dev_addr));
5227 +       }
5228 +       return 0;
5229 +}
5230 +
5231 +/*
5232 + * Stop a device
5233 + */
5234 +void fec_stop(struct net_device *dev)
5235 +{
5236 +       struct fec_priv *fp = netdev_priv(dev);
5237 +
5238 +       dma_remove_initiator(fp->fecpriv_initiator_tx);
5239 +       dma_remove_initiator(fp->fecpriv_initiator_rx);
5240 +
5241 +       if (dev->irq)
5242 +               free_irq(dev->irq, dev);
5243 +}
5244 +
5245 +/************************************************************************
5246 +* NAME: fec_open
5247 +*
5248 +* DESCRIPTION: This function performs the initialization of
5249 +*                              of FEC and corresponding KS8721 transiver
5250 +*
5251 +* RETURNS: If no error occurs, this function returns zero.
5252 +*************************************************************************/
5253 +
5254 +int fec_open(struct net_device *dev)
5255 +{
5256 +       struct fec_priv *fp = netdev_priv(dev);
5257 +       unsigned long base_addr = (unsigned long) dev->base_addr;
5258 +       int fduplex;
5259 +       int i;
5260 +       int channel;
5261 +       int error_code = -EBUSY;
5262 +
5263 +printk(KERN_INFO "FECOPEN: index=%d\n", fp->index);
5264 +
5265 +       //Receive the DMA channels
5266 +       channel = dma_set_channel_fec(fp->fecpriv_rx_requestor);
5267 +
5268 +       if (channel == -1)
5269 +       {
5270 +               printk("Dma channel cannot be reserved\n");
5271 +               goto ERRORS;
5272 +       }
5273 +
5274 +       fp->fecpriv_fec_rx_channel = channel;
5275 +
5276 +       dma_connect(channel, (int) fp->fecpriv_interrupt_fec_rx_handler);
5277 +
5278 +       channel = dma_set_channel_fec(fp->fecpriv_tx_requestor);
5279 +
5280 +       if (channel == -1)
5281 +       {
5282 +               printk("Dma channel cannot be reserved\n");
5283 +               goto ERRORS;
5284 +       }
5285 +printk(KERN_INFO "FECOPEN2\n");
5286 +
5287 +       fp->fecpriv_fec_tx_channel = channel;
5288 +
5289 +       dma_connect(channel, (int) fp->fecpriv_interrupt_fec_tx_handler);
5290 +
5291 +       // init tasklet for controller reinitialization
5292 +       tasklet_init(&fp->fecpriv_tasklet_reinit, fec_interrupt_fec_reinit, (unsigned long) dev);
5293 +printk(KERN_INFO "FECOPEN3\n");
5294 +
5295 +       // Reset FIFOs
5296 +       FEC_FECFRST(base_addr) |= FEC_SW_RST | FEC_RST_CTL;
5297 +       FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
5298 +
5299 +       // Reset and disable FEC
5300 +       FEC_ECR(base_addr) = FEC_ECR_RESET;
5301 +
5302 +       // Wait
5303 +       udelay(10);
5304 +
5305 +       // Clear all events
5306 +       FEC_EIR(base_addr) = FEC_EIR_CLEAR;
5307 +
5308 +       // Reset FIFO status
5309 +       FEC_FECTFSR(base_addr) = FEC_FECTFSR_MSK;
5310 +       FEC_FECRFSR(base_addr) = FEC_FECRFSR_MSK;
5311 +
5312 +#if 0
5313 +/* JKM -- move into HW init */
5314 +       // Copy the default address to the device structure
5315 +       memcpy(dev->dev_addr, fp->fecpriv_mac_addr, ETH_ALEN);
5316 +#endif
5317 +
5318 +       // Set the default address
5319 +       FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | (fp->fecpriv_mac_addr[1] << 16) | (fp->fecpriv_mac_addr[2] << 8) | fp->fecpriv_mac_addr[3];
5320 +       FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
5321 +
5322 +       // Reset the group address descriptor
5323 +       FEC_GALR(base_addr) = 0x00000000;
5324 +       FEC_GAUR(base_addr) = 0x00000000;
5325 +
5326 +       // Reset the individual address descriptor
5327 +       FEC_IALR(base_addr) = 0x00000000;
5328 +       FEC_IAUR(base_addr) = 0x00000000;
5329 +
5330 +       // Set the receive control register
5331 +       FEC_RCR(base_addr) = FEC_RCR_MAX_FRM_SIZE | FEC_RCR_MII;
5332 +
5333 +       // Set the receive FIFO control register
5334 +//     FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR | FEC_FECRFCR_MSK;
5335 +       FEC_FECRFCR(base_addr) = FEC_FECRFCR_FRM | FEC_FECRFCR_GR
5336 +                             | (FEC_FECRFCR_MSK     // disable all but ...
5337 +                                & ~FEC_FECRFCR_FAE  // enable frame accept error
5338 +                                & ~FEC_FECRFCR_RXW  // enable receive wait condition
5339 +//                                & ~FEC_FECRFCR_UF   // enable FIFO underflow
5340 +                             );
5341 +
5342 +       //Set the receive FIFO alarm register
5343 +       FEC_FECRFAR(base_addr) = FEC_FECRFAR_ALARM;
5344 +
5345 +       // Set the transmit FIFO control register
5346 +//     FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR | FEC_FECTFCR_MSK;
5347 +       FEC_FECTFCR(base_addr) = FEC_FECTFCR_FRM | FEC_FECTFCR_GR
5348 +                             | (FEC_FECTFCR_MSK     // disable all but ...
5349 +                                & ~FEC_FECTFCR_FAE  // enable frame accept error
5350 +//                                & ~FEC_FECTFCR_TXW  // enable transmit wait condition
5351 +//                                & ~FEC_FECTFCR_UF   // enable FIFO underflow
5352 +                                & ~FEC_FECTFCR_OF); // enable FIFO overflow
5353 +
5354 +       //Set the transmit FIFO alarm register
5355 +       FEC_FECTFAR(base_addr) = FEC_FECTFAR_ALARM;
5356 +
5357 +       // Set the Tx FIFO watermark
5358 +       FEC_FECTFWR(base_addr) = FEC_FECTFWR_XWMRK;
5359 +
5360 +       // Enable the transmitter to append the CRC
5361 +       FEC_CTCWR(base_addr) = FEC_CTCWR_TFCW_CRC;
5362 +
5363 +       // Enable the ethernet interrupts
5364 +//     FEC_EIMR(base_addr) = FEC_EIMR_MASK;
5365 +       FEC_EIMR(base_addr) = FEC_EIMR_DISABLE
5366 +                            | FEC_EIR_LC
5367 +                            | FEC_EIR_RL
5368 +                            | FEC_EIR_HBERR
5369 +                            | FEC_EIR_XFUN
5370 +                            | FEC_EIR_XFERR
5371 +                            | FEC_EIR_RFERR
5372 +                            ;
5373 +printk(KERN_INFO "FECOPEN4\n");
5374 +
5375 +#ifdef   CONFIG_FEC_548x_AUTO_NEGOTIATION
5376 +       if ((error_code = init_transceiver(base_addr, &fduplex)) != 0)
5377 +       {
5378 +               printk("Initialization of the transceiver is failed\n");
5379 +               goto ERRORS;
5380 +       }
5381 +#else
5382 +       fduplex = 1;
5383 +#endif
5384 +printk(KERN_INFO "FECOPEN5\n");
5385 +
5386 +       if (fduplex)
5387 +               // Enable the full duplex mode
5388 +               FEC_TCR(base_addr) = FEC_TCR_FDEN | FEC_TCR_HBC;
5389 +       else
5390 +               // Disable reception of frames while transmitting
5391 +               FEC_RCR(base_addr) |= FEC_RCR_DRT;
5392 +
5393 +       // Enable MIB
5394 +       FEC_MIBC(base_addr) = FEC_MIBC_ENABLE;
5395 +
5396 +       // Enable FEC
5397 +       FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
5398 +
5399 +       // Initialize transmission descriptors and start DMA for the transmission
5400 +       for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
5401 +               fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
5402 +printk(KERN_INFO "FECOPEN6\n");
5403 +
5404 +       fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
5405 +
5406 +       fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
5407 +
5408 +       MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
5409 +                    (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
5410 +                    FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
5411 +                    FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
5412 +                    MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
5413 +
5414 +       // Initialize reception descriptors and start DMA for the reception
5415 +       for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
5416 +       {
5417 +               fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_DMA);
5418 +               if (!fp->askb_rx[i])
5419 +               {
5420 +               fp->fecpriv_rxdesc[i].dataPointer = 0;
5421 +               fp->fecpriv_rxdesc[i].statCtrl = 0;
5422 +               fp->fecpriv_rxdesc[i].length = 0;
5423 +               }
5424 +               else
5425 +               {
5426 +                   skb_reserve(fp->askb_rx[i], 16);
5427 +                       fp->askb_rx[i]->dev = dev;
5428 +               fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
5429 +               fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
5430 +               fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
5431 +           }
5432 +       }
5433 +printk(KERN_INFO "FECOPEN7\n");
5434 +
5435 +       fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
5436 +       fp->fecpriv_current_rx = 0;
5437 +
5438 +       // flush entire data cache before restarting the DMA
5439 +#if 0
5440 +/* JKM -- currently running with cache turned off */
5441 +       DcacheFlushInvalidate();
5442 +#endif
5443 +
5444 +       MCD_startDma(fp->fecpriv_fec_rx_channel, (char *) fp->fecpriv_rxdesc, 0,
5445 +                    (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
5446 +                    FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx,
5447 +                    FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT,
5448 +                    MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
5449 +
5450 +       netif_start_queue(dev);
5451 +
5452 +//     MOD_INC_USE_COUNT;
5453 +printk(KERN_INFO "FECOPEN: finished\n");
5454 +
5455 +       return 0;
5456 +
5457 +ERRORS:
5458 +
5459 +       // Remove the channels and return with the error code
5460 +       if (fp->fecpriv_fec_rx_channel != -1)
5461 +       {
5462 +               dma_disconnect(fp->fecpriv_fec_rx_channel);
5463 +               dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
5464 +               fp->fecpriv_fec_rx_channel = -1;
5465 +       }
5466 +
5467 +       if (fp->fecpriv_fec_tx_channel != -1)
5468 +       {
5469 +               dma_disconnect(fp->fecpriv_fec_tx_channel);
5470 +               dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
5471 +               fp->fecpriv_fec_tx_channel = -1;
5472 +       }
5473 +
5474 +       return error_code;
5475 +
5476 +}
5477 +
5478 +/************************************************************************
5479 +* NAME: fec_close
5480 +*
5481 +* DESCRIPTION: This function performs the graceful stop of the
5482 +*                              transmission and disables FEC
5483 +*
5484 +* RETURNS: This function always returns zero.
5485 +*************************************************************************/
5486 +int fec_close(struct net_device *dev)
5487 +{
5488 +       //Receive the pointer to the private structure
5489 +       struct fec_priv *fp = netdev_priv(dev);
5490 +
5491 +       // Receive the base address
5492 +       unsigned long base_addr = (unsigned long) dev->base_addr;
5493 +
5494 +       unsigned long time;
5495 +
5496 +       int i;
5497 +
5498 +       netif_stop_queue(dev);
5499 +
5500 +       // Perform the graceful stop
5501 +       FEC_TCR(base_addr) |= FEC_TCR_GTS;
5502 +
5503 +       time = jiffies;
5504 +
5505 +       // Wait for the graceful stop
5506 +       while (!(FEC_EIR(base_addr) & FEC_EIR_GRA) && jiffies - time < FEC_GR_TIMEOUT * HZ)
5507 +               schedule();
5508 +
5509 +       // Disable FEC
5510 +       FEC_ECR(base_addr) = FEC_ECR_DISABLE;
5511 +
5512 +       // Reset the DMA channels
5513 +       spin_lock_irq(&fp->fecpriv_lock);
5514 +       MCD_killDma(fp->fecpriv_fec_tx_channel);
5515 +       spin_unlock_irq(&fp->fecpriv_lock);
5516 +       dma_remove_channel_by_number(fp->fecpriv_fec_tx_channel);
5517 +       dma_disconnect(fp->fecpriv_fec_tx_channel);
5518 +       fp->fecpriv_fec_tx_channel = -1;
5519 +
5520 +       for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
5521 +               if (fp->fecpriv_txbuf[i])
5522 +               {
5523 +                       kfree(fp->fecpriv_txbuf[i]);
5524 +                       fp->fecpriv_txbuf[i] = NULL;
5525 +               }
5526 +
5527 +       spin_lock_irq(&fp->fecpriv_lock);
5528 +       MCD_killDma(fp->fecpriv_fec_rx_channel);
5529 +       spin_unlock_irq(&fp->fecpriv_lock);
5530 +
5531 +       dma_remove_channel_by_number(fp->fecpriv_fec_rx_channel);
5532 +       dma_disconnect(fp->fecpriv_fec_rx_channel);
5533 +       fp->fecpriv_fec_rx_channel = -1;
5534 +
5535 +       for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
5536 +       {
5537 +               if (fp->askb_rx[i])
5538 +               {
5539 +                   kfree_skb(fp->askb_rx[i]);
5540 +                   fp->askb_rx[i] = NULL;
5541 +           }
5542 +       }
5543 +//     MOD_DEC_USE_COUNT;
5544 +
5545 +       return 0;
5546 +}
5547 +
5548 +/************************************************************************
5549 +* +NAME: fec_get_stat
5550 +*
5551 +* RETURNS: This function returns the statistical information.
5552 +*************************************************************************/
5553 +struct net_device_stats * fec_get_stat(struct net_device *dev)
5554 +{
5555 +
5556 +       //Receive the pointer to the private structure
5557 +       struct fec_priv *fp = netdev_priv(dev);
5558 +
5559 +       // Receive the base address
5560 +       unsigned long base_addr = dev->base_addr;
5561 +
5562 +       // Receive the statistical information
5563 +       fp->fecpriv_stat.rx_packets = FECSTAT_RMON_R_PACKETS(base_addr);
5564 +       fp->fecpriv_stat.tx_packets = FECSTAT_RMON_T_PACKETS(base_addr);
5565 +       fp->fecpriv_stat.rx_bytes = FECSTAT_RMON_R_OCTETS(base_addr);
5566 +       fp->fecpriv_stat.tx_bytes = FECSTAT_RMON_T_OCTETS(base_addr);
5567 +
5568 +       fp->fecpriv_stat.multicast = FECSTAT_RMON_R_MC_PKT(base_addr);
5569 +       fp->fecpriv_stat.collisions = FECSTAT_RMON_T_COL(base_addr);
5570 +
5571 +       fp->fecpriv_stat.rx_length_errors = FECSTAT_RMON_R_UNDERSIZE(base_addr) + FECSTAT_RMON_R_OVERSIZE(base_addr) + FECSTAT_RMON_R_FRAG(base_addr) + FECSTAT_RMON_R_JAB(base_addr);
5572 +       fp->fecpriv_stat.rx_crc_errors = FECSTAT_IEEE_R_CRC(base_addr);
5573 +       fp->fecpriv_stat.rx_frame_errors = FECSTAT_IEEE_R_ALIGN(base_addr);
5574 +       fp->fecpriv_stat.rx_over_errors = FECSTAT_IEEE_R_MACERR(base_addr);
5575 +
5576 +       fp->fecpriv_stat.tx_carrier_errors = FECSTAT_IEEE_T_CSERR(base_addr);
5577 +       fp->fecpriv_stat.tx_fifo_errors = FECSTAT_IEEE_T_MACERR(base_addr);
5578 +       fp->fecpriv_stat.tx_window_errors = FECSTAT_IEEE_T_LCOL(base_addr);
5579 +
5580 +       // I hope that one frame doesn't have more than one error
5581 +       fp->fecpriv_stat.rx_errors = fp->fecpriv_stat.rx_length_errors + fp->fecpriv_stat.rx_crc_errors + fp->fecpriv_stat.rx_frame_errors + fp->fecpriv_stat.rx_over_errors + fp->fecpriv_stat.rx_dropped;
5582 +       fp->fecpriv_stat.tx_errors = fp->fecpriv_stat.tx_carrier_errors + fp->fecpriv_stat.tx_fifo_errors + fp->fecpriv_stat.tx_window_errors + fp->fecpriv_stat.tx_aborted_errors + fp->fecpriv_stat.tx_heartbeat_errors + fp->fecpriv_stat.tx_dropped;
5583 +
5584 +       return &fp->fecpriv_stat;
5585 +}
5586 +
5587 +/************************************************************************
5588 +* NAME: fec_set_multicast_list
5589 +*
5590 +* DESCRIPTION: This function sets the frame filtering parameters
5591 +*************************************************************************/
5592 +void fec_set_multicast_list(struct net_device *dev)
5593 +{
5594 +       // Pointer to the address list
5595 +       struct dev_mc_list *dmi;
5596 +
5597 +       unsigned int crc, data;
5598 +       int i, j, k;
5599 +
5600 +       // Receive the base address
5601 +       unsigned long base_addr = (unsigned long) dev->base_addr;
5602 +
5603 +       if (dev->flags & IFF_PROMISC || dev->flags & IFF_ALLMULTI)
5604 +       {
5605 +               // Allow all incoming frames
5606 +               FEC_GALR(base_addr) = 0xFFFFFFFF;
5607 +               FEC_GAUR(base_addr) = 0xFFFFFFFF;
5608 +               return;
5609 +       }
5610 +       // Reset the group address register
5611 +       FEC_GALR(base_addr) = 0x00000000;
5612 +       FEC_GAUR(base_addr) = 0x00000000;
5613 +
5614 +       // Process all addresses
5615 +       for (i = 0, dmi = dev->mc_list; i < dev->mc_count; i++, dmi = dmi->next)
5616 +       {
5617 +               // Processing must be only for the group addresses
5618 +               if (!(dmi->dmi_addr[0] & 1))
5619 +                       continue;
5620 +
5621 +               // Calculate crc value for the current address
5622 +               crc = 0xFFFFFFFF;
5623 +               for (j = 0; j < dmi->dmi_addrlen; j++)
5624 +               {
5625 +
5626 +                       for (k = 0, data = dmi->dmi_addr[j]; k < 8;  k++, data >>= 1)
5627 +                       {
5628 +                               if ((crc ^ data) & 1)
5629 +                                       crc = (crc >> 1) ^ FEC_CRCPOL;
5630 +                               else
5631 +                                       crc >>= 1;
5632 +
5633 +                       }
5634 +
5635 +               }
5636 +
5637 +               // Add this value
5638 +               crc >>= 26;
5639 +               crc &= 0x3F;
5640 +               if (crc > 31)
5641 +                       FEC_GAUR(base_addr) |= 0x1 << (crc - 32);
5642 +               else
5643 +                       FEC_GALR(base_addr) |= 0x1 << crc;
5644 +
5645 +       }
5646 +
5647 +}
5648 +
5649 +/************************************************************************
5650 +* NAME: fec_set_mac_address
5651 +*
5652 +* DESCRIPTION: This function sets the MAC address
5653 +*************************************************************************/
5654 +int fec_set_mac_address(struct net_device *dev, void *p)
5655 +{
5656 +       //Receive the pointer to the private structure
5657 +       struct fec_priv *fp = netdev_priv(dev);
5658 +
5659 +       // Receive the base address
5660 +       unsigned long base_addr = (unsigned long) dev->base_addr;
5661 +
5662 +       struct sockaddr *addr = p;
5663 +
5664 +       if (netif_running(dev))
5665 +               return -EBUSY;
5666 +
5667 +       // Copy a new address to the device structure
5668 +       memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5669 +
5670 +       // Copy a new address to the private structure
5671 +       memcpy(fp->fecpriv_mac_addr, addr->sa_data, 6);
5672 +
5673 +       // Set the address to the registers
5674 +       FEC_PALR(base_addr) = (fp->fecpriv_mac_addr[0] << 24) | (fp->fecpriv_mac_addr[1] << 16) | (fp->fecpriv_mac_addr[2] << 8) | fp->fecpriv_mac_addr[3];
5675 +       FEC_PAUR(base_addr) = (fp->fecpriv_mac_addr[4] << 24) | (fp->fecpriv_mac_addr[5] << 16) | 0x8808;
5676 +
5677 +       return 0;
5678 +}
5679 +
5680 +/************************************************************************
5681 +* NAME: fec_tx
5682 +*
5683 +* DESCRIPTION: This function starts transmission of the frame using DMA
5684 +*
5685 +* RETURNS: This function always returns zero.
5686 +*************************************************************************/
5687 +int fec_tx(struct sk_buff *skb, struct net_device *dev)
5688 +{
5689 +
5690 +       //Receive the pointer to the private structure
5691 +       struct fec_priv *fp = netdev_priv(dev);
5692 +
5693 +       void *data, *data_aligned;
5694 +       int offset;
5695 +
5696 +printk(KERN_INFO "fec_tx\n");
5697 +       data = kmalloc(skb->len + 15, GFP_DMA | GFP_ATOMIC);
5698 +
5699 +       if (!data)
5700 +       {
5701 +               fp->fecpriv_stat.tx_dropped++;
5702 +               dev_kfree_skb(skb);
5703 +               return 0;
5704 +       }
5705 +
5706 +       offset = (((unsigned long)virt_to_phys(data) + 15) & 0xFFFFFFF0) - (unsigned long)virt_to_phys(data);
5707 +       data_aligned = (void*)((unsigned long)data + offset);
5708 +       memcpy(data_aligned, skb->data, skb->len);
5709 +
5710 +       // flush data cache before initializing the descriptor and starting DMA
5711 +#if 0
5712 +/* JKM -- currently running with cache turned off */
5713 +       DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(data_aligned), skb->len);
5714 +#endif
5715 +
5716 +       spin_lock_irq(&fp->fecpriv_lock);
5717 +
5718 +       // Initialize the descriptor
5719 +       fp->fecpriv_txbuf[fp->fecpriv_next_tx] = data;
5720 +       fp->fecpriv_txdesc[fp->fecpriv_next_tx].dataPointer = (unsigned int) virt_to_phys(data_aligned);
5721 +       fp->fecpriv_txdesc[fp->fecpriv_next_tx].length = skb->len;
5722 +       fp->fecpriv_txdesc[fp->fecpriv_next_tx].statCtrl |= (MCD_FEC_END_FRAME | MCD_FEC_BUF_READY);
5723 +       fp->fecpriv_next_tx = (fp->fecpriv_next_tx + 1) & FEC_TX_INDEX_MASK;
5724 +
5725 +       if (fp->fecpriv_txbuf[fp->fecpriv_current_tx] && fp->fecpriv_current_tx == fp->fecpriv_next_tx)
5726 +               netif_stop_queue(dev);
5727 +
5728 +       spin_unlock_irq(&fp->fecpriv_lock);
5729 +
5730 +       // Tell the DMA to continue the transmission
5731 +       MCD_continDma(fp->fecpriv_fec_tx_channel);
5732 +
5733 +       dev_kfree_skb(skb);
5734 +
5735 +       dev->trans_start = jiffies;
5736 +
5737 +       return 0;
5738 +}
5739 +
5740 +/************************************************************************
5741 +* NAME: fec_tx_timeout
5742 +*
5743 +* DESCRIPTION: If the interrupt processing of received frames was lost
5744 +*              and DMA stopped the reception, this function clears
5745 +*              the transmission descriptors and starts DMA
5746 +*
5747 +*************************************************************************/
5748 +void fec_tx_timeout(struct net_device *dev)
5749 +{
5750 +       int i;
5751 +       struct fec_priv *fp = netdev_priv(dev);
5752 +       unsigned long base_addr = (unsigned long) dev->base_addr;
5753 +
5754 +printk(KERN_INFO "fec_tx_timeout\n");
5755 +       spin_lock_irq(&fp->fecpriv_lock);
5756 +       MCD_killDma(fp->fecpriv_fec_tx_channel);
5757 +       for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
5758 +       {
5759 +               if (fp->fecpriv_txbuf[i])
5760 +               {
5761 +
5762 +                       kfree(fp->fecpriv_txbuf[i]);
5763 +                       fp->fecpriv_txbuf[i] = NULL;
5764 +
5765 +               }
5766 +               fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
5767 +       }
5768 +       fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
5769 +
5770 +       fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
5771 +
5772 +    // Reset FIFOs
5773 +    FEC_FECFRST(base_addr) |= FEC_SW_RST;
5774 +    FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
5775 +
5776 +       // Reset and disable FEC
5777 +//     FEC_ECR(base_addr) = FEC_ECR_RESET;
5778 +
5779 +       // Enable FEC
5780 +       FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
5781 +
5782 +       MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
5783 +                    (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
5784 +                    FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
5785 +                    FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
5786 +                    MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
5787 +
5788 +       spin_unlock_irq(&fp->fecpriv_lock);
5789 +
5790 +       netif_wake_queue(dev);
5791 +
5792 +}
5793 +
5794 +/************************************************************************
5795 +* NAME: fec_read_mii
5796 +*
5797 +* DESCRIPTION: This function reads the value from the MII register
5798 +*
5799 +* RETURNS: If no error occurs, this function returns zero.
5800 +*************************************************************************/
5801 +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int *data)
5802 +{
5803 +       unsigned long time;
5804 +
5805 +       // Clear the MII interrupt bit
5806 +       FEC_EIR(base_addr) = FEC_EIR_MII;
5807 +
5808 +       // Write to the MII management frame register
5809 +       FEC_MMFR(base_addr) = FEC_MMFR_READ | (pa << 23) | (ra << 18);
5810 +
5811 +       time = jiffies;
5812 +
5813 +       // Wait for the reading
5814 +       while (!(FEC_EIR(base_addr) & FEC_EIR_MII))
5815 +       {
5816 +               if (jiffies - time > FEC_MII_TIMEOUT * HZ)
5817 +                       return -ETIME;
5818 +               schedule();
5819 +       }
5820 +
5821 +       // Clear the MII interrupt bit
5822 +       FEC_EIR(base_addr) = FEC_EIR_MII;
5823 +
5824 +       *data = FEC_MMFR(base_addr) & 0x0000FFFF;
5825 +
5826 +       return 0;
5827 +}
5828 +
5829 +/************************************************************************
5830 +* NAME: fec_write_mii
5831 +*
5832 +* DESCRIPTION: This function writes the value to the MII register
5833 +*
5834 +* RETURNS: If no error occurs, this function returns zero.
5835 +*************************************************************************/
5836 +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra, unsigned int data)
5837 +{
5838 +       unsigned long time;
5839 +
5840 +       // Clear the MII interrupt bit
5841 +       FEC_EIR(base_addr) = FEC_EIR_MII;
5842 +
5843 +       // Write to the MII management frame register
5844 +       FEC_MMFR(base_addr) = FEC_MMFR_WRITE | (pa << 23) | (ra << 18) | data;
5845 +
5846 +       time = jiffies;
5847 +
5848 +       // Wait for the writing
5849 +
5850 +       while (!(FEC_EIR(base_addr) & FEC_EIR_MII))
5851 +       {
5852 +               if (jiffies - time > FEC_MII_TIMEOUT * HZ)
5853 +                       return -ETIME;
5854 +
5855 +               schedule();
5856 +       }
5857 +
5858 +       // Clear the MII interrupt bit
5859 +       FEC_EIR(base_addr) = FEC_EIR_MII;
5860 +
5861 +       return 0;
5862 +}
5863 +
5864 +/************************************************************************
5865 +* NAME: fec_interrupt_tx_handler
5866 +*
5867 +* DESCRIPTION: This function is called when the data
5868 +*              transmission from the buffer to the FEC is completed.
5869 +*
5870 +*************************************************************************/
5871 +void fec_interrupt_fec_tx_handler(struct net_device *dev)
5872 +{
5873 +       struct fec_priv *fp = netdev_priv(dev);
5874 +
5875 +printk(KERN_INFO "fectxint\n");
5876 +       //Release the socket buffer
5877 +       if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
5878 +       {
5879 +               kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
5880 +               fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
5881 +       }
5882 +       fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK;
5883 +
5884 +       if (MCD_dmaStatus(fp->fecpriv_fec_tx_channel) == MCD_DONE)
5885 +               for (; fp->fecpriv_current_tx != fp->fecpriv_next_tx; fp->fecpriv_current_tx = (fp->fecpriv_current_tx + 1) & FEC_TX_INDEX_MASK)
5886 +               {
5887 +                       if(fp->fecpriv_txbuf[fp->fecpriv_current_tx])
5888 +                       {
5889 +                               kfree(fp->fecpriv_txbuf[fp->fecpriv_current_tx]);
5890 +                               fp->fecpriv_txbuf[fp->fecpriv_current_tx] = NULL;
5891 +                       }
5892 +               }
5893 +
5894 +       if (netif_queue_stopped(dev))
5895 +               netif_wake_queue(dev);
5896 +
5897 +}
5898 +
5899 +/************************************************************************
5900 +* NAME: fec_interrupt_rx_handler
5901 +*
5902 +* DESCRIPTION: This function is called when the data
5903 +*              reception from the FEC to the reception buffer is completed.
5904 +*
5905 +*************************************************************************/
5906 +void fec_interrupt_fec_rx_handler(struct net_device *dev)
5907 +{
5908 +       struct fec_priv *fp = netdev_priv(dev);
5909 +       struct sk_buff *skb;
5910 +
5911 +printk(KERN_INFO "fecrxint\n");
5912 +       fp->fecpriv_rxflag = 1;
5913 +/*
5914 +       // Some buffers can be missed
5915 +       if(!(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME))
5916 +       {
5917 +               // Find a valid index
5918 +               for(i = 0; i < FEC_RX_BUF_NUMBER && !(fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME); i++, fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK);
5919 +
5920 +               if(i == FEC_RX_BUF_NUMBER)
5921 +               {
5922 +                       // There are no data to process
5923 +                       // Tell the DMA to continue the reception
5924 +                       MCD_continDma(fp->fecpriv_fec_rx_channel);
5925 +
5926 +                       fp->fecpriv_rxflag = 0;
5927 +
5928 +                       return;
5929 +               }
5930 +       }
5931 +*/
5932 +       for (; fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl & MCD_FEC_END_FRAME; fp->fecpriv_current_rx = (fp->fecpriv_current_rx + 1) & FEC_RX_INDEX_MASK)
5933 +       {
5934 +           if( (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length <= FEC_MAXBUF_SIZE) &&
5935 +                   (fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length > 4)) // --tym--
5936 +           {
5937 +               skb = fp->askb_rx[fp->fecpriv_current_rx];
5938 +               if (!skb)
5939 +               {
5940 +                   fp->fecpriv_stat.rx_dropped++;
5941 +            }
5942 +               else
5943 +               {
5944 +                   // flush data cache before initializing the descriptor and starting DMA
5945 +//                 DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), fp->askb_rx[fp->fecpriv_current_rx]->len);
5946 +
5947 +                       skb_put(skb, fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length - 4);
5948 +//                     skb->dev = dev;
5949 +                       skb->protocol = eth_type_trans(skb, dev);
5950 +                       netif_rx(skb);
5951 +               }
5952 +                   fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl &= ~MCD_FEC_END_FRAME;
5953 +               // allocate new skbuff
5954 +               fp->askb_rx[fp->fecpriv_current_rx] = alloc_skb(FEC_MAXBUF_SIZE + 16, /*GFP_ATOMIC |*/ GFP_DMA);
5955 +                   if (!fp->askb_rx[fp->fecpriv_current_rx])
5956 +           {
5957 +                       fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = 0;
5958 +                   fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = 0;
5959 +                   fp->fecpriv_stat.rx_dropped++;
5960 +                   }
5961 +               else
5962 +               {
5963 +                   skb_reserve(fp->askb_rx[fp->fecpriv_current_rx], 16);
5964 +                       fp->askb_rx[fp->fecpriv_current_rx]->dev = dev;
5965 +
5966 +                   // flush data cache before initializing the descriptor and starting DMA
5967 +#if 0
5968 +/* JKM -- currently running with cache turned off */
5969 +                   DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
5970 +#endif
5971 +
5972 +               fp->fecpriv_rxdesc[fp->fecpriv_current_rx].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail);
5973 +               fp->fecpriv_rxdesc[fp->fecpriv_current_rx].length = FEC_MAXBUF_SIZE;
5974 +                       fp->fecpriv_rxdesc[fp->fecpriv_current_rx].statCtrl |= MCD_FEC_BUF_READY;
5975 +
5976 +                   // flush data cache before initializing the descriptor and starting DMA
5977 +//                 DcacheFlushInvalidateCacheBlock((void*)virt_to_phys(fp->askb_rx[fp->fecpriv_current_rx]->tail), FEC_MAXBUF_SIZE);
5978 +           }
5979 +        }
5980 +
5981 +       }
5982 +
5983 +       // Tell the DMA to continue the reception
5984 +       MCD_continDma(fp->fecpriv_fec_rx_channel);
5985 +
5986 +       fp->fecpriv_rxflag = 0;
5987 +
5988 +}
5989 +
5990 +/************************************************************************
5991 +* NAME: fec_interrupt_handler
5992 +*
5993 +* DESCRIPTION: This function is called when some special errors occur
5994 +*
5995 +*************************************************************************/
5996 +irqreturn_t fec_interrupt_handler(int irq, void *dev_id)
5997 +{
5998 +
5999 +       struct net_device *dev = (struct net_device *)dev_id;
6000 +       struct fec_priv *fp = netdev_priv(dev);
6001 +       unsigned long base_addr = (unsigned long) dev->base_addr;
6002 +       unsigned long events;
6003 +
6004 +printk(KERN_INFO "fecerrint\n");
6005 +       // Read and clear the events
6006 +       events = FEC_EIR(base_addr) & FEC_EIMR(base_addr);
6007 +
6008 +       if (events & FEC_EIR_HBERR)
6009 +       {
6010 +               fp->fecpriv_stat.tx_heartbeat_errors++;
6011 +       FEC_EIR(base_addr) = FEC_EIR_HBERR;
6012 +       }
6013 +
6014 +    // receive/transmit FIFO error
6015 +    if (((events & FEC_EIR_RFERR) != 0) || ((events & FEC_EIR_XFERR) != 0))
6016 +    {
6017 +        // kill DMA receive channel
6018 +        MCD_killDma (fp->fecpriv_fec_rx_channel);
6019 +        // kill running transmission by DMA
6020 +        MCD_killDma (fp->fecpriv_fec_tx_channel);
6021 +
6022 +        // Reset FIFOs
6023 +        FEC_FECFRST(base_addr) |= FEC_SW_RST;
6024 +        FEC_FECFRST(base_addr) &= ~FEC_SW_RST;
6025 +
6026 +        // reset receive FIFO status register
6027 +        FEC_FECRFSR(base_addr) = FEC_FECRFSR_FAE
6028 +                                 | FEC_FECRFSR_RXW
6029 +                                 | FEC_FECRFSR_UF;
6030 +
6031 +        // reset transmit FIFO status register
6032 +        FEC_FECTFSR(base_addr) = FEC_FECTFSR_FAE
6033 +                                 | FEC_FECTFSR_TXW
6034 +                                 | FEC_FECTFSR_UF
6035 +                                 | FEC_FECTFSR_OF;
6036 +
6037 +        // reset RFERR and XFERR event
6038 +        FEC_EIR(base_addr) = FEC_EIR_RFERR | FEC_EIR_XFERR;
6039 +
6040 +       // stop queue
6041 +       netif_stop_queue(dev);
6042 +
6043 +        // execute reinitialization as tasklet
6044 +       tasklet_schedule(&fp->fecpriv_tasklet_reinit);
6045 +
6046 +        fp->fecpriv_stat.rx_dropped++;
6047 +
6048 +    }
6049 +
6050 +    // transmit FIFO underrun
6051 +    if ((events & FEC_EIR_XFUN) != 0)
6052 +    {
6053 +        // reset XFUN event
6054 +        FEC_EIR(base_addr) = FEC_EIR_XFUN;
6055 +               fp->fecpriv_stat.tx_aborted_errors++;
6056 +    }
6057 +
6058 +    // late collision
6059 +    if ((events & FEC_EIR_LC) != 0)
6060 +    {
6061 +        // reset LC event
6062 +        FEC_EIR(base_addr) = FEC_EIR_LC;
6063 +               fp->fecpriv_stat.tx_aborted_errors++;
6064 +    }
6065 +
6066 +    // collision retry limit
6067 +    if ((events & FEC_EIR_RL) != 0)
6068 +    {
6069 +        // reset RL event
6070 +        FEC_EIR(base_addr) = FEC_EIR_RL;
6071 +               fp->fecpriv_stat.tx_aborted_errors++;
6072 +    }
6073 +
6074 +    return 0;
6075 +}
6076 +
6077 +/************************************************************************
6078 +* NAME: fec_interrupt_reinit
6079 +*
6080 +* DESCRIPTION: This function is called from interrupt handler
6081 +*              when controller must be reinitialized.
6082 +*
6083 +*************************************************************************/
6084 +void fec_interrupt_fec_reinit(unsigned long data)
6085 +{
6086 +       int i;
6087 +       struct net_device *dev = (struct net_device*)data;
6088 +       struct fec_priv *fp = netdev_priv(dev);
6089 +       unsigned long base_addr = (unsigned long) dev->base_addr;
6090 +
6091 +printk(KERN_INFO "fecreinit\n");
6092 +       // Initialize reception descriptors and start DMA for the reception
6093 +       for (i = 0; i < FEC_RX_BUF_NUMBER; i++)
6094 +       {
6095 +               if (!fp->askb_rx[i])
6096 +               {
6097 +               fp->askb_rx[i] = alloc_skb(FEC_MAXBUF_SIZE + 16, GFP_ATOMIC | GFP_DMA);
6098 +               if (!fp->askb_rx[i])
6099 +                   {
6100 +                       fp->fecpriv_rxdesc[i].dataPointer = 0;
6101 +                       fp->fecpriv_rxdesc[i].statCtrl = 0;
6102 +               fp->fecpriv_rxdesc[i].length = 0;
6103 +               continue;
6104 +               }
6105 +                       fp->askb_rx[i]->dev = dev;
6106 +           skb_reserve(fp->askb_rx[i], 16);
6107 +           }
6108 +           fp->fecpriv_rxdesc[i].dataPointer = (unsigned int) virt_to_phys(fp->askb_rx[i]->tail);
6109 +               fp->fecpriv_rxdesc[i].statCtrl = MCD_FEC_BUF_READY | MCD_FEC_INTERRUPT;
6110 +       fp->fecpriv_rxdesc[i].length = FEC_MAXBUF_SIZE;
6111 +       }
6112 +
6113 +       fp->fecpriv_rxdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
6114 +       fp->fecpriv_current_rx = 0;
6115 +
6116 +    // restart frame transmission
6117 +       for (i = 0; i < FEC_TX_BUF_NUMBER; i++)
6118 +       {
6119 +               if (fp->fecpriv_txbuf[i])
6120 +               {
6121 +
6122 +                       kfree(fp->fecpriv_txbuf[i]);
6123 +                       fp->fecpriv_txbuf[i] = NULL;
6124 +               fp->fecpriv_stat.tx_dropped++;
6125 +               }
6126 +               fp->fecpriv_txdesc[i].statCtrl = MCD_FEC_INTERRUPT;
6127 +       }
6128 +       fp->fecpriv_txdesc[i - 1].statCtrl |= MCD_FEC_WRAP;
6129 +       fp->fecpriv_current_tx = fp->fecpriv_next_tx = 0;
6130 +
6131 +       // flush entire data cache before restarting the DMA
6132 +#if 0
6133 +/* JKM -- currently running with cache turned off */
6134 +       DcacheFlushInvalidate();
6135 +#endif
6136 +
6137 +    // restart DMA from beginning
6138 +       MCD_startDma(fp->fecpriv_fec_rx_channel,
6139 +                    (char *) fp->fecpriv_rxdesc, 0,
6140 +                    (unsigned char *) &(FEC_FECRFDR(base_addr)), 0,
6141 +                    FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_rx,
6142 +                    FEC_RX_DMA_PRI, MCD_FECRX_DMA | MCD_INTERRUPT,
6143 +                    MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
6144 +
6145 +       MCD_startDma(fp->fecpriv_fec_tx_channel, (char *) fp->fecpriv_txdesc, 0,
6146 +                    (unsigned char *) &(FEC_FECTFDR(base_addr)), 0,
6147 +                    FEC_MAX_FRM_SIZE, 0, fp->fecpriv_initiator_tx,
6148 +                    FEC_TX_DMA_PRI, MCD_FECTX_DMA | MCD_INTERRUPT,
6149 +                    MCD_NO_CSUM | MCD_NO_BYTE_SWAP);
6150 +
6151 +    // Enable FEC
6152 +    FEC_ECR(base_addr) |= FEC_ECR_ETHEREN;
6153 +
6154 +       netif_wake_queue(dev);
6155 +
6156 +}
6157 +
6158 +/************************************************************************
6159 +* NAME: fec_interrupt_tx_handler_fec0
6160 +*
6161 +* DESCRIPTION: This is the DMA interrupt handler using  for FEC0
6162 +*              transmission.
6163 +*
6164 +*************************************************************************/
6165 +void fec_interrupt_fec_tx_handler_fec0(void)
6166 +{
6167 +       fec_interrupt_fec_tx_handler(fec_dev[0]);
6168 +}
6169 +
6170 +#ifdef   FEC_2
6171 +/************************************************************************
6172 +* NAME: fec_interrupt_tx_handler_fec1
6173 +*
6174 +* DESCRIPTION: This is the DMA interrupt handler using for the FEC1
6175 +*              transmission.
6176 +*
6177 +*************************************************************************/
6178 +void fec_interrupt_fec_tx_handler_fec1(void)
6179 +{
6180 +       fec_interrupt_fec_tx_handler(fec_dev[1]);
6181 +}
6182 +#endif
6183 +
6184 +/************************************************************************
6185 +* NAME: fec_interrupt_rx_handler_fec0
6186 +*
6187 +* DESCRIPTION: This is the DMA interrupt handler using for the FEC0
6188 +*              reception.
6189 +*
6190 +*************************************************************************/
6191 +void fec_interrupt_fec_rx_handler_fec0(void)
6192 +{
6193 +       fec_interrupt_fec_rx_handler(fec_dev[0]);
6194 +}
6195 +
6196 +#ifdef   FEC_2
6197 +/************************************************************************
6198 +* NAME: fec_interrupt_rx_handler_fec1
6199 +*
6200 +* DESCRIPTION: This is the DMA interrupt handler using for the FEC1
6201 +*              reception.
6202 +*
6203 +*************************************************************************/
6204 +void fec_interrupt_fec_rx_handler_fec1(void)
6205 +{
6206 +       fec_interrupt_fec_rx_handler(fec_dev[1]);
6207 +}
6208 +
6209 +#endif
6210 +#ifndef MODULE
6211 +
6212 +/************************************************************************
6213 +* NAME: fec_mac_setup0
6214 +*
6215 +* DESCRIPTION: This function sets the MAC address of FEC0 from command line
6216 +*
6217 +*************************************************************************/
6218 +int __init fec_mac_setup0(char *s)
6219 +{
6220 +       if(!s || !*s)
6221 +               return 1;
6222 +
6223 +       if(fec_str_to_mac(s, fec_mac_addr_fec0))
6224 +               printk("The MAC address of FEC0 cannot be set from command line");
6225 +       return 1;
6226 +
6227 +}
6228 +
6229 +#ifdef   FEC_2
6230 +
6231 +/************************************************************************
6232 +* NAME: fec_mac_setup1
6233 +*
6234 +* DESCRIPTION: This function sets the MAC address of FEC1 from command line
6235 +*
6236 +*************************************************************************/
6237 +int __init fec_mac_setup1(char *s)
6238 +{
6239 +       if(!s || !*s)
6240 +               return 1;
6241 +
6242 +
6243 +       if(fec_str_to_mac(s, fec_mac_addr_fec1))
6244 +               printk("The MAC address of FEC1 cannot be set from command line");
6245 +       return 1;
6246 +
6247 +}
6248 +#endif
6249 +
6250 +/************************************************************************
6251 +* NAME: fec_str_to_mac
6252 +*
6253 +* DESCRIPTION: This function interprets the character string into MAC addr
6254 +*
6255 +*************************************************************************/
6256 +int fec_str_to_mac( char *str_mac, unsigned char* addr)
6257 +{
6258 +    unsigned long val;
6259 +       char c;
6260 +       unsigned long octet[6], *octetptr = octet;
6261 +       int i;
6262 +again:
6263 +
6264 +       val = 0;
6265 +       while ((c = *str_mac) != '\0')
6266 +       {
6267 +               if ((c>='0')&&(c<='9'))
6268 +               {
6269 +                       val = (val * 16) + (c - '0');
6270 +                       str_mac++;
6271 +                       continue;
6272 +               }
6273 +               else
6274 +               if (((c>='a')&&(c<='f'))||((c>='A')&&(c<='F')))
6275 +               {
6276 +                       val = (val << 4) + (c + 10 - (((c>='a')&&(c<='f')) ? 'a' : 'A'));
6277 +                       str_mac++;
6278 +                       continue;
6279 +               }
6280 +               break;
6281 +       }
6282 +       if (*str_mac == ':')
6283 +       {
6284 +               *octetptr++ = val, str_mac++;
6285 +               if (octetptr >= octet + 6)
6286 +                       return 1;
6287 +               goto again;
6288 +       }
6289 +
6290 +        //Check for trailing characters.
6291 +       if (*str_mac && !(*str_mac==' '))
6292 +               return 1;
6293 +       *octetptr++ = val;
6294 +
6295 +       if ((octetptr - octet)==6)
6296 +       {
6297 +          for(i=0;i<=6;i++)
6298 +             addr[i]=octet[i];
6299 +       }
6300 +    else
6301 +               return 1;
6302 +
6303 +       return 0;
6304 +
6305 +}
6306 +#endif
6307 --- /dev/null
6308 +++ b/drivers/net/fec/fec.h
6309 @@ -0,0 +1,162 @@
6310 +
6311 +#define   FEC_BASE_ADDR_FEC0                ((unsigned int)MCF_MBAR + 0x9000)
6312 +#define   FEC_BASE_ADDR_FEC1                ((unsigned int)MCF_MBAR + 0x9800)
6313 +
6314 +//#define   FEC_INTC_IMRH_INT_MASK38          (0x00000040)
6315 +//#define   FEC_INTC_IMRH_INT_MASK39          (0x00000080)
6316 +//#define   FEC_INTC_ICR_FEC0                 (0x30)
6317 +//#define   FEC_INTC_ICR_FEC1                 (0x31)
6318 +#define   FEC_FECI2CIRQ                     (0xFFC0)
6319 +#define   FEC_GPIO_PAR_FECI2CIRQ            *(volatile unsigned short*)((unsigned int)MCF_MBAR + 0xA44)
6320 +//#define   FEC_INTC_ICRn(x)                  (*(volatile unsigned char *)(void*)((unsigned int) MCF_MBAR + 0x000740+((x)*0x001)))
6321 +//#define   FEC_INTC_IMRH                     *(volatile unsigned int*)((unsigned int)MCF_MBAR + 0x000708)
6322 +
6323 +#define   FEC_ECR_DISABLE                   (0x00000000)
6324 +
6325 +#define   FEC_ECR(x)                        *(volatile unsigned int *)(x + 0x024)
6326 +#define   FEC_EIR(x)                        *(volatile unsigned int*)(x + 0x004)
6327 +#define   FEC_PALR(x)                       *(volatile unsigned int*)(x + 0x0E4)
6328 +#define   FEC_PAUR(x)                       *(volatile unsigned int*)(x + 0x0E8)
6329 +#define   FEC_IALR(x)                       *(volatile unsigned int*)(x + 0x11C)
6330 +#define   FEC_IAUR(x)                       *(volatile unsigned int*)(x + 0x118)
6331 +#define   FEC_GALR(x)                       *(volatile unsigned int*)(x + 0x124)
6332 +#define   FEC_GAUR(x)                       *(volatile unsigned int*)(x + 0x120)
6333 +#define   FEC_RCR(x)                        *(volatile unsigned int*)(x + 0x084)
6334 +#define   FEC_FECRFCR(x)                    *(volatile unsigned int*)(x + 0x18C)
6335 +#define   FEC_FECRFAR(x)                    *(volatile unsigned int*)(x + 0x198)
6336 +#define   FEC_FECTFCR(x)                    *(volatile unsigned int*)(x + 0x1AC)
6337 +#define   FEC_FECTFAR(x)                    *(volatile unsigned int*)(x + 0x1B8)
6338 +#define   FEC_FECTFWR(x)                    *(volatile unsigned int*)(x + 0x144)
6339 +#define   FEC_CTCWR(x)                      *(volatile unsigned int*)(x + 0x1C8)
6340 +#define   FEC_EIMR(x)                       *(volatile unsigned int*)(x + 0x008)
6341 +#define   FEC_TCR(x)                        *(volatile unsigned int*)(x + 0x0C4)
6342 +#define   FEC_MIBC(x)                       *(volatile unsigned int*)(x + 0x064)
6343 +#define   FEC_MSCR(x)                       *(volatile unsigned int*)(x + 0x044)
6344 +#define   FEC_FECTFDR(x)                    *(volatile unsigned int*)(x + 0x1A4)
6345 +#define   FEC_FECRFDR(x)                    *(volatile unsigned int*)(x + 0x184)
6346 +#define   FEC_FECTFSR(x)                    *(volatile unsigned int*)(x + 0x1A8)
6347 +#define   FEC_FECRFSR(x)                                       *(volatile unsigned int*)(x + 0x188)
6348 +#define   FECSTAT_RMON_R_PACKETS(x)         *(volatile unsigned int*)(x + 0x284)
6349 +#define   FECSTAT_RMON_T_PACKETS(x)         *(volatile unsigned int*)(x + 0x204)
6350 +#define   FECSTAT_RMON_R_OCTETS(x)          *(volatile unsigned int*)(x + 0x2C4)
6351 +#define   FECSTAT_RMON_T_OCTETS(x)          *(volatile unsigned int*)(x + 0x244)
6352 +#define   FECSTAT_RMON_R_UNDERSIZE(x)       *(volatile unsigned int*)(x + 0x294)
6353 +#define   FECSTAT_RMON_R_OVERSIZE(x)        *(volatile unsigned int*)(x + 0x298)
6354 +#define   FECSTAT_RMON_R_FRAG(x)            *(volatile unsigned int*)(x + 0x29C)
6355 +#define   FECSTAT_RMON_R_JAB(x)             *(volatile unsigned int*)(x + 0x2A0)
6356 +#define   FECSTAT_RMON_R_MC_PKT(x)          *(volatile unsigned int*)(x + 0x28C)
6357 +#define   FECSTAT_RMON_T_COL(x)             *(volatile unsigned int*)(x + 0x224)
6358 +#define   FECSTAT_IEEE_R_ALIGN(x)           *(volatile unsigned int*)(x + 0x2D4)
6359 +#define   FECSTAT_IEEE_R_CRC(x)             *(volatile unsigned int*)(x + 0x2D0)
6360 +#define   FECSTAT_IEEE_R_MACERR(x)          *(volatile unsigned int*)(x + 0x2D8)
6361 +#define   FECSTAT_IEEE_T_CSERR(x)           *(volatile unsigned int*)(x + 0x268)
6362 +#define   FECSTAT_IEEE_T_MACERR(x)          *(volatile unsigned int*)(x + 0x264)
6363 +#define   FECSTAT_IEEE_T_LCOL(x)            *(volatile unsigned int*)(x + 0x25C)
6364 +#define   FECSTAT_IEEE_R_OCTETS_OK(x)       *(volatile unsigned int*)(x + 0x2E0)
6365 +#define   FECSTAT_IEEE_T_OCTETS_OK(x)       *(volatile unsigned int*)(x + 0x274)
6366 +#define   FECSTAT_IEEE_R_DROP(x)            *(volatile unsigned int*)(x + 0x2C8)
6367 +#define   FECSTAT_IEEE_T_DROP(x)            *(volatile unsigned int*)(x + 0x248)
6368 +#define   FECSTAT_IEEE_R_FRAME_OK(x)        *(volatile unsigned int*)(x + 0x2CC)
6369 +#define   FECSTAT_IEEE_T_FRAME_OK(x)        *(volatile unsigned int*)(x + 0x24C)
6370 +#define   FEC_MMFR(x)                       *(volatile unsigned int*)(x + 0x040)
6371 +#define   FEC_FECFRST(x)                                       *(volatile unsigned int*)(x + 0x1C4)
6372 +
6373 +#define   FEC_MAX_FRM_SIZE                  (1518)
6374 +#define   FEC_MAXBUF_SIZE                   (1520)
6375 +
6376 +// Register values
6377 +#define   FEC_ECR_RESET                     (0x00000001)
6378 +#define   FEC_EIR_CLEAR                     (0xFFFFFFFF)
6379 +#define   FEC_EIR_RL                        (0x00100000)
6380 +#define   FEC_EIR_HBERR                     (0x80000000)
6381 +#define   FEC_EIR_BABR                                         (0x40000000)   // babbling receive error
6382 +#define   FEC_EIR_BABT                                         (0x20000000)   // babbling transmit error
6383 +#define   FEC_EIR_TXF                          (0x08000000)   // transmit frame interrupt
6384 +#define   FEC_EIR_MII                                          (0x00800000)   // MII interrupt
6385 +#define   FEC_EIR_LC                                           (0x00200000)   // late collision
6386 +#define   FEC_EIR_XFUN                                         (0x00080000)   // transmit FIFO underrun
6387 +#define   FEC_EIR_XFERR                                                (0x00040000)   // transmit FIFO error
6388 +#define   FEC_EIR_RFERR                                                (0x00020000)   // receive FIFO error
6389 +#define   FEC_RCR_MAX_FRM_SIZE              (FEC_MAX_FRM_SIZE << 16)
6390 +#define   FEC_RCR_MII                       (0x00000004)
6391 +#define   FEC_FECRFCR_FAE                                      (0x00400000)   // frame accept error
6392 +#define   FEC_FECRFCR_RXW                                      (0x00200000)   // receive wait condition
6393 +#define   FEC_FECRFCR_UF                                       (0x00100000)   // receive FIFO underflow
6394 +#define   FEC_FECRFCR_FRM                   (0x08000000)
6395 +#define   FEC_FECRFCR_GR                    (0x7 << 24)
6396 +
6397 +#define   FEC_EIMR_DISABLE                                     (0x00000000)
6398 +
6399 +#define   FEC_FECRFAR_ALARM                 (0x300)
6400 +#define   FEC_FECTFCR_FRM                   (0x08000000)
6401 +#define   FEC_FECTFCR_GR                    (0x7 << 24)
6402 +#define   FEC_FECTFCR_FAE                                      (0x00400000)   // frame accept error
6403 +#define   FEC_FECTFCR_TXW                                      (0x00040000)   // transmit wait condition
6404 +#define   FEC_FECTFCR_UF                                       (0x00100000)   // transmit FIFO underflow
6405 +#define   FEC_FECTFCR_OF                                       (0x00080000)   // transmit FIFO overflow
6406 +
6407 +#define   FEC_FECTFAR_ALARM                 (0x100)
6408 +#define   FEC_FECTFWR_XWMRK                 (0x00000000)
6409 +
6410 +#define   FEC_FECTFSR_MSK                   (0xC0B00000)
6411 +#define   FEC_FECTFSR_TXW                   (0x40000000)   // transmit wait condition
6412 +#define   FEC_FECTFSR_FAE                   (0x00800000)   // frame accept error
6413 +#define   FEC_FECTFSR_UF                    (0x00200000)   // transmit FIFO underflow
6414 +#define   FEC_FECTFSR_OF                    (0x00100000)   // transmit FIFO overflow
6415 +
6416 +#define   FEC_FECRFSR_MSK                   (0x80F00000)
6417 +#define   FEC_FECRFSR_FAE                   (0x00800000)   // frame accept error
6418 +#define   FEC_FECRFSR_RXW                   (0x00400000)   // receive wait condition
6419 +#define   FEC_FECRFSR_UF                    (0x00200000)   // receive FIFO underflow
6420 +
6421 +#define   FEC_CTCWR_TFCW_CRC                (0x03000000)
6422 +#define   FEC_TCR_FDEN                      (0x00000004)
6423 +#define   FEC_TCR_HBC                       (0x00000002)
6424 +#define   FEC_RCR_DRT                       (0x00000002)
6425 +#define   FEC_EIMR_MASK                     (FEC_EIR_RL | FEC_EIR_HBERR)
6426 +#define   FEC_ECR_ETHEREN                   (0x00000002)
6427 +#define   FEC_FECTFCR_MSK                   (0x00FC0000)
6428 +#define   FEC_FECRFCR_MSK                   (0x00F80000)
6429 +#define   FEC_EIR_GRA                       (0x10000000)
6430 +#define   FEC_TCR_GTS                       (0x00000001)
6431 +#define   FEC_MIBC_ENABLE                   (0x00000000)
6432 +#define   FEC_MIB_LEN                       (228)
6433 +#define   FEC_PHY_ADDR                      (0x01)
6434 +
6435 +#define FEC_RX_DMA_PRI                      (6)
6436 +#define FEC_TX_DMA_PRI                      (6)
6437 +
6438 +#define   FEC_TX_BUF_NUMBER                 (8)
6439 +#define   FEC_RX_BUF_NUMBER                 (64)
6440 +
6441 +#define   FEC_TX_INDEX_MASK                 (0x7)
6442 +#define   FEC_RX_INDEX_MASK                 (0x3f)
6443 +
6444 +#define   FEC_RX_DESC_FEC0                  SYS_SRAM_FEC_START
6445 +#define   FEC_TX_DESC_FEC0                  FEC_RX_DESC_FEC0 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)
6446 +
6447 +#define   FEC_RX_DESC_FEC1                  SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE/2
6448 +#define   FEC_TX_DESC_FEC1                  FEC_RX_DESC_FEC1 + FEC_RX_BUF_NUMBER * sizeof(MCD_bufDescFec)
6449 +
6450 +#define   FEC_EIR_MII                       (0x00800000)
6451 +#define   FEC_MMFR_READ                     (0x60020000)
6452 +#define   FEC_MMFR_WRITE                    (0x50020000)
6453 +
6454 +#define   FEC_FLAGS_RX                      (0x00000001)
6455 +
6456 +#define   FEC_CRCPOL                        (0xEDB88320)
6457 +
6458 +#define   FEC_MII_TIMEOUT                   (2)
6459 +#define   FEC_GR_TIMEOUT                    (1)
6460 +#define   FEC_TX_TIMEOUT                    (1)
6461 +#define   FEC_RX_TIMEOUT                    (1)
6462 +
6463 +#define   FEC_SW_RST                        0x2000000
6464 +#define   FEC_RST_CTL                       0x1000000
6465 +
6466 +int fec_read_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
6467 +                unsigned int *data);
6468 +int fec_write_mii(unsigned int base_addr, unsigned int pa, unsigned int ra,
6469 +                 unsigned int data);
6470 +
6471 +#define init_transceiver ks8721_init_transceiver
6472 --- /dev/null
6473 +++ b/drivers/net/fec/ks8721.c
6474 @@ -0,0 +1,125 @@
6475 +#include <linux/module.h>
6476 +#include <linux/kernel.h>
6477 +#include <linux/string.h>
6478 +#include <linux/ptrace.h>
6479 +#include <linux/errno.h>
6480 +#include <linux/ioport.h>
6481 +#include <linux/slab.h>
6482 +#include <linux/interrupt.h>
6483 +#include <linux/pci.h>
6484 +#include <linux/init.h>
6485 +#include <linux/delay.h>
6486 +#include <linux/netdevice.h>
6487 +#include <linux/etherdevice.h>
6488 +#include <linux/skbuff.h>
6489 +#include <linux/spinlock.h>
6490 +#include <linux/workqueue.h>
6491 +#include <linux/bitops.h>
6492 +
6493 +#if 0
6494 +#include <linux/config.h>
6495 +#include <linux/sched.h>
6496 +#include <linux/errno.h>
6497 +#include <asm/coldfire.h>
6498 +#endif
6499 +#include <asm/coldfire.h>
6500 +#include <asm/mcfsim.h>
6501 +
6502 +#include   "fec.h"
6503 +#include   "ks8721.h"
6504 +
6505 +#ifdef   CONFIG_FEC_548x_AUTO_NEGOTIATION
6506 +#define   KS8721_AUTO_NEGOTIATION_ENABLE
6507 +#endif
6508 +
6509 +/************************************************************************
6510 +* +NAME: ks8721_init_transceiver
6511 +*
6512 +* DESCRIPTION: This function initializes the transceiver
6513 +*
6514 +* RETURNS: If no error occurs, this function returns zero.
6515 +*          Otherwise, it returns 1
6516 +*************************************************************************/
6517 +
6518 +int ks8721_init_transceiver(unsigned long base_addr, int *fduplex)
6519 +{
6520 +
6521 +       int data;
6522 +       unsigned long time;
6523 +       int flag = 1;
6524 +
6525 +       int result;
6526 +
6527 +       // Set the frequency of MII
6528 +       FEC_MSCR(base_addr) = FEC_MII_SPEED;
6529 +
6530 +       // Reset
6531 +       if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, KS8721_CTRL_RESET)))
6532 +               return result;
6533 +
6534 +       // Read back
6535 +       if ((result = fec_read_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, &data)) != 0)
6536 +               return result;
6537 +
6538 +       // If reset bit is set, return
6539 +       if (data & KS8721_CTRL_RESET)
6540 +               return -ETIME;
6541 +
6542 +#ifdef KS8721_AUTO_NEGOTIATION_ENABLE
6543 +
6544 +       // Disable  the auto-negotiation
6545 +       if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, 0)) != 0)
6546 +               return result;
6547 +
6548 +       // Set the auto-negotiation advertisement register
6549 +       if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_ANADV, KS8721_ANADV_ADV_ALL)) != 0)
6550 +               return result;
6551 +
6552 +       // Enable the auto-negotiation
6553 +       if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, KS8721_CTRL_AN_ENABLE)) != 0)
6554 +               return result;
6555 +
6556 +       // Read PHY status register
6557 +       if ((result = fec_read_mii(base_addr, FEC_PHY_ADDR, KS8721_STAT, &data)) != 0)
6558 +               return result;
6559 +       // Set the current time
6560 +       time = jiffies;
6561 +
6562 +       // Wait for the auto-negotiation completion
6563 +       while (!(data & KS8721_STAT_ANCOMPLETE))
6564 +       {
6565 +
6566 +               if (jiffies - time > KS8721_TIMEOUT * HZ)
6567 +               {
6568 +                       flag = 0;
6569 +                       break;
6570 +               }
6571 +
6572 +               schedule();
6573 +
6574 +               // Read PHY status register
6575 +               if ((result = fec_read_mii(base_addr, FEC_PHY_ADDR, KS8721_STAT, &data)) != 0)
6576 +                       return result;
6577 +       }
6578 +
6579 +       if (flag)
6580 +       {
6581 +               // Set the duplex flag
6582 +               if (data & KS8721_STAT_FDUPLEX)
6583 +                       *fduplex = 1;
6584 +               else
6585 +                       *fduplex = 0;
6586 +
6587 +               return 0;
6588 +       }
6589 +
6590 +#endif
6591 +
6592 +       // Set the default mode (Full duplex, 100 Mbps)
6593 +       if ((result = fec_write_mii(base_addr, FEC_PHY_ADDR, KS8721_CTRL, KS8721_CTRL_DEFAULT_MODE)) != 0)
6594 +               return result;
6595 +       *fduplex = KS8721_CTRL_DEFAULT_MODE & 0x100;
6596 +
6597 +       return 0;
6598 +
6599 +}
6600 --- /dev/null
6601 +++ b/drivers/net/fec/ks8721.h
6602 @@ -0,0 +1,21 @@
6603 +
6604 +#define   FEC_MII_SPEED              (((unsigned int)(MCF_BUSCLK / 5000000)) << 1)
6605 +
6606 +// Numbers of the transceiver registers
6607 +#define   KS8721_CTRL                0x00
6608 +#define   KS8721_ANADV               0x04
6609 +#define   KS8721_STAT                0x01
6610 +
6611 +// Register values
6612 +#define   KS8721_CTRL_RESET          0x8000
6613 +#define   KS8721_ANADV_ADV_ALL       0x01E1
6614 +#define   KS8721_CTRL_AN_ENABLE      0x1280
6615 +#define   KS8721_CTRL_DEFAULT_MODE   0x2100
6616 +#define   KS8721_STAT_ANCOMPLETE     0x0020
6617 +#define   KS8721_STAT_LINK           0x0004
6618 +#define   KS8721_STAT_FDUPLEX        0x5000
6619 +
6620 +// Timeout for the auto-negotiation mode
6621 +#define   KS8721_TIMEOUT             5
6622 +
6623 +int ks8721_init_transceiver(unsigned long base_addr, int *fduplex);
6624 --- /dev/null
6625 +++ b/include/asm-m68k/MCD_dma.h
6626 @@ -0,0 +1,408 @@
6627 +/*********************************************************************
6628 + *
6629 + * Copyright (C) 2004  Motorola, Inc.
6630 + *  MOTOROLA, INC. All Rights Reserved.
6631 + *  You are hereby granted a copyright license to use
6632 + *  the SOFTWARE so long as this entire notice is
6633 + *  retained without alteration in any modified and/or redistributed
6634 + *  versions, and that such modified versions are clearly identified
6635 + *  as such. No licenses are granted by implication, estoppel or
6636 + *  otherwise under any patents or trademarks of Motorola, Inc. This
6637 + *  software is provided on an "AS IS" basis and without warranty.
6638 + *
6639 + *  To the maximum extent permitted by applicable law, MOTOROLA
6640 + *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
6641 + *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
6642 + *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
6643 + *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
6644 + *  ACCOMPANYING WRITTEN MATERIALS.
6645 + *
6646 + *  To the maximum extent permitted by applicable law, IN NO EVENT
6647 + *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
6648 + *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
6649 + *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
6650 + *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
6651 + *
6652 + *  Motorola assumes no responsibility for the maintenance and support
6653 + *  of this software
6654 + ********************************************************************/
6655 +
6656 +/*
6657 + * File:        MCD_dma.h
6658 + * Purpose:     Main header file for multi-channel DMA API.
6659 + *
6660 + * Notes:
6661 + *
6662 + * Modifications:
6663 + */
6664 +#ifndef _MCD_API_H
6665 +#define _MCD_API_H
6666 +
6667 +#include <asm/types.h>
6668 +
6669 +/*
6670 + * Turn Execution Unit tasks ON (#define) or OFF (#undef)
6671 + */
6672 +#undef MCD_INCLUDE_EU
6673 +
6674 +/*
6675 + * Number of DMA channels
6676 + */
6677 +#define NCHANNELS 16
6678 +
6679 +/*
6680 + * Total number of variants
6681 + */
6682 +#ifdef MCD_INCLUDE_EU
6683 +#define NUMOFVARIANTS   6
6684 +#else
6685 +#define NUMOFVARIANTS   4
6686 +#endif
6687 +
6688 +/*
6689 + * Define sizes of the various tables
6690 + */
6691 +#define TASK_TABLE_SIZE     (NCHANNELS*32)
6692 +#define VAR_TAB_SIZE        (128)
6693 +#define CONTEXT_SAVE_SIZE   (128)
6694 +#define FUNCDESC_TAB_SIZE   (256)
6695 +
6696 +#ifdef MCD_INCLUDE_EU
6697 +#define FUNCDESC_TAB_NUM    16
6698 +#else
6699 +#define FUNCDESC_TAB_NUM    1
6700 +#endif
6701 +
6702 +
6703 +#ifndef DEFINESONLY
6704 +
6705 +/*
6706 + * Portability typedefs
6707 + */
6708 + /*
6709 +#ifndef s32
6710 +typedef int s32;
6711 +#endif
6712 +#ifndef u32
6713 +typedef unsigned int u32;
6714 +#endif
6715 +#ifndef s16
6716 +typedef short s16;
6717 +#endif
6718 +#ifndef u16
6719 +typedef unsigned short u16;
6720 +#endif
6721 +#ifndef s8
6722 +typedef char s8;
6723 +#endif
6724 +#ifndef u8
6725 +typedef unsigned char u8;
6726 +#endif
6727 +*/
6728 +/*
6729 + * These structures represent the internal registers of the
6730 + * multi-channel DMA
6731 + */
6732 +struct dmaRegs_s {
6733 +   u32 taskbar;         /* task table base address register */
6734 +   u32 currPtr;
6735 +   u32 endPtr;
6736 +   u32 varTablePtr;
6737 +   u16 dma_rsvd0;
6738 +   u16 ptdControl;      /* ptd control */
6739 +   u32 intPending;      /* interrupt pending register */
6740 +   u32 intMask;         /* interrupt mask register */
6741 +   u16 taskControl[16]; /* task control registers */
6742 +   u8  priority[32];    /* priority registers */
6743 +   u32 initiatorMux;    /* initiator mux control */
6744 +   u32 taskSize0;       /* task size control register 0. */
6745 +   u32 taskSize1;       /* task size control register 1. */
6746 +   u32 dma_rsvd1;       /* reserved */
6747 +   u32 dma_rsvd2;       /* reserved */
6748 +   u32 debugComp1;      /* debug comparator 1 */
6749 +   u32 debugComp2;      /* debug comparator 2 */
6750 +   u32 debugControl;    /* debug control */
6751 +   u32 debugStatus;     /* debug status */
6752 +   u32 ptdDebug;        /* priority task decode debug */
6753 +   u32 dma_rsvd3[31];   /* reserved */
6754 +};
6755 +typedef volatile struct dmaRegs_s dmaRegs;
6756 +
6757 +#endif
6758 +
6759 +/*
6760 + * PTD contrl reg bits
6761 + */
6762 +#define PTD_CTL_TSK_PRI         0x8000
6763 +#define PTD_CTL_COMM_PREFETCH   0x0001
6764 +
6765 +/*
6766 + * Task Control reg bits and field masks
6767 + */
6768 +#define TASK_CTL_EN             0x8000
6769 +#define TASK_CTL_VALID          0x4000
6770 +#define TASK_CTL_ALWAYS         0x2000
6771 +#define TASK_CTL_INIT_MASK      0x1f00
6772 +#define TASK_CTL_ASTRT          0x0080
6773 +#define TASK_CTL_HIPRITSKEN     0x0040
6774 +#define TASK_CTL_HLDINITNUM     0x0020
6775 +#define TASK_CTL_ASTSKNUM_MASK  0x000f
6776 +
6777 +/*
6778 + * Priority reg bits and field masks
6779 + */
6780 +#define PRIORITY_HLD            0x80
6781 +#define PRIORITY_PRI_MASK       0x07
6782 +
6783 +/*
6784 + * Debug Control reg bits and field masks
6785 + */
6786 +#define DBG_CTL_BLOCK_TASKS_MASK    0xffff0000
6787 +#define DBG_CTL_AUTO_ARM            0x00008000
6788 +#define DBG_CTL_BREAK               0x00004000
6789 +#define DBG_CTL_COMP1_TYP_MASK      0x00003800
6790 +#define DBG_CTL_COMP2_TYP_MASK      0x00000070
6791 +#define DBG_CTL_EXT_BREAK           0x00000004
6792 +#define DBG_CTL_INT_BREAK           0x00000002
6793 +
6794 +/*
6795 + * PTD Debug reg selector addresses
6796 + * This reg must be written with a value to show the contents of
6797 + * one of the desired internal register.
6798 + */
6799 +#define PTD_DBG_REQ             0x00 /* shows the state of 31 initiators */
6800 +#define PTD_DBG_TSK_VLD_INIT    0x01 /* shows which 16 tasks are valid and
6801 +                                        have initiators asserted */
6802 +
6803 +
6804 +/*
6805 + * General return values
6806 + */
6807 +#define MCD_OK                   0
6808 +#define MCD_ERROR               -1
6809 +#define MCD_TABLE_UNALIGNED     -2
6810 +#define MCD_CHANNEL_INVALID     -3
6811 +
6812 +/*
6813 + * MCD_initDma input flags
6814 + */
6815 +#define MCD_RELOC_TASKS         0x00000001
6816 +#define MCD_NO_RELOC_TASKS      0x00000000
6817 +#define MCD_COMM_PREFETCH_EN    0x00000002  /* Commbus Prefetching - MCF547x/548x ONLY */
6818 +
6819 +/*
6820 + * MCD_dmaStatus Status Values for each channel
6821 + */
6822 +#define MCD_NO_DMA  1 /* No DMA has been requested since reset */
6823 +#define MCD_IDLE    2 /* DMA active, but the initiator is currently inactive */
6824 +#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
6825 +#define MCD_PAUSED  4 /* DMA active but it is currently paused */
6826 +#define MCD_HALTED  5 /* the most recent DMA has been killed with MCD_killTask() */
6827 +#define MCD_DONE    6 /* the most recent DMA has completed. */
6828 +
6829 +
6830 +/*
6831 + * MCD_startDma parameter defines
6832 + */
6833 +
6834 +/*
6835 + * Constants for the funcDesc parameter
6836 + */
6837 +/* Byte swapping: */
6838 +#define MCD_NO_BYTE_SWAP    0x00045670  /* to disable byte swapping. */
6839 +#define MCD_BYTE_REVERSE    0x00076540  /* to reverse the bytes of each u32 of the DMAed data. */
6840 +#define MCD_U16_REVERSE     0x00067450  /* to reverse the 16-bit halves of
6841 +                                           each 32-bit data value being DMAed.*/
6842 +#define MCD_U16_BYTE_REVERSE    0x00054760 /* to reverse the byte halves of each
6843 +                                            16-bit half of each 32-bit data value DMAed */
6844 +#define MCD_NO_BIT_REV  0x00000000  /* do not reverse the bits of each byte DMAed. */
6845 +#define MCD_BIT_REV     0x00088880  /* reverse the bits of each byte DMAed */
6846 +/* CRCing: */
6847 +#define MCD_CRC16       0xc0100000  /* to perform CRC-16 on DMAed data. */
6848 +#define MCD_CRCCCITT    0xc0200000  /* to perform CRC-CCITT on DMAed data. */
6849 +#define MCD_CRC32       0xc0300000  /* to perform CRC-32 on DMAed data. */
6850 +#define MCD_CSUMINET    0xc0400000  /* to perform internet checksums on DMAed data.*/
6851 +#define MCD_NO_CSUM     0xa0000000  /* to perform no checksumming. */
6852 +
6853 +#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
6854 +#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
6855 +
6856 +/*
6857 + * Constants for the flags parameter
6858 + */
6859 +#define MCD_TT_FLAGS_RL   0x00000001 /* Read line */
6860 +#define MCD_TT_FLAGS_CW   0x00000002 /* Combine Writes */
6861 +#define MCD_TT_FLAGS_SP   0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY  */
6862 +#define MCD_TT_FLAGS_MASK 0x000000ff
6863 +#define MCD_TT_FLAGS_DEF  (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
6864 +
6865 +#define MCD_SINGLE_DMA  0x00000100 /* Unchained DMA */
6866 +#define MCD_CHAIN_DMA              /* TBD */
6867 +#define MCD_EU_DMA                 /* TBD */
6868 +#define MCD_FECTX_DMA   0x00001000 /* FEC TX ring DMA */
6869 +#define MCD_FECRX_DMA   0x00002000 /* FEC RX ring DMA */
6870 +
6871 +
6872 +/* these flags are valid for MCD_startDma and the chained buffer descriptors */
6873 +#define MCD_BUF_READY   0x80000000 /* indicates that this buffer is now under the DMA's control */
6874 +#define MCD_WRAP        0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
6875 +#define MCD_INTERRUPT   0x10000000 /* to generate an interrupt after completion of the DMA. */
6876 +#define MCD_END_FRAME   0x08000000 /* tell the DMA to end the frame when transferring
6877 +                                      last byte of data in buffer */
6878 +#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
6879 +                                      prior to performing the DMA. */
6880 +
6881 +/* Defines for the FEC buffer descriptor control/status word*/
6882 +#define MCD_FEC_BUF_READY   0x8000
6883 +#define MCD_FEC_WRAP        0x2000
6884 +#define MCD_FEC_INTERRUPT   0x1000
6885 +#define MCD_FEC_END_FRAME   0x0800
6886 +
6887 +
6888 +/*
6889 + * Defines for general intuitiveness
6890 + */
6891 +
6892 +#define MCD_TRUE  1
6893 +#define MCD_FALSE 0
6894 +
6895 +/*
6896 + * Three different cases for destination and source.
6897 + */
6898 +#define MINUS1          -1
6899 +#define ZERO            0
6900 +#define PLUS1           1
6901 +
6902 +#ifndef DEFINESONLY
6903 +
6904 +/* Task Table Entry struct*/
6905 +typedef struct {
6906 +    u32 TDTstart;   /* task descriptor table start */
6907 +    u32 TDTend;     /* task descriptor table end */
6908 +    u32 varTab;     /* variable table start */
6909 +    u32 FDTandFlags;    /* function descriptor table start and flags */
6910 +    volatile u32 descAddrAndStatus;
6911 +    volatile u32 modifiedVarTab;
6912 +    u32 contextSaveSpace;   /* context save space start */
6913 +    u32 literalBases;
6914 +} TaskTableEntry;
6915 +
6916 +
6917 +/* Chained buffer descriptor */
6918 +typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
6919 +struct MCD_bufDesc_struct {
6920 +   u32 flags;         /* flags describing the DMA */
6921 +   u32 csumResult;    /* checksum from checksumming performed since last checksum reset */
6922 +   s8  *srcAddr;      /* the address to move data from */
6923 +   s8  *destAddr;     /* the address to move data to */
6924 +   s8  *lastDestAddr; /* the last address written to */
6925 +   u32 dmaSize;       /* the number of bytes to transfer independent of the transfer size */
6926 +   MCD_bufDesc *next; /* next buffer descriptor in chain */
6927 +   u32 info;          /* private information about this descriptor;  DMA does not affect it */
6928 +};
6929 +
6930 +/* Progress Query struct */
6931 +typedef volatile struct MCD_XferProg_struct {
6932 +   s8 *lastSrcAddr;         /* the most-recent or last, post-increment source address */
6933 +   s8 *lastDestAddr;        /* the most-recent or last, post-increment destination address */
6934 +   u32  dmaSize;            /* the amount of data transferred for the current buffer */
6935 +   MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
6936 +} MCD_XferProg;
6937 +
6938 +
6939 +/* FEC buffer descriptor */
6940 +typedef volatile struct MCD_bufDescFec_struct {
6941 +    u16 statCtrl;
6942 +    u16 length;
6943 +    u32 dataPointer;
6944 +} MCD_bufDescFec;
6945 +
6946 +
6947 +/*************************************************************************/
6948 +/*
6949 + * API function Prototypes  - see MCD_dmaApi.c for further notes
6950 + */
6951 +
6952 +/*
6953 + * MCD_startDma starts a particular kind of DMA .
6954 + */
6955 +int MCD_startDma (
6956 +   int channel,   /* the channel on which to run the DMA */
6957 +   s8  *srcAddr,  /* the address to move data from, or buffer-descriptor address */
6958 +   s16 srcIncr,   /* the amount to increment the source address per transfer */
6959 +   s8  *destAddr, /* the address to move data to */
6960 +   s16 destIncr,  /* the amount to increment the destination address per transfer */
6961 +   u32 dmaSize,   /* the number of bytes to transfer independent of the transfer size */
6962 +   u32 xferSize,  /* the number bytes in of each data movement (1, 2, or 4) */
6963 +   u32 initiator, /* what device initiates the DMA */
6964 +   int priority,  /* priority of the DMA */
6965 +   u32 flags,     /* flags describing the DMA */
6966 +   u32 funcDesc   /* a description of byte swapping, bit swapping, and CRC actions */
6967 +);
6968 +
6969 +/*
6970 + * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
6971 + * registers, relocating and creating the appropriate task structures, and
6972 + * setting up some global settings
6973 + */
6974 +int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
6975 +
6976 +/*
6977 + * MCD_dmaStatus() returns the status of the DMA on the requested channel.
6978 + */
6979 +int MCD_dmaStatus (int channel);
6980 +
6981 +/*
6982 + * MCD_XferProgrQuery() returns progress of DMA on requested channel
6983 + */
6984 +int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
6985 +
6986 +/*
6987 + * MCD_killDma() halts the DMA on the requested channel, without any
6988 + * intention of resuming the DMA.
6989 + */
6990 +int MCD_killDma (int channel);
6991 +
6992 +/*
6993 + * MCD_continDma() continues a DMA which as stopped due to encountering an
6994 + * unready buffer descriptor.
6995 + */
6996 +int MCD_continDma (int channel);
6997 +
6998 +/*
6999 + * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
7000 + * running on that channel).
7001 + */
7002 +int MCD_pauseDma (int channel);
7003 +
7004 +/*
7005 + * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
7006 + * running on that channel).
7007 + */
7008 +int MCD_resumeDma (int channel);
7009 +
7010 +/*
7011 + * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
7012 + */
7013 +int MCD_csumQuery (int channel, u32 *csum);
7014 +
7015 +/*
7016 + * MCD_getCodeSize provides the packed size required by the microcoded task
7017 + * and structures.
7018 + */
7019 +int MCD_getCodeSize(void);
7020 +
7021 +/*
7022 + * MCD_getVersion provides a pointer to a version string and returns a
7023 + * version number.
7024 + */
7025 +int MCD_getVersion(char **longVersion);
7026 +
7027 +/* macro for setting a location in the variable table */
7028 +#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
7029 +   /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
7030 +      so I'm avoiding surrounding it with "do {} while(0)" */
7031 +
7032 +#endif  /* DEFINESONLY */
7033 +
7034 +#endif /* _MCD_API_H */
7035 --- a/include/asm-m68k/coldfire.h
7036 +++ b/include/asm-m68k/coldfire.h
7037 @@ -7,6 +7,7 @@
7038  #define MCF_SRAM       0x80000000
7039  #elif defined(CONFIG_M547X_8X)
7040  #define MCF_MBAR       0xE0000000
7041 +#define MCF_MMUBAR     0xE1000000
7042  #define MCF_RAMBAR0    0xE3000000
7043  #define MCF_RAMBAR1    0xE3001000
7044  #endif
7045 --- a/include/asm-m68k/dma.h
7046 +++ b/include/asm-m68k/dma.h
7047 @@ -1,16 +1,120 @@
7048  #ifndef _M68K_DMA_H
7049  #define _M68K_DMA_H 1
7050
7051 -
7052  /* it's useless on the m68k, but unfortunately needed by the new
7053     bootmem allocator (but this should do it for this) */
7054  #define MAX_DMA_ADDRESS PAGE_OFFSET
7055
7056 +#ifndef CONFIG_COLDFIRE
7057  #define MAX_DMA_CHANNELS 8
7058
7059  extern int request_dma(unsigned int dmanr, const char * device_id);    /* reserve a DMA channel */
7060  extern void free_dma(unsigned int dmanr);      /* release it again */
7061
7062 +#else /* not (defined(CONFIG_MCF5474) || defined(CONFIG_MCF5484) || defined(CONFIG_MCF5475) || defined(CONFIG_MCF5485)) */
7063 +
7064 +/************************************************
7065 + *     Multichannel DMA definitions            *
7066 + ************************************************/
7067 +#ifdef CONFIG_MCD_DMA
7068 +#include <asm/MCD_dma.h>
7069 +#include <asm/m5485dma.h>
7070 +
7071 +struct scatterlist;
7072 +
7073 +#define MAX_DMA_CHANNELS NCHANNELS
7074 +/*
7075 + *  identifiers for each initiator/requestor
7076 + */
7077 +#define DMA_ALWAYS      (0)
7078 +#define DMA_DSPI_RX     (1)
7079 +#define DMA_DSPI_TX     (2)
7080 +#define DMA_DREQ0       (3)
7081 +#define DMA_PSC0_RX     (4)
7082 +#define DMA_PSC0_TX     (5)
7083 +#define DMA_USBEP0      (6)
7084 +#define DMA_USBEP1      (7)
7085 +#define DMA_USBEP2      (8)
7086 +#define DMA_USBEP3      (9)
7087 +#define DMA_PCI_TX      (10)
7088 +#define DMA_PCI_RX      (11)
7089 +#define DMA_PSC1_RX     (12)
7090 +#define DMA_PSC1_TX     (13)
7091 +#define DMA_I2C_RX      (14)
7092 +#define DMA_I2C_TX      (15)
7093 +#define DMA_FEC0_RX     (16)
7094 +#define DMA_FEC0_TX     (17)
7095 +#define DMA_FEC1_RX     (18)
7096 +#define DMA_FEC1_TX     (19)
7097 +#define DMA_DREQ1       (20)
7098 +#define DMA_CTM0        (21)
7099 +#define DMA_CTM1        (22)
7100 +#define DMA_CTM2        (23)
7101 +#define DMA_CTM3        (24)
7102 +#define DMA_CTM4        (25)
7103 +#define DMA_CTM5        (26)
7104 +#define DMA_CTM6        (27)
7105 +#define DMA_CTM7        (28)
7106 +#define DMA_USBEP4      (29)
7107 +#define DMA_USBEP5      (30)
7108 +#define DMA_USBEP6      (31)
7109 +#define DMA_PSC2_RX     (32)
7110 +#define DMA_PSC2_TX     (33)
7111 +#define DMA_PSC3_RX     (34)
7112 +#define DMA_PSC3_TX     (35)
7113 +#define DMA_FEC_RX(x)   ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX)
7114 +#define DMA_FEC_TX(x)   ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX)
7115 +
7116 +int  dma_set_initiator(int);
7117 +unsigned int dma_get_initiator(int);
7118 +void dma_remove_initiator(int);
7119 +int dma_set_channel(int);
7120 +int dma_get_channel(int);
7121 +void dma_remove_channel(int);
7122 +int dma_set_channel_fec(int requestor);
7123 +int dma_connect(int channel, int address);
7124 +int dma_disconnect(int channel);
7125 +void dma_remove_channel_by_number(int channel);
7126 +int dma_init(void);
7127 +
7128 +#endif /* CONFIG_MCD_DMA */
7129 +
7130 +extern spinlock_t dma_spin_lock;
7131 +
7132 +static __inline__ unsigned long claim_dma_lock(void)
7133 +{
7134 +       unsigned long flags;
7135 +       spin_lock_irqsave(&dma_spin_lock, flags);
7136 +       return flags;
7137 +}
7138 +
7139 +static __inline__ void release_dma_lock(unsigned long flags)
7140 +{
7141 +       spin_unlock_irqrestore(&dma_spin_lock, flags);
7142 +}
7143 +
7144 +
7145 +/*
7146 + *  Linux standard DMA stuff
7147 + */
7148 +#if 0
7149 +int  request_dma(unsigned int channel, const char * device_id);
7150 +void free_dma(unsigned int channel);
7151 +void enable_dma(unsigned int channel);
7152 +void disable_dma(unsigned int channel);
7153 +int  dma_channel_active(unsigned int channel);
7154 +void set_dma_sg(unsigned int channel, struct scatterlist *sg, int nr_sg);
7155 +void set_dma_page(unsigned int channel, char pagenr);
7156 +void set_dma_addr(unsigned int channel, unsigned long physaddr);
7157 +void set_dma_count(unsigned int channel, unsigned long count);
7158 +void set_dma_mode(unsigned int channel, unsigned int mode);
7159 +void set_dma_speed(unsigned int channel, int cycle_ns);
7160 +int  get_dma_residue(unsigned int channel);
7161 +#endif
7162 +#define clear_dma_ff(channel)
7163 +
7164 +#endif /* not (defined(CONFIG_MCF5474) || defined(CONFIG_MCF5484) || defined(CONFIG_MCF5475) || defined(CONFIG_MCF5485)) */
7165 +
7166  #ifdef CONFIG_PCI
7167  extern int isa_dma_bridge_buggy;
7168  #else
7169 --- /dev/null
7170 +++ b/include/asm-m68k/m5485dma.h
7171 @@ -0,0 +1,97 @@
7172 +/*
7173 + *     m5485dma.h -- ColdFire 547x/548x DMA controller support.
7174 + */
7175 +#ifndef __MCF548X_DMA_H__
7176 +#define __MCF548X_DMA_H__
7177 +
7178 +
7179 +/* Register read/write macros */
7180 +#define MCF_DMA_DIPR    (*(volatile u32*)(void*)(MCF_MBAR+0x008014))
7181 +#define MCF_DMA_DIMR    (*(volatile u32*)(void*)(MCF_MBAR+0x008018))
7182 +#define MCF_DMA_IMCR    (*(volatile u32*)(void*)(MCF_MBAR+0x00805C))
7183 +
7184 +/* Bit definitions and macros for MCF_DMA_DIPR */
7185 +#define MCF_DMA_DIPR_TASK0           (0x00000001)
7186 +#define MCF_DMA_DIPR_TASK1           (0x00000002)
7187 +#define MCF_DMA_DIPR_TASK2           (0x00000004)
7188 +#define MCF_DMA_DIPR_TASK3           (0x00000008)
7189 +#define MCF_DMA_DIPR_TASK4           (0x00000010)
7190 +#define MCF_DMA_DIPR_TASK5           (0x00000020)
7191 +#define MCF_DMA_DIPR_TASK6           (0x00000040)
7192 +#define MCF_DMA_DIPR_TASK7           (0x00000080)
7193 +#define MCF_DMA_DIPR_TASK8           (0x00000100)
7194 +#define MCF_DMA_DIPR_TASK9           (0x00000200)
7195 +#define MCF_DMA_DIPR_TASK10          (0x00000400)
7196 +#define MCF_DMA_DIPR_TASK11          (0x00000800)
7197 +#define MCF_DMA_DIPR_TASK12          (0x00001000)
7198 +#define MCF_DMA_DIPR_TASK13          (0x00002000)
7199 +#define MCF_DMA_DIPR_TASK14          (0x00004000)
7200 +#define MCF_DMA_DIPR_TASK15          (0x00008000)
7201 +
7202 +/* Bit definitions and macros for MCF_DMA_DIMR */
7203 +#define MCF_DMA_DIMR_TASK0           (0x00000001)
7204 +#define MCF_DMA_DIMR_TASK1           (0x00000002)
7205 +#define MCF_DMA_DIMR_TASK2           (0x00000004)
7206 +#define MCF_DMA_DIMR_TASK3           (0x00000008)
7207 +#define MCF_DMA_DIMR_TASK4           (0x00000010)
7208 +#define MCF_DMA_DIMR_TASK5           (0x00000020)
7209 +#define MCF_DMA_DIMR_TASK6           (0x00000040)
7210 +#define MCF_DMA_DIMR_TASK7           (0x00000080)
7211 +#define MCF_DMA_DIMR_TASK8           (0x00000100)
7212 +#define MCF_DMA_DIMR_TASK9           (0x00000200)
7213 +#define MCF_DMA_DIMR_TASK10          (0x00000400)
7214 +#define MCF_DMA_DIMR_TASK11          (0x00000800)
7215 +#define MCF_DMA_DIMR_TASK12          (0x00001000)
7216 +#define MCF_DMA_DIMR_TASK13          (0x00002000)
7217 +#define MCF_DMA_DIMR_TASK14          (0x00004000)
7218 +#define MCF_DMA_DIMR_TASK15          (0x00008000)
7219 +
7220 +/* Bit definitions and macros for MCF_DMA_IMCR */
7221 +#define MCF_DMA_IMCR_SRC16(x)        (((x)&0x00000003)<<0)
7222 +#define MCF_DMA_IMCR_SRC17(x)        (((x)&0x00000003)<<2)
7223 +#define MCF_DMA_IMCR_SRC18(x)        (((x)&0x00000003)<<4)
7224 +#define MCF_DMA_IMCR_SRC19(x)        (((x)&0x00000003)<<6)
7225 +#define MCF_DMA_IMCR_SRC20(x)        (((x)&0x00000003)<<8)
7226 +#define MCF_DMA_IMCR_SRC21(x)        (((x)&0x00000003)<<10)
7227 +#define MCF_DMA_IMCR_SRC22(x)        (((x)&0x00000003)<<12)
7228 +#define MCF_DMA_IMCR_SRC23(x)        (((x)&0x00000003)<<14)
7229 +#define MCF_DMA_IMCR_SRC24(x)        (((x)&0x00000003)<<16)
7230 +#define MCF_DMA_IMCR_SRC25(x)        (((x)&0x00000003)<<18)
7231 +#define MCF_DMA_IMCR_SRC26(x)        (((x)&0x00000003)<<20)
7232 +#define MCF_DMA_IMCR_SRC27(x)        (((x)&0x00000003)<<22)
7233 +#define MCF_DMA_IMCR_SRC28(x)        (((x)&0x00000003)<<24)
7234 +#define MCF_DMA_IMCR_SRC29(x)        (((x)&0x00000003)<<26)
7235 +#define MCF_DMA_IMCR_SRC30(x)        (((x)&0x00000003)<<28)
7236 +#define MCF_DMA_IMCR_SRC31(x)        (((x)&0x00000003)<<30)
7237 +#define MCF_DMA_IMCR_SRC16_FEC0RX    (0x00000000)
7238 +#define MCF_DMA_IMCR_SRC17_FEC0TX    (0x00000000)
7239 +#define MCF_DMA_IMCR_SRC18_FEC0RX    (0x00000020)
7240 +#define MCF_DMA_IMCR_SRC19_FEC0TX    (0x00000080)
7241 +#define MCF_DMA_IMCR_SRC20_FEC1RX    (0x00000100)
7242 +#define MCF_DMA_IMCR_SRC21_DREQ1     (0x00000000)
7243 +#define MCF_DMA_IMCR_SRC21_FEC1TX    (0x00000400)
7244 +#define MCF_DMA_IMCR_SRC22_FEC0RX    (0x00001000)
7245 +#define MCF_DMA_IMCR_SRC23_FEC0TX    (0x00004000)
7246 +#define MCF_DMA_IMCR_SRC24_CTM0      (0x00010000)
7247 +#define MCF_DMA_IMCR_SRC24_FEC1RX    (0x00020000)
7248 +#define MCF_DMA_IMCR_SRC25_CTM1      (0x00040000)
7249 +#define MCF_DMA_IMCR_SRC25_FEC1TX    (0x00080000)
7250 +#define MCF_DMA_IMCR_SRC26_USBEP4    (0x00000000)
7251 +#define MCF_DMA_IMCR_SRC26_CTM2      (0x00200000)
7252 +#define MCF_DMA_IMCR_SRC27_USBEP5    (0x00000000)
7253 +#define MCF_DMA_IMCR_SRC27_CTM3      (0x00800000)
7254 +#define MCF_DMA_IMCR_SRC28_USBEP6    (0x00000000)
7255 +#define MCF_DMA_IMCR_SRC28_CTM4      (0x01000000)
7256 +#define MCF_DMA_IMCR_SRC28_DREQ1     (0x02000000)
7257 +#define MCF_DMA_IMCR_SRC28_PSC2RX    (0x03000000)
7258 +#define MCF_DMA_IMCR_SRC29_DREQ1     (0x04000000)
7259 +#define MCF_DMA_IMCR_SRC29_CTM5      (0x08000000)
7260 +#define MCF_DMA_IMCR_SRC29_PSC2TX    (0x0C000000)
7261 +#define MCF_DMA_IMCR_SRC30_FEC1RX    (0x00000000)
7262 +#define MCF_DMA_IMCR_SRC30_CTM6      (0x10000000)
7263 +#define MCF_DMA_IMCR_SRC30_PSC3RX    (0x30000000)
7264 +#define MCF_DMA_IMCR_SRC31_FEC1TX    (0x00000000)
7265 +#define MCF_DMA_IMCR_SRC31_CTM7      (0x80000000)
7266 +#define MCF_DMA_IMCR_SRC31_PSC3TX    (0xC0000000)
7267 +
7268 +#endif /* __MCF548X_DMA_H__ */
7269 --- /dev/null
7270 +++ b/include/asm-m68k/m5485sram.h
7271 @@ -0,0 +1,12 @@
7272 +#ifndef SYS_SRAM_H
7273 +#define SYS_SRAM_H
7274 +
7275 +
7276 +#define SYS_SRAM_DMA_START        MCF_MBAR + 0x10000
7277 +#define SYS_SRAM_DMA_SIZE         8192
7278 +#define SYS_SRAM_FEC_START        SYS_SRAM_DMA_START + SYS_SRAM_DMA_SIZE
7279 +#define SYS_SRAM_FEC_SIZE         2048
7280 +#define SYS_SRAM_SEC_START        SYS_SRAM_FEC_START + SYS_SRAM_FEC_SIZE
7281 +#define SYS_SRAM_SEC_SIZE         1280
7282 +
7283 +#endif /* SYS_SRAM_H */