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upgrade iop32x to 2.6.30
[openwrt.git] / target / linux / coldfire / patches / 078-m547x_8x_pci_initial.patch
1 From 7f92b68c12c1891435c75f7f83a6390b4c73eaa6 Mon Sep 17 00:00:00 2001
2 From: Kurt Mahan <kmahan@freescale.com>
3 Date: Thu, 10 Jul 2008 19:17:11 -0600
4 Subject: [PATCH] Add PCI to m547x/m548x.
5
6 LTIBName: m547x-8x-pci-initial
7 Signed-off-by: Kurt Mahan <kmahan@freescale.com>
8 Signed-off-by: Shrek Wu <b16972@freescale.com>
9 ---
10 arch/m68k/Kconfig | 4 +-
11 arch/m68k/coldfire/Makefile | 7 +-
12 arch/m68k/coldfire/ints.c | 8 +-
13 arch/m68k/coldfire/mcf548x-pci.c | 934 +++++++++++++++++++++++++++++++++++++
14 arch/m68k/kernel/Makefile | 3 +
15 arch/m68k/kernel/bios32_mcf548x.c | 631 +++++++++++++++++++++++++
16 arch/m68k/kernel/dma.c | 32 +-
17 arch/m68k/mm/kmap.c | 11 +-
18 drivers/pci/access.c | 16 +-
19 drivers/usb/host/Makefile | 2 +-
20 include/asm-m68k/5445x_pci.h | 94 ++++
21 include/asm-m68k/548x_pci.h | 99 ++++
22 include/asm-m68k/io.h | 65 +++-
23 include/asm-m68k/m5485pci.h | 330 +++++++++++++
24 include/asm-m68k/pci.h | 96 +----
25 include/asm-m68k/raw_io.h | 26 +
26 include/asm-m68k/virtconvert.h | 5 +
27 include/linux/pci.h | 2 +
28 18 files changed, 2250 insertions(+), 115 deletions(-)
29 create mode 100644 arch/m68k/coldfire/mcf548x-pci.c
30 create mode 100644 arch/m68k/kernel/bios32_mcf548x.c
31 create mode 100644 include/asm-m68k/5445x_pci.h
32 create mode 100644 include/asm-m68k/548x_pci.h
33 create mode 100644 include/asm-m68k/m5485pci.h
34
35 --- a/arch/m68k/Kconfig
36 +++ b/arch/m68k/Kconfig
37 @@ -175,8 +175,8 @@ config HADES
38 to use this kernel on a Hades, say Y here; otherwise say N.
39
40 config PCI
41 - bool
42 - depends on HADES || M54455
43 + bool "PCI bus support"
44 + depends on HADES || M54455 || M547X_8X
45 default n
46 help
47 Find out whether you have a PCI motherboard. PCI is the name of a
48 --- a/arch/m68k/coldfire/Makefile
49 +++ b/arch/m68k/coldfire/Makefile
50 @@ -3,12 +3,17 @@
51 #
52
53 obj-y:= entry.o config.o cache.o signal.o muldi3.o traps.o ints.o
54 -
55 +ifdef CONFIG_M5445X
56 ifneq ($(strip $(CONFIG_USB) $(CONFIG_USB_GADGET_MCF5445X)),)
57 obj-y += usb.o usb/
58 endif
59 +endif
60
61 +ifdef CONFIG_M547X_8X
62 +obj-$(CONFIG_PCI) += mcf548x-pci.o
63 +else
64 obj-$(CONFIG_PCI) += pci.o mcf5445x-pci.o iomap.o
65 +endif
66 obj-$(CONFIG_M5445X) += mcf5445x-devices.o
67 obj-$(CONFIG_M547X_8X) += m547x_8x-devices.o
68 obj-$(CONFIG_M547X_8X) += mcf548x-devices.o
69 --- a/arch/m68k/coldfire/ints.c
70 +++ b/arch/m68k/coldfire/ints.c
71 @@ -192,6 +192,8 @@ int setup_irq(unsigned int irq, struct i
72 /* Can't share interrupts unless both agree to */
73 if (!((*prev)->flags & node->flags & IRQF_SHARED)) {
74 spin_unlock_irqrestore(&contr->lock, flags);
75 + printk(KERN_INFO "%s: -BUSY-Incorrect IRQ %d \n",
76 + __FUNCTION__, irq);
77 return -EBUSY;
78 }
79 while (*prev)
80 @@ -219,9 +221,11 @@ int request_irq(unsigned int irq,
81 struct irq_node *node = get_irq_node();
82 int res;
83
84 - if (!node)
85 + if (!node) {
86 + printk(KERN_INFO "%s:get_irq_node error %x\n",
87 + __FUNCTION__,(unsigned int) node);
88 return -ENOMEM;
89 -
90 + }
91 node->handler = handler;
92 node->flags = flags;
93 node->dev_id = dev_id;
94 --- /dev/null
95 +++ b/arch/m68k/coldfire/mcf548x-pci.c
96 @@ -0,0 +1,934 @@
97 +/*
98 + * ColdFire 547x/548x PCI Host Controller functions
99 + */
100 +#include <linux/kernel.h>
101 +#include <linux/types.h>
102 +#include <linux/init.h>
103 +#include <linux/mm.h>
104 +#include <linux/string.h>
105 +#include <linux/pci.h>
106 +#include <linux/ioport.h>
107 +#include <linux/slab.h>
108 +#include <linux/version.h>
109 +#include <linux/interrupt.h>
110 +
111 +#include <linux/dma-mapping.h>
112 +#include <asm/coldfire.h>
113 +#include <asm/io.h>
114 +#include <asm/m5485sim.h>
115 +#include <asm/m5485pci.h>
116 +#include <asm/irq.h>
117 +#include <asm/pci.h>
118 +#include <asm/virtconvert.h>
119 +
120 +
121 +#undef DEBUG
122 +//#define DEBUG
123 +
124 +#ifdef DEBUG
125 +//#define DBG(x...) printk(KERN_DEBUG x)
126 +#define DBG(x...) printk(x)
127 +#else
128 +#define DBG(x...)
129 +#endif
130 +
131 +#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,75))
132 +# define irqreturn_t void
133 +# define IRQ_HANDLED
134 +# define IRQ_NONE
135 +#endif
136 +
137 +/*
138 + * Bridge configration dafaults
139 + */
140 +#define PCI_RETRIES 0
141 +#define PCI_CACHE_LINE 8
142 +#define PCI_MINGNT 1
143 +#define PCI_MAXLAT 42
144 +
145 +
146 +/*
147 + * Initiator windows setting
148 + */
149 +#define HOST_MEM_BASE 0xD0000000 /* ColdFire Memory window base */
150 +#define PCI_MEM_BASE 0xD0000000 /* PCI Memory window base */
151 +#define PCI_MEM_SIZE 0x08000000 /* Memory window size (128M) */
152 +#define HOST_IO_BASE 0xD8000000 /* ColdFire I/O window base */
153 +#define PCI_IO_BASE_ADDR 0x00000000 /* PCI I/O window base */
154 +#define PCI_IO_SIZE 0x00010000 /* I/O window size (64K) */
155 +#define HOST_CFG_BASE 0xD8000000 /* ColdFire config window base */
156 +#define HOST_DMA_BASE CONFIG_SDRAM_BASE /* ColdFire PCI-DMA window base */
157 +#define PCI_HDR_BASE (MCF_MBAR+0xB00)/* ColdFire config registers */
158 +
159 +#define PCI_MEM_MASK (PCI_MEM_SIZE-1)
160 +#define PCI_IO_MASK (PCI_IO_SIZE-1)
161 +
162 +/* Macro to set initiator window */
163 +#define WxBAR(host_address, pci_address, size) \
164 + (((host_address) & 0xff000000) | \
165 + ((((size)-1) & 0xff000000) >> 8) | \
166 + ((pci_address) & 0xff000000) >> 16)
167 +
168 +/*
169 + * BIOS internal data
170 + */
171 +static u8 revision; /* controller revision */
172 +
173 +/*
174 + * Board specific setting
175 + */
176 +const unsigned int irq_lines[] = { 5, 7 };
177 +
178 +#define N_SLOTS (sizeof(board_info) / sizeof(board_info[0]))
179 +#define N_IRQS (sizeof(irq_lines) / sizeof(irq_lines[0]))
180 +#define BRIDGE_SLOT 0
181 +
182 +const struct slotinfo {
183 + unsigned char idsel; /* device number */
184 + unsigned char irq; /* external IRQ */
185 + unsigned char req; /* REQ line number */
186 + unsigned char gnt; /* GNT line number */
187 +} board_info[] = {
188 + {0, 0, 0, 0}, /* Bridge */
189 + {17, 5, 1, 1}, /* Slot #1 */
190 + {18, 5, 2, 2}, /* Slot #2 */
191 + {20, 7, 3, 3}, /* Slot #3 */
192 + {21, 7, 4, 4}, /* Slot #4 */
193 +};
194 +
195 +/************************************************************************/
196 +
197 +/*
198 + * static int mk_conf_addr()
199 + *
200 + * Return type0 or type1 configuration address
201 + * by the means of device address and PCI dword location
202 + * 0 - for not existing slots
203 + */
204 +static int mk_conf_addr(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where)
205 +{
206 + int slot, func, address, idsel, dev_fn;
207 +
208 + if (bus->number) {
209 + address = MCF_PCICAR_E | (bus->number << 16) |
210 + (devfn << 8) | (where & 0xfc);
211 + } else {
212 + slot = PCI_SLOT(devfn);
213 + if (slot > N_SLOTS || slot == BRIDGE_SLOT)
214 + return 0;
215 + else {
216 + func = PCI_FUNC(devfn);
217 + idsel = board_info[slot].idsel;
218 +
219 + dev_fn = PCI_DEVFN(idsel, func);
220 + address = MCF_PCICAR_E | (bus->number << 16) |
221 + (dev_fn << 8) | (where & 0xfc);
222 + }
223 + }
224 +
225 + return (address);
226 +}
227 +
228 +/*
229 + * static int read_config_byte()
230 + *
231 + * Read a byte from configuration space of specified device
232 + */
233 +static int read_config_byte(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u8 *value)
234 +{
235 + int slot;
236 + int address;
237 + int result;
238 +
239 + *value = 0xff;
240 + result = PCIBIOS_SUCCESSFUL;
241 +
242 + slot = PCI_SLOT(devfn);
243 + if (slot == BRIDGE_SLOT) {
244 + if (where <= 0x40)
245 + *value = *(volatile u8 *) (PCI_HDR_BASE + (where ^ 3));
246 + else
247 + *value = 0;
248 + } else {
249 + address = mk_conf_addr(bus, devfn, where);
250 + if (!address)
251 + result = PCIBIOS_DEVICE_NOT_FOUND;
252 + else {
253 + MCF_PCICAR = address;
254 + *value = *(volatile u8 *) (HOST_CFG_BASE + (where & 3));
255 + }
256 + }
257 + __asm__ __volatile__("nop");
258 + __asm__ __volatile__("nop");
259 + MCF_PCICAR &= ~MCF_PCICAR_E;
260 +
261 + DBG("PCI: read_config_byte bus=%d, devfn=%d, addr=0x%02X, val=0x%02X, ret=%02X\n",
262 + bus->number, devfn, where, *value, result);
263 +
264 + return (result);
265 +}
266 +
267 +/*
268 + * static int read_config_word()
269 + *
270 + * Read a word from configuration space of specified device
271 + */
272 +static int read_config_word(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u16 *value)
273 +{
274 + int slot;
275 + int address;
276 + int result;
277 +
278 + *value = 0xffff;
279 + result = PCIBIOS_SUCCESSFUL;
280 +
281 + if (where & 0x1)
282 + result = PCIBIOS_BAD_REGISTER_NUMBER;
283 + else {
284 + slot = PCI_SLOT(devfn);
285 + if (slot == BRIDGE_SLOT) {
286 + if (where <= 0x3f)
287 + *value =
288 + *(volatile u16 *) (PCI_HDR_BASE +
289 + (where ^ 2));
290 + else
291 + *value = 0;
292 + } else {
293 + address = mk_conf_addr(bus, devfn, where);
294 + if (!address)
295 + result = PCIBIOS_DEVICE_NOT_FOUND;
296 + else {
297 + MCF_PCICAR = address;
298 + *value = le16_to_cpu(*(volatile u16 *)
299 + (HOST_CFG_BASE +
300 + (where & 2)));
301 + }
302 + }
303 + }
304 + __asm__ __volatile__("nop");
305 + __asm__ __volatile__("nop");
306 + MCF_PCICAR &= ~MCF_PCICAR_E;
307 +
308 + DBG("PCI: read_config_word bus=%d, devfn=%d, addr=0x%02X, val=0x%04X ret=%02X\n",
309 + bus->number, devfn, where, *value, result);
310 +
311 + return (result);
312 +}
313 +
314 +/*
315 + * static int read_config_dword()
316 + *
317 + * Read a long word from configuration space of specified device
318 + */
319 +static int read_config_dword(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u32 *value)
320 +{
321 + int slot;
322 + int address;
323 + int result;
324 +
325 + *value = 0xffffffff;
326 + result = PCIBIOS_SUCCESSFUL;
327 +
328 + if (where & 0x3)
329 + result = PCIBIOS_BAD_REGISTER_NUMBER;
330 + else {
331 + slot = PCI_SLOT(devfn);
332 + if (slot == BRIDGE_SLOT) {
333 + if (where <= 0x3d)
334 + *value =
335 + *(volatile u32 *) (PCI_HDR_BASE + where);
336 + else
337 + *value = 0;
338 + __asm__ __volatile__("nop");
339 + __asm__ __volatile__("nop");
340 + } else {
341 + address = mk_conf_addr(bus, devfn, where);
342 + if (!address)
343 + result = PCIBIOS_DEVICE_NOT_FOUND;
344 + else {
345 + MCF_PCICAR = address;
346 + *value = le32_to_cpu(*(volatile u32 *)
347 + (HOST_CFG_BASE));
348 + __asm__ __volatile__("nop");
349 + __asm__ __volatile__("nop");
350 + if (bus->number != 0 && revision < 1) {
351 + volatile u32 temp;
352 +
353 + MCF_PCICAR |= 0xff0000;
354 + temp = *(volatile u32 *) (HOST_CFG_BASE);
355 + }
356 + }
357 + }
358 + }
359 +
360 + MCF_PCICAR &= ~MCF_PCICAR_E;
361 +
362 + DBG("PCI: read_config_dword bus=%d, devfn=%d, addr=0x%02X, value=0x%08X ret=%02X\n",
363 + bus->number, devfn, where, *value, result);
364 +
365 + return (result);
366 +}
367 +
368 +/*
369 + * static int write_config_byte()
370 + *
371 + * Write a byte to configuration space of specified device
372 + */
373 +static int write_config_byte(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u8 value)
374 +{
375 + int slot;
376 + int address;
377 + int result;
378 +
379 + result = PCIBIOS_SUCCESSFUL;
380 +
381 + slot = PCI_SLOT(devfn);
382 + if (slot == BRIDGE_SLOT) {
383 + if (where <= 0x40)
384 + *(volatile u8 *) (PCI_HDR_BASE + (where ^ 3)) = value;
385 + } else {
386 + address = mk_conf_addr(bus, devfn, where);
387 + if (!address)
388 + result = PCIBIOS_DEVICE_NOT_FOUND;
389 + else {
390 + MCF_PCICAR = address;
391 + *(volatile u8 *) (HOST_CFG_BASE + (where & 3)) = value;
392 + }
393 + }
394 + __asm__ __volatile__("nop");
395 + __asm__ __volatile__("nop");
396 + MCF_PCICAR &= ~MCF_PCICAR_E;
397 +
398 + DBG("PCI: write_config_byte bus=%d, devfn=%d, addr=0x%02X, value=0x%02X ret=%02X\n",
399 + bus->number, devfn, where, value, result);
400 +
401 + return (result);
402 +}
403 +
404 +/*
405 + * static int write_config_word()
406 + *
407 + * Write a word to configuration space of specified device
408 + */
409 +static int write_config_word(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u16 value)
410 +{
411 + int slot;
412 + int address;
413 + int result;
414 +
415 + result = PCIBIOS_SUCCESSFUL;
416 +
417 + if (where & 0x1)
418 + result = PCIBIOS_BAD_REGISTER_NUMBER;
419 + else {
420 + slot = PCI_SLOT(devfn);
421 + if (slot == BRIDGE_SLOT) {
422 + if (where <= 0x3f)
423 + *(volatile u16 *) (PCI_HDR_BASE + (where ^ 2)) =
424 + value;
425 + } else {
426 + address = mk_conf_addr(bus, devfn, where);
427 + if (!address)
428 + result = PCIBIOS_DEVICE_NOT_FOUND;
429 + else {
430 + MCF_PCICAR = address;
431 + *(volatile u16 *) (HOST_CFG_BASE + (where & 2)) =
432 + cpu_to_le16(value);
433 + }
434 + }
435 + }
436 + __asm__ __volatile__("nop");
437 + __asm__ __volatile__("nop");
438 + MCF_PCICAR &= ~MCF_PCICAR_E;
439 +
440 + DBG("PCI: write_config_word bus=%d, devfn=%d, addr=0x%02X, value=0x%04X ret=%02X\n",
441 + bus->number, devfn, where, value, result);
442 +
443 + return (result);
444 +}
445 +
446 +/*
447 + * static int write_config_dword()
448 + *
449 + * Write a long word to configuration space of specified device
450 + */
451 +static int write_config_dword(/*struct pci_dev *dev*/struct pci_bus *bus, unsigned int devfn, int where, u32 value)
452 +{
453 + int slot;
454 + int address;
455 + int result;
456 +
457 + result = PCIBIOS_SUCCESSFUL;
458 +
459 + if (where & 0x3)
460 + result = PCIBIOS_BAD_REGISTER_NUMBER;
461 + else {
462 + slot = PCI_SLOT(devfn);
463 + if (slot == BRIDGE_SLOT) {
464 + if (where <= 0x3d)
465 + *(volatile u32 *) (PCI_HDR_BASE + where) =
466 + value;
467 + } else {
468 + address = mk_conf_addr(bus, devfn, where);
469 + if (!address)
470 + result = PCIBIOS_DEVICE_NOT_FOUND;
471 + else {
472 + MCF_PCICAR = address;
473 + *(volatile u32 *) (HOST_CFG_BASE) =
474 + cpu_to_le32(value);
475 + }
476 + }
477 + }
478 + __asm__ __volatile__("nop");
479 + __asm__ __volatile__("nop");
480 + MCF_PCICAR &= ~MCF_PCICAR_E;
481 +
482 + DBG("PCI: write_config_dword dev=%d, fn=%d, addr=0x%02X, value=0x%08X ret=%02X\n",
483 + PCI_SLOT(devfn), PCI_FUNC(devfn), where, value, result);
484 +
485 + return (result);
486 +}
487 +
488 +static int config_read(struct pci_bus *bus, unsigned int devfn,
489 + int where, int size, u32 * val)
490 +{
491 + switch (size) {
492 + case 1:
493 + return read_config_byte(bus, devfn, where, (u8 *) val);
494 + case 2:
495 + return read_config_word(bus, devfn, where, (u16 *) val);
496 + default:
497 + return read_config_dword(bus, devfn, where, val);
498 + }
499 +}
500 +
501 +static int config_write(struct pci_bus *bus, unsigned int devfn,
502 + int where, int size, u32 val)
503 +{
504 + switch (size) {
505 + case 1:
506 + return write_config_byte(bus, devfn, where, (u8) val);
507 + case 2:
508 + return write_config_word(bus, devfn, where, (u16) val);
509 + default:
510 + return write_config_dword(bus, devfn, where, val);
511 + }
512 +}
513 +
514 +/*
515 + * configuration routines entry points
516 + */
517 +static struct pci_ops bus_ops = {
518 + read: config_read,
519 + write: config_write
520 +};
521 +
522 +/************************************************************************/
523 +
524 +/*
525 + * u8 pci_inb()
526 + *
527 + * Read a byte at specified address from I/O space
528 + */
529 +unsigned char pci_inb(long addr)
530 +{
531 + char value;
532 +
533 + value = *(volatile unsigned char *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
534 + DBG("PCI: inb addr=0x%08X, value=0x%02X\n", addr, value);
535 +
536 + return (unsigned char) value;
537 +}
538 +
539 +
540 +/*
541 + * u16 pci_inw()
542 + *
543 + * Read a word at specified address from I/O space
544 + */
545 +unsigned short pci_inw(long addr)
546 +{
547 + short value;
548 + volatile unsigned short *ptr;
549 +
550 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
551 + value = le16_to_cpu(*ptr);
552 +
553 + DBG("PCI: inw addr=0x%08X, value=0x%04X\n", addr, value);
554 + return (unsigned short) value;
555 +}
556 +
557 +/*
558 + * u16 pci_raw_inw()
559 + *
560 + * Read a raw word at specified address from I/O space
561 + */
562 +unsigned short pci_raw_inw(long addr)
563 +{
564 + short value;
565 + volatile unsigned short *ptr;
566 +
567 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
568 + value = *ptr;
569 +
570 + DBG("PCI: raw_inw addr=0x%08X, value=0x%04X\n", addr, value);
571 + return (unsigned short) value;
572 +}
573 +
574 +/*
575 + * u32 pci_inl()
576 + *
577 + * Read a dword at specified address from I/O space
578 + */
579 +unsigned long pci_inl(long addr)
580 +{
581 + long value;
582 + volatile unsigned long *ptr;
583 +
584 + ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
585 + value = le32_to_cpu(*ptr);
586 +
587 + DBG("PCI: inl addr=0x%08X, value=0x%08X\n", addr, value);
588 + return (unsigned long) value;
589 +}
590 +
591 +/*
592 + * u32 pci_raw_inl()
593 + *
594 + * Read a raw dword at specified address from I/O space
595 + */
596 +unsigned long pci_raw_inl(long addr)
597 +{
598 + long value;
599 + volatile unsigned long *ptr;
600 +
601 + ptr = (volatile unsigned long *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
602 + value = *ptr;
603 +
604 + DBG("PCI: raw_inl addr=0x%08X, value=0x%08X\n", addr, value);
605 + return (unsigned long) value;
606 +}
607 +
608 +/*
609 + * void pci_outb()
610 + *
611 + * Write a byte value at specified address to I/O space
612 + */
613 +void pci_outb( unsigned char value, long addr)
614 +{
615 +
616 + *(volatile unsigned char *) (HOST_IO_BASE | (addr & PCI_IO_MASK)) = value;
617 + DBG("PCI: outb addr=0x%08X, value=0x%02X\n", addr, value);
618 +}
619 +
620 +
621 +/*
622 + * void pci_outw()
623 + *
624 + * Write a word value at specified address to I/O space
625 + */
626 +void pci_outw(volatile unsigned short value, volatile long addr)
627 +{
628 + volatile unsigned short *ptr;
629 +
630 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
631 + *ptr = cpu_to_le16(value);
632 + DBG("PCI: outw addr=0x%08X, value=0x%04X\n", addr, value);
633 +}
634 +
635 +/*
636 + * void pci_raw_outw()
637 + *
638 + * Write a raw word value at specified address to I/O space
639 + */
640 +void pci_raw_outw(volatile unsigned short value, volatile long addr)
641 +{
642 + volatile unsigned short *ptr;
643 +
644 + ptr = (volatile unsigned short *) (HOST_IO_BASE | (addr & PCI_IO_MASK));
645 + *ptr = value;
646 + DBG("PCI: raw_outw addr=0x%08X, value=0x%04X\n", addr, value);
647 +}
648 +
649 +/*
650 + * void pci_outl()
651 + *
652 + * Write a long word value at specified address to I/O space
653 + */
654 +void pci_outl(volatile unsigned long value, volatile long addr)
655 +{
656 + volatile unsigned long *ptr;
657 +
658 + ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
659 + *ptr = cpu_to_le32(value);
660 + DBG("PCI: outl addr=0x%08X, value=0x%08X\n", addr, value);
661 +}
662 +
663 +/*
664 + * void pci_raw_outl()
665 + *
666 + * Write a raw long word value at specified address to I/O space
667 + */
668 +void pci_raw_outl(volatile unsigned long value, volatile long addr)
669 +{
670 + volatile unsigned long *ptr;
671 +
672 + ptr = (volatile unsigned long *)(HOST_IO_BASE | (addr & PCI_IO_MASK));
673 + *ptr = value;
674 + DBG("PCI: raw_outl addr=0x%08X, value=0x%08X\n", addr, value);
675 +}
676 +
677 +/*
678 + * void pci_insb()
679 + *
680 + * Read several byte values from specified I/O port
681 + */
682 +void pci_insb(volatile unsigned char *addr, unsigned char *buf, int len)
683 +{
684 + for (; len--; buf++)
685 + *buf = pci_inb((unsigned long)addr);
686 + DBG("PCI: pci_insb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
687 +}
688 +
689 +
690 +/*
691 + * void pci_insw()
692 + *
693 + * Read several word values from specified I/O port
694 + */
695 +void pci_insw(volatile unsigned short *addr, unsigned short *buf, int len)
696 +{
697 + for (; len--; buf++)
698 + *buf = pci_inw((unsigned long)addr);
699 + DBG("PCI: pci_insw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
700 +}
701 +
702 +/*
703 + * void pci_insl()
704 + *
705 + * Read several dword values from specified I/O port
706 + */
707 +void pci_insl(volatile unsigned long *addr, unsigned long *buf, int len)
708 +{
709 + for (; len--; buf++)
710 + *buf = pci_inl((unsigned long)addr);
711 + DBG("PCI: pci_insl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
712 +}
713 +
714 +/*
715 + * void pci_outsb()
716 + *
717 + * Write several byte values to specified I/O port
718 + */
719 +void pci_outsb(volatile unsigned char *addr, const unsigned char *buf, int len)
720 +{
721 + for (; len--; buf++)
722 + pci_outb((unsigned long)addr, *buf);
723 + DBG("PCI: pci_outsb addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
724 +}
725 +
726 +/*
727 + * void pci_outsw()
728 + *
729 + * Write several word values to specified I/O port
730 + */
731 +void pci_outsw(volatile unsigned short *addr, const unsigned short *buf, int len)
732 +{
733 + for (; len--; buf++)
734 + pci_outw((unsigned long)addr, *buf);
735 + DBG("PCI: pci_outsw addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
736 +}
737 +
738 +/*
739 + * void pci_outsl()
740 + *
741 + * Write several dword values to specified I/O port
742 + */
743 +void pci_outsl(volatile unsigned long *addr, const unsigned long *buf, int len)
744 +{
745 + for (; len--; buf++)
746 + pci_outl((unsigned long)addr, *buf);
747 + DBG("PCI: pci_outsl addr=0x%08X, buf=%p, len=%d\n", addr, buf, len);
748 +}
749 +
750 +/*
751 + * void pci_xlb_handler()
752 + *
753 + * PCI XLB interrupt handler
754 + */
755 +irqreturn_t xlb_interrupt(int irq, void *dev)
756 +{
757 + volatile int xlb_error = MCF_PCIISR;
758 +
759 + /* Acknowlege interrupt */
760 + MCF_PCIISR = xlb_error;
761 +
762 + /* Dump interrupt reason */
763 + if (xlb_error & MCF_PCIISR_RE)
764 + DBG("PCI: Retry Error Received\n");
765 +
766 + if (xlb_error & MCF_PCIISR_IA)
767 + DBG("PCI: Initiator Abort Received\n");
768 +
769 + if (xlb_error & MCF_PCIISR_TA)
770 + DBG("PCI: Target Abort Received\n");
771 +
772 + return IRQ_HANDLED;
773 +}
774 +
775 +
776 +/*
777 + * void pci_arbiter_handler()
778 + *
779 + * PCI arbiter interrupt handler
780 + */
781 +irqreturn_t arb_interrupt(int irq, void *dev)
782 +{
783 + volatile unsigned long arb_error = MCF_PCIARB_PASR;
784 +
785 + /* Acknowlege interrupt */
786 + printk("%s\n",__FUNCTION__);
787 + MCF_PCIARB_PASR = arb_error;
788 +
789 + if (arb_error & MCF_PCIARB_PASR_ITLMBK) {
790 + DBG("PCI: coldfire master time-out\n");
791 +
792 + /* Set infinite number of retries */
793 + MCF_PCIICR &= ~0xFF;
794 + }
795 +
796 + if (arb_error & MCF_PCIARB_PASR_EXTMBK(0x1F)) {
797 + arb_error >>= 17;
798 + DBG("PCI: external master time-out (mask = 0x%X)\n", arb_error);
799 +
800 + /* raise arbitration priority level */
801 + MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMPRI(arb_error);
802 + }
803 +
804 + return IRQ_HANDLED;
805 +}
806 +
807 +
808 +/*
809 + * void pci_eint_handler()
810 + *
811 + * Eport interrupt handler
812 + */
813 +irqreturn_t eint_handler(int irq, void *dev)
814 +{
815 + /* Just acknowlege interrupt and exit */
816 + MCF_EPFR = 0x1 << (irq - 64);
817 + return IRQ_HANDLED;
818 +}
819 +
820 +
821 +/*
822 + * void __init coldfire_fixup(int pci_modify)
823 + *
824 + * Assign IRQ numbers as used by Linux to the interrupt pins
825 + * of the PCI cards.
826 + */
827 +static void __init coldfire_fixup(int pci_modify)
828 +{
829 + struct pci_dev *dev;
830 + unsigned char slot, pin;
831 +
832 + DBG("%s\n",__FUNCTION__);
833 +#ifdef NL_ORIGINAL
834 + pci_for_each_dev(dev) {
835 +#else
836 + dev = NULL;
837 + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
838 +#endif
839 + if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
840 + slot = PCI_SLOT(dev->devfn);
841 + dev->irq = 64 + board_info[slot].irq;
842 +
843 + /* Check if device needs interrupt */
844 +#ifdef NL_ORIGINAL
845 + pcibios_read_config_byte(
846 + dev->bus->number, dev->devfn,
847 + PCI_INTERRUPT_PIN, &pin);
848 +
849 + if ( pin ) {
850 + pcibios_write_config_byte(
851 + dev->bus->number, dev->devfn,
852 + PCI_INTERRUPT_LINE, dev->irq);
853 + }
854 +#else
855 + pci_read_config_byte(dev,
856 + PCI_INTERRUPT_PIN, &pin);
857 +
858 + if ( pin ) {
859 + pci_write_config_byte(dev,
860 + PCI_INTERRUPT_LINE, dev->irq);
861 + }
862 +#endif
863 + }
864 + }
865 +}
866 +
867 +static void __init configure_device(struct pci_dev *dev)
868 +{
869 + /* TODO: This should depend from disable_pci_burst setting */
870 + DBG("%s\n",__FUNCTION__);
871 +#ifdef NL_ORIGINAL
872 + pcibios_write_config_byte(bus, devfn, PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE);
873 +#else
874 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, PCI_CACHE_LINE);
875 +#endif
876 +}
877 +
878 +struct pci_bus_info *__init init_coldfire_pci(void)
879 +{
880 + static struct pci_bus_info bus;
881 + int i;
882 + int pci_mem_va;
883 + static char irq_name[N_IRQS][15];
884 +
885 + /* Get controller revision */
886 + revision = MCF_PCICCRIR;
887 + printk("ColdFire PCI Host Bridge (Rev. %d) detected:"
888 + "MEMBase %x,MEMLen %x,IOBase %x,IOLen %x\n",
889 + revision, HOST_MEM_BASE, PCI_MEM_SIZE - 1, 0, PCI_IO_SIZE - 1);
890 +
891 + /* Setup bus info structure. */
892 + memset(&bus, 0, sizeof (struct pci_bus_info));
893 +
894 + /* Request intiator memory resource */
895 + bus.mem_space.start = PCI_MEM_BASE;//HOST_MEM_BASE;
896 + bus.mem_space.end = bus.mem_space.start + PCI_MEM_SIZE - 1;
897 + bus.mem_space.name = "PCI Bus #0";
898 + if (request_resource(&iomem_resource, &bus.mem_space) != 0)
899 + {
900 + printk("Failed to request bridge iomem resource\n");
901 + return NULL;
902 + }
903 +
904 + /* Request intiator memory resource */
905 + bus.io_space.start = 0;
906 + bus.io_space.end = bus.io_space.start + PCI_IO_SIZE - 1;
907 + bus.io_space.name = "PCI Bus #0";
908 + if (request_resource(&ioport_resource, &bus.io_space) != 0)
909 + {
910 + printk("Failed to request bridge ioport resource\n");
911 + return NULL;
912 + }
913 +
914 + /* Set up the arbiter */
915 + MCF_PCIARB_PACR = 0 /*MCF_PCIARB_PACR_PKMD*/
916 + | MCF_PCIARB_PACR_INTMPRI
917 + | MCF_PCIARB_PACR_INTMINTEN
918 + | MCF_PCIARB_PACR_EXTMPRI(0x1F)
919 + | MCF_PCIARB_PACR_EXTMINTEN(0x1F);
920 +
921 + /* GNT and REQ */
922 + MCF_PAR_PCIBG = 0x3FF;
923 + MCF_PAR_PCIBR = 0x3FF;
924 +
925 + /* Enable bus mastering, memory access and MWI */
926 + MCF_PCISCR = MCF_PCISCR_B | MCF_PCISCR_M | MCF_PCISCR_MW;
927 +
928 + /* Setup burst parameters */
929 + MCF_PCICR1 = MCF_PCICR1_LATTIMER(32) |
930 + MCF_PCICR1_CACHELINESIZE(PCI_CACHE_LINE);
931 +
932 + MCF_PCICR2 = 0;
933 + /*MCF_PCICR2_MINGNT(PCI_MINGNT) |
934 + MCF_PCICR2_MAXLAT(PCI_MAXLAT);
935 + */
936 + /* Turn on error signaling */
937 + MCF_PCIICR = MCF_PCIICR_TAE | MCF_PCIICR_IAE | PCI_RETRIES;
938 + MCF_PCIGSCR |= MCF_PCIGSCR_SEE;
939 + /*
940 + * Configure Initiator Windows
941 + * Window 0: 128M PCI Memory @ HOST_MEM_BASE, 1:1 mapping
942 + * Window 1: 64K I/O Memory @ HOST_IO_BASE, 1:0 mapping
943 + */
944 + MCF_PCIIW0BTAR = WxBAR(HOST_MEM_BASE, PCI_MEM_BASE, PCI_MEM_SIZE);
945 + MCF_PCIIW1BTAR = WxBAR(HOST_IO_BASE, PCI_IO_BASE_ADDR, PCI_IO_SIZE);
946 +
947 + MCF_PCIIWCR = MCF_PCIIWCR_WINCTRL1_IO |
948 + MCF_PCIIWCR_WINCTRL0_MEMRDLINE;
949 +
950 + /* Target PCI DMA Windows */
951 + MCF_PCIBAR1 = PCI_DMA_BASE;
952 + MCF_PCITBATR1 = HOST_DMA_BASE | MCF_PCITBATR1_EN;
953 + MCF_PCIBAR0 = MCF_RAMBAR0;;
954 + MCF_PCITBATR0 = MCF_RAMBAR0 | MCF_PCITBATR0_EN;
955 + DBG("PCI TCR %x,MCF_PCIBAR1 %x,MCF_PCITBATR1 %x."
956 + "MCF_PCIBAR0 %x,MCF_PCITBATR9 %x\n", MCF_PCITCR, MCF_PCIBAR1,
957 + MCF_PCITBATR1, MCF_PCIBAR0, MCF_PCITBATR0);
958 + /* Enable internal PCI controller interrupts */
959 + MCF_ICR(ISC_PCI_XLB) = ILP_PCI_XLB;
960 + /*request_irq(64+ISC_PCI_XLB, xlb_interrupt,
961 + SA_INTERRUPT, "PCI XL Bus", (void*)-1);
962 + enable_irq (64+ISC_PCI_XLB);
963 + */
964 + if(request_irq(64+ISC_PCI_XLB, xlb_interrupt,
965 + IRQF_DISABLED, "PCI XL Bus", (void*)-1)){
966 + printk("Cannot allocate ISC_PCI_XLB IRQ\n");
967 + return (struct pci_bus_info *)-EBUSY;
968 + }
969 +
970 + MCF_ICR(ISC_PCI_ARB) = ILP_PCI_ARB;
971 + /*request_irq(64+ISC_PCI_ARB, arb_interrupt,
972 + SA_INTERRUPT, "PCI Arbiter", (void*)-1);
973 + enable_irq (64+ISC_PCI_ARB);
974 + */
975 + if(request_irq(64+ISC_PCI_ARB, arb_interrupt,
976 + IRQF_DISABLED, "PCI Arbiter", (void*)-1)){
977 + printk("Cannot allocate ISC_PCI_ARB IRQ\n");
978 + return (struct pci_bus_info *)-EBUSY;
979 + }
980 +
981 + /* Set slots interrupt setting */
982 + for (i = 0; i < N_IRQS; i++)
983 + {
984 + /* Set trailing edge for PCI interrupts */
985 + MCF_EPPAR &= ~MCF_EPPAR_EPPA(irq_lines[i], 0x3);
986 + if (irq_lines[i] == 5)
987 + MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i], MCF_EPPAR_EPPAx_FALLING);
988 + else
989 + MCF_EPPAR |= MCF_EPPAR_EPPA(irq_lines[i], 0/*MCF_EPPAR_EPPAx_FALLING*/);
990 + /* Turn on irq line in eport */
991 + MCF_EPIER |= MCF_EPIER_EPIE(irq_lines[i]);
992 +
993 + /* Enable irq in gpio */
994 + if (irq_lines[i] == 5)
995 + MCF_PAR_FECI2CIRQ |= 1;
996 +
997 + if (irq_lines[i] == 6)
998 + MCF_PAR_FECI2CIRQ |= 2;
999 +
1000 + /* Register external interrupt handlers */
1001 + sprintf(irq_name[i], "PCI IRQ%d", irq_lines[i]);
1002 + /*request_irq(64 + irq_lines[i], eint_handler,
1003 + SA_SHIRQ, irq_name[i], (void*)-1);
1004 + enable_irq(64 + irq_lines[i]);*/
1005 + if(request_irq(64 + irq_lines[i], eint_handler,
1006 + IRQF_SHARED, irq_name[i], (void*)-1)){
1007 + printk("Cannot allocate irq_lines[%d] IRQ\n", irq_lines[i]);
1008 + return (struct pci_bus_info *)-EBUSY;
1009 + }
1010 + }
1011 +
1012 + /* Clear PCI Reset and wait for devices to reset */
1013 + MCF_PCIGSCR &= ~MCF_PCIGSCR_PR;
1014 + schedule_timeout((5 * HZ) / 10);
1015 + /* Remap initiator windows (should be 1:1 to the physical memory) */
1016 + pci_mem_va = (int) ioremap_nocache(HOST_MEM_BASE, PCI_MEM_SIZE + PCI_IO_SIZE);
1017 +#if 1
1018 + printk("%s: MEMBase_phy %x, Virt %x, len %x\n",__FUNCTION__,
1019 + HOST_MEM_BASE,pci_mem_va,PCI_MEM_SIZE + PCI_IO_SIZE);
1020 +#endif
1021 + BUG_ON(pci_mem_va != HOST_MEM_BASE);
1022 +
1023 + /* Setup bios32 and pci bus driver callbacks */
1024 + bus.m68k_pci_ops = &bus_ops;
1025 + bus.fixup = coldfire_fixup;
1026 + bus.conf_device = configure_device;
1027 +
1028 + return &bus;
1029 +}
1030 +
1031 --- a/arch/m68k/kernel/Makefile
1032 +++ b/arch/m68k/kernel/Makefile
1033 @@ -12,6 +12,9 @@ ifndef CONFIG_COLDFIRE
1034 obj-$(CONFIG_PCI) += bios32.o
1035 else # CONFIG_COLDFIRE
1036 extra-y := ../coldfire/head.o vmlinux.lds
1037 +ifdef CONFIG_M547X_8X
1038 + obj-$(CONFIG_PCI) += bios32_mcf548x.o
1039 +endif
1040 endif
1041 endif
1042
1043 --- /dev/null
1044 +++ b/arch/m68k/kernel/bios32_mcf548x.c
1045 @@ -0,0 +1,631 @@
1046 +/*
1047 + * bios32.c - PCI BIOS functions for m68k systems.
1048 + *
1049 + * Written by Wout Klaren.
1050 + *
1051 + * Based on the DEC Alpha bios32.c by Dave Rusling and David Mosberger.
1052 + */
1053 +#include <linux/init.h>
1054 +#include <linux/kernel.h>
1055 +
1056 +#if 0
1057 +# define DBG_DEVS(args) printk args
1058 +#else
1059 +# define DBG_DEVS(args)
1060 +#endif
1061 +
1062 +#ifdef CONFIG_PCI
1063 +
1064 +/*
1065 + * PCI support for Linux/m68k. Currently only the Hades is supported.
1066 + *
1067 + * The support for PCI bridges in the DEC Alpha version has
1068 + * been removed in this version.
1069 + */
1070 +
1071 +#include <linux/pci.h>
1072 +#include <linux/slab.h>
1073 +#include <linux/mm.h>
1074 +
1075 +#include <asm/io.h>
1076 +#include <asm/pci.h>
1077 +#include <asm/uaccess.h>
1078 +
1079 +#define KB 1024
1080 +#define MB (1024*KB)
1081 +#define GB (1024*MB)
1082 +
1083 +#define MAJOR_REV 0
1084 +#define MINOR_REV 5
1085 +
1086 +/*
1087 + * Align VAL to ALIGN, which must be a power of two.
1088 + */
1089 +
1090 +#define MAX(val1, val2) (((val1) > (val2)) ? val1 : val2)
1091 +
1092 +/*
1093 + * Offsets relative to the I/O and memory base addresses from where resources
1094 + * are allocated.
1095 + */
1096 +
1097 +#ifdef CONFIG_COLDFIRE
1098 +#define IO_ALLOC_OFFSET 0x00000100
1099 +#define MEM_ALLOC_OFFSET 0x00000000
1100 +#else /* CONFIG_COLDFIRE */
1101 +#define IO_ALLOC_OFFSET 0x00004000
1102 +#define MEM_ALLOC_OFFSET 0x04000000
1103 +#endif /* CONFIG_COLDFIRE */
1104 +
1105 +/*
1106 + * Declarations of hardware specific initialisation functions.
1107 + */
1108 +
1109 +extern struct pci_bus_info *init_hades_pci(void);
1110 +
1111 +/*
1112 + * Bus info structure of the PCI bus. A pointer to this structure is
1113 + * put in the sysdata member of the pci_bus structure.
1114 + */
1115 +
1116 +static struct pci_bus_info *bus_info;
1117 +
1118 +static int pci_modify = 1; /* If set, layout the PCI bus ourself. */
1119 +static int skip_vga; /* If set do not modify base addresses
1120 + of vga cards.*/
1121 +static int disable_pci_burst; /* If set do not allow PCI bursts. */
1122 +
1123 +static unsigned int io_base;
1124 +static unsigned int mem_base;
1125 +
1126 +/*
1127 + * static void disable_dev(struct pci_dev *dev)
1128 + *
1129 + * Disable PCI device DEV so that it does not respond to I/O or memory
1130 + * accesses.
1131 + *
1132 + * Parameters:
1133 + *
1134 + * dev - device to disable.
1135 + */
1136 +
1137 +static void __init disable_dev(struct pci_dev *dev)
1138 +{
1139 + unsigned short cmd;
1140 +
1141 + if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
1142 + (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
1143 + (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga)
1144 + return;
1145 +
1146 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
1147 +
1148 + cmd &= (~PCI_COMMAND_IO & ~PCI_COMMAND_MEMORY & ~PCI_COMMAND_MASTER);
1149 + pci_write_config_word(dev, PCI_COMMAND, cmd);
1150 +}
1151 +
1152 +/* Stolen from pcibios_enable_resources/i386 */
1153 +int pcibios_enable_device(struct pci_dev *dev, int mask)
1154 +{
1155 + u16 cmd, old_cmd;
1156 + int idx;
1157 + struct resource *r;
1158 +
1159 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
1160 + old_cmd = cmd;
1161 + for(idx=0; idx<6; idx++) {
1162 + /* Only set up the requested stuff */
1163 + if (!(mask & (1<<idx)))
1164 + continue;
1165 +
1166 + r = &dev->resource[idx];
1167 + if (!r->start && r->end) {
1168 + printk("PCI: Device %s not available because"
1169 + " of resource collisions\n", dev->dev.bus_id);
1170 + return -EINVAL;
1171 + }
1172 + if (r->flags & IORESOURCE_IO)
1173 + cmd |= PCI_COMMAND_IO;
1174 + if (r->flags & IORESOURCE_MEM)
1175 + cmd |= PCI_COMMAND_MEMORY;
1176 + }
1177 + if (dev->resource[PCI_ROM_RESOURCE].start)
1178 + cmd |= PCI_COMMAND_MEMORY;
1179 + if (cmd != old_cmd) {
1180 + printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->dev.bus_id, old_cmd, cmd);
1181 + pci_write_config_word(dev, PCI_COMMAND, cmd);
1182 + }
1183 + return 0;
1184 +}
1185 +
1186 +/*
1187 + * static void layout_dev(struct pci_dev *dev)
1188 + *
1189 + * Layout memory and I/O for a device.
1190 + *
1191 + * Parameters:
1192 + *
1193 + * device - device to layout memory and I/O for.
1194 + */
1195 +
1196 +static void __init layout_dev(struct pci_dev *dev)
1197 +{
1198 + unsigned short cmd;
1199 + unsigned int base, mask, size, reg;
1200 + unsigned int alignto;
1201 + int i;
1202 +
1203 + /*
1204 + * Skip video cards if requested.
1205 + */
1206 + if (((dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA) ||
1207 + (dev->class >> 8 == PCI_CLASS_DISPLAY_VGA) ||
1208 + (dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)) && skip_vga){
1209 + printk("%s: VGA\n",__FUNCTION__);
1210 + return;
1211 + }
1212 + pci_read_config_word(dev, PCI_COMMAND, &cmd);
1213 +
1214 + for (reg = PCI_BASE_ADDRESS_0, i = 0; reg <= PCI_BASE_ADDRESS_5; reg += 4, i++)
1215 + {
1216 + /*
1217 + * Figure out how much space and of what type this
1218 + * device wants.
1219 + */
1220 +
1221 + pci_write_config_dword(dev, reg, 0xffffffff);
1222 + pci_read_config_dword(dev, reg, &base);
1223 + if (!base)
1224 + {
1225 + /* this base-address register is unused */
1226 + dev->resource[i].start = 0;
1227 + dev->resource[i].end = 0;
1228 + dev->resource[i].flags = 0;
1229 + continue;
1230 + }
1231 +
1232 + /*
1233 + * We've read the base address register back after
1234 + * writing all ones and so now we must decode it.
1235 + */
1236 +
1237 + if (base & PCI_BASE_ADDRESS_SPACE_IO)
1238 + {
1239 + /*
1240 + * I/O space base address register.
1241 + */
1242 +
1243 + cmd |= PCI_COMMAND_IO;
1244 +
1245 + base &= PCI_BASE_ADDRESS_IO_MASK;
1246 + mask = (~base << 1) | 0x1;
1247 + size = (mask & base) & 0xffffffff;
1248 +
1249 + /*
1250 + * Align to multiple of size of minimum base.
1251 + */
1252 +
1253 +#ifdef CONFIG_COLDFIRE
1254 + alignto = MAX(PAGE_SIZE, size) ;
1255 +#else /* CONFIG_COLDFIRE */
1256 + alignto = MAX(0x040, size) ;
1257 +#endif /* CONFIG_COLDFIRE */
1258 + base = ALIGN(io_base, alignto);
1259 + io_base = base + size;
1260 + pci_write_config_dword(dev, reg, base | PCI_BASE_ADDRESS_SPACE_IO);
1261 +
1262 + dev->resource[i].start = base;
1263 + dev->resource[i].end = dev->resource[i].start + size - 1;
1264 + dev->resource[i].flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
1265 +
1266 + DBG_DEVS(("layout_dev: IO address: %x\n", base));
1267 + }
1268 + else
1269 + {
1270 + unsigned int type;
1271 +
1272 + /*
1273 + * Memory space base address register.
1274 + */
1275 +
1276 + cmd |= PCI_COMMAND_MEMORY;
1277 + type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
1278 + base &= PCI_BASE_ADDRESS_MEM_MASK;
1279 + mask = (~base << 1) | 0x1;
1280 + size = (mask & base) & 0xffffffff;
1281 + switch (type)
1282 + {
1283 + case PCI_BASE_ADDRESS_MEM_TYPE_32:
1284 + case PCI_BASE_ADDRESS_MEM_TYPE_64:
1285 + break;
1286 +
1287 + case PCI_BASE_ADDRESS_MEM_TYPE_1M:
1288 + printk("bios32 WARNING: slot %d, function %d "
1289 + "requests memory below 1MB---don't "
1290 + "know how to do that.\n",
1291 + PCI_SLOT(dev->devfn),
1292 + PCI_FUNC(dev->devfn));
1293 + continue;
1294 + }
1295 + DBG_DEVS(("%s MEM: base %x,type %x,mask %x,size %x\n",
1296 + __FUNCTION__, base, type, mask, size));
1297 + /*
1298 + * Align to multiple of size of minimum base.
1299 + */
1300 +
1301 + alignto = max_t(unsigned int, 0x1000, size);
1302 + base = ALIGN(mem_base, alignto);
1303 + mem_base = base + size;
1304 + pci_write_config_dword(dev, reg, base);
1305 +
1306 + dev->resource[i].start = base;
1307 + dev->resource[i].end = dev->resource[i].start + size - 1;
1308 + dev->resource[i].flags = IORESOURCE_MEM;
1309 + DBG_DEVS(("%s MEM :base %x,size %x\n",
1310 + __FUNCTION__, base, size));
1311 + if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
1312 + {
1313 + /*
1314 + * 64-bit address, set the highest 32 bits
1315 + * to zero.
1316 + */
1317 +
1318 + reg += 4;
1319 + pci_write_config_dword(dev, reg, 0);
1320 +
1321 + i++;
1322 + dev->resource[i].start = 0;
1323 + dev->resource[i].end = 0;
1324 + dev->resource[i].flags = 0;
1325 + printk("%s:type == 64\n",__FUNCTION__);
1326 + }
1327 + }
1328 + }
1329 +
1330 + /*
1331 + * Enable device:
1332 + */
1333 +
1334 + if (dev->class >> 8 == PCI_CLASS_NOT_DEFINED ||
1335 + dev->class >> 8 == PCI_CLASS_NOT_DEFINED_VGA ||
1336 + dev->class >> 8 == PCI_CLASS_DISPLAY_VGA ||
1337 + dev->class >> 8 == PCI_CLASS_DISPLAY_XGA)
1338 + {
1339 + /*
1340 + * All of these (may) have I/O scattered all around
1341 + * and may not use i/o-base address registers at all.
1342 + * So we just have to always enable I/O to these
1343 + * devices.
1344 + */
1345 + cmd |= PCI_COMMAND_IO;
1346 + }
1347 +
1348 + pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MASTER);
1349 +
1350 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, (disable_pci_burst) ? 0 : 32);
1351 +
1352 + if (bus_info != NULL)
1353 + bus_info->conf_device(dev); /* Machine dependent configuration. */
1354 +
1355 + printk(KERN_INFO "layout_dev: bus %d slot 0x%x VID 0x%x DID 0x%x class 0x%x\n",
1356 + dev->bus->number, PCI_SLOT(dev->devfn),
1357 + dev->vendor, dev->device, dev->class);
1358 +}
1359 +
1360 +/*
1361 + * static void layout_bus(struct pci_bus *bus)
1362 + *
1363 + * Layout memory and I/O for all devices on the given bus.
1364 + *
1365 + * Parameters:
1366 + *
1367 + * bus - bus.
1368 + */
1369 +
1370 +static void __init layout_bus(struct pci_bus *bus)
1371 +{
1372 + unsigned int bio, bmem;
1373 + struct pci_dev *dev;
1374 +
1375 + DBG_DEVS(("layout_bus: starting bus %d\n", bus->number));
1376 +
1377 + if (list_empty(&bus->devices) && list_empty(&bus->children))
1378 + return;
1379 +
1380 + /*
1381 + * Align the current bases on appropriate boundaries (4K for
1382 + * IO and 1MB for memory).
1383 + */
1384 +
1385 + bio = io_base = ALIGN(io_base, 4*KB);
1386 + bmem = mem_base = ALIGN(mem_base, 1*MB);
1387 +
1388 + /*
1389 + * PCI devices might have been setup by a PCI BIOS emulation
1390 + * running under TOS. In these cases there is a
1391 + * window during which two devices may have an overlapping
1392 + * address range. To avoid this causing trouble, we first
1393 + * turn off the I/O and memory address decoders for all PCI
1394 + * devices. They'll be re-enabled only once all address
1395 + * decoders are programmed consistently.
1396 + */
1397 +
1398 + DBG_DEVS(("layout_bus: disable_dev for bus %d\n", bus->number));
1399 +
1400 +#ifdef NL_ORIGINAL
1401 + for (dev = bus->devices; dev; dev = dev->sibling)
1402 +#else
1403 + dev = NULL;
1404 + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
1405 +#endif
1406 + {
1407 + if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
1408 + (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
1409 + disable_dev(dev);
1410 + }
1411 +
1412 + /*
1413 + * Allocate space to each device:
1414 + */
1415 +
1416 + DBG_DEVS(("layout_bus: starting bus %d devices\n", bus->number));
1417 +
1418 +#ifdef NL_ORIGINAL
1419 + for (dev = bus->devices; dev; dev = dev->sibling)
1420 +#else
1421 + dev = NULL;
1422 + while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
1423 +#endif
1424 + {
1425 + if ((dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) ||
1426 + (dev->class >> 8 == PCI_CLASS_BRIDGE_PCMCIA))
1427 + layout_dev(dev);
1428 + }
1429 +
1430 + DBG_DEVS(("layout_bus: bus %d finished\n", bus->number));
1431 +}
1432 +
1433 +/*
1434 + * static void pcibios_fixup(void)
1435 + *
1436 + * Layout memory and I/O of all devices on the PCI bus if 'pci_modify' is
1437 + * true. This might be necessary because not every m68k machine with a PCI
1438 + * bus has a PCI BIOS. This function should be called right after
1439 + * pci_scan_bus() in pcibios_init().
1440 + */
1441 +
1442 +static void __init pcibios_fixup(void)
1443 +{
1444 + DBG_DEVS(("%s\n", __FUNCTION__));
1445 + if (pci_modify)
1446 + {
1447 + /*
1448 + * Set base addresses for allocation of I/O and memory space.
1449 + */
1450 +
1451 + io_base = bus_info->io_space.start + IO_ALLOC_OFFSET;
1452 + mem_base = bus_info->mem_space.start + MEM_ALLOC_OFFSET;
1453 +
1454 + /*
1455 + * Scan the tree, allocating PCI memory and I/O space.
1456 + */
1457 +
1458 +#ifdef NL_ORIGINAL
1459 + layout_bus(pci_bus_b(pci_root.next));
1460 +#else
1461 + layout_bus(pci_bus_b(pci_root_buses.next));
1462 +#endif
1463 + }
1464 +
1465 + /*
1466 + * Fix interrupt assignments, etc.
1467 + */
1468 +
1469 + bus_info->fixup(pci_modify);
1470 +}
1471 +
1472 +/*
1473 + * static void pcibios_claim_resources(struct pci_bus *bus)
1474 + *
1475 + * Claim all resources that are assigned to devices on the given bus.
1476 + *
1477 + * Parameters:
1478 + *
1479 + * bus - bus.
1480 + */
1481 +
1482 +static void __init pcibios_claim_resources(struct pci_bus *bus)
1483 +{
1484 + struct pci_dev *dev;
1485 + int i;
1486 + DBG_DEVS(("%s\n", __FUNCTION__));
1487 +#ifdef NL_ORIGINAL
1488 + while (bus)
1489 +#else
1490 + while ((bus = pci_find_next_bus(bus)) != NULL)
1491 +#endif
1492 + {
1493 +
1494 +#ifdef NL_ORIGINAL
1495 + for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
1496 +#else
1497 + dev = NULL;
1498 + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
1499 +#endif
1500 + {
1501 + for (i = 0; i < PCI_NUM_RESOURCES; i++)
1502 + {
1503 + struct resource *r = &dev->resource[i];
1504 + struct resource *pr;
1505 + struct pci_bus_info *bus_info =
1506 + (struct pci_bus_info *) dev->sysdata;
1507 +
1508 + if ((r->start == 0) || (r->parent != NULL))
1509 + continue;
1510 +
1511 +#ifdef CONFIG_COLDFIRE
1512 + if (dev->class >> 16 == PCI_BASE_CLASS_BRIDGE)
1513 + continue;
1514 +#endif /* CONFIG_COLDFIRE */
1515 +#if 1
1516 + if (r->flags & IORESOURCE_IO)
1517 + pr = &bus_info->io_space;
1518 + else
1519 + pr = &bus_info->mem_space;
1520 +#else
1521 + if (r->flags & IORESOURCE_IO)
1522 + pr = &ioport_resource;
1523 + else
1524 + pr = &iomem_resource;
1525 +#endif
1526 + if (request_resource(pr, r) < 0)
1527 + {
1528 +#ifdef NL_ORIGINAL
1529 + DBG_DEVS(("PCI: Address space collision on "
1530 + "region %d of device %s\n", i, dev->name));
1531 +#else
1532 + printk("PCI: Address space collision on region %d of device %s\n", i, dev->dev.bus_id);
1533 +#endif
1534 + }
1535 + }
1536 + }
1537 +
1538 +#ifdef NL_ORIGINAL
1539 + if (bus->children)
1540 + pcibios_claim_resources(bus->children);
1541 +#else
1542 + if (!list_empty(&bus->children))
1543 + pcibios_claim_resources(pci_bus_b(bus->children.next));
1544 +#endif
1545 +
1546 +#ifdef NL_ORIGINAL
1547 + bus = bus->next;
1548 +#endif
1549 + }
1550 +}
1551 +
1552 +/*
1553 + * int pcibios_assign_resource(struct pci_dev *dev, int i)
1554 + *
1555 + * Assign a new address to a PCI resource.
1556 + *
1557 + * Parameters:
1558 + *
1559 + * dev - device.
1560 + * i - resource.
1561 + *
1562 + * Result: 0 if successful.
1563 + */
1564 +
1565 +int __init pcibios_assign_resource(struct pci_dev *dev, int i)
1566 +{
1567 + struct resource *r = &dev->resource[i];
1568 + struct resource *pr = pci_find_parent_resource(dev, r);
1569 + unsigned long size = r->end + 1;
1570 + DBG_DEVS(("%s:IO_ALLOC_OFFSET %x\n", __FUNCTION__, IO_ALLOC_OFFSET));
1571 + if (!pr)
1572 + return -EINVAL;
1573 +
1574 + if (r->flags & IORESOURCE_IO)
1575 + {
1576 + DBG_DEVS(("%s:IORESOURCE_IO:start %x, size %lx\n",
1577 + __FUNCTION__, bus_info->io_space.start, size));
1578 + if (size > 0x100)
1579 + return -EFBIG;
1580 +
1581 +#ifdef NL_ORIGINAL
1582 + if (allocate_resource(pr, r, size, bus_info->io_space.start +
1583 + IO_ALLOC_OFFSET, bus_info->io_space.end, 1024))
1584 +#else
1585 + if (allocate_resource(pr, r, size, bus_info->io_space.start +
1586 + IO_ALLOC_OFFSET, bus_info->io_space.end, 1024, NULL, NULL))
1587 +#endif
1588 + return -EBUSY;
1589 + }
1590 + else
1591 + {
1592 + DBG_DEVS(("%s:IORESOURCE_MEM:start %x, size %lx\n",
1593 + __FUNCTION__, bus_info->mem_space.start, size));
1594 +#ifdef NL_ORIGINAL
1595 + if (allocate_resource(pr, r, size, bus_info->mem_space.start +
1596 + MEM_ALLOC_OFFSET, bus_info->mem_space.end, size))
1597 +#else
1598 + if (allocate_resource(pr, r, size, bus_info->io_space.start +
1599 + IO_ALLOC_OFFSET, bus_info->io_space.end, 1024, NULL, NULL))
1600 +#endif
1601 + return -EBUSY;
1602 + }
1603 +
1604 + if (i < 6)
1605 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, r->start);
1606 +
1607 + return 0;
1608 +}
1609 +
1610 +void pcibios_fixup_bus(struct pci_bus *bus)
1611 +{
1612 + struct pci_dev *dev;
1613 + void *sysdata;
1614 +
1615 + sysdata = (bus->parent) ? bus->parent->sysdata : bus->sysdata;
1616 +
1617 +#ifdef NL_ORIGINAL
1618 + for (dev = bus->devices; (dev != NULL); dev = dev->sibling)
1619 +#else
1620 + dev = NULL;
1621 + while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
1622 +#endif
1623 + dev->sysdata = sysdata;
1624 +}
1625 +
1626 +int __init pcibios_init(void)
1627 +{
1628 + printk("Linux/m68k PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
1629 +
1630 + bus_info = NULL;
1631 +#ifdef CONFIG_COLDFIRE
1632 + bus_info = init_coldfire_pci();
1633 +#endif /* CONFIG_COLDFIRE */
1634 +#ifdef CONFIG_HADES
1635 + if (MACH_IS_HADES)
1636 + bus_info = init_hades_pci();
1637 +#endif
1638 + if (bus_info != NULL)
1639 + {
1640 + printk("PCI: Probing PCI hardware\n");
1641 + pci_scan_bus(0, bus_info->m68k_pci_ops, bus_info);
1642 + pcibios_fixup();
1643 +#ifdef NL_ORIGINAL
1644 + pcibios_claim_resources(pci_root);
1645 +#else
1646 + pcibios_claim_resources(pci_bus_b(pci_root_buses.next));
1647 +#endif
1648 + }
1649 + else
1650 + printk("PCI: No PCI bus detected\n");
1651 + return 0;
1652 +}
1653 +
1654 +subsys_initcall(pcibios_init);
1655 +
1656 +char * pcibios_setup(char *str)
1657 +{
1658 + if (!strcmp(str, "nomodify"))
1659 + {
1660 + pci_modify = 0;
1661 + return NULL;
1662 + }
1663 + else if (!strcmp(str, "skipvga"))
1664 + {
1665 + skip_vga = 1;
1666 + return NULL;
1667 + }
1668 + else if (!strcmp(str, "noburst"))
1669 + {
1670 + disable_pci_burst = 1;
1671 + return NULL;
1672 + }
1673 +
1674 + return str;
1675 +}
1676 +#endif /* CONFIG_PCI */
1677 --- a/arch/m68k/kernel/dma.c
1678 +++ b/arch/m68k/kernel/dma.c
1679 @@ -11,13 +11,24 @@
1680 #include <linux/kernel.h>
1681 #include <linux/scatterlist.h>
1682 #include <linux/vmalloc.h>
1683 -
1684 +#include <linux/pci.h>
1685 #include <asm/pgalloc.h>
1686
1687 void *dma_alloc_coherent(struct device *dev, size_t size,
1688 dma_addr_t *handle, gfp_t flag)
1689 {
1690 -#ifndef CONFIG_M5445X
1691 +#if defined(CONFIG_M547X_8X) | defined(CONFIG_M54455)
1692 + /*
1693 + * On the M5445x platform the memory allocated with GFP_DMA
1694 + * is guaranteed to be DMA'able.
1695 + */
1696 + void *addr;
1697 +
1698 + size = PAGE_ALIGN(size);
1699 + addr = kmalloc(size, GFP_DMA);
1700 + *handle = virt_to_phys(addr);
1701 + return addr;
1702 +#else
1703 struct page *page, **map;
1704 pgprot_t pgprot;
1705 void *addr;
1706 @@ -56,17 +67,6 @@ void *dma_alloc_coherent(struct device *
1707 kfree(map);
1708
1709 return addr;
1710 -#else
1711 - /*
1712 - * On the M5445x platform the memory allocated with GFP_DMA
1713 - * is guaranteed to be DMA'able.
1714 - */
1715 - void *addr;
1716 -
1717 - size = PAGE_ALIGN(size);
1718 - addr = kmalloc(size, GFP_DMA);
1719 - *handle = virt_to_phys(addr);
1720 - return addr;
1721 #endif
1722 }
1723 EXPORT_SYMBOL(dma_alloc_coherent);
1724 @@ -75,10 +75,10 @@ void dma_free_coherent(struct device *de
1725 void *addr, dma_addr_t handle)
1726 {
1727 pr_debug("dma_free_coherent: %p, %x\n", addr, handle);
1728 -#ifndef CONFIG_M5445X
1729 - vfree(addr);
1730 -#else
1731 +#if defined(CONFIG_M547X_8X) | defined(CONFIG_M54455)
1732 kfree(addr);
1733 +#else
1734 + vfree(addr);
1735 #endif
1736 }
1737 EXPORT_SYMBOL(dma_free_coherent);
1738 --- a/arch/m68k/mm/kmap.c
1739 +++ b/arch/m68k/mm/kmap.c
1740 @@ -153,6 +153,10 @@ void __iomem *__ioremap(unsigned long ph
1741 */
1742 return (void __iomem *)physaddr;
1743 }
1744 + if ((physaddr >= 0xd0000000) && (physaddr + size < 0xd800ffff)) {
1745 + printk("ioremap:PCI 0x%lx,0x%lx(%d) - PCI area hit\n", physaddr, size, cacheflag);
1746 + return (void *)physaddr;
1747 + }
1748 #endif
1749
1750 #ifdef DEBUG
1751 @@ -284,7 +288,12 @@ void __iounmap(void *addr, unsigned long
1752 pgd_t *pgd_dir;
1753 pmd_t *pmd_dir;
1754 pte_t *pte_dir;
1755 -
1756 +#ifdef CONFIG_M547X_8X
1757 + if ((addr >= (void*)0xd0000000) && (addr + size < (void*)0xd800ffff)) {
1758 + printk("%s: PCI address\n",__FUNCTION__);
1759 + return;
1760 + }
1761 +#endif
1762 while ((long)size > 0) {
1763 pgd_dir = pgd_offset_k(virtaddr);
1764 if (pgd_bad(*pgd_dir)) {
1765 --- a/drivers/pci/access.c
1766 +++ b/drivers/pci/access.c
1767 @@ -23,6 +23,7 @@ static DEFINE_SPINLOCK(pci_lock);
1768 #define PCI_word_BAD (pos & 1)
1769 #define PCI_dword_BAD (pos & 3)
1770
1771 +#ifdef NL_ORIGINAL
1772 #define PCI_OP_READ(size,type,len) \
1773 int pci_bus_read_config_##size \
1774 (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
1775 @@ -37,7 +38,20 @@ int pci_bus_read_config_##size \
1776 spin_unlock_irqrestore(&pci_lock, flags); \
1777 return res; \
1778 }
1779 -
1780 +#else /* NL_ORIGINAL */
1781 +#define PCI_OP_READ(size,type,len) \
1782 +int pci_bus_read_config_##size \
1783 + (struct pci_bus *bus, unsigned int devfn, int pos, type *value) \
1784 +{ \
1785 + int res; \
1786 + unsigned long flags; \
1787 + if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
1788 + spin_lock_irqsave(&pci_lock, flags); \
1789 + res = bus->ops->read(bus, devfn, pos, len, (u32 *)value); \
1790 + spin_unlock_irqrestore(&pci_lock, flags); \
1791 + return res; \
1792 +}
1793 +#endif /* NL_ORIGINAL */
1794 #define PCI_OP_WRITE(size,type,len) \
1795 int pci_bus_write_config_##size \
1796 (struct pci_bus *bus, unsigned int devfn, int pos, type value) \
1797 --- a/drivers/usb/host/Makefile
1798 +++ b/drivers/usb/host/Makefile
1799 @@ -6,7 +6,7 @@ ifeq ($(CONFIG_USB_DEBUG),y)
1800 EXTRA_CFLAGS += -DDEBUG
1801 endif
1802
1803 -obj-$(CONFIG_PCI) += pci-quirks.o
1804 +#obj-$(CONFIG_PCI) += pci-quirks.o
1805
1806 obj-$(CONFIG_USB_EHCI_HCD) += ehci-hcd.o
1807 obj-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o
1808 --- /dev/null
1809 +++ b/include/asm-m68k/5445x_pci.h
1810 @@ -0,0 +1,94 @@
1811 +/*
1812 + * asm-m68k/pci.h - m68k specific PCI declarations.
1813 + *
1814 + * Coldfire Implementation Copyright (c) 2007 Freescale Semiconductor, Inc.
1815 + * Kurt Mahan <kmahan@freescale.com>
1816 + */
1817 +#ifndef _ASM_M68K_5445X_PCI_H
1818 +#define _ASM_M68K_5445x_PCI_H
1819 +
1820 +#ifndef CONFIG_PCI
1821 +/*
1822 + * The PCI address space does equal the physical memory
1823 + * address space. The networking and block device layers use
1824 + * this boolean for bounce buffer decisions.
1825 + */
1826 +#define PCI_DMA_BUS_IS_PHYS (1)
1827 +#else
1828 +#include <asm-generic/pci-dma-compat.h>
1829 +
1830 +/*
1831 + * The PCI address space does equal the physical memory
1832 + * address space. The networking and block device layers use
1833 + * this boolean for bounce buffer decisions.
1834 + */
1835 +#define PCI_DMA_BUS_IS_PHYS (1)
1836 +
1837 +#define PCIBIOS_MIN_IO 0x00004000
1838 +#define PCIBIOS_MIN_MEM 0x02000000
1839 +
1840 +#define pcibios_assign_all_busses() 0
1841 +#define pcibios_scan_all_fns(a, b) 0
1842 +
1843 +static inline void
1844 +pcibios_set_master(struct pci_dev *dev)
1845 +{
1846 + /* no special bus mastering setup handling */
1847 +}
1848 +
1849 +static inline void
1850 +pcibios_penalize_isa_irq(int irq, int active)
1851 +{
1852 + /* no dynamic PCI IRQ allocation */
1853 +}
1854 +
1855 +#if 0
1856 +static inline void
1857 +pcibios_add_platform_entries(struct pci_dev *dev)
1858 +{
1859 + /* no special handling */
1860 +}
1861 +#endif
1862 +
1863 +static inline void
1864 +pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
1865 + struct resource *res)
1866 +{
1867 +#ifdef CONFIG_M54455
1868 + if ((res->start == 0xa0000000) || (res->start == 0xa8000000)) {
1869 + /* HACK! FIX! kludge to fix bridge mapping */
1870 + region->start = res->start & 0x0fffffff;
1871 + region->end = res->end & 0x0fffffff;
1872 + } else {
1873 + region->start = res->start;
1874 + region->end = res->end;
1875 + }
1876 +#else
1877 + region->start = res->start;
1878 + region->end = res->end;
1879 +#endif
1880 +}
1881 +
1882 +static inline void
1883 +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
1884 + struct pci_bus_region *region)
1885 +{
1886 + res->start = region->start;
1887 + res->end = region->end;
1888 +}
1889 +
1890 +static inline struct resource *
1891 +pcibios_select_root(struct pci_dev *pdev, struct resource *res)
1892 +{
1893 + struct resource *root = NULL;
1894 +
1895 + if (res->flags & IORESOURCE_IO)
1896 + root = &ioport_resource;
1897 + if (res->flags & IORESOURCE_MEM)
1898 + root = &iomem_resource;
1899 +
1900 + return root;
1901 +}
1902 +
1903 +#endif /* CONFIG_PCI */
1904 +#endif /* _ASM_M68K_5445X_PCI_H */
1905 --- /dev/null
1906 +++ b/include/asm-m68k/548x_pci.h
1907 @@ -0,0 +1,99 @@
1908 +#ifndef _ASM_M68K_548X_PCI_H
1909 +#define _ASM_M68K_548X_PCI_H
1910 +
1911 +/*
1912 + * asm-m68k/pci_m68k.h - m68k specific PCI declarations.
1913 + *
1914 + * Written by Wout Klaren.
1915 + */
1916 +#include <linux/mm.h>
1917 +#include <asm/scatterlist.h>
1918 +
1919 +#include <asm-generic/pci.h>
1920 +
1921 +struct pci_ops;
1922 +
1923 +/*
1924 + * Structure with hardware dependent information and functions of the
1925 + * PCI bus.
1926 + */
1927 +
1928 +struct pci_bus_info
1929 +{
1930 + /*
1931 + * Resources of the PCI bus.
1932 + */
1933 +
1934 + struct resource mem_space;
1935 + struct resource io_space;
1936 +
1937 + /*
1938 + * System dependent functions.
1939 + */
1940 +
1941 + struct pci_ops *m68k_pci_ops;
1942 +
1943 + void (*fixup)(int pci_modify);
1944 + void (*conf_device)(struct pci_dev *dev);
1945 +};
1946 +
1947 +#define pcibios_assign_all_busses() 0
1948 +#define pcibios_scan_all_fns(a, b) 0
1949 +
1950 +static inline void pcibios_set_master(struct pci_dev *dev)
1951 +{
1952 + /* No special bus mastering setup handling */
1953 +}
1954 +
1955 +static inline void pcibios_penalize_isa_irq(int irq)
1956 +{
1957 + /* We don't do dynamic PCI IRQ allocation */
1958 +}
1959 +
1960 +#ifndef CONFIG_COLDFIRE
1961 +/* The PCI address space does equal the physical memory
1962 + * address space. The networking and block device layers use
1963 + * this boolean for bounce buffer decisions.
1964 + */
1965 +#define PCI_DMA_BUS_IS_PHYS (1)
1966 +
1967 +#define PCIBIOS_MIN_IO 0x00004000
1968 +#define PCIBIOS_MIN_MEM 0x04000000
1969 +
1970 +#else /* !CONFIG_COLDFIRE */
1971 +#include <asm-generic/pci-dma-compat.h>
1972 +#define PCI_DMA_BASE /*0x40000000*/0 /* PCI-DMA window base */
1973 +
1974 +extern struct pci_bus_info *__init init_coldfire_pci(void);
1975 +extern void * pci_alloc_son(struct pci_dev *, size_t,
1976 + dma_addr_t *, int);
1977 +/*
1978 + * The PCI address space equal the virtual memory
1979 + * address space on m547X/m548X.
1980 + */
1981 +#define PCI_DMA_BUS_IS_PHYS (1)
1982 +
1983 +#define PCIBIOS_MIN_IO 0x00000100
1984 +#define PCIBIOS_MIN_MEM 0x02000000
1985 +
1986 +struct scatterlist;
1987 +
1988 +
1989 +/* This is always fine. */
1990 +#define pci_dac_dma_supported(pci_dev, mask) (1)
1991 +
1992 +
1993 +/* These macros should be used after a pci_map_sg call has been done
1994 + * to get bus addresses of each of the SG entries and their lengths.
1995 + * You should only work with the number of sg entries pci_map_sg
1996 + * returns.
1997 + */
1998 +#define sg_dma_address(sg) ((sg)->dma_address)
1999 +#define sg_dma_len(sg) ((sg)->length)
2000 +
2001 +static inline void pcibios_align_resource(void *data, struct resource *res, unsigned long size, unsigned long align)
2002 +{
2003 +}
2004 +
2005 +#endif /* !CONFIG_COLDFIRE*/
2006 +#endif /* _ASM_M68K_548X_PCI_H */
2007 --- a/include/asm-m68k/io.h
2008 +++ b/include/asm-m68k/io.h
2009 @@ -204,6 +204,12 @@ static inline u16 __iomem *isa_mtw(unsig
2010 #define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
2011 #define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
2012
2013 +#ifndef CONFIG_COLDFIRE
2014 +#define isa_readb(p) in_8(isa_mtb(p))
2015 +#define isa_readw(p) (ISA_SEX ? in_be16(isa_mtw(p)) : in_le16(isa_mtw(p)))
2016 +#define isa_writeb(val,p) out_8(isa_mtb(p),(val))
2017 +#define isa_writew(val,p) (ISA_SEX ? out_be16(isa_mtw(p),(val)) : out_le16(isa_mtw(p),(val)))
2018 +#else
2019 #define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
2020 #define isa_readw(p) \
2021 (ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
2022 @@ -212,7 +218,7 @@ static inline u16 __iomem *isa_mtw(unsig
2023 #define isa_writew(val,p) \
2024 (ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
2025 : out_le16(isa_mtw((unsigned long)(p)),(val)))
2026 -
2027 +#endif
2028 static inline void isa_delay(void)
2029 {
2030 switch(ISA_TYPE)
2031 @@ -285,6 +291,29 @@ static inline void isa_delay(void)
2032 #endif /* CONFIG_ISA */
2033
2034 #if defined(CONFIG_PCI)
2035 +#ifdef CONFIG_COLDFIRE
2036 +#define inb_p inb
2037 +#define inw_p inw
2038 +#define inl_p inl
2039 +#define outb_p outb
2040 +#define outw_p outw
2041 +#define outl_p outl
2042 +
2043 +unsigned char pci_inb(long addr);
2044 +unsigned short pci_inw(long addr);
2045 +unsigned long pci_inl(long addr);
2046 +void pci_outb(unsigned char val, long addr);
2047 +void pci_outw(unsigned short val, long addr);
2048 +void pci_outl(unsigned long val, long addr);
2049 +
2050 +void pci_insb(volatile unsigned char* addr, unsigned char* buf, int len);
2051 +void pci_insw(volatile unsigned short* addr, unsigned short* buf, int len);
2052 +void pci_insl(volatile unsigned long* addr, unsigned long* buf, int len);
2053 +
2054 +void pci_outsb(volatile unsigned char* addr, const unsigned char* buf, int len);
2055 +void pci_outsw(volatile unsigned short* addr, const unsigned short* buf, int len);
2056 +void pci_outsl(volatile unsigned long* addr, const unsigned long* buf, int len);
2057 +#endif
2058
2059 #define readl(addr) in_le32(addr)
2060 #define writel(val,addr) out_le32((addr),(val))
2061 @@ -300,6 +329,7 @@ static inline void isa_delay(void)
2062 #define readl_relaxed(addr) readl(addr)
2063
2064 #ifndef CONFIG_ISA
2065 +#ifndef CONFIG_COLDFIRE
2066 #define inb(port) in_8(port)
2067 #define outb(val,port) out_8((port),(val))
2068 #define inw(port) in_le16(port)
2069 @@ -319,6 +349,30 @@ static inline void isa_delay(void)
2070 #define outsl(port, buf, nr) \
2071 raw_outsw_swapw((u16 *)(port), (u16 *)(buf), (nr)<<1)
2072 #else
2073 +#define inb(port) pci_inb(port)
2074 +#define outb(val,port) pci_outb((val),(port))
2075 +#define inw(port) pci_inw(port)
2076 +#define outw(val,port) pci_outw((val),(port))
2077 +#define insb(a,b,c) pci_insb((volatile unsigned char*)a,(unsigned char*)b,c)
2078 +#define insw(a,b,c) pci_insw((volatile unsigned short*)a,(const unsigned short*)b,c)
2079 +#define insl(a,b,c) pci_insl((volatile unsigned long*)a,(const unsigned long*)b,c)
2080 +#define outsb(a,b,c) pci_outsb((volatile unsigned char*)a,(const unsigned char*)b,c)
2081 +#define outsw(a,b,c) pci_outsw((volatile unsigned short*)a,(const unsigned short*)b,c)
2082 +#define outsl(a,b,c) pci_outsl((volatile unsigned long*)a,(const unsigned long*)b,c)
2083 +#define inl(port) pci_inl(port)
2084 +#define outl(val,port) pci_outl((val),(port))
2085 +#endif
2086 +
2087 +#ifndef CONFIG_COLDFIRE
2088 +#define __raw_readb readb
2089 +#define __raw_readw readw
2090 +#define __raw_readl readl
2091 +#define __raw_writeb writeb
2092 +#define __raw_writew writew
2093 +#define __raw_writel writel
2094 +#endif
2095 +
2096 +#else
2097 /*
2098 * kernel with both ISA and PCI compiled in, those have
2099 * conflicting defs for in/out. Simply consider port < 1024
2100 @@ -432,6 +486,15 @@ static inline void memcpy_toio(volatile
2101 #define xlate_dev_kmem_ptr(p) p
2102
2103 #ifdef CONFIG_COLDFIRE
2104 +#define __raw_readb(addr) \
2105 + ({ unsigned char __v = (*(volatile unsigned char *) (addr)); __v; })
2106 +#define __raw_readw(addr) \
2107 + ({ unsigned short __v = (*(volatile unsigned short *) (addr)); __v; })
2108 +#define __raw_readl(addr) \
2109 + ({ unsigned long __v = (*(volatile unsigned long *) (addr)); __v; })
2110 +#define __raw_writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
2111 +#define __raw_writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
2112 +#define __raw_writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
2113
2114 #define memset_io(a, b, c) memset((void *)(a), (b), (c))
2115 #define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
2116 --- /dev/null
2117 +++ b/include/asm-m68k/m5485pci.h
2118 @@ -0,0 +1,330 @@
2119 +/*
2120 + * m5485pci.h -- ColdFire 547x/548x PCI controller support.
2121 + */
2122 +#ifndef __MCF548X_PCI_H__
2123 +#define __MCF548X_PCI_H__
2124 +
2125 +
2126 +/* PCI Type 0 Configuration Registers */
2127 +#define MCF_PCIIDR MCF_REG32(0x000B00) /* PCI Device ID/Vendor ID */
2128 +#define MCF_PCISCR MCF_REG32(0x000B04) /* PCI Status/Command */
2129 +#define MCF_PCICCRIR MCF_REG32(0x000B08) /* PCI Class Code / Revision ID */
2130 +#define MCF_PCICR1 MCF_REG32(0x000B0C) /* PCI Configuration 1 Register */
2131 +#define MCF_PCIBAR0 MCF_REG32(0x000B10) /* PCI Base Address Register 0 */
2132 +#define MCF_PCIBAR1 MCF_REG32(0x000B14) /* PCI Base Address Register 1 */
2133 +#define MCF_PCICCPR MCF_REG32(0x000B28) /* PCI Cardbus CIS Pointer */
2134 +#define MCF_PCISID MCF_REG32(0x000B2C) /* Subsystem ID/Subsystem Vendor ID*/
2135 +#define MCF_PCIERBAR MCF_REG32(0x000B30) /* PCI Expansion ROM */
2136 +#define MCF_PCICPR MCF_REG32(0x000B30) /* PCI Capabilities Pointer */
2137 +#define MCF_PCICR2 MCF_REG32(0x000B3C) /* PCI Configuration Register 2 */
2138 +
2139 +/* General Control/Status Registers */
2140 +#define MCF_PCIGSCR MCF_REG32(0x000B60) /* Global Status/Control Register */
2141 +#define MCF_PCITBATR0 MCF_REG32(0x000B64) /* Target Base Address Translation 0*/
2142 +#define MCF_PCITBATR1 MCF_REG32(0x000B68) /* Target Base Address Translation 1*/
2143 +#define MCF_PCITCR MCF_REG32(0x000B6C) /* Target Control Register */
2144 +#define MCF_PCIIW0BTAR MCF_REG32(0x000B70) /* Initiator Window 0 Base Address */
2145 +#define MCF_PCIIW1BTAR MCF_REG32(0x000B74) /* Initiator Window 1 Base Address */
2146 +#define MCF_PCIIW2BTAR MCF_REG32(0x000B78) /* Initiator Window 2 Base Address */
2147 +#define MCF_PCIIWCR MCF_REG32(0x000B80) /* Initiator Window Configuration */
2148 +#define MCF_PCIICR MCF_REG32(0x000B84) /* Initiator Control Register */
2149 +#define MCF_PCIISR MCF_REG32(0x000B88) /* Initiator Status Register */
2150 +#define MCF_PCICAR MCF_REG32(0x000BF8) /* Configuration Address Register */
2151 +
2152 +/* CommBus FIFO Transmit Interface Registers */
2153 +#define MCF_PCITPSR MCF_REG32(0x008400) /* Tx Packet Size Register */
2154 +#define MCF_PCITSAR MCF_REG32(0x008404) /* Tx Start Address Register */
2155 +#define MCF_PCITTCR MCF_REG32(0x008408) /* Tx Transaction Control Register */
2156 +#define MCF_PCITER MCF_REG32(0x00840C) /* Tx Enables Register */
2157 +#define MCF_PCITNAR MCF_REG32(0x008410) /* Tx Next Address Register */
2158 +#define MCF_PCITLWR MCF_REG32(0x008414) /* Tx Last Word Register */
2159 +#define MCF_PCITDCR MCF_REG32(0x008418) /* Tx Done Counts Register */
2160 +#define MCF_PCITSR MCF_REG32(0x00841C) /* Tx Status Register */
2161 +#define MCF_PCITFDR MCF_REG32(0x008440) /* Tx FIFO Data Register */
2162 +#define MCF_PCITFSR MCF_REG32(0x008444) /* Tx FIFO Status Register */
2163 +#define MCF_PCITFCR MCF_REG32(0x008448) /* Tx FIFO Control Register */
2164 +#define MCF_PCITFAR MCF_REG32(0x00844C) /* Tx FIFO Alarm Register */
2165 +#define MCF_PCITFRPR MCF_REG32(0x008450) /* Tx FIFO Read Pointer Register */
2166 +#define MCF_PCITFWPR MCF_REG32(0x008454) /* Tx FIFO Write Pointer Register */
2167 +
2168 +/* CommBus FIFO Receive Interface Registers */
2169 +#define MCF_PCIRPSR MCF_REG32(0x008480) /* Tx Packet Size Register */
2170 +#define MCF_PCIRSAR MCF_REG32(0x008484) /* Tx Start Address Register */
2171 +#define MCF_PCIRTCR MCF_REG32(0x008488) /* Tx Transaction Control Register */
2172 +#define MCF_PCIRER MCF_REG32(0x00848C) /* Tx Enables Register */
2173 +#define MCF_PCIRNAR MCF_REG32(0x008490) /* Tx Next Address Register */
2174 +#define MCF_PCIRDCR MCF_REG32(0x008498) /* Tx Done Counts Register */
2175 +#define MCF_PCIRSR MCF_REG32(0x00849C) /* Tx Status Register */
2176 +#define MCF_PCIRFDR MCF_REG32(0x0084C0) /* Tx FIFO Data Register */
2177 +#define MCF_PCIRFSR MCF_REG32(0x0084C4) /* Tx FIFO Status Register */
2178 +#define MCF_PCIRFCR MCF_REG32(0x0084C8) /* Tx FIFO Control Register */
2179 +#define MCF_PCIRFAR MCF_REG32(0x0084CC) /* Tx FIFO Alarm Register */
2180 +#define MCF_PCIRFRPR MCF_REG32(0x0084D0) /* Tx FIFO Read Pointer Register */
2181 +#define MCF_PCIRFWPR MCF_REG32(0x0084D4) /* Tx FIFO Write Pointer Register */
2182 +
2183 +/* PCI Arbiter Registers */
2184 +#define MCF_PCIARB_PACR MCF_REG32(0x000C00)
2185 +#define MCF_PCIARB_PASR MCF_REG32(0x000C04)
2186 +
2187 +
2188 +/* Bit definitions and macros for MCF_PCIIDR */
2189 +#define MCF_PCIIDR_VENDORID(x) (((x)&0x0000FFFF)<<0)
2190 +#define MCF_PCIIDR_DEVICEID(x) (((x)&0x0000FFFF)<<16)
2191 +
2192 +/* Bit definitions and macros for MCF_PCISCR */
2193 +#define MCF_PCISCR_M (0x00000002)
2194 +#define MCF_PCISCR_B (0x00000004)
2195 +#define MCF_PCISCR_SP (0x00000008)
2196 +#define MCF_PCISCR_MW (0x00000010)
2197 +#define MCF_PCISCR_PER (0x00000040)
2198 +#define MCF_PCISCR_S (0x00000100)
2199 +#define MCF_PCISCR_F (0x00000200)
2200 +#define MCF_PCISCR_C (0x00100000)
2201 +#define MCF_PCISCR_66M (0x00200000)
2202 +#define MCF_PCISCR_R (0x00400000)
2203 +#define MCF_PCISCR_FC (0x00800000)
2204 +#define MCF_PCISCR_DP (0x01000000)
2205 +#define MCF_PCISCR_DT(x) (((x)&0x00000003)<<25)
2206 +#define MCF_PCISCR_TS (0x08000000)
2207 +#define MCF_PCISCR_TR (0x10000000)
2208 +#define MCF_PCISCR_MA (0x20000000)
2209 +#define MCF_PCISCR_SE (0x40000000)
2210 +#define MCF_PCISCR_PE (0x80000000)
2211 +
2212 +/* Bit definitions and macros for MCF_PCICCRIR */
2213 +#define MCF_PCICCRIR_REVID(x) (((x)&0x000000FF)<<0)
2214 +#define MCF_PCICCRIR_CLASSCODE(x) (((x)&0x00FFFFFF)<<8)
2215 +
2216 +/* Bit definitions and macros for MCF_PCICR1 */
2217 +#define MCF_PCICR1_CACHELINESIZE(x) (((x)&0x0000000F)<<0)
2218 +#define MCF_PCICR1_LATTIMER(x) (((x)&0x000000FF)<<8)
2219 +#define MCF_PCICR1_HEADERTYPE(x) (((x)&0x000000FF)<<16)
2220 +#define MCF_PCICR1_BIST(x) (((x)&0x000000FF)<<24)
2221 +
2222 +/* Bit definitions and macros for MCF_PCIBAR# */
2223 +#define MCF_PCIBAR0_ADDR(x) (((x)&0x00003FFF)<<18)
2224 +#define MCF_PCIBAR1_ADDR(x) (((x)&0x00000003)<<30)
2225 +
2226 +/* Bit definitions and macros for MCF_PCICR2 */
2227 +#define MCF_PCICR2_INTLINE(x) (((x)&0x000000FF)<<0)
2228 +#define MCF_PCICR2_INTPIN(x) (((x)&0x000000FF)<<8)
2229 +#define MCF_PCICR2_MINGNT(x) (((x)&0x000000FF)<<16)
2230 +#define MCF_PCICR2_MAXLAT(x) (((x)&0x000000FF)<<24)
2231 +
2232 +/* Bit definitions and macros for MCF_PCIGSCR */
2233 +#define MCF_PCIGSCR_PR (0x00000001)
2234 +#define MCF_PCIGSCR_SEE (0x00001000)
2235 +#define MCF_PCIGSCR_PEE (0x00002000)
2236 +#define MCF_PCIGSCR_SE (0x10000000)
2237 +#define MCF_PCIGSCR_PE (0x20000000)
2238 +
2239 +/* Bit definitions and macros for MCF_PCITBATR0 */
2240 +#define MCF_PCITBATR0_EN (0x00000001)
2241 +#define MCF_PCITBATR0_BAT0(x) (((x)&0x00003FFF)<<18)
2242 +
2243 +/* Bit definitions and macros for MCF_PCITBATR1 */
2244 +#define MCF_PCITBATR1_EN (0x00000001)
2245 +#define MCF_PCITBATR1_BAT1(x) (((x)&0x00000003)<<30)
2246 +
2247 +/* Bit definitions and macros for MCF_PCITCR */
2248 +#define MCF_PCITCR_P (0x00010000)
2249 +#define MCF_PCITCR_LD (0x01000000)
2250 +
2251 +/* Bit definitions and macros for MCF_PCIIW0BTAR */
2252 +#define MCF_PCIIW0BTAR_WTA0(x) (((x)&0x000000FF)<<8)
2253 +#define MCF_PCIIW0BTAR_WAM0(x) (((x)&0x000000FF)<<16)
2254 +#define MCF_PCIIW0BTAR_WBA0(x) (((x)&0x000000FF)<<24)
2255 +
2256 +/* Bit definitions and macros for MCF_PCIIW1BTAR */
2257 +#define MCF_PCIIW1BTAR_WTA1(x) (((x)&0x000000FF)<<8)
2258 +#define MCF_PCIIW1BTAR_WAM1(x) (((x)&0x000000FF)<<16)
2259 +#define MCF_PCIIW1BTAR_WBA1(x) (((x)&0x000000FF)<<24)
2260 +
2261 +/* Bit definitions and macros for MCF_PCIIW2BTAR */
2262 +#define MCF_PCIIW2BTAR_WTA2(x) (((x)&0x000000FF)<<8)
2263 +#define MCF_PCIIW2BTAR_WAM2(x) (((x)&0x000000FF)<<16)
2264 +#define MCF_PCIIW2BTAR_WBA2(x) (((x)&0x000000FF)<<24)
2265 +
2266 +/* Bit definitions and macros for MCF_PCIIWCR */
2267 +#define MCF_PCIIWCR_WINCTRL2(x) (((x)&0x0000000F)<<8)
2268 +#define MCF_PCIIWCR_WINCTRL1(x) (((x)&0x0000000F)<<16)
2269 +#define MCF_PCIIWCR_WINCTRL0(x) (((x)&0x0000000F)<<24)
2270 +#define MCF_PCIIWCR_WINCTRL0_MEMREAD (0x01000000)
2271 +#define MCF_PCIIWCR_WINCTRL0_MEMRDLINE (0x03000000)
2272 +#define MCF_PCIIWCR_WINCTRL0_MEMRDMUL (0x05000000)
2273 +#define MCF_PCIIWCR_WINCTRL0_IO (0x09000000)
2274 +#define MCF_PCIIWCR_WINCTRL0_E (0x01000000)
2275 +#define MCF_PCIIWCR_WINCTRL1_MEMREAD (0x00010000)
2276 +#define MCF_PCIIWCR_WINCTRL1_MEMRDLINE (0x00030000)
2277 +#define MCF_PCIIWCR_WINCTRL1_MEMRDMUL (0x00050000)
2278 +#define MCF_PCIIWCR_WINCTRL1_IO (0x00090000)
2279 +#define MCF_PCIIWCR_WINCTRL1_E (0x00010000)
2280 +#define MCF_PCIIWCR_WINCTRL2_MEMREAD (0x00000100)
2281 +#define MCF_PCIIWCR_WINCTRL2_MEMRDLINE (0x00000300)
2282 +#define MCF_PCIIWCR_WINCTRL2_MEMRDMUL (0x00000500)
2283 +#define MCF_PCIIWCR_WINCTRL2_IO (0x00000900)
2284 +#define MCF_PCIIWCR_WINCTRL2_E (0x00000100)
2285 +
2286 +
2287 +/* Bit definitions and macros for MCF_PCIICR */
2288 +#define MCF_PCIICR_MAXRETRY(x) (((x)&0x000000FF)<<0)
2289 +#define MCF_PCIICR_TAE (0x01000000)
2290 +#define MCF_PCIICR_IAE (0x02000000)
2291 +#define MCF_PCIICR_REE (0x04000000)
2292 +
2293 +/* Bit definitions and macros for MCF_PCIISR */
2294 +#define MCF_PCIISR_TA (0x01000000)
2295 +#define MCF_PCIISR_IA (0x02000000)
2296 +#define MCF_PCIISR_RE (0x04000000)
2297 +
2298 +/* Bit definitions and macros for MCF_PCICAR */
2299 +#define MCF_PCICAR_DWORD(x) (((x)&0x0000003F)<<2)
2300 +#define MCF_PCICAR_FUNCNUM(x) (((x)&0x00000007)<<8)
2301 +#define MCF_PCICAR_DEVNUM(x) (((x)&0x0000001F)<<11)
2302 +#define MCF_PCICAR_BUSNUM(x) (((x)&0x000000FF)<<16)
2303 +#define MCF_PCICAR_E (0x80000000)
2304 +
2305 +/* Bit definitions and macros for MCF_PCITPSR */
2306 +#define MCF_PCITPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
2307 +
2308 +/* Bit definitions and macros for MCF_PCITTCR */
2309 +#define MCF_PCITTCR_DI (0x00000001)
2310 +#define MCF_PCITTCR_W (0x00000010)
2311 +#define MCF_PCITTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
2312 +#define MCF_PCITTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
2313 +#define MCF_PCITTCR_PCICMD(x) (((x)&0x0000000F)<<24)
2314 +
2315 +/* Bit definitions and macros for MCF_PCITER */
2316 +#define MCF_PCITER_NE (0x00010000)
2317 +#define MCF_PCITER_IAE (0x00020000)
2318 +#define MCF_PCITER_TAE (0x00040000)
2319 +#define MCF_PCITER_RE (0x00080000)
2320 +#define MCF_PCITER_SE (0x00100000)
2321 +#define MCF_PCITER_FEE (0x00200000)
2322 +#define MCF_PCITER_ME (0x01000000)
2323 +#define MCF_PCITER_BE (0x08000000)
2324 +#define MCF_PCITER_CM (0x10000000)
2325 +#define MCF_PCITER_RF (0x40000000)
2326 +#define MCF_PCITER_RC (0x80000000)
2327 +
2328 +/* Bit definitions and macros for MCF_PCITDCR */
2329 +#define MCF_PCITDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
2330 +#define MCF_PCITDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
2331 +
2332 +/* Bit definitions and macros for MCF_PCITSR */
2333 +#define MCF_PCITSR_IA (0x00010000)
2334 +#define MCF_PCITSR_TA (0x00020000)
2335 +#define MCF_PCITSR_RE (0x00040000)
2336 +#define MCF_PCITSR_SE (0x00080000)
2337 +#define MCF_PCITSR_FE (0x00100000)
2338 +#define MCF_PCITSR_BE1 (0x00200000)
2339 +#define MCF_PCITSR_BE2 (0x00400000)
2340 +#define MCF_PCITSR_BE3 (0x00800000)
2341 +#define MCF_PCITSR_NT (0x01000000)
2342 +
2343 +/* Bit definitions and macros for MCF_PCITFSR */
2344 +#define MCF_PCITFSR_EMT (0x00010000)
2345 +#define MCF_PCITFSR_ALARM (0x00020000)
2346 +#define MCF_PCITFSR_FU (0x00040000)
2347 +#define MCF_PCITFSR_FR (0x00080000)
2348 +#define MCF_PCITFSR_OF (0x00100000)
2349 +#define MCF_PCITFSR_UF (0x00200000)
2350 +#define MCF_PCITFSR_RXW (0x00400000)
2351 +
2352 +/* Bit definitions and macros for MCF_PCITFCR */
2353 +#define MCF_PCITFCR_OF_MSK (0x00080000)
2354 +#define MCF_PCITFCR_UF_MSK (0x00100000)
2355 +#define MCF_PCITFCR_RXW_MSK (0x00200000)
2356 +#define MCF_PCITFCR_FAE_MSK (0x00400000)
2357 +#define MCF_PCITFCR_IP_MSK (0x00800000)
2358 +#define MCF_PCITFCR_GR(x) (((x)&0x00000007)<<24)
2359 +
2360 +/* Bit definitions and macros for MCF_PCITFAR */
2361 +#define MCF_PCITFAR_ALARM(x) (((x)&0x0000007F)<<0)
2362 +
2363 +/* Bit definitions and macros for MCF_PCITFRPR */
2364 +#define MCF_PCITFRPR_READ(x) (((x)&0x00000FFF)<<0)
2365 +
2366 +/* Bit definitions and macros for MCF_PCITFWPR */
2367 +#define MCF_PCITFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
2368 +
2369 +/* Bit definitions and macros for MCF_PCIRPSR */
2370 +#define MCF_PCIRPSR_PKTSIZE(x) (((x)&0x0000FFFF)<<16)
2371 +
2372 +/* Bit definitions and macros for MCF_PCIRTCR */
2373 +#define MCF_PCIRTCR_DI (0x00000001)
2374 +#define MCF_PCIRTCR_W (0x00000010)
2375 +#define MCF_PCIRTCR_MAXBEATS(x) (((x)&0x00000007)<<8)
2376 +#define MCF_PCIRTCR_FB (0x00001000)
2377 +#define MCF_PCIRTCR_MAXRETRY(x) (((x)&0x000000FF)<<16)
2378 +#define MCF_PCIRTCR_PCICMD(x) (((x)&0x0000000F)<<24)
2379 +
2380 +/* Bit definitions and macros for MCF_PCIRER */
2381 +#define MCF_PCIRER_NE (0x00010000)
2382 +#define MCF_PCIRER_IAE (0x00020000)
2383 +#define MCF_PCIRER_TAE (0x00040000)
2384 +#define MCF_PCIRER_RE (0x00080000)
2385 +#define MCF_PCIRER_SE (0x00100000)
2386 +#define MCF_PCIRER_FEE (0x00200000)
2387 +#define MCF_PCIRER_ME (0x01000000)
2388 +#define MCF_PCIRER_BE (0x08000000)
2389 +#define MCF_PCIRER_CM (0x10000000)
2390 +#define MCF_PCIRER_FE (0x20000000)
2391 +#define MCF_PCIRER_RF (0x40000000)
2392 +#define MCF_PCIRER_RC (0x80000000)
2393 +
2394 +/* Bit definitions and macros for MCF_PCIRDCR */
2395 +#define MCF_PCIRDCR_PKTSDONE(x) (((x)&0x0000FFFF)<<0)
2396 +#define MCF_PCIRDCR_BYTESDONE(x) (((x)&0x0000FFFF)<<16)
2397 +
2398 +/* Bit definitions and macros for MCF_PCIRSR */
2399 +#define MCF_PCIRSR_IA (0x00010000)
2400 +#define MCF_PCIRSR_TA (0x00020000)
2401 +#define MCF_PCIRSR_RE (0x00040000)
2402 +#define MCF_PCIRSR_SE (0x00080000)
2403 +#define MCF_PCIRSR_FE (0x00100000)
2404 +#define MCF_PCIRSR_BE1 (0x00200000)
2405 +#define MCF_PCIRSR_BE2 (0x00400000)
2406 +#define MCF_PCIRSR_BE3 (0x00800000)
2407 +#define MCF_PCIRSR_NT (0x01000000)
2408 +
2409 +/* Bit definitions and macros for MCF_PCIRFSR */
2410 +#define MCF_PCIRFSR_EMT (0x00010000)
2411 +#define MCF_PCIRFSR_ALARM (0x00020000)
2412 +#define MCF_PCIRFSR_FU (0x00040000)
2413 +#define MCF_PCIRFSR_FR (0x00080000)
2414 +#define MCF_PCIRFSR_OF (0x00100000)
2415 +#define MCF_PCIRFSR_UF (0x00200000)
2416 +#define MCF_PCIRFSR_RXW (0x00400000)
2417 +
2418 +/* Bit definitions and macros for MCF_PCIRFCR */
2419 +#define MCF_PCIRFCR_OF_MSK (0x00080000)
2420 +#define MCF_PCIRFCR_UF_MSK (0x00100000)
2421 +#define MCF_PCIRFCR_RXW_MSK (0x00200000)
2422 +#define MCF_PCIRFCR_FAE_MSK (0x00400000)
2423 +#define MCF_PCIRFCR_IP_MSK (0x00800000)
2424 +#define MCF_PCIRFCR_GR(x) (((x)&0x00000007)<<24)
2425 +
2426 +/* Bit definitions and macros for MCF_PCIRFAR */
2427 +#define MCF_PCIRFAR_ALARM(x) (((x)&0x0000007F)<<0)
2428 +
2429 +/* Bit definitions and macros for MCF_PCIRFRPR */
2430 +#define MCF_PCIRFRPR_READ(x) (((x)&0x00000FFF)<<0)
2431 +
2432 +/* Bit definitions and macros for MCF_PCIRFWPR */
2433 +#define MCF_PCIRFWPR_WRITE(x) (((x)&0x00000FFF)<<0)
2434 +
2435 +
2436 +/* Bit definitions and macros for MCF_PCIARB_PACR */
2437 +#define MCF_PCIARB_PACR_INTMPRI (0x00000001)
2438 +#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x0000001F)<<1)
2439 +#define MCF_PCIARB_PACR_INTMINTEN (0x00010000)
2440 +#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x0000001F)<<17)
2441 +#define MCF_PCIARB_PACR_PKMD (0x40000000)
2442 +#define MCF_PCIARB_PACR_DS (0x80000000)
2443 +
2444 +/* Bit definitions and macros for MCF_PCIARB_PASR */
2445 +#define MCF_PCIARB_PASR_ITLMBK (0x00010000)
2446 +#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x0000001F)<<17)
2447 +
2448 +#endif /* __MCF548X_PCI_H__ */
2449 --- a/include/asm-m68k/pci.h
2450 +++ b/include/asm-m68k/pci.h
2451 @@ -1,94 +1,10 @@
2452 -/*
2453 - * asm-m68k/pci.h - m68k specific PCI declarations.
2454 - *
2455 - * Coldfire Implementation Copyright (c) 2007 Freescale Semiconductor, Inc.
2456 - * Kurt Mahan <kmahan@freescale.com>
2457 - */
2458 -#ifndef _ASM_M68K_PCI_H
2459 -#define _ASM_M68K_PCI_H
2460 +#ifndef M68K_PCI_H
2461 +#define M68K_PCI_H
2462
2463 -#ifndef CONFIG_PCI
2464 -/*
2465 - * The PCI address space does equal the physical memory
2466 - * address space. The networking and block device layers use
2467 - * this boolean for bounce buffer decisions.
2468 - */
2469 -#define PCI_DMA_BUS_IS_PHYS (1)
2470 +#ifdef CONFIG_M5445X
2471 +#include "5445x_pci.h"
2472 #else
2473 -#include <asm-generic/pci-dma-compat.h>
2474 -
2475 -/*
2476 - * The PCI address space does equal the physical memory
2477 - * address space. The networking and block device layers use
2478 - * this boolean for bounce buffer decisions.
2479 - */
2480 -#define PCI_DMA_BUS_IS_PHYS (1)
2481 -
2482 -#define PCIBIOS_MIN_IO 0x00004000
2483 -#define PCIBIOS_MIN_MEM 0x02000000
2484 -
2485 -#define pcibios_assign_all_busses() 0
2486 -#define pcibios_scan_all_fns(a, b) 0
2487 -
2488 -static inline void
2489 -pcibios_set_master(struct pci_dev *dev)
2490 -{
2491 - /* no special bus mastering setup handling */
2492 -}
2493 -
2494 -static inline void
2495 -pcibios_penalize_isa_irq(int irq, int active)
2496 -{
2497 - /* no dynamic PCI IRQ allocation */
2498 -}
2499 -
2500 -#if 0
2501 -static inline void
2502 -pcibios_add_platform_entries(struct pci_dev *dev)
2503 -{
2504 - /* no special handling */
2505 -}
2506 +#include "548x_pci.h"
2507 #endif
2508
2509 -static inline void
2510 -pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
2511 - struct resource *res)
2512 -{
2513 -#ifdef CONFIG_M54455
2514 - if ((res->start == 0xa0000000) || (res->start == 0xa8000000)) {
2515 - /* HACK! FIX! kludge to fix bridge mapping */
2516 - region->start = res->start & 0x0fffffff;
2517 - region->end = res->end & 0x0fffffff;
2518 - } else {
2519 - region->start = res->start;
2520 - region->end = res->end;
2521 - }
2522 -#else
2523 - region->start = res->start;
2524 - region->end = res->end;
2525 -#endif
2526 -}
2527 -
2528 -static inline void
2529 -pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
2530 - struct pci_bus_region *region)
2531 -{
2532 - res->start = region->start;
2533 - res->end = region->end;
2534 -}
2535 -
2536 -static inline struct resource *
2537 -pcibios_select_root(struct pci_dev *pdev, struct resource *res)
2538 -{
2539 - struct resource *root = NULL;
2540 -
2541 - if (res->flags & IORESOURCE_IO)
2542 - root = &ioport_resource;
2543 - if (res->flags & IORESOURCE_MEM)
2544 - root = &iomem_resource;
2545 -
2546 - return root;
2547 -}
2548 -
2549 -#endif /* CONFIG_PCI */
2550 -#endif /* _ASM_M68K_PCI_H */
2551 +#endif /* M68K_PCI_H */
2552 --- a/include/asm-m68k/raw_io.h
2553 +++ b/include/asm-m68k/raw_io.h
2554 @@ -46,6 +46,29 @@ extern void __iounmap(void *addr, unsign
2555 #define out_le16(addr,w) (void)((*(__force volatile __le16 *) (addr)) = cpu_to_le16(w))
2556 #define out_le32(addr,l) (void)((*(__force volatile __le32 *) (addr)) = cpu_to_le32(l))
2557
2558 +#if (defined CONFIG_COLDFIRE) && (defined CONFIG_PCI)
2559 +unsigned char pci_inb(long addr);
2560 +unsigned short pci_inw(long addr);
2561 +unsigned long pci_inl(long addr);
2562 +void pci_outb(unsigned char val, long addr);
2563 +void pci_outw(unsigned short val, long addr);
2564 +void pci_outl(unsigned long val, long addr);
2565 +unsigned short pci_raw_inw(long addr);
2566 +unsigned long pci_raw_inl(long addr);
2567 +void pci_raw_outw(unsigned short val, long addr);
2568 +void pci_raw_outl(unsigned long val, long addr);
2569 +#define raw_inb(port) pci_inb((long)((volatile unsigned char *)(port)))
2570 +#define raw_inw(port) pci_raw_inw((long)((volatile unsigned short *)(port)))
2571 +#define raw_inl(port) pci_raw_inl((long)((volatile unsigned long *)(port)))
2572 +
2573 +#define raw_outb(val,port) pci_outb((val),(long)((volatile unsigned char *)(port)))
2574 +#define raw_outw(val,port) pci_raw_outw((val),(long)((volatile unsigned short *)(port)))
2575 +#define raw_outl(val,port) pci_raw_outl((val),(long)((volatile unsigned long *)(port)))
2576 +
2577 +#define swap_inw(port) pci_inw((long)((volatile unsigned short *)(port)))
2578 +#define swap_outw(val,port) pci_outw((val),(long)((volatile unsigned short *)(port)))
2579 +
2580 +#else
2581 #define raw_inb in_8
2582 #define raw_inw in_be16
2583 #define raw_inl in_be32
2584 @@ -60,6 +83,9 @@ extern void __iounmap(void *addr, unsign
2585 #define __raw_writew(val,addr) out_be16((addr),(val))
2586 #define __raw_writel(val,addr) out_be32((addr),(val))
2587
2588 +#define swap_inw(port) in_le16((port))
2589 +#define swap_outw(val,port) out_le16((port),(val))
2590 +#endif
2591 static inline void raw_insb(volatile u8 __iomem *port, u8 *buf, unsigned int len)
2592 {
2593 unsigned int i;
2594 --- a/include/asm-m68k/virtconvert.h
2595 +++ b/include/asm-m68k/virtconvert.h
2596 @@ -46,9 +46,14 @@ static inline void *phys_to_virt(unsigne
2597 #define virt_to_bus(a) (virt_to_phys(a) + (MACH_IS_HADES ? 0x80000000 : 0))
2598 #define bus_to_virt(a) (phys_to_virt((a) - (MACH_IS_HADES ? 0x80000000 : 0)))
2599 #else
2600 +#ifdef CONFIG_COLDFIRE
2601 +#define virt_to_bus(a) (a - PAGE_OFFSET + PCI_DMA_BASE)
2602 +#define bus_to_virt(a) (a - PCI_DMA_BASE + PAGE_OFFSET)
2603 +#else /* CONFIG_COLDFIRE */
2604 #define virt_to_bus virt_to_phys
2605 #define bus_to_virt phys_to_virt
2606 #endif
2607 +#endif
2608
2609 #endif
2610 #endif
2611 --- a/include/linux/pci.h
2612 +++ b/include/linux/pci.h
2613 @@ -458,8 +458,10 @@ int __must_check pcibios_enable_device(s
2614 char *pcibios_setup(char *str);
2615
2616 /* Used only when drivers/pci/setup.c is used */
2617 +#ifndef CONFIG_COLDFIRE
2618 void pcibios_align_resource(void *, struct resource *, resource_size_t,
2619 resource_size_t);
2620 +#endif
2621 void pcibios_update_irq(struct pci_dev *, int irq);
2622
2623 /* Generic PCI functions used internally */
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