target/linux/ramips/files/drivers/net/ramips_esw.c

   1 #include <rt305x.h>
   2 #include <rt305x_regs.h>
   3
   4 #define GPIO_PRUPOSE           0x60
   5 #define GPIO_MDIO_BIT          (1<<7)
   6 #define RT305X_ESW_PHY_WRITE            (1 << 13)
   7 #define RT305X_ESW_PHY_TOUT                     (5 * HZ)
   8 #define RT305X_ESW_PHY_CONTROL_0        0xC0
   9 #define RT305X_ESW_PHY_CONTROL_1        0xC4
  10
  11 static void __iomem *ramips_esw_base = 0;
  12
  13 static inline void
  14 ramips_esw_wr(u32 val, unsigned reg)
  15 {
  16         __raw_writel(val, ramips_esw_base + reg);
  17 }
  18
  19 static inline u32
  20 ramips_esw_rr(unsigned reg)
  21 {
  22         return __raw_readl(ramips_esw_base + reg);
  23 }
  24
  25 static void
  26 ramips_enable_mdio(int s)
  27 {
  28         u32 gpio = rt305x_sysc_rr(GPIO_PRUPOSE);
  29         if(s)
  30                 gpio &= ~GPIO_MDIO_BIT;
  31         else
  32                 gpio |= GPIO_MDIO_BIT;
  33         rt305x_sysc_wr(gpio, GPIO_PRUPOSE);
  34 }
  35
  36 u32
  37 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
  38 {
  39         unsigned long volatile t_start = jiffies;
  40         int ret = 0;
  41
  42         ramips_enable_mdio(1);
  43         while(1)
  44         {
  45                 if(!(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0)))
  46                         break;
  47                 if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
  48                 {
  49                         ret = 1;
  50                         goto out;
  51                 }
  52         }
  53         ramips_esw_wr(((write_data & 0xFFFF) << 16) | (phy_register << 8) |
  54                 (phy_addr) | RT305X_ESW_PHY_WRITE, RT305X_ESW_PHY_CONTROL_0);
  55         t_start = jiffies;
  56         while(1)
  57         {
  58                 if(ramips_esw_rr(RT305X_ESW_PHY_CONTROL_1) & (0x1 << 0))
  59                         break;
  60                 if(time_after(jiffies, t_start + RT305X_ESW_PHY_TOUT))
  61                 {
  62                         ret = 1;
  63                         break;
  64                 }
  65         }
  66 out:
  67         ramips_enable_mdio(0);
  68         if(ret)
  69                 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
  70         return ret;
  71 }
  72
  73 static int
  74 rt305x_esw_init(void)
  75 {
  76         int i;
  77
  78         ramips_esw_base = ioremap_nocache(RT305X_SWITCH_BASE, PAGE_SIZE);
  79         if(!ramips_esw_base)
  80                 return -ENOMEM;
  81
  82         /* vodoo from original driver */
  83         ramips_esw_wr(0xC8A07850, 0x08);
  84         ramips_esw_wr(0x00000000, 0xe4);
  85         ramips_esw_wr(0x00405555, 0x14);
  86         ramips_esw_wr(0x00002001, 0x50);
  87         ramips_esw_wr(0x00007f7f, 0x90);
  88         ramips_esw_wr(0x00007f3f, 0x98);
  89         ramips_esw_wr(0x00d6500c, 0xcc);
  90         ramips_esw_wr(0x0008a301, 0x9c);
  91         ramips_esw_wr(0x02404040, 0x8c);
  92         ramips_esw_wr(0x00001002, 0x48);
  93         ramips_esw_wr(0x3f502b28, 0xc8);
  94         ramips_esw_wr(0x00000000, 0x84);
  95
  96         mii_mgr_write(0, 31, 0x8000);
  97         for(i = 0; i < 5; i++)
  98         {
  99                 mii_mgr_write(i, 0, 0x3100);   //TX10 waveform coefficient
 100                 mii_mgr_write(i, 26, 0x1601);   //TX10 waveform coefficient
 101                 mii_mgr_write(i, 29, 0x7058);   //TX100/TX10 AD/DA current bias
 102                 mii_mgr_write(i, 30, 0x0018);   //TX100 slew rate control
 103         }
 104         /* PHY IOT */
 105         mii_mgr_write(0, 31, 0x0);      //select global register
 106         mii_mgr_write(0, 22, 0x052f);   //tune TP_IDL tail and head waveform
 107         mii_mgr_write(0, 17, 0x0fe0);   //set TX10 signal amplitude threshold to minimum
 108         mii_mgr_write(0, 18, 0x40ba);   //set squelch amplitude to higher threshold
 109         mii_mgr_write(0, 14, 0x65);     //longer TP_IDL tail length
 110         mii_mgr_write(0, 31, 0x8000);   //select local register
 111
 112         /* Port 5 Disabled */
 113         rt305x_sysc_wr(rt305x_sysc_rr(0x60) | (1 << 9), 0x60); //set RGMII to GPIO mode (GPIO41-GPIO50)
 114         rt305x_sysc_wr(0xfff, 0x674); //GPIO41-GPIO50 output mode
 115         rt305x_sysc_wr(0x0, 0x670); //GPIO41-GPIO50 output low
 116
 117         /* set default vlan */
 118         ramips_esw_wr(0x2001, 0x50);
 119         ramips_esw_wr(0x504f, 0x70);
 120
 121         return 0;
 122 }