target/linux/coldfire/files-2.6.31/arch/m68k/include/asm/m5485dma.h

   1 /*
   2  * m5485dma.h -- ColdFire 547x/548x DMA controller support.
   3  * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5 #ifndef __MCF548X_DMA_H__
   6 #define __MCF548X_DMA_H__
   7
   8
   9 /* Register read/write macros */
  10 #define MCF_DMA_DIPR    MCF_REG32(0x008014)
  11 #define MCF_DMA_DIMR    MCF_REG32(0x008018)
  12 #define MCF_DMA_IMCR    MCF_REG32(0x00805C)
  13
  14 /* Bit definitions and macros for MCF_DMA_DIPR */
  15 #define MCF_DMA_DIPR_TASK0           (0x00000001)
  16 #define MCF_DMA_DIPR_TASK1           (0x00000002)
  17 #define MCF_DMA_DIPR_TASK2           (0x00000004)
  18 #define MCF_DMA_DIPR_TASK3           (0x00000008)
  19 #define MCF_DMA_DIPR_TASK4           (0x00000010)
  20 #define MCF_DMA_DIPR_TASK5           (0x00000020)
  21 #define MCF_DMA_DIPR_TASK6           (0x00000040)
  22 #define MCF_DMA_DIPR_TASK7           (0x00000080)
  23 #define MCF_DMA_DIPR_TASK8           (0x00000100)
  24 #define MCF_DMA_DIPR_TASK9           (0x00000200)
  25 #define MCF_DMA_DIPR_TASK10          (0x00000400)
  26 #define MCF_DMA_DIPR_TASK11          (0x00000800)
  27 #define MCF_DMA_DIPR_TASK12          (0x00001000)
  28 #define MCF_DMA_DIPR_TASK13          (0x00002000)
  29 #define MCF_DMA_DIPR_TASK14          (0x00004000)
  30 #define MCF_DMA_DIPR_TASK15          (0x00008000)
  31
  32 /* Bit definitions and macros for MCF_DMA_DIMR */
  33 #define MCF_DMA_DIMR_TASK0           (0x00000001)
  34 #define MCF_DMA_DIMR_TASK1           (0x00000002)
  35 #define MCF_DMA_DIMR_TASK2           (0x00000004)
  36 #define MCF_DMA_DIMR_TASK3           (0x00000008)
  37 #define MCF_DMA_DIMR_TASK4           (0x00000010)
  38 #define MCF_DMA_DIMR_TASK5           (0x00000020)
  39 #define MCF_DMA_DIMR_TASK6           (0x00000040)
  40 #define MCF_DMA_DIMR_TASK7           (0x00000080)
  41 #define MCF_DMA_DIMR_TASK8           (0x00000100)
  42 #define MCF_DMA_DIMR_TASK9           (0x00000200)
  43 #define MCF_DMA_DIMR_TASK10          (0x00000400)
  44 #define MCF_DMA_DIMR_TASK11          (0x00000800)
  45 #define MCF_DMA_DIMR_TASK12          (0x00001000)
  46 #define MCF_DMA_DIMR_TASK13          (0x00002000)
  47 #define MCF_DMA_DIMR_TASK14          (0x00004000)
  48 #define MCF_DMA_DIMR_TASK15          (0x00008000)
  49
  50 /* Bit definitions and macros for MCF_DMA_IMCR */
  51 #define MCF_DMA_IMCR_SRC16(x)        (((x)&0x00000003)<<0)
  52 #define MCF_DMA_IMCR_SRC17(x)        (((x)&0x00000003)<<2)
  53 #define MCF_DMA_IMCR_SRC18(x)        (((x)&0x00000003)<<4)
  54 #define MCF_DMA_IMCR_SRC19(x)        (((x)&0x00000003)<<6)
  55 #define MCF_DMA_IMCR_SRC20(x)        (((x)&0x00000003)<<8)
  56 #define MCF_DMA_IMCR_SRC21(x)        (((x)&0x00000003)<<10)
  57 #define MCF_DMA_IMCR_SRC22(x)        (((x)&0x00000003)<<12)
  58 #define MCF_DMA_IMCR_SRC23(x)        (((x)&0x00000003)<<14)
  59 #define MCF_DMA_IMCR_SRC24(x)        (((x)&0x00000003)<<16)
  60 #define MCF_DMA_IMCR_SRC25(x)        (((x)&0x00000003)<<18)
  61 #define MCF_DMA_IMCR_SRC26(x)        (((x)&0x00000003)<<20)
  62 #define MCF_DMA_IMCR_SRC27(x)        (((x)&0x00000003)<<22)
  63 #define MCF_DMA_IMCR_SRC28(x)        (((x)&0x00000003)<<24)
  64 #define MCF_DMA_IMCR_SRC29(x)        (((x)&0x00000003)<<26)
  65 #define MCF_DMA_IMCR_SRC30(x)        (((x)&0x00000003)<<28)
  66 #define MCF_DMA_IMCR_SRC31(x)        (((x)&0x00000003)<<30)
  67 #define MCF_DMA_IMCR_SRC16_FEC0RX    (0x00000000)
  68 #define MCF_DMA_IMCR_SRC17_FEC0TX    (0x00000000)
  69 #define MCF_DMA_IMCR_SRC18_FEC0RX    (0x00000020)
  70 #define MCF_DMA_IMCR_SRC19_FEC0TX    (0x00000080)
  71 #define MCF_DMA_IMCR_SRC20_FEC1RX    (0x00000100)
  72 #define MCF_DMA_IMCR_SRC21_DREQ1     (0x00000000)
  73 #define MCF_DMA_IMCR_SRC21_FEC1TX    (0x00000400)
  74 #define MCF_DMA_IMCR_SRC22_FEC0RX    (0x00001000)
  75 #define MCF_DMA_IMCR_SRC23_FEC0TX    (0x00004000)
  76 #define MCF_DMA_IMCR_SRC24_CTM0      (0x00010000)
  77 #define MCF_DMA_IMCR_SRC24_FEC1RX    (0x00020000)
  78 #define MCF_DMA_IMCR_SRC25_CTM1      (0x00040000)
  79 #define MCF_DMA_IMCR_SRC25_FEC1TX    (0x00080000)
  80 #define MCF_DMA_IMCR_SRC26_USBEP4    (0x00000000)
  81 #define MCF_DMA_IMCR_SRC26_CTM2      (0x00200000)
  82 #define MCF_DMA_IMCR_SRC27_USBEP5    (0x00000000)
  83 #define MCF_DMA_IMCR_SRC27_CTM3      (0x00800000)
  84 #define MCF_DMA_IMCR_SRC28_USBEP6    (0x00000000)
  85 #define MCF_DMA_IMCR_SRC28_CTM4      (0x01000000)
  86 #define MCF_DMA_IMCR_SRC28_DREQ1     (0x02000000)
  87 #define MCF_DMA_IMCR_SRC28_PSC2RX    (0x03000000)
  88 #define MCF_DMA_IMCR_SRC29_DREQ1     (0x04000000)
  89 #define MCF_DMA_IMCR_SRC29_CTM5      (0x08000000)
  90 #define MCF_DMA_IMCR_SRC29_PSC2TX    (0x0C000000)
  91 #define MCF_DMA_IMCR_SRC30_FEC1RX    (0x00000000)
  92 #define MCF_DMA_IMCR_SRC30_CTM6      (0x10000000)
  93 #define MCF_DMA_IMCR_SRC30_PSC3RX    (0x30000000)
  94 #define MCF_DMA_IMCR_SRC31_FEC1TX    (0x00000000)
  95 #define MCF_DMA_IMCR_SRC31_CTM7      (0x80000000)
  96 #define MCF_DMA_IMCR_SRC31_PSC3TX    (0xC0000000)
  97
  98 #endif /* __MCF548X_DMA_H__ */