projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
[xburst] Add 2.6.37 support
[openwrt.git] / target / linux / xburst / patches-2.6.34 / 001-core.patch
1 From e1828438bbdd0623cf7f9c6672f2fe65b1349aa6 Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 17:35:05 +0200
4 Subject: [PATCH] Add JZ4740 SoC core support
5
6 ---
7 arch/mips/Kconfig | 4 +
8 arch/mips/Makefile | 6 +
9 arch/mips/include/asm/bootinfo.h | 6 +
10 arch/mips/include/asm/cpu.h | 13 +-
11 arch/mips/include/asm/mach-jz4740/base.h | 28 +
12 arch/mips/include/asm/mach-jz4740/clock.h | 28 +
13 arch/mips/include/asm/mach-jz4740/dma.h | 90 +++
14 arch/mips/include/asm/mach-jz4740/gpio.h | 398 +++++++++++
15 arch/mips/include/asm/mach-jz4740/irq.h | 55 ++
16 arch/mips/include/asm/mach-jz4740/platform.h | 34 +
17 arch/mips/include/asm/mach-jz4740/serial.h | 30 +
18 arch/mips/include/asm/mach-jz4740/timer.h | 22 +
19 arch/mips/include/asm/mach-jz4740/war.h | 25 +
20 arch/mips/jz4740/Kconfig | 29 +
21 arch/mips/jz4740/Makefile | 18 +
22 arch/mips/jz4740/clock-debugfs.c | 109 +++
23 arch/mips/jz4740/clock.c | 935 ++++++++++++++++++++++++++
24 arch/mips/jz4740/clock.h | 75 ++
25 arch/mips/jz4740/dma.c | 336 +++++++++
26 arch/mips/jz4740/gpio.c | 598 ++++++++++++++++
27 arch/mips/jz4740/irq.c | 170 +++++
28 arch/mips/jz4740/irq.h | 21 +
29 arch/mips/jz4740/platform.c | 246 +++++++
30 arch/mips/jz4740/pm.c | 59 ++
31 arch/mips/jz4740/prom.c | 69 ++
32 arch/mips/jz4740/pwm.c | 167 +++++
33 arch/mips/jz4740/reset.c | 81 +++
34 arch/mips/jz4740/reset.h | 7 +
35 arch/mips/jz4740/setup.c | 64 ++
36 arch/mips/jz4740/time.c | 144 ++++
37 arch/mips/jz4740/timer.c | 48 ++
38 arch/mips/jz4740/timer.h | 130 ++++
39 arch/mips/kernel/cpu-probe.c | 20 +
40 arch/mips/mm/tlbex.c | 5 +
41 34 files changed, 4069 insertions(+), 1 deletions(-)
42 create mode 100644 arch/mips/include/asm/mach-jz4740/base.h
43 create mode 100644 arch/mips/include/asm/mach-jz4740/clock.h
44 create mode 100644 arch/mips/include/asm/mach-jz4740/dma.h
45 create mode 100644 arch/mips/include/asm/mach-jz4740/gpio.h
46 create mode 100644 arch/mips/include/asm/mach-jz4740/irq.h
47 create mode 100644 arch/mips/include/asm/mach-jz4740/platform.h
48 create mode 100644 arch/mips/include/asm/mach-jz4740/serial.h
49 create mode 100644 arch/mips/include/asm/mach-jz4740/timer.h
50 create mode 100644 arch/mips/include/asm/mach-jz4740/war.h
51 create mode 100644 arch/mips/jz4740/Kconfig
52 create mode 100644 arch/mips/jz4740/Makefile
53 create mode 100644 arch/mips/jz4740/clock-debugfs.c
54 create mode 100644 arch/mips/jz4740/clock.c
55 create mode 100644 arch/mips/jz4740/clock.h
56 create mode 100644 arch/mips/jz4740/dma.c
57 create mode 100644 arch/mips/jz4740/gpio.c
58 create mode 100644 arch/mips/jz4740/irq.c
59 create mode 100644 arch/mips/jz4740/irq.h
60 create mode 100644 arch/mips/jz4740/platform.c
61 create mode 100644 arch/mips/jz4740/pm.c
62 create mode 100644 arch/mips/jz4740/prom.c
63 create mode 100644 arch/mips/jz4740/pwm.c
64 create mode 100644 arch/mips/jz4740/reset.c
65 create mode 100644 arch/mips/jz4740/reset.h
66 create mode 100644 arch/mips/jz4740/setup.c
67 create mode 100644 arch/mips/jz4740/time.c
68 create mode 100644 arch/mips/jz4740/timer.c
69 create mode 100644 arch/mips/jz4740/timer.h
70
71 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
72 index 7e6fd1c..e902f02 100644
73 --- a/arch/mips/Kconfig
74 +++ b/arch/mips/Kconfig
75 @@ -162,6 +162,9 @@ config MACH_JAZZ
76 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
77 Olivetti M700-10 workstations.
78
79 +config MACH_JZ
80 + bool "Ingenic JZ4720/JZ4740 based machines"
81 +
82 config LASAT
83 bool "LASAT Networks platforms"
84 select CEVT_R4K
85 @@ -686,6 +689,7 @@ endchoice
86 source "arch/mips/alchemy/Kconfig"
87 source "arch/mips/bcm63xx/Kconfig"
88 source "arch/mips/jazz/Kconfig"
89 +source "arch/mips/jz4740/Kconfig"
90 source "arch/mips/lasat/Kconfig"
91 source "arch/mips/pmc-sierra/Kconfig"
92 source "arch/mips/powertv/Kconfig"
93 diff --git a/arch/mips/Makefile b/arch/mips/Makefile
94 index 0b9c01a..007a82e 100644
95 --- a/arch/mips/Makefile
96 +++ b/arch/mips/Makefile
97 @@ -659,6 +659,12 @@ else
98 load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
99 endif
100
101 +# Ingenic JZ4740
102 +#
103 +core-$(CONFIG_SOC_JZ4740) += arch/mips/jz4740/
104 +cflags-$(CONFIG_SOC_JZ4740) += -I$(srctree)/arch/mips/include/asm/mach-jz4740
105 +load-$(CONFIG_SOC_JZ4740) += 0xffffffff80010000
106 +
107 cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
108 drivers-$(CONFIG_PCI) += arch/mips/pci/
109
110 diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h
111 index 09eee09..15a8ef0 100644
112 --- a/arch/mips/include/asm/bootinfo.h
113 +++ b/arch/mips/include/asm/bootinfo.h
114 @@ -71,6 +71,12 @@
115 #define MACH_LEMOTE_LL2F 7
116 #define MACH_LOONGSON_END 8
117
118 +/*
119 + * Valid machtype for group INGENIC
120 + */
121 +#define MACH_INGENIC_JZ4730 0 /* JZ4730 SOC */
122 +#define MACH_INGENIC_JZ4740 1 /* JZ4740 SOC */
123 +
124 extern char *system_type;
125 const char *get_system_type(void);
126
127 diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
128 index a5acda4..e67aebb 100644
129 --- a/arch/mips/include/asm/cpu.h
130 +++ b/arch/mips/include/asm/cpu.h
131 @@ -34,7 +34,7 @@
132 #define PRID_COMP_LSI 0x080000
133 #define PRID_COMP_LEXRA 0x0b0000
134 #define PRID_COMP_CAVIUM 0x0d0000
135 -
136 +#define PRID_COMP_INGENIC 0xd00000
137
138 /*
139 * Assigned values for the product ID register. In order to detect a
140 @@ -133,6 +133,12 @@
141 #define PRID_IMP_CAVIUM_CN52XX 0x0700
142
143 /*
144 + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
145 + */
146 +
147 +#define PRID_IMP_JZRISC 0x0200
148 +
149 +/*
150 * Definitions for 7:0 on legacy processors
151 */
152
153 @@ -226,6 +232,11 @@ enum cpu_type_enum {
154 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
155 CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS,
156
157 + /*
158 + * Ingenic class processors
159 + */
160 + CPU_JZRISC, CPU_XBURST,
161 +
162 CPU_LAST
163 };
164
165 diff --git a/arch/mips/include/asm/mach-jz4740/base.h b/arch/mips/include/asm/mach-jz4740/base.h
166 new file mode 100644
167 index 0000000..a281972
168 --- /dev/null
169 +++ b/arch/mips/include/asm/mach-jz4740/base.h
170 @@ -0,0 +1,28 @@
171 +#ifndef __JZ4740_BASE_ADDR_H__
172 +#define __JZ4740_BASE_ADDR_H__
173 +
174 +#define JZ4740_CPM_BASE_ADDR 0xb0000000
175 +#define JZ4740_INTC_BASE_ADDR 0xb0001000
176 +#define JZ4740_TCU_BASE_ADDR 0xb0002000
177 +#define JZ4740_WDT_BASE_ADDR 0xb0002000
178 +#define JZ4740_RTC_BASE_ADDR 0xb0003000
179 +#define JZ4740_GPIO_BASE_ADDR 0xb0010000
180 +#define JZ4740_AIC_BASE_ADDR 0xb0020000
181 +#define JZ4740_ICDC_BASE_ADDR 0xb0020000
182 +#define JZ4740_MSC_BASE_ADDR 0xb0021000
183 +#define JZ4740_UART0_BASE_ADDR 0xb0030000
184 +#define JZ4740_UART1_BASE_ADDR 0xb0031000
185 +#define JZ4740_I2C_BASE_ADDR 0xb0042000
186 +#define JZ4740_SSI_BASE_ADDR 0xb0043000
187 +#define JZ4740_SADC_BASE_ADDR 0xb0070000
188 +#define JZ4740_EMC_BASE_ADDR 0xb3010000
189 +#define JZ4740_DMAC_BASE_ADDR 0xb3020000
190 +#define JZ4740_UHC_BASE_ADDR 0xb3030000
191 +#define JZ4740_UDC_BASE_ADDR 0xb3040000
192 +#define JZ4740_LCD_BASE_ADDR 0xb3050000
193 +#define JZ4740_SLCD_BASE_ADDR 0xb3050000
194 +#define JZ4740_CIM_BASE_ADDR 0xb3060000
195 +#define JZ4740_IPU_BASE_ADDR 0xb3080000
196 +#define JZ4740_ETH_BASE_ADDR 0xb3100000
197 +
198 +#endif
199 diff --git a/arch/mips/include/asm/mach-jz4740/clock.h b/arch/mips/include/asm/mach-jz4740/clock.h
200 new file mode 100644
201 index 0000000..9069727
202 --- /dev/null
203 +++ b/arch/mips/include/asm/mach-jz4740/clock.h
204 @@ -0,0 +1,28 @@
205 +/*
206 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
207 + *
208 + * This program is free software; you can redistribute it and/or modify it
209 + * under the terms of the GNU General Public License as published by the
210 + * Free Software Foundation; either version 2 of the License, or (at your
211 + * option) any later version.
212 + *
213 + * You should have received a copy of the GNU General Public License along
214 + * with this program; if not, write to the Free Software Foundation, Inc.,
215 + * 675 Mass Ave, Cambridge, MA 02139, USA.
216 + *
217 + */
218 +
219 +#ifndef __ASM_JZ4740_CLOCK_H__
220 +#define __ASM_JZ4740_CLOCK_H__
221 +
222 +enum jz4740_wait_mode {
223 + JZ4740_WAIT_MODE_IDLE,
224 + JZ4740_WAIT_MODE_SLEEP,
225 +};
226 +
227 +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode);
228 +
229 +void jz4740_clock_udc_enable_auto_suspend(void);
230 +void jz4740_clock_udc_disable_auto_suspend(void);
231 +
232 +#endif
233 diff --git a/arch/mips/include/asm/mach-jz4740/dma.h b/arch/mips/include/asm/mach-jz4740/dma.h
234 new file mode 100644
235 index 0000000..bb7fc1e
236 --- /dev/null
237 +++ b/arch/mips/include/asm/mach-jz4740/dma.h
238 @@ -0,0 +1,90 @@
239 +/*
240 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
241 + * JZ7420/JZ4740 DMA definitions
242 + *
243 + * This program is free software; you can redistribute it and/or modify it
244 + * under the terms of the GNU General Public License as published by the
245 + * Free Software Foundation; either version 2 of the License, or (at your
246 + * option) any later version.
247 + *
248 + * You should have received a copy of the GNU General Public License along
249 + * with this program; if not, write to the Free Software Foundation, Inc.,
250 + * 675 Mass Ave, Cambridge, MA 02139, USA.
251 + *
252 + */
253 +
254 +#ifndef __ASM_MACH_JZ4740_DMA_H__
255 +#define __ASM_MACH_JZ4740_DMA_H__
256 +
257 +struct jz4740_dma_chan;
258 +
259 +enum jz4740_dma_request_type {
260 + JZ4740_DMA_TYPE_AUTO_REQUEST = 8,
261 + JZ4740_DMA_TYPE_UART_TRANSMIT = 20,
262 + JZ4740_DMA_TYPE_UART_RECEIVE = 21,
263 + JZ4740_DMA_TYPE_SPI_TRANSMIT = 22,
264 + JZ4740_DMA_TYPE_SPI_RECEIVE = 23,
265 + JZ4740_DMA_TYPE_AIC_TRANSMIT = 24,
266 + JZ4740_DMA_TYPE_AIC_RECEIVE = 25,
267 + JZ4740_DMA_TYPE_MMC_TRANSMIT = 26,
268 + JZ4740_DMA_TYPE_MMC_RECEIVE = 27,
269 + JZ4740_DMA_TYPE_TCU = 28,
270 + JZ4740_DMA_TYPE_SADC = 29,
271 + JZ4740_DMA_TYPE_SLCD = 30,
272 +};
273 +
274 +enum jz4740_dma_width {
275 + JZ4740_DMA_WIDTH_32BIT = 0,
276 + JZ4740_DMA_WIDTH_8BIT = 1,
277 + JZ4740_DMA_WIDTH_16BIT = 2,
278 +};
279 +
280 +enum jz4740_dma_transfer_size {
281 + JZ4740_DMA_TRANSFER_SIZE_4BYTE = 0,
282 + JZ4740_DMA_TRANSFER_SIZE_1BYTE = 1,
283 + JZ4740_DMA_TRANSFER_SIZE_2BYTE = 2,
284 + JZ4740_DMA_TRANSFER_SIZE_16BYTE = 3,
285 + JZ4740_DMA_TRANSFER_SIZE_32BYTE = 4,
286 +};
287 +
288 +enum jz4740_dma_flags {
289 + JZ4740_DMA_SRC_AUTOINC = 0x2,
290 + JZ4740_DMA_DST_AUTOINC = 0x1,
291 +};
292 +
293 +enum jz4740_dma_mode {
294 + JZ4740_DMA_MODE_SINGLE = 0,
295 + JZ4740_DMA_MODE_BLOCK = 1,
296 +};
297 +
298 +struct jz4740_dma_config {
299 + enum jz4740_dma_width src_width;
300 + enum jz4740_dma_width dst_width;
301 + enum jz4740_dma_transfer_size transfer_size;
302 + enum jz4740_dma_request_type request_type;
303 + enum jz4740_dma_flags flags;
304 + enum jz4740_dma_mode mode;
305 +};
306 +
307 +typedef void (*jz4740_dma_complete_callback_t)(struct jz4740_dma_chan *, int, void *);
308 +
309 +struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name);
310 +void jz4740_dma_free(struct jz4740_dma_chan *dma);
311 +
312 +void jz4740_dma_configure(struct jz4740_dma_chan *dma,
313 + const struct jz4740_dma_config *config);
314 +
315 +
316 +void jz4740_dma_enable(struct jz4740_dma_chan *dma);
317 +void jz4740_dma_disable(struct jz4740_dma_chan *dma);
318 +
319 +void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src);
320 +void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst);
321 +void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count);
322 +
323 +uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma);
324 +
325 +void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
326 + jz4740_dma_complete_callback_t cb);
327 +
328 +#endif /* __ASM_JZ4740_DMA_H__ */
329 diff --git a/arch/mips/include/asm/mach-jz4740/gpio.h b/arch/mips/include/asm/mach-jz4740/gpio.h
330 new file mode 100644
331 index 0000000..5f175d7
332 --- /dev/null
333 +++ b/arch/mips/include/asm/mach-jz4740/gpio.h
334 @@ -0,0 +1,398 @@
335 +/*
336 + * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
337 + * JZ7420/JZ4740 GPIO pin definitions
338 + *
339 + * This program is free software; you can redistribute it and/or modify it
340 + * under the terms of the GNU General Public License as published by the
341 + * Free Software Foundation; either version 2 of the License, or (at your
342 + * option) any later version.
343 + *
344 + * You should have received a copy of the GNU General Public License along
345 + * with this program; if not, write to the Free Software Foundation, Inc.,
346 + * 675 Mass Ave, Cambridge, MA 02139, USA.
347 + *
348 + */
349 +
350 +#ifndef _JZ_GPIO_H
351 +#define _JZ_GPIO_H
352 +
353 +#include <linux/types.h>
354 +
355 +enum jz_gpio_function {
356 + JZ_GPIO_FUNC_NONE,
357 + JZ_GPIO_FUNC1,
358 + JZ_GPIO_FUNC2,
359 + JZ_GPIO_FUNC3,
360 +};
361 +
362 +
363 +/*
364 + Usually a driver for a SoC component has to request several gpio pins and
365 + configure them as funcion pins.
366 + jz_gpio_bulk_request can be used to ease this process.
367 + Usually one would do something like:
368 +
369 + const static struct jz_gpio_bulk_request i2c_pins[] = {
370 + JZ_GPIO_BULK_PIN(I2C_SDA),
371 + JZ_GPIO_BULK_PIN(I2C_SCK),
372 + };
373 +
374 + inside the probe function:
375 +
376 + ret = jz_gpio_bulk_request(i2c_pins, ARRAY_SIZE(i2c_pins));
377 + if (ret) {
378 + ...
379 +
380 + inside the remove function:
381 +
382 + jz_gpio_bulk_free(i2c_pins, ARRAY_SIZE(i2c_pins));
383 +
384 +
385 +*/
386 +struct jz_gpio_bulk_request {
387 + int gpio;
388 + const char *name;
389 + enum jz_gpio_function function;
390 +};
391 +
392 +#define JZ_GPIO_BULK_PIN(pin) { \
393 + .gpio = JZ_GPIO_ ## pin, \
394 + .name = #pin, \
395 + .function = JZ_GPIO_FUNC_ ## pin \
396 +}
397 +
398 +int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num);
399 +void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num);
400 +void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num);
401 +void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num);
402 +void jz_gpio_enable_pullup(unsigned gpio);
403 +void jz_gpio_disable_pullup(unsigned gpio);
404 +int jz_gpio_set_function(int gpio, enum jz_gpio_function function);
405 +
406 +int jz_gpio_port_direction_input(int port, uint32_t mask);
407 +int jz_gpio_port_direction_output(int port, uint32_t mask);
408 +void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask);
409 +uint32_t jz_gpio_port_get_value(int port, uint32_t mask);
410 +
411 +#include <asm/mach-generic/gpio.h>
412 +
413 +#define JZ_GPIO_PORTA(x) ((x) + 32 * 0)
414 +#define JZ_GPIO_PORTB(x) ((x) + 32 * 1)
415 +#define JZ_GPIO_PORTC(x) ((x) + 32 * 2)
416 +#define JZ_GPIO_PORTD(x) ((x) + 32 * 3)
417 +
418 +/* Port A function pins */
419 +#define JZ_GPIO_MEM_DATA0 JZ_GPIO_PORTA(0)
420 +#define JZ_GPIO_MEM_DATA1 JZ_GPIO_PORTA(1)
421 +#define JZ_GPIO_MEM_DATA2 JZ_GPIO_PORTA(2)
422 +#define JZ_GPIO_MEM_DATA3 JZ_GPIO_PORTA(3)
423 +#define JZ_GPIO_MEM_DATA4 JZ_GPIO_PORTA(4)
424 +#define JZ_GPIO_MEM_DATA5 JZ_GPIO_PORTA(5)
425 +#define JZ_GPIO_MEM_DATA6 JZ_GPIO_PORTA(6)
426 +#define JZ_GPIO_MEM_DATA7 JZ_GPIO_PORTA(7)
427 +#define JZ_GPIO_MEM_DATA8 JZ_GPIO_PORTA(8)
428 +#define JZ_GPIO_MEM_DATA9 JZ_GPIO_PORTA(9)
429 +#define JZ_GPIO_MEM_DATA10 JZ_GPIO_PORTA(10)
430 +#define JZ_GPIO_MEM_DATA11 JZ_GPIO_PORTA(11)
431 +#define JZ_GPIO_MEM_DATA12 JZ_GPIO_PORTA(12)
432 +#define JZ_GPIO_MEM_DATA13 JZ_GPIO_PORTA(13)
433 +#define JZ_GPIO_MEM_DATA14 JZ_GPIO_PORTA(14)
434 +#define JZ_GPIO_MEM_DATA15 JZ_GPIO_PORTA(15)
435 +#define JZ_GPIO_MEM_DATA16 JZ_GPIO_PORTA(16)
436 +#define JZ_GPIO_MEM_DATA17 JZ_GPIO_PORTA(17)
437 +#define JZ_GPIO_MEM_DATA18 JZ_GPIO_PORTA(18)
438 +#define JZ_GPIO_MEM_DATA19 JZ_GPIO_PORTA(19)
439 +#define JZ_GPIO_MEM_DATA20 JZ_GPIO_PORTA(20)
440 +#define JZ_GPIO_MEM_DATA21 JZ_GPIO_PORTA(21)
441 +#define JZ_GPIO_MEM_DATA22 JZ_GPIO_PORTA(22)
442 +#define JZ_GPIO_MEM_DATA23 JZ_GPIO_PORTA(23)
443 +#define JZ_GPIO_MEM_DATA24 JZ_GPIO_PORTA(24)
444 +#define JZ_GPIO_MEM_DATA25 JZ_GPIO_PORTA(25)
445 +#define JZ_GPIO_MEM_DATA26 JZ_GPIO_PORTA(26)
446 +#define JZ_GPIO_MEM_DATA27 JZ_GPIO_PORTA(27)
447 +#define JZ_GPIO_MEM_DATA28 JZ_GPIO_PORTA(28)
448 +#define JZ_GPIO_MEM_DATA29 JZ_GPIO_PORTA(29)
449 +#define JZ_GPIO_MEM_DATA30 JZ_GPIO_PORTA(30)
450 +#define JZ_GPIO_MEM_DATA31 JZ_GPIO_PORTA(31)
451 +
452 +#define JZ_GPIO_FUNC_MEM_DATA0 JZ_GPIO_FUNC1
453 +#define JZ_GPIO_FUNC_MEM_DATA1 JZ_GPIO_FUNC1
454 +#define JZ_GPIO_FUNC_MEM_DATA2 JZ_GPIO_FUNC1
455 +#define JZ_GPIO_FUNC_MEM_DATA3 JZ_GPIO_FUNC1
456 +#define JZ_GPIO_FUNC_MEM_DATA4 JZ_GPIO_FUNC1
457 +#define JZ_GPIO_FUNC_MEM_DATA5 JZ_GPIO_FUNC1
458 +#define JZ_GPIO_FUNC_MEM_DATA6 JZ_GPIO_FUNC1
459 +#define JZ_GPIO_FUNC_MEM_DATA7 JZ_GPIO_FUNC1
460 +#define JZ_GPIO_FUNC_MEM_DATA8 JZ_GPIO_FUNC1
461 +#define JZ_GPIO_FUNC_MEM_DATA9 JZ_GPIO_FUNC1
462 +#define JZ_GPIO_FUNC_MEM_DATA10 JZ_GPIO_FUNC1
463 +#define JZ_GPIO_FUNC_MEM_DATA11 JZ_GPIO_FUNC1
464 +#define JZ_GPIO_FUNC_MEM_DATA12 JZ_GPIO_FUNC1
465 +#define JZ_GPIO_FUNC_MEM_DATA13 JZ_GPIO_FUNC1
466 +#define JZ_GPIO_FUNC_MEM_DATA14 JZ_GPIO_FUNC1
467 +#define JZ_GPIO_FUNC_MEM_DATA15 JZ_GPIO_FUNC1
468 +#define JZ_GPIO_FUNC_MEM_DATA16 JZ_GPIO_FUNC1
469 +#define JZ_GPIO_FUNC_MEM_DATA17 JZ_GPIO_FUNC1
470 +#define JZ_GPIO_FUNC_MEM_DATA18 JZ_GPIO_FUNC1
471 +#define JZ_GPIO_FUNC_MEM_DATA19 JZ_GPIO_FUNC1
472 +#define JZ_GPIO_FUNC_MEM_DATA20 JZ_GPIO_FUNC1
473 +#define JZ_GPIO_FUNC_MEM_DATA21 JZ_GPIO_FUNC1
474 +#define JZ_GPIO_FUNC_MEM_DATA22 JZ_GPIO_FUNC1
475 +#define JZ_GPIO_FUNC_MEM_DATA23 JZ_GPIO_FUNC1
476 +#define JZ_GPIO_FUNC_MEM_DATA24 JZ_GPIO_FUNC1
477 +#define JZ_GPIO_FUNC_MEM_DATA25 JZ_GPIO_FUNC1
478 +#define JZ_GPIO_FUNC_MEM_DATA26 JZ_GPIO_FUNC1
479 +#define JZ_GPIO_FUNC_MEM_DATA27 JZ_GPIO_FUNC1
480 +#define JZ_GPIO_FUNC_MEM_DATA28 JZ_GPIO_FUNC1
481 +#define JZ_GPIO_FUNC_MEM_DATA29 JZ_GPIO_FUNC1
482 +#define JZ_GPIO_FUNC_MEM_DATA30 JZ_GPIO_FUNC1
483 +#define JZ_GPIO_FUNC_MEM_DATA31 JZ_GPIO_FUNC1
484 +
485 +/* Port B function pins */
486 +#define JZ_GPIO_MEM_ADDR0 JZ_GPIO_PORTB(0)
487 +#define JZ_GPIO_MEM_ADDR1 JZ_GPIO_PORTB(1)
488 +#define JZ_GPIO_MEM_ADDR2 JZ_GPIO_PORTB(2)
489 +#define JZ_GPIO_MEM_ADDR3 JZ_GPIO_PORTB(3)
490 +#define JZ_GPIO_MEM_ADDR4 JZ_GPIO_PORTB(4)
491 +#define JZ_GPIO_MEM_ADDR5 JZ_GPIO_PORTB(5)
492 +#define JZ_GPIO_MEM_ADDR6 JZ_GPIO_PORTB(6)
493 +#define JZ_GPIO_MEM_ADDR7 JZ_GPIO_PORTB(7)
494 +#define JZ_GPIO_MEM_ADDR8 JZ_GPIO_PORTB(8)
495 +#define JZ_GPIO_MEM_ADDR9 JZ_GPIO_PORTB(9)
496 +#define JZ_GPIO_MEM_ADDR10 JZ_GPIO_PORTB(10)
497 +#define JZ_GPIO_MEM_ADDR11 JZ_GPIO_PORTB(11)
498 +#define JZ_GPIO_MEM_ADDR12 JZ_GPIO_PORTB(12)
499 +#define JZ_GPIO_MEM_ADDR13 JZ_GPIO_PORTB(13)
500 +#define JZ_GPIO_MEM_ADDR14 JZ_GPIO_PORTB(14)
501 +#define JZ_GPIO_MEM_ADDR15 JZ_GPIO_PORTB(15)
502 +#define JZ_GPIO_MEM_ADDR16 JZ_GPIO_PORTB(16)
503 +#define JZ_GPIO_MEM_CLS JZ_GPIO_PORTB(17)
504 +#define JZ_GPIO_MEM_SPL JZ_GPIO_PORTB(18)
505 +#define JZ_GPIO_MEM_DCS JZ_GPIO_PORTB(19)
506 +#define JZ_GPIO_MEM_RAS JZ_GPIO_PORTB(20)
507 +#define JZ_GPIO_MEM_CAS JZ_GPIO_PORTB(21)
508 +#define JZ_GPIO_MEM_SDWE JZ_GPIO_PORTB(22)
509 +#define JZ_GPIO_MEM_CKE JZ_GPIO_PORTB(23)
510 +#define JZ_GPIO_MEM_CKO JZ_GPIO_PORTB(24)
511 +#define JZ_GPIO_MEM_CS0 JZ_GPIO_PORTB(25)
512 +#define JZ_GPIO_MEM_CS1 JZ_GPIO_PORTB(26)
513 +#define JZ_GPIO_MEM_CS2 JZ_GPIO_PORTB(27)
514 +#define JZ_GPIO_MEM_CS3 JZ_GPIO_PORTB(28)
515 +#define JZ_GPIO_MEM_RD JZ_GPIO_PORTB(29)
516 +#define JZ_GPIO_MEM_WR JZ_GPIO_PORTB(30)
517 +#define JZ_GPIO_MEM_WE0 JZ_GPIO_PORTB(31)
518 +
519 +#define JZ_GPIO_FUNC_MEM_ADDR0 JZ_GPIO_FUNC1
520 +#define JZ_GPIO_FUNC_MEM_ADDR1 JZ_GPIO_FUNC1
521 +#define JZ_GPIO_FUNC_MEM_ADDR2 JZ_GPIO_FUNC1
522 +#define JZ_GPIO_FUNC_MEM_ADDR3 JZ_GPIO_FUNC1
523 +#define JZ_GPIO_FUNC_MEM_ADDR4 JZ_GPIO_FUNC1
524 +#define JZ_GPIO_FUNC_MEM_ADDR5 JZ_GPIO_FUNC1
525 +#define JZ_GPIO_FUNC_MEM_ADDR6 JZ_GPIO_FUNC1
526 +#define JZ_GPIO_FUNC_MEM_ADDR7 JZ_GPIO_FUNC1
527 +#define JZ_GPIO_FUNC_MEM_ADDR8 JZ_GPIO_FUNC1
528 +#define JZ_GPIO_FUNC_MEM_ADDR9 JZ_GPIO_FUNC1
529 +#define JZ_GPIO_FUNC_MEM_ADDR10 JZ_GPIO_FUNC1
530 +#define JZ_GPIO_FUNC_MEM_ADDR11 JZ_GPIO_FUNC1
531 +#define JZ_GPIO_FUNC_MEM_ADDR12 JZ_GPIO_FUNC1
532 +#define JZ_GPIO_FUNC_MEM_ADDR13 JZ_GPIO_FUNC1
533 +#define JZ_GPIO_FUNC_MEM_ADDR14 JZ_GPIO_FUNC1
534 +#define JZ_GPIO_FUNC_MEM_ADDR15 JZ_GPIO_FUNC1
535 +#define JZ_GPIO_FUNC_MEM_ADDR16 JZ_GPIO_FUNC1
536 +#define JZ_GPIO_FUNC_MEM_CLS JZ_GPIO_FUNC1
537 +#define JZ_GPIO_FUNC_MEM_SPL JZ_GPIO_FUNC1
538 +#define JZ_GPIO_FUNC_MEM_DCS JZ_GPIO_FUNC1
539 +#define JZ_GPIO_FUNC_MEM_RAS JZ_GPIO_FUNC1
540 +#define JZ_GPIO_FUNC_MEM_CAS JZ_GPIO_FUNC1
541 +#define JZ_GPIO_FUNC_MEM_SDWE JZ_GPIO_FUNC1
542 +#define JZ_GPIO_FUNC_MEM_CKE JZ_GPIO_FUNC1
543 +#define JZ_GPIO_FUNC_MEM_CKO JZ_GPIO_FUNC1
544 +#define JZ_GPIO_FUNC_MEM_CS0 JZ_GPIO_FUNC1
545 +#define JZ_GPIO_FUNC_MEM_CS1 JZ_GPIO_FUNC1
546 +#define JZ_GPIO_FUNC_MEM_CS2 JZ_GPIO_FUNC1
547 +#define JZ_GPIO_FUNC_MEM_CS3 JZ_GPIO_FUNC1
548 +#define JZ_GPIO_FUNC_MEM_RD JZ_GPIO_FUNC1
549 +#define JZ_GPIO_FUNC_MEM_WR JZ_GPIO_FUNC1
550 +#define JZ_GPIO_FUNC_MEM_WE0 JZ_GPIO_FUNC1
551 +
552 +
553 +#define JZ_GPIO_MEM_ADDR21 JZ_GPIO_PORTB(17)
554 +#define JZ_GPIO_MEM_ADDR22 JZ_GPIO_PORTB(18)
555 +
556 +#define JZ_GPIO_FUNC_MEM_ADDR21 JZ_GPIO_FUNC2
557 +#define JZ_GPIO_FUNC_MEM_ADDR22 JZ_GPIO_FUNC2
558 +
559 +/* Port C function pins */
560 +#define JZ_GPIO_LCD_DATA0 JZ_GPIO_PORTC(0)
561 +#define JZ_GPIO_LCD_DATA1 JZ_GPIO_PORTC(1)
562 +#define JZ_GPIO_LCD_DATA2 JZ_GPIO_PORTC(2)
563 +#define JZ_GPIO_LCD_DATA3 JZ_GPIO_PORTC(3)
564 +#define JZ_GPIO_LCD_DATA4 JZ_GPIO_PORTC(4)
565 +#define JZ_GPIO_LCD_DATA5 JZ_GPIO_PORTC(5)
566 +#define JZ_GPIO_LCD_DATA6 JZ_GPIO_PORTC(6)
567 +#define JZ_GPIO_LCD_DATA7 JZ_GPIO_PORTC(7)
568 +#define JZ_GPIO_LCD_DATA8 JZ_GPIO_PORTC(8)
569 +#define JZ_GPIO_LCD_DATA9 JZ_GPIO_PORTC(9)
570 +#define JZ_GPIO_LCD_DATA10 JZ_GPIO_PORTC(10)
571 +#define JZ_GPIO_LCD_DATA11 JZ_GPIO_PORTC(11)
572 +#define JZ_GPIO_LCD_DATA12 JZ_GPIO_PORTC(12)
573 +#define JZ_GPIO_LCD_DATA13 JZ_GPIO_PORTC(13)
574 +#define JZ_GPIO_LCD_DATA14 JZ_GPIO_PORTC(14)
575 +#define JZ_GPIO_LCD_DATA15 JZ_GPIO_PORTC(15)
576 +#define JZ_GPIO_LCD_DATA16 JZ_GPIO_PORTC(16)
577 +#define JZ_GPIO_LCD_DATA17 JZ_GPIO_PORTC(17)
578 +#define JZ_GPIO_LCD_PCLK JZ_GPIO_PORTC(18)
579 +#define JZ_GPIO_LCD_HSYNC JZ_GPIO_PORTC(19)
580 +#define JZ_GPIO_LCD_VSYNC JZ_GPIO_PORTC(20)
581 +#define JZ_GPIO_LCD_DE JZ_GPIO_PORTC(21)
582 +#define JZ_GPIO_LCD_PS JZ_GPIO_PORTC(22)
583 +#define JZ_GPIO_LCD_REV JZ_GPIO_PORTC(23)
584 +#define JZ_GPIO_MEM_WE1 JZ_GPIO_PORTC(24)
585 +#define JZ_GPIO_MEM_WE2 JZ_GPIO_PORTC(25)
586 +#define JZ_GPIO_MEM_WE3 JZ_GPIO_PORTC(26)
587 +#define JZ_GPIO_MEM_WAIT JZ_GPIO_PORTC(27)
588 +#define JZ_GPIO_MEM_FRE JZ_GPIO_PORTC(28)
589 +#define JZ_GPIO_MEM_FWE JZ_GPIO_PORTC(29)
590 +
591 +#define JZ_GPIO_FUNC_LCD_DATA0 JZ_GPIO_FUNC1
592 +#define JZ_GPIO_FUNC_LCD_DATA1 JZ_GPIO_FUNC1
593 +#define JZ_GPIO_FUNC_LCD_DATA2 JZ_GPIO_FUNC1
594 +#define JZ_GPIO_FUNC_LCD_DATA3 JZ_GPIO_FUNC1
595 +#define JZ_GPIO_FUNC_LCD_DATA4 JZ_GPIO_FUNC1
596 +#define JZ_GPIO_FUNC_LCD_DATA5 JZ_GPIO_FUNC1
597 +#define JZ_GPIO_FUNC_LCD_DATA6 JZ_GPIO_FUNC1
598 +#define JZ_GPIO_FUNC_LCD_DATA7 JZ_GPIO_FUNC1
599 +#define JZ_GPIO_FUNC_LCD_DATA8 JZ_GPIO_FUNC1
600 +#define JZ_GPIO_FUNC_LCD_DATA9 JZ_GPIO_FUNC1
601 +#define JZ_GPIO_FUNC_LCD_DATA10 JZ_GPIO_FUNC1
602 +#define JZ_GPIO_FUNC_LCD_DATA11 JZ_GPIO_FUNC1
603 +#define JZ_GPIO_FUNC_LCD_DATA12 JZ_GPIO_FUNC1
604 +#define JZ_GPIO_FUNC_LCD_DATA13 JZ_GPIO_FUNC1
605 +#define JZ_GPIO_FUNC_LCD_DATA14 JZ_GPIO_FUNC1
606 +#define JZ_GPIO_FUNC_LCD_DATA15 JZ_GPIO_FUNC1
607 +#define JZ_GPIO_FUNC_LCD_DATA16 JZ_GPIO_FUNC1
608 +#define JZ_GPIO_FUNC_LCD_DATA17 JZ_GPIO_FUNC1
609 +#define JZ_GPIO_FUNC_LCD_PCLK JZ_GPIO_FUNC1
610 +#define JZ_GPIO_FUNC_LCD_VSYNC JZ_GPIO_FUNC1
611 +#define JZ_GPIO_FUNC_LCD_HSYNC JZ_GPIO_FUNC1
612 +#define JZ_GPIO_FUNC_LCD_DE JZ_GPIO_FUNC1
613 +#define JZ_GPIO_FUNC_LCD_PS JZ_GPIO_FUNC1
614 +#define JZ_GPIO_FUNC_LCD_REV JZ_GPIO_FUNC1
615 +#define JZ_GPIO_FUNC_MEM_WE1 JZ_GPIO_FUNC1
616 +#define JZ_GPIO_FUNC_MEM_WE2 JZ_GPIO_FUNC1
617 +#define JZ_GPIO_FUNC_MEM_WE3 JZ_GPIO_FUNC1
618 +#define JZ_GPIO_FUNC_MEM_WAIT JZ_GPIO_FUNC1
619 +#define JZ_GPIO_FUNC_MEM_FRE JZ_GPIO_FUNC1
620 +#define JZ_GPIO_FUNC_MEM_FWE JZ_GPIO_FUNC1
621 +
622 +
623 +#define JZ_GPIO_MEM_ADDR19 JZ_GPIO_PORTB(22)
624 +#define JZ_GPIO_MEM_ADDR20 JZ_GPIO_PORTB(23)
625 +
626 +#define JZ_GPIO_FUNC_MEM_ADDR19 JZ_GPIO_FUNC2
627 +#define JZ_GPIO_FUNC_MEM_ADDR20 JZ_GPIO_FUNC2
628 +
629 +/* Port D function pins */
630 +#define JZ_GPIO_CIM_DATA0 JZ_GPIO_PORTD(0)
631 +#define JZ_GPIO_CIM_DATA1 JZ_GPIO_PORTD(1)
632 +#define JZ_GPIO_CIM_DATA2 JZ_GPIO_PORTD(2)
633 +#define JZ_GPIO_CIM_DATA3 JZ_GPIO_PORTD(3)
634 +#define JZ_GPIO_CIM_DATA4 JZ_GPIO_PORTD(4)
635 +#define JZ_GPIO_CIM_DATA5 JZ_GPIO_PORTD(5)
636 +#define JZ_GPIO_CIM_DATA6 JZ_GPIO_PORTD(6)
637 +#define JZ_GPIO_CIM_DATA7 JZ_GPIO_PORTD(7)
638 +#define JZ_GPIO_MSC_CMD JZ_GPIO_PORTD(8)
639 +#define JZ_GPIO_MSC_CLK JZ_GPIO_PORTD(9)
640 +#define JZ_GPIO_MSC_DATA0 JZ_GPIO_PORTD(10)
641 +#define JZ_GPIO_MSC_DATA1 JZ_GPIO_PORTD(11)
642 +#define JZ_GPIO_MSC_DATA2 JZ_GPIO_PORTD(12)
643 +#define JZ_GPIO_MSC_DATA3 JZ_GPIO_PORTD(13)
644 +#define JZ_GPIO_CIM_MCLK JZ_GPIO_PORTD(14)
645 +#define JZ_GPIO_CIM_PCLK JZ_GPIO_PORTD(15)
646 +#define JZ_GPIO_CIM_VSYNC JZ_GPIO_PORTD(16)
647 +#define JZ_GPIO_CIM_HSYNC JZ_GPIO_PORTD(17)
648 +#define JZ_GPIO_SPI_CLK JZ_GPIO_PORTD(18)
649 +#define JZ_GPIO_SPI_CE0 JZ_GPIO_PORTD(19)
650 +#define JZ_GPIO_SPI_DT JZ_GPIO_PORTD(20)
651 +#define JZ_GPIO_SPI_DR JZ_GPIO_PORTD(21)
652 +#define JZ_GPIO_SPI_CE1 JZ_GPIO_PORTD(22)
653 +#define JZ_GPIO_PWM0 JZ_GPIO_PORTD(23)
654 +#define JZ_GPIO_PWM1 JZ_GPIO_PORTD(24)
655 +#define JZ_GPIO_PWM2 JZ_GPIO_PORTD(25)
656 +#define JZ_GPIO_PWM3 JZ_GPIO_PORTD(26)
657 +#define JZ_GPIO_PWM4 JZ_GPIO_PORTD(27)
658 +#define JZ_GPIO_PWM5 JZ_GPIO_PORTD(28)
659 +#define JZ_GPIO_PWM6 JZ_GPIO_PORTD(30)
660 +#define JZ_GPIO_PWM7 JZ_GPIO_PORTD(31)
661 +
662 +#define JZ_GPIO_FUNC_CIM_DATA JZ_GPIO_FUNC1
663 +#define JZ_GPIO_FUNC_CIM_DATA0 JZ_GPIO_FUNC_CIM_DATA
664 +#define JZ_GPIO_FUNC_CIM_DATA1 JZ_GPIO_FUNC_CIM_DATA
665 +#define JZ_GPIO_FUNC_CIM_DATA2 JZ_GPIO_FUNC_CIM_DATA
666 +#define JZ_GPIO_FUNC_CIM_DATA3 JZ_GPIO_FUNC_CIM_DATA
667 +#define JZ_GPIO_FUNC_CIM_DATA4 JZ_GPIO_FUNC_CIM_DATA
668 +#define JZ_GPIO_FUNC_CIM_DATA5 JZ_GPIO_FUNC_CIM_DATA
669 +#define JZ_GPIO_FUNC_CIM_DATA6 JZ_GPIO_FUNC_CIM_DATA
670 +#define JZ_GPIO_FUNC_CIM_DATA7 JZ_GPIO_FUNC_CIM_DATA
671 +#define JZ_GPIO_FUNC_MSC_CMD JZ_GPIO_FUNC1
672 +#define JZ_GPIO_FUNC_MSC_CLK JZ_GPIO_FUNC1
673 +#define JZ_GPIO_FUNC_MSC_DATA JZ_GPIO_FUNC1
674 +#define JZ_GPIO_FUNC_MSC_DATA0 JZ_GPIO_FUNC_MSC_DATA
675 +#define JZ_GPIO_FUNC_MSC_DATA1 JZ_GPIO_FUNC_MSC_DATA
676 +#define JZ_GPIO_FUNC_MSC_DATA2 JZ_GPIO_FUNC_MSC_DATA
677 +#define JZ_GPIO_FUNC_MSC_DATA3 JZ_GPIO_FUNC_MSC_DATA
678 +#define JZ_GPIO_FUNC_CIM_MCLK JZ_GPIO_FUNC1
679 +#define JZ_GPIO_FUNC_CIM_PCLK JZ_GPIO_FUNC1
680 +#define JZ_GPIO_FUNC_CIM_VSYNC JZ_GPIO_FUNC1
681 +#define JZ_GPIO_FUNC_CIM_HSYNC JZ_GPIO_FUNC1
682 +#define JZ_GPIO_FUNC_SPI_CLK JZ_GPIO_FUNC1
683 +#define JZ_GPIO_FUNC_SPI_CE0 JZ_GPIO_FUNC1
684 +#define JZ_GPIO_FUNC_SPI_DT JZ_GPIO_FUNC1
685 +#define JZ_GPIO_FUNC_SPI_DR JZ_GPIO_FUNC1
686 +#define JZ_GPIO_FUNC_SPI_CE1 JZ_GPIO_FUNC1
687 +
688 +#define JZ_GPIO_FUNC_PWM JZ_GPIO_FUNC1
689 +#define JZ_GPIO_FUNC_PWM0 JZ_GPIO_FUNC_PWM
690 +#define JZ_GPIO_FUNC_PWM1 JZ_GPIO_FUNC_PWM
691 +#define JZ_GPIO_FUNC_PWM2 JZ_GPIO_FUNC_PWM
692 +#define JZ_GPIO_FUNC_PWM3 JZ_GPIO_FUNC_PWM
693 +#define JZ_GPIO_FUNC_PWM4 JZ_GPIO_FUNC_PWM
694 +#define JZ_GPIO_FUNC_PWM5 JZ_GPIO_FUNC_PWM
695 +#define JZ_GPIO_FUNC_PWM6 JZ_GPIO_FUNC_PWM
696 +#define JZ_GPIO_FUNC_PWM7 JZ_GPIO_FUNC_PWM
697 +
698 +#define JZ_GPIO_MEM_SCLK_RSTN JZ_GPIO_PORTD(18)
699 +#define JZ_GPIO_MEM_BCLK JZ_GPIO_PORTD(19)
700 +#define JZ_GPIO_MEM_SDATO JZ_GPIO_PORTD(20)
701 +#define JZ_GPIO_MEM_SDATI JZ_GPIO_PORTD(21)
702 +#define JZ_GPIO_MEM_SYNC JZ_GPIO_PORTD(22)
703 +#define JZ_GPIO_I2C_SDA JZ_GPIO_PORTD(23)
704 +#define JZ_GPIO_I2C_SCK JZ_GPIO_PORTD(24)
705 +#define JZ_GPIO_UART0_TXD JZ_GPIO_PORTD(25)
706 +#define JZ_GPIO_UART0_RXD JZ_GPIO_PORTD(26)
707 +#define JZ_GPIO_MEM_ADDR17 JZ_GPIO_PORTD(27)
708 +#define JZ_GPIO_MEM_ADDR18 JZ_GPIO_PORTD(28)
709 +#define JZ_GPIO_UART0_CTS JZ_GPIO_PORTD(30)
710 +#define JZ_GPIO_UART0_RTS JZ_GPIO_PORTD(31)
711 +
712 +#define JZ_GPIO_FUNC_MEM_SCLK_RSTN JZ_GPIO_FUNC2
713 +#define JZ_GPIO_FUNC_MEM_BCLK JZ_GPIO_FUNC2
714 +#define JZ_GPIO_FUNC_MEM_SDATO JZ_GPIO_FUNC2
715 +#define JZ_GPIO_FUNC_MEM_SDATI JZ_GPIO_FUNC2
716 +#define JZ_GPIO_FUNC_MEM_SYNC JZ_GPIO_FUNC2
717 +#define JZ_GPIO_FUNC_I2C_SDA JZ_GPIO_FUNC2
718 +#define JZ_GPIO_FUNC_I2C_SCK JZ_GPIO_FUNC2
719 +#define JZ_GPIO_FUNC_UART0_TXD JZ_GPIO_FUNC2
720 +#define JZ_GPIO_FUNC_UART0_RXD JZ_GPIO_FUNC2
721 +#define JZ_GPIO_FUNC_MEM_ADDR17 JZ_GPIO_FUNC2
722 +#define JZ_GPIO_FUNC_MEM_ADDR18 JZ_GPIO_FUNC2
723 +#define JZ_GPIO_FUNC_UART0_CTS JZ_GPIO_FUNC2
724 +#define JZ_GPIO_FUNC_UART0_RTS JZ_GPIO_FUNC2
725 +
726 +#define JZ_GPIO_UART1_RXD JZ_GPIO_PORTD(30)
727 +#define JZ_GPIO_UART1_TXD JZ_GPIO_PORTD(31)
728 +
729 +#define JZ_GPIO_FUNC_UART1_RXD JZ_GPIO_FUNC3
730 +#define JZ_GPIO_FUNC_UART1_TXD JZ_GPIO_FUNC3
731 +
732 +#endif
733 diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
734 new file mode 100644
735 index 0000000..5e27b78
736 --- /dev/null
737 +++ b/arch/mips/include/asm/mach-jz4740/irq.h
738 @@ -0,0 +1,55 @@
739 +/*
740 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
741 + * JZ7420/JZ4740 IRQ definitions
742 + *
743 + * This program is free software; you can redistribute it and/or modify it
744 + * under the terms of the GNU General Public License as published by the
745 + * Free Software Foundation; either version 2 of the License, or (at your
746 + * option) any later version.
747 + *
748 + * You should have received a copy of the GNU General Public License along
749 + * with this program; if not, write to the Free Software Foundation, Inc.,
750 + * 675 Mass Ave, Cambridge, MA 02139, USA.
751 + *
752 + */
753 +
754 +#ifndef __ASM_MACH_JZ4740_IRQ_H__
755 +#define __ASM_MACH_JZ4740_IRQ_H__
756 +
757 +#define MIPS_CPU_IRQ_BASE 0
758 +#define JZ4740_IRQ_BASE 8
759 +
760 +/* 1st-level interrupts */
761 +#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x))
762 +#define JZ4740_IRQ_I2C JZ4740_IRQ(1)
763 +#define JZ4740_IRQ_UHC JZ4740_IRQ(3)
764 +#define JZ4740_IRQ_UART1 JZ4740_IRQ(8)
765 +#define JZ4740_IRQ_UART0 JZ4740_IRQ(9)
766 +#define JZ4740_IRQ_SADC JZ4740_IRQ(12)
767 +#define JZ4740_IRQ_MSC JZ4740_IRQ(14)
768 +#define JZ4740_IRQ_RTC JZ4740_IRQ(15)
769 +#define JZ4740_IRQ_SSI JZ4740_IRQ(16)
770 +#define JZ4740_IRQ_CIM JZ4740_IRQ(17)
771 +#define JZ4740_IRQ_AIC JZ4740_IRQ(18)
772 +#define JZ4740_IRQ_ETH JZ4740_IRQ(19)
773 +#define JZ4740_IRQ_DMAC JZ4740_IRQ(20)
774 +#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21)
775 +#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22)
776 +#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23)
777 +#define JZ4740_IRQ_UDC JZ4740_IRQ(24)
778 +#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25)
779 +#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26)
780 +#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27)
781 +#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28)
782 +#define JZ4740_IRQ_IPU JZ4740_IRQ(29)
783 +#define JZ4740_IRQ_LCD JZ4740_IRQ(30)
784 +
785 +/* 2nd-level interrupts */
786 +#define JZ4740_IRQ_DMA(x) ((x) + JZ4740_IRQ(32))
787 +
788 +#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
789 +#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x))
790 +
791 +#define NR_IRQS (JZ4740_IRQ_GPIO(127) + 1)
792 +
793 +#endif
794 diff --git a/arch/mips/include/asm/mach-jz4740/platform.h b/arch/mips/include/asm/mach-jz4740/platform.h
795 new file mode 100644
796 index 0000000..a2e2871
797 --- /dev/null
798 +++ b/arch/mips/include/asm/mach-jz4740/platform.h
799 @@ -0,0 +1,34 @@
800 +/*
801 + * Copyright (C) 2009, Lars-Peter Clausen <lars@metafoo.de>
802 + * JZ7420/JZ4740 platform device definitions
803 + *
804 + * This program is free software; you can redistribute it and/or modify it
805 + * under the terms of the GNU General Public License as published by the
806 + * Free Software Foundation; either version 2 of the License, or (at your
807 + * option) any later version.
808 + *
809 + * You should have received a copy of the GNU General Public License along
810 + * with this program; if not, write to the Free Software Foundation, Inc.,
811 + * 675 Mass Ave, Cambridge, MA 02139, USA.
812 + *
813 + */
814 +
815 +
816 +#ifndef __JZ4740_PLATFORM_H
817 +#define __JZ4740_PLATFORM_H
818 +
819 +#include <linux/platform_device.h>
820 +
821 +extern struct platform_device jz4740_usb_ohci_device;
822 +extern struct platform_device jz4740_usb_gdt_device;
823 +extern struct platform_device jz4740_mmc_device;
824 +extern struct platform_device jz4740_rtc_device;
825 +extern struct platform_device jz4740_i2c_device;
826 +extern struct platform_device jz4740_nand_device;
827 +extern struct platform_device jz4740_framebuffer_device;
828 +extern struct platform_device jz4740_i2s_device;
829 +extern struct platform_device jz4740_codec_device;
830 +extern struct platform_device jz4740_adc_device;
831 +extern struct platform_device jz4740_battery_device;
832 +
833 +#endif
834 diff --git a/arch/mips/include/asm/mach-jz4740/serial.h b/arch/mips/include/asm/mach-jz4740/serial.h
835 new file mode 100644
836 index 0000000..c4819b9
837 --- /dev/null
838 +++ b/arch/mips/include/asm/mach-jz4740/serial.h
839 @@ -0,0 +1,30 @@
840 +/*
841 + * linux/include/asm-mips/mach-jz4740/serial.h
842 + *
843 + * Ingenic's JZ4740 common include.
844 + *
845 + * Copyright (C) 2006 - 2007 Ingenic Semiconductor Inc.
846 + *
847 + * Author: <yliu@ingenic.cn>
848 + *
849 + * This program is free software; you can redistribute it and/or modify
850 + * it under the terms of the GNU General Public License version 2 as
851 + * published by the Free Software Foundation.
852 + */
853 +
854 +#ifndef __ASM_BOARD_SERIAL_H__
855 +#define __ASM_BOARD_SERIAL_H__
856 +
857 +#ifndef CONFIG_SERIAL_MANY_PORTS
858 +#undef RS_TABLE_SIZE
859 +#define RS_TABLE_SIZE 1
860 +#endif
861 +
862 +#define JZ_BASE_BAUD (12000000/16)
863 +
864 +#define JZ_SERIAL_PORT_DEFNS \
865 + { .baud_base = JZ_BASE_BAUD, .irq = IRQ_UART0, \
866 + .flags = STD_COM_FLAGS, .iomem_base = (u8 *)UART0_BASE, \
867 + .iomem_reg_shift = 2, .io_type = SERIAL_IO_MEM },
868 +
869 +#endif /* __ASM_BORAD_SERIAL_H__ */
870 diff --git a/arch/mips/include/asm/mach-jz4740/timer.h b/arch/mips/include/asm/mach-jz4740/timer.h
871 new file mode 100644
872 index 0000000..30153ff
873 --- /dev/null
874 +++ b/arch/mips/include/asm/mach-jz4740/timer.h
875 @@ -0,0 +1,22 @@
876 +/*
877 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
878 + * JZ4740 platform timer support
879 + *
880 + * This program is free software; you can redistribute it and/or modify it
881 + * under the terms of the GNU General Public License as published by the
882 + * Free Software Foundation; either version 2 of the License, or (at your
883 + * option) any later version.
884 + *
885 + * You should have received a copy of the GNU General Public License along
886 + * with this program; if not, write to the Free Software Foundation, Inc.,
887 + * 675 Mass Ave, Cambridge, MA 02139, USA.
888 + *
889 + */
890 +
891 +#ifndef __ASM_MACH_JZ4740_TIMER
892 +#define __ASM_MACH_JZ4740_TIMER
893 +
894 +void jz4740_timer_enable_watchdog(void);
895 +void jz4740_timer_disable_watchdog(void);
896 +
897 +#endif
898 diff --git a/arch/mips/include/asm/mach-jz4740/war.h b/arch/mips/include/asm/mach-jz4740/war.h
899 new file mode 100644
900 index 0000000..3a5bc17
901 --- /dev/null
902 +++ b/arch/mips/include/asm/mach-jz4740/war.h
903 @@ -0,0 +1,25 @@
904 +/*
905 + * This file is subject to the terms and conditions of the GNU General Public
906 + * License. See the file "COPYING" in the main directory of this archive
907 + * for more details.
908 + *
909 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
910 + */
911 +#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
912 +#define __ASM_MIPS_MACH_JZ4740_WAR_H
913 +
914 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
915 +#define R4600_V1_HIT_CACHEOP_WAR 0
916 +#define R4600_V2_HIT_CACHEOP_WAR 0
917 +#define R5432_CP0_INTERRUPT_WAR 0
918 +#define BCM1250_M3_WAR 0
919 +#define SIBYTE_1956_WAR 0
920 +#define MIPS4K_ICACHE_REFILL_WAR 0
921 +#define MIPS_CACHE_SYNC_WAR 0
922 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
923 +#define RM9000_CDEX_SMP_WAR 0
924 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
925 +#define R10000_LLSC_WAR 0
926 +#define MIPS34K_MISSED_ITLB_WAR 0
927 +
928 +#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
929 diff --git a/arch/mips/jz4740/Kconfig b/arch/mips/jz4740/Kconfig
930 new file mode 100644
931 index 0000000..b959769
932 --- /dev/null
933 +++ b/arch/mips/jz4740/Kconfig
934 @@ -0,0 +1,29 @@
935 +choice
936 + prompt "Machine type"
937 + depends on MACH_JZ
938 + default JZ4740_QI_LB60
939 +
940 +endchoice
941 +
942 +config HAVE_PWM
943 + bool
944 +
945 +config SOC_JZ4740
946 + bool
947 + select JZSOC
948 + select GENERIC_GPIO
949 + select ARCH_REQUIRE_GPIOLIB
950 + select SYS_HAS_EARLY_PRINTK
951 + select SYS_SUPPORTS_LITTLE_ENDIAN
952 + select IRQ_CPU
953 + select DMA_NONCOHERENT
954 + select HAVE_PWM
955 +
956 +config JZSOC
957 + bool
958 + select JZRISC
959 + select SYS_HAS_CPU_MIPS32_R1
960 + select SYS_SUPPORTS_32BIT_KERNEL
961 +
962 +config JZRISC
963 + bool
964 diff --git a/arch/mips/jz4740/Makefile b/arch/mips/jz4740/Makefile
965 new file mode 100644
966 index 0000000..398ee91
967 --- /dev/null
968 +++ b/arch/mips/jz4740/Makefile
969 @@ -0,0 +1,18 @@
970 +#
971 +# Makefile for the Ingenic JZ4740.
972 +#
973 +
974 +# Object file lists.
975 +
976 +obj-y += prom.o irq.o time.o reset.o setup.o dma.o \
977 + gpio.o clock.o platform.o timer.o pwm.o
978 +
979 +obj-$(CONFIG_DEBUG_FS) += clock-debugfs.o
980 +
981 +# board specific support
982 +
983 +# PM support
984 +
985 +obj-$(CONFIG_PM) += pm.o
986 +
987 +EXTRA_CFLAGS += -Werror -Wall
988 diff --git a/arch/mips/jz4740/clock-debugfs.c b/arch/mips/jz4740/clock-debugfs.c
989 new file mode 100644
990 index 0000000..993b91b
991 --- /dev/null
992 +++ b/arch/mips/jz4740/clock-debugfs.c
993 @@ -0,0 +1,109 @@
994 +/*
995 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
996 + * JZ4740 SoC clock support debugfs entries
997 + *
998 + * This program is free software; you can redistribute it and/or modify it
999 + * under the terms of the GNU General Public License as published by the
1000 + * Free Software Foundation; either version 2 of the License, or (at your
1001 + * option) any later version.
1002 + *
1003 + * You should have received a copy of the GNU General Public License along
1004 + * with this program; if not, write to the Free Software Foundation, Inc.,
1005 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1006 + *
1007 + */
1008 +
1009 +#include <linux/kernel.h>
1010 +#include <linux/module.h>
1011 +#include <linux/clk.h>
1012 +#include <linux/err.h>
1013 +
1014 +#include <linux/debugfs.h>
1015 +#include <linux/uaccess.h>
1016 +
1017 +#include <asm/mach-jz4740/clock.h>
1018 +#include "clock.h"
1019 +
1020 +static struct dentry *jz4740_clock_debugfs;
1021 +
1022 +static int jz4740_clock_debugfs_show_enabled(void *data, uint64_t *value)
1023 +{
1024 + struct clk *clk = data;
1025 + *value = clk_is_enabled(clk);
1026 +
1027 + return 0;
1028 +}
1029 +
1030 +static int jz4740_clock_debugfs_set_enabled(void *data, uint64_t value)
1031 +{
1032 + struct clk *clk = data;
1033 +
1034 + if (value)
1035 + return clk_enable(clk);
1036 + else
1037 + clk_disable(clk);
1038 +
1039 + return 0;
1040 +}
1041 +
1042 +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_enabled,
1043 + jz4740_clock_debugfs_show_enabled,
1044 + jz4740_clock_debugfs_set_enabled,
1045 + "%llu\n");
1046 +
1047 +static int jz4740_clock_debugfs_show_rate(void *data, uint64_t *value)
1048 +{
1049 + struct clk *clk = data;
1050 + *value = clk_get_rate(clk);
1051 +
1052 + return 0;
1053 +}
1054 +
1055 +DEFINE_SIMPLE_ATTRIBUTE(jz4740_clock_debugfs_ops_rate,
1056 + jz4740_clock_debugfs_show_rate,
1057 + NULL,
1058 + "%llu\n");
1059 +
1060 +void jz4740_clock_debugfs_add_clk(struct clk *clk)
1061 +{
1062 + if (!jz4740_clock_debugfs)
1063 + return;
1064 +
1065 + clk->debugfs_entry = debugfs_create_dir(clk->name, jz4740_clock_debugfs);
1066 + debugfs_create_file("rate", S_IWUGO | S_IRUGO, clk->debugfs_entry, clk,
1067 + &jz4740_clock_debugfs_ops_rate);
1068 + debugfs_create_file("enabled", S_IRUGO, clk->debugfs_entry, clk,
1069 + &jz4740_clock_debugfs_ops_enabled);
1070 +
1071 + if (clk->parent) {
1072 + char parent_path[100];
1073 + snprintf(parent_path, 100, "../%s", clk->parent->name);
1074 + clk->debugfs_parent_entry = debugfs_create_symlink("parent",
1075 + clk->debugfs_entry,
1076 + parent_path);
1077 + }
1078 +}
1079 +
1080 +/* TODO: Locking */
1081 +void jz4740_clock_debugfs_update_parent(struct clk *clk)
1082 +{
1083 + if (clk->debugfs_parent_entry)
1084 + debugfs_remove(clk->debugfs_parent_entry);
1085 +
1086 + if (clk->parent) {
1087 + char parent_path[100];
1088 + snprintf(parent_path, 100, "../%s", clk->parent->name);
1089 + clk->debugfs_parent_entry = debugfs_create_symlink("parent",
1090 + clk->debugfs_entry,
1091 + parent_path);
1092 + } else {
1093 + clk->debugfs_parent_entry = NULL;
1094 + }
1095 +}
1096 +
1097 +void jz4740_clock_debugfs_init(void)
1098 +{
1099 + jz4740_clock_debugfs = debugfs_create_dir("jz4740-clock", NULL);
1100 + if (IS_ERR(jz4740_clock_debugfs))
1101 + jz4740_clock_debugfs = NULL;
1102 +}
1103 diff --git a/arch/mips/jz4740/clock.c b/arch/mips/jz4740/clock.c
1104 new file mode 100644
1105 index 0000000..df0d6d3
1106 --- /dev/null
1107 +++ b/arch/mips/jz4740/clock.c
1108 @@ -0,0 +1,935 @@
1109 +/*
1110 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
1111 + * JZ4740 SoC clock support
1112 + *
1113 + * This program is free software; you can redistribute it and/or modify it
1114 + * under the terms of the GNU General Public License as published by the
1115 + * Free Software Foundation; either version 2 of the License, or (at your
1116 + * option) any later version.
1117 + *
1118 + * You should have received a copy of the GNU General Public License along
1119 + * with this program; if not, write to the Free Software Foundation, Inc.,
1120 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1121 + *
1122 + */
1123 +
1124 +#include <linux/kernel.h>
1125 +#include <linux/errno.h>
1126 +#include <linux/clk.h>
1127 +#include <linux/spinlock.h>
1128 +#include <linux/io.h>
1129 +#include <linux/module.h>
1130 +#include <linux/list.h>
1131 +#include <linux/err.h>
1132 +
1133 +#include <asm/mach-jz4740/clock.h>
1134 +#include <asm/mach-jz4740/base.h>
1135 +
1136 +#include "clock.h"
1137 +
1138 +#define JZ_REG_CLOCK_CTRL 0x00
1139 +#define JZ_REG_CLOCK_LOW_POWER 0x04
1140 +#define JZ_REG_CLOCK_PLL 0x10
1141 +#define JZ_REG_CLOCK_GATE 0x20
1142 +#define JZ_REG_CLOCK_SLEEP_CTRL 0x24
1143 +#define JZ_REG_CLOCK_I2S 0x60
1144 +#define JZ_REG_CLOCK_LCD 0x64
1145 +#define JZ_REG_CLOCK_MMC 0x68
1146 +#define JZ_REG_CLOCK_UHC 0x6C
1147 +#define JZ_REG_CLOCK_SPI 0x74
1148 +
1149 +#define JZ_CLOCK_CTRL_I2S_SRC_PLL BIT(31)
1150 +#define JZ_CLOCK_CTRL_KO_ENABLE BIT(30)
1151 +#define JZ_CLOCK_CTRL_UDC_SRC_PLL BIT(29)
1152 +#define JZ_CLOCK_CTRL_UDIV_MASK 0x1f800000
1153 +#define JZ_CLOCK_CTRL_CHANGE_ENABLE BIT(22)
1154 +#define JZ_CLOCK_CTRL_PLL_HALF BIT(21)
1155 +#define JZ_CLOCK_CTRL_LDIV_MASK 0x001f0000
1156 +#define JZ_CLOCK_CTRL_UDIV_OFFSET 23
1157 +#define JZ_CLOCK_CTRL_LDIV_OFFSET 16
1158 +#define JZ_CLOCK_CTRL_MDIV_OFFSET 12
1159 +#define JZ_CLOCK_CTRL_PDIV_OFFSET 8
1160 +#define JZ_CLOCK_CTRL_HDIV_OFFSET 4
1161 +#define JZ_CLOCK_CTRL_CDIV_OFFSET 0
1162 +
1163 +#define JZ_CLOCK_GATE_UART0 BIT(0)
1164 +#define JZ_CLOCK_GATE_TCU BIT(1)
1165 +#define JZ_CLOCK_GATE_RTC BIT(2)
1166 +#define JZ_CLOCK_GATE_I2C BIT(3)
1167 +#define JZ_CLOCK_GATE_SPI BIT(4)
1168 +#define JZ_CLOCK_GATE_AIC BIT(5)
1169 +#define JZ_CLOCK_GATE_I2S BIT(6)
1170 +#define JZ_CLOCK_GATE_MMC BIT(7)
1171 +#define JZ_CLOCK_GATE_ADC BIT(8)
1172 +#define JZ_CLOCK_GATE_CIM BIT(9)
1173 +#define JZ_CLOCK_GATE_LCD BIT(10)
1174 +#define JZ_CLOCK_GATE_UDC BIT(11)
1175 +#define JZ_CLOCK_GATE_DMAC BIT(12)
1176 +#define JZ_CLOCK_GATE_IPU BIT(13)
1177 +#define JZ_CLOCK_GATE_UHC BIT(14)
1178 +#define JZ_CLOCK_GATE_UART1 BIT(15)
1179 +
1180 +#define JZ_CLOCK_I2S_DIV_MASK 0x01ff
1181 +
1182 +#define JZ_CLOCK_LCD_DIV_MASK 0x01ff
1183 +
1184 +#define JZ_CLOCK_MMC_DIV_MASK 0x001f
1185 +
1186 +#define JZ_CLOCK_UHC_DIV_MASK 0x000f
1187 +
1188 +#define JZ_CLOCK_SPI_SRC_PLL BIT(31)
1189 +#define JZ_CLOCK_SPI_DIV_MASK 0x000f
1190 +
1191 +#define JZ_CLOCK_PLL_M_MASK 0x01ff
1192 +#define JZ_CLOCK_PLL_N_MASK 0x001f
1193 +#define JZ_CLOCK_PLL_OD_MASK 0x0003
1194 +#define JZ_CLOCK_PLL_STABLE BIT(10)
1195 +#define JZ_CLOCK_PLL_BYPASS BIT(9)
1196 +#define JZ_CLOCK_PLL_ENABLED BIT(8)
1197 +#define JZ_CLOCK_PLL_STABLIZE_MASK 0x000f
1198 +#define JZ_CLOCK_PLL_M_OFFSET 23
1199 +#define JZ_CLOCK_PLL_N_OFFSET 18
1200 +#define JZ_CLOCK_PLL_OD_OFFSET 16
1201 +
1202 +#define JZ_CLOCK_LOW_POWER_MODE_DOZE BIT(2)
1203 +#define JZ_CLOCK_LOW_POWER_MODE_SLEEP BIT(0)
1204 +
1205 +#define JZ_CLOCK_SLEEP_CTRL_SUSPEND_UHC BIT(7)
1206 +#define JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC BIT(6)
1207 +
1208 +static void __iomem *jz_clock_base;
1209 +static spinlock_t jz_clock_lock;
1210 +static LIST_HEAD(jz_clocks);
1211 +
1212 +struct main_clk {
1213 + struct clk clk;
1214 + uint32_t div_offset;
1215 +};
1216 +
1217 +struct divided_clk {
1218 + struct clk clk;
1219 + uint32_t reg;
1220 + uint32_t mask;
1221 +};
1222 +
1223 +struct static_clk {
1224 + struct clk clk;
1225 + unsigned long rate;
1226 +};
1227 +
1228 +static uint32_t jz_clk_reg_read(int reg)
1229 +{
1230 + return readl(jz_clock_base + reg);
1231 +}
1232 +
1233 +static void jz_clk_reg_write_mask(int reg, uint32_t val, uint32_t mask)
1234 +{
1235 + uint32_t val2;
1236 +
1237 + spin_lock(&jz_clock_lock);
1238 + val2 = readl(jz_clock_base + reg);
1239 + val2 &= ~mask;
1240 + val2 |= val;
1241 + writel(val2, jz_clock_base + reg);
1242 + spin_unlock(&jz_clock_lock);
1243 +}
1244 +
1245 +static void jz_clk_reg_set_bits(int reg, uint32_t mask)
1246 +{
1247 + uint32_t val;
1248 +
1249 + spin_lock(&jz_clock_lock);
1250 + val = readl(jz_clock_base + reg);
1251 + val |= mask;
1252 + writel(val, jz_clock_base + reg);
1253 + spin_unlock(&jz_clock_lock);
1254 +}
1255 +
1256 +static void jz_clk_reg_clear_bits(int reg, uint32_t mask)
1257 +{
1258 + uint32_t val;
1259 +
1260 + spin_lock(&jz_clock_lock);
1261 + val = readl(jz_clock_base + reg);
1262 + val &= ~mask;
1263 + writel(val, jz_clock_base + reg);
1264 + spin_unlock(&jz_clock_lock);
1265 +}
1266 +
1267 +static int jz_clk_enable_gating(struct clk *clk)
1268 +{
1269 + if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
1270 + return -EINVAL;
1271 +
1272 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
1273 + return 0;
1274 +}
1275 +
1276 +static int jz_clk_disable_gating(struct clk *clk)
1277 +{
1278 + if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
1279 + return -EINVAL;
1280 +
1281 + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, clk->gate_bit);
1282 + return 0;
1283 +}
1284 +
1285 +static int jz_clk_is_enabled_gating(struct clk *clk)
1286 +{
1287 + if (clk->gate_bit == JZ4740_CLK_NOT_GATED)
1288 + return 1;
1289 +
1290 + return !(jz_clk_reg_read(JZ_REG_CLOCK_GATE) & clk->gate_bit);
1291 +}
1292 +
1293 +static unsigned long jz_clk_static_get_rate(struct clk *clk)
1294 +{
1295 + return ((struct static_clk *)clk)->rate;
1296 +}
1297 +
1298 +static int jz_clk_ko_enable(struct clk *clk)
1299 +{
1300 + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
1301 + return 0;
1302 +}
1303 +
1304 +static int jz_clk_ko_disable(struct clk *clk)
1305 +{
1306 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_KO_ENABLE);
1307 + return 0;
1308 +}
1309 +
1310 +static int jz_clk_ko_is_enabled(struct clk *clk)
1311 +{
1312 + return !!(jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_KO_ENABLE);
1313 +}
1314 +
1315 +static const int pllno[] = {1, 2, 2, 4};
1316 +
1317 +static unsigned long jz_clk_pll_get_rate(struct clk *clk)
1318 +{
1319 + uint32_t val;
1320 + int m;
1321 + int n;
1322 + int od;
1323 +
1324 + val = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
1325 +
1326 + if (val & JZ_CLOCK_PLL_BYPASS)
1327 + return clk_get_rate(clk->parent);
1328 +
1329 + m = ((val >> 23) & 0x1ff) + 2;
1330 + n = ((val >> 18) & 0x1f) + 2;
1331 + od = (val >> 16) & 0x3;
1332 +
1333 + return clk_get_rate(clk->parent) * (m / n) / pllno[od];
1334 +}
1335 +
1336 +static unsigned long jz_clk_pll_half_get_rate(struct clk *clk)
1337 +{
1338 + uint32_t reg;
1339 +
1340 + reg = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
1341 + if (reg & JZ_CLOCK_CTRL_PLL_HALF)
1342 + return jz_clk_pll_get_rate(clk->parent);
1343 + return jz_clk_pll_get_rate(clk->parent) >> 1;
1344 +}
1345 +
1346 +static const int jz_clk_main_divs[] = {1, 2, 3, 4, 6, 8, 12, 16, 24, 32};
1347 +
1348 +static unsigned long jz_clk_main_round_rate(struct clk *clk, unsigned long rate)
1349 +{
1350 + unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
1351 + int div;
1352 +
1353 + div = parent_rate / rate;
1354 + if (div > 32)
1355 + return parent_rate / 32;
1356 + else if (div < 1)
1357 + return parent_rate;
1358 +
1359 + div &= (0x3 << (ffs(div) - 1));
1360 +
1361 + return parent_rate / div;
1362 +}
1363 +
1364 +static unsigned long jz_clk_main_get_rate(struct clk *clk)
1365 +{
1366 + struct main_clk *mclk = (struct main_clk *)clk;
1367 + uint32_t div;
1368 +
1369 + div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
1370 +
1371 + div >>= mclk->div_offset;
1372 + div &= 0xf;
1373 +
1374 + if (div >= ARRAY_SIZE(jz_clk_main_divs))
1375 + div = ARRAY_SIZE(jz_clk_main_divs) - 1;
1376 +
1377 + return jz_clk_pll_get_rate(clk->parent) / jz_clk_main_divs[div];
1378 +}
1379 +
1380 +static int jz_clk_main_set_rate(struct clk *clk, unsigned long rate)
1381 +{
1382 + struct main_clk *mclk = (struct main_clk *)clk;
1383 + int i;
1384 + int div;
1385 + unsigned long parent_rate = jz_clk_pll_get_rate(clk->parent);
1386 +
1387 + rate = jz_clk_main_round_rate(clk, rate);
1388 +
1389 + div = parent_rate / rate;
1390 +
1391 + i = (ffs(div) - 1) << 1;
1392 + if (i > 0 && !(div & BIT(i-1)))
1393 + i -= 1;
1394 +
1395 + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, i << mclk->div_offset,
1396 + 0xf << mclk->div_offset);
1397 +
1398 + return 0;
1399 +}
1400 +
1401 +static struct clk_ops jz_clk_static_ops = {
1402 + .get_rate = jz_clk_static_get_rate,
1403 + .enable = jz_clk_enable_gating,
1404 + .disable = jz_clk_disable_gating,
1405 + .is_enabled = jz_clk_is_enabled_gating,
1406 +};
1407 +
1408 +static struct static_clk jz_clk_ext = {
1409 + .clk = {
1410 + .name = "ext",
1411 + .gate_bit = JZ4740_CLK_NOT_GATED,
1412 + .ops = &jz_clk_static_ops,
1413 + },
1414 +};
1415 +
1416 +static struct clk_ops jz_clk_pll_ops = {
1417 + .get_rate = jz_clk_static_get_rate,
1418 +};
1419 +
1420 +static struct clk jz_clk_pll = {
1421 + .name = "pll",
1422 + .parent = &jz_clk_ext.clk,
1423 + .ops = &jz_clk_pll_ops,
1424 +};
1425 +
1426 +static struct clk_ops jz_clk_pll_half_ops = {
1427 + .get_rate = jz_clk_pll_half_get_rate,
1428 +};
1429 +
1430 +static struct clk jz_clk_pll_half = {
1431 + .name = "pll half",
1432 + .parent = &jz_clk_pll,
1433 + .ops = &jz_clk_pll_half_ops,
1434 +};
1435 +
1436 +static const struct clk_ops jz_clk_main_ops = {
1437 + .get_rate = jz_clk_main_get_rate,
1438 + .set_rate = jz_clk_main_set_rate,
1439 + .round_rate = jz_clk_main_round_rate,
1440 +};
1441 +
1442 +static struct main_clk jz_clk_cpu = {
1443 + .clk = {
1444 + .name = "cclk",
1445 + .parent = &jz_clk_pll,
1446 + .ops = &jz_clk_main_ops,
1447 + },
1448 + .div_offset = JZ_CLOCK_CTRL_CDIV_OFFSET,
1449 +};
1450 +
1451 +static struct main_clk jz_clk_memory = {
1452 + .clk = {
1453 + .name = "mclk",
1454 + .parent = &jz_clk_pll,
1455 + .ops = &jz_clk_main_ops,
1456 + },
1457 + .div_offset = JZ_CLOCK_CTRL_MDIV_OFFSET,
1458 +};
1459 +
1460 +static struct main_clk jz_clk_high_speed_peripheral = {
1461 + .clk = {
1462 + .name = "hclk",
1463 + .parent = &jz_clk_pll,
1464 + .ops = &jz_clk_main_ops,
1465 + },
1466 + .div_offset = JZ_CLOCK_CTRL_HDIV_OFFSET,
1467 +};
1468 +
1469 +
1470 +static struct main_clk jz_clk_low_speed_peripheral = {
1471 + .clk = {
1472 + .name = "pclk",
1473 + .parent = &jz_clk_pll,
1474 + .ops = &jz_clk_main_ops,
1475 + },
1476 + .div_offset = JZ_CLOCK_CTRL_PDIV_OFFSET,
1477 +};
1478 +
1479 +static const struct clk_ops jz_clk_ko_ops = {
1480 + .enable = jz_clk_ko_enable,
1481 + .disable = jz_clk_ko_disable,
1482 + .is_enabled = jz_clk_ko_is_enabled,
1483 +};
1484 +
1485 +static struct clk jz_clk_ko = {
1486 + .name = "cko",
1487 + .parent = &jz_clk_memory.clk,
1488 + .ops = &jz_clk_ko_ops,
1489 +};
1490 +
1491 +static int jz_clk_spi_set_parent(struct clk *clk, struct clk *parent)
1492 +{
1493 + if (parent == &jz_clk_pll)
1494 + jz_clk_reg_set_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
1495 + else if (parent == &jz_clk_ext.clk)
1496 + jz_clk_reg_clear_bits(JZ_CLOCK_SPI_SRC_PLL, JZ_REG_CLOCK_SPI);
1497 + else
1498 + return -EINVAL;
1499 +
1500 + clk->parent = parent;
1501 +
1502 + return 0;
1503 +}
1504 +
1505 +static int jz_clk_i2s_set_parent(struct clk *clk, struct clk *parent)
1506 +{
1507 + if (parent == &jz_clk_pll_half)
1508 + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
1509 + else if (parent == &jz_clk_ext.clk)
1510 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_I2S_SRC_PLL);
1511 + else
1512 + return -EINVAL;
1513 +
1514 + clk->parent = parent;
1515 +
1516 + return 0;
1517 +}
1518 +
1519 +static int jz_clk_udc_enable(struct clk *clk)
1520 +{
1521 + jz_clk_reg_set_bits(JZ_REG_CLOCK_SLEEP_CTRL,
1522 + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
1523 +
1524 + return 0;
1525 +}
1526 +
1527 +static int jz_clk_udc_disable(struct clk *clk)
1528 +{
1529 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_SLEEP_CTRL,
1530 + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
1531 +
1532 + return 0;
1533 +}
1534 +
1535 +static int jz_clk_udc_is_enabled(struct clk *clk)
1536 +{
1537 + return !!(jz_clk_reg_read(JZ_REG_CLOCK_SLEEP_CTRL) &
1538 + JZ_CLOCK_SLEEP_CTRL_ENABLE_UDC);
1539 +}
1540 +static int jz_clk_udc_set_parent(struct clk *clk, struct clk *parent)
1541 +{
1542 + if (parent == &jz_clk_pll_half)
1543 + jz_clk_reg_set_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
1544 + else if (parent == &jz_clk_ext.clk)
1545 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_CTRL, JZ_CLOCK_CTRL_UDC_SRC_PLL);
1546 + else
1547 + return -EINVAL;
1548 +
1549 + clk->parent = parent;
1550 +
1551 + return 0;
1552 +}
1553 +
1554 +static int jz_clk_udc_set_rate(struct clk *clk, unsigned long rate)
1555 +{
1556 + int div;
1557 +
1558 + if (clk->parent == &jz_clk_ext.clk)
1559 + return -EINVAL;
1560 +
1561 + div = clk_get_rate(clk->parent) / rate - 1;
1562 +
1563 + if (div < 0)
1564 + div = 0;
1565 + else if (div > 63)
1566 + div = 63;
1567 +
1568 + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_UDIV_OFFSET,
1569 + JZ_CLOCK_CTRL_UDIV_MASK);
1570 + return 0;
1571 +}
1572 +
1573 +static unsigned long jz_clk_udc_get_rate(struct clk *clk)
1574 +{
1575 + int div;
1576 +
1577 + if (clk->parent == &jz_clk_ext.clk)
1578 + return clk_get_rate(clk->parent);
1579 +
1580 + div = (jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_UDIV_MASK);
1581 + div >>= JZ_CLOCK_CTRL_UDIV_OFFSET;
1582 + div += 1;
1583 +
1584 + return clk_get_rate(clk->parent) / div;
1585 +}
1586 +
1587 +static unsigned long jz_clk_divided_get_rate(struct clk *clk)
1588 +{
1589 + struct divided_clk *dclk = (struct divided_clk *)clk;
1590 + int div;
1591 +
1592 + if (clk->parent == &jz_clk_ext.clk)
1593 + return clk_get_rate(clk->parent);
1594 +
1595 + div = (jz_clk_reg_read(dclk->reg) & dclk->mask) + 1;
1596 +
1597 + return clk_get_rate(clk->parent) / div;
1598 +}
1599 +
1600 +static int jz_clk_divided_set_rate(struct clk *clk, unsigned long rate)
1601 +{
1602 + struct divided_clk *dclk = (struct divided_clk *)clk;
1603 + int div;
1604 +
1605 + if (clk->parent == &jz_clk_ext.clk)
1606 + return -EINVAL;
1607 +
1608 + div = clk_get_rate(clk->parent) / rate - 1;
1609 +
1610 + if (div < 0)
1611 + div = 0;
1612 + else if (div > dclk->mask)
1613 + div = dclk->mask;
1614 +
1615 + jz_clk_reg_write_mask(dclk->reg, div, dclk->mask);
1616 +
1617 + return 0;
1618 +}
1619 +
1620 +static unsigned long jz_clk_ldclk_round_rate(struct clk *clk, unsigned long rate)
1621 +{
1622 + int div;
1623 + unsigned long parent_rate = jz_clk_pll_half_get_rate(clk->parent);
1624 +
1625 + if (rate > 150000000)
1626 + return 150000000;
1627 +
1628 + div = parent_rate / rate;
1629 + if (div < 1)
1630 + div = 1;
1631 + else if (div > 32)
1632 + div = 32;
1633 +
1634 + return parent_rate / div;
1635 +}
1636 +
1637 +static int jz_clk_ldclk_set_rate(struct clk *clk, unsigned long rate)
1638 +{
1639 + int div;
1640 +
1641 + if (rate > 150000000)
1642 + return -EINVAL;
1643 +
1644 + div = jz_clk_pll_half_get_rate(clk->parent) / rate - 1;
1645 + if (div < 0)
1646 + div = 0;
1647 + else if (div > 31)
1648 + div = 31;
1649 +
1650 + jz_clk_reg_write_mask(JZ_REG_CLOCK_CTRL, div << JZ_CLOCK_CTRL_LDIV_OFFSET,
1651 + JZ_CLOCK_CTRL_LDIV_MASK);
1652 +
1653 + return 0;
1654 +}
1655 +
1656 +static unsigned long jz_clk_ldclk_get_rate(struct clk *clk)
1657 +{
1658 + int div;
1659 +
1660 + div = jz_clk_reg_read(JZ_REG_CLOCK_CTRL) & JZ_CLOCK_CTRL_LDIV_MASK;
1661 + div >>= JZ_CLOCK_CTRL_LDIV_OFFSET;
1662 +
1663 + return jz_clk_pll_half_get_rate(clk->parent) / (div + 1);
1664 +}
1665 +
1666 +static const struct clk_ops jz_clk_ops_ld = {
1667 + .set_rate = jz_clk_ldclk_set_rate,
1668 + .get_rate = jz_clk_ldclk_get_rate,
1669 + .round_rate = jz_clk_ldclk_round_rate,
1670 + .enable = jz_clk_enable_gating,
1671 + .disable = jz_clk_disable_gating,
1672 + .is_enabled = jz_clk_is_enabled_gating,
1673 +};
1674 +
1675 +static struct clk jz_clk_ld = {
1676 + .name = "lcd",
1677 + .gate_bit = JZ_CLOCK_GATE_LCD,
1678 + .parent = &jz_clk_pll_half,
1679 + .ops = &jz_clk_ops_ld,
1680 +};
1681 +
1682 +/* TODO: ops!!! */
1683 +static struct clk jz_clk_cim_mclk = {
1684 + .name = "cim_mclk",
1685 + .parent = &jz_clk_high_speed_peripheral.clk,
1686 +};
1687 +
1688 +static struct static_clk jz_clk_cim_pclk = {
1689 + .clk = {
1690 + .name = "cim_pclk",
1691 + .gate_bit = JZ_CLOCK_GATE_CIM,
1692 + .ops = &jz_clk_static_ops,
1693 + },
1694 +};
1695 +
1696 +static const struct clk_ops jz_clk_i2s_ops = {
1697 + .set_rate = jz_clk_divided_set_rate,
1698 + .get_rate = jz_clk_divided_get_rate,
1699 + .enable = jz_clk_enable_gating,
1700 + .disable = jz_clk_disable_gating,
1701 + .is_enabled = jz_clk_is_enabled_gating,
1702 + .set_parent = jz_clk_i2s_set_parent,
1703 +};
1704 +
1705 +static const struct clk_ops jz_clk_spi_ops = {
1706 + .set_rate = jz_clk_divided_set_rate,
1707 + .get_rate = jz_clk_divided_get_rate,
1708 + .enable = jz_clk_enable_gating,
1709 + .disable = jz_clk_disable_gating,
1710 + .is_enabled = jz_clk_is_enabled_gating,
1711 + .set_parent = jz_clk_spi_set_parent,
1712 +};
1713 +
1714 +static const struct clk_ops jz_clk_divided_ops = {
1715 + .set_rate = jz_clk_divided_set_rate,
1716 + .get_rate = jz_clk_divided_get_rate,
1717 + .enable = jz_clk_enable_gating,
1718 + .disable = jz_clk_disable_gating,
1719 + .is_enabled = jz_clk_is_enabled_gating,
1720 +};
1721 +
1722 +static struct divided_clk jz4740_clock_divided_clks[] = {
1723 + {
1724 + .clk = {
1725 + .name = "lcd_pclk",
1726 + .parent = &jz_clk_pll_half,
1727 + .gate_bit = JZ4740_CLK_NOT_GATED,
1728 + .ops = &jz_clk_divided_ops,
1729 + },
1730 + .reg = JZ_REG_CLOCK_LCD,
1731 + .mask = JZ_CLOCK_LCD_DIV_MASK,
1732 + },
1733 + {
1734 + .clk = {
1735 + .name = "i2s",
1736 + .parent = &jz_clk_ext.clk,
1737 + .gate_bit = JZ_CLOCK_GATE_I2S,
1738 + .ops = &jz_clk_i2s_ops,
1739 + },
1740 + .reg = JZ_REG_CLOCK_I2S,
1741 + .mask = JZ_CLOCK_I2S_DIV_MASK,
1742 + },
1743 + {
1744 + .clk = {
1745 + .name = "spi",
1746 + .parent = &jz_clk_ext.clk,
1747 + .gate_bit = JZ_CLOCK_GATE_SPI,
1748 + .ops = &jz_clk_spi_ops,
1749 + },
1750 + .reg = JZ_REG_CLOCK_SPI,
1751 + .mask = JZ_CLOCK_SPI_DIV_MASK,
1752 + },
1753 + {
1754 + .clk = {
1755 + .name = "mmc",
1756 + .parent = &jz_clk_pll_half,
1757 + .gate_bit = JZ_CLOCK_GATE_MMC,
1758 + .ops = &jz_clk_divided_ops,
1759 + },
1760 + .reg = JZ_REG_CLOCK_MMC,
1761 + .mask = JZ_CLOCK_MMC_DIV_MASK,
1762 + },
1763 + {
1764 + .clk = {
1765 + .name = "uhc",
1766 + .parent = &jz_clk_pll_half,
1767 + .gate_bit = JZ_CLOCK_GATE_UHC,
1768 + .ops = &jz_clk_divided_ops,
1769 + },
1770 + .reg = JZ_REG_CLOCK_UHC,
1771 + .mask = JZ_CLOCK_UHC_DIV_MASK,
1772 + },
1773 +};
1774 +
1775 +static const struct clk_ops jz_clk_udc_ops = {
1776 + .set_parent = jz_clk_udc_set_parent,
1777 + .set_rate = jz_clk_udc_set_rate,
1778 + .get_rate = jz_clk_udc_get_rate,
1779 + .enable = jz_clk_udc_enable,
1780 + .disable = jz_clk_udc_disable,
1781 + .is_enabled = jz_clk_udc_is_enabled,
1782 +};
1783 +
1784 +static const struct clk_ops jz_clk_simple_ops = {
1785 + .enable = jz_clk_enable_gating,
1786 + .disable = jz_clk_disable_gating,
1787 + .is_enabled = jz_clk_is_enabled_gating,
1788 +};
1789 +
1790 +static struct clk jz4740_clock_simple_clks[] = {
1791 + {
1792 + .name = "udc",
1793 + .parent = &jz_clk_ext.clk,
1794 + .ops = &jz_clk_udc_ops,
1795 + },
1796 + {
1797 + .name = "uart0",
1798 + .parent = &jz_clk_ext.clk,
1799 + .gate_bit = JZ_CLOCK_GATE_UART0,
1800 + .ops = &jz_clk_simple_ops,
1801 + },
1802 + {
1803 + .name = "uart1",
1804 + .parent = &jz_clk_ext.clk,
1805 + .gate_bit = JZ_CLOCK_GATE_UART1,
1806 + .ops = &jz_clk_simple_ops,
1807 + },
1808 + {
1809 + .name = "dma",
1810 + .parent = &jz_clk_high_speed_peripheral.clk,
1811 + .gate_bit = JZ_CLOCK_GATE_UART0,
1812 + .ops = &jz_clk_simple_ops,
1813 + },
1814 + {
1815 + .name = "ipu",
1816 + .parent = &jz_clk_high_speed_peripheral.clk,
1817 + .gate_bit = JZ_CLOCK_GATE_IPU,
1818 + .ops = &jz_clk_simple_ops,
1819 + },
1820 + {
1821 + .name = "adc",
1822 + .parent = &jz_clk_ext.clk,
1823 + .gate_bit = JZ_CLOCK_GATE_ADC,
1824 + .ops = &jz_clk_simple_ops,
1825 + },
1826 + {
1827 + .name = "i2c",
1828 + .parent = &jz_clk_ext.clk,
1829 + .gate_bit = JZ_CLOCK_GATE_I2C,
1830 + .ops = &jz_clk_simple_ops,
1831 + },
1832 + {
1833 + .name = "aic",
1834 + .parent = &jz_clk_ext.clk,
1835 + .gate_bit = JZ_CLOCK_GATE_AIC,
1836 + .ops = &jz_clk_simple_ops,
1837 + },
1838 +};
1839 +
1840 +static struct static_clk jz_clk_rtc = {
1841 + .clk = {
1842 + .name = "rtc",
1843 + .gate_bit = JZ_CLOCK_GATE_RTC,
1844 + .ops = &jz_clk_static_ops,
1845 + },
1846 + .rate = 32768,
1847 +};
1848 +
1849 +int clk_enable(struct clk *clk)
1850 +{
1851 + if (!clk->ops->enable)
1852 + return -EINVAL;
1853 +
1854 + return clk->ops->enable(clk);
1855 +}
1856 +EXPORT_SYMBOL_GPL(clk_enable);
1857 +
1858 +void clk_disable(struct clk *clk)
1859 +{
1860 + if (clk->ops->disable)
1861 + clk->ops->disable(clk);
1862 +}
1863 +EXPORT_SYMBOL_GPL(clk_disable);
1864 +
1865 +int clk_is_enabled(struct clk *clk)
1866 +{
1867 + if (clk->ops->is_enabled)
1868 + return clk->ops->is_enabled(clk);
1869 +
1870 + return 1;
1871 +}
1872 +
1873 +unsigned long clk_get_rate(struct clk *clk)
1874 +{
1875 + if (clk->ops->get_rate)
1876 + return clk->ops->get_rate(clk);
1877 + if (clk->parent)
1878 + return clk_get_rate(clk->parent);
1879 +
1880 + return -EINVAL;
1881 +}
1882 +EXPORT_SYMBOL_GPL(clk_get_rate);
1883 +
1884 +int clk_set_rate(struct clk *clk, unsigned long rate)
1885 +{
1886 + if (!clk->ops->set_rate)
1887 + return -EINVAL;
1888 + return clk->ops->set_rate(clk, rate);
1889 +}
1890 +EXPORT_SYMBOL_GPL(clk_set_rate);
1891 +
1892 +long clk_round_rate(struct clk *clk, unsigned long rate)
1893 +{
1894 + if (clk->ops->round_rate)
1895 + return clk->ops->round_rate(clk, rate);
1896 +
1897 + return -EINVAL;
1898 +}
1899 +EXPORT_SYMBOL_GPL(clk_round_rate);
1900 +
1901 +int clk_set_parent(struct clk *clk, struct clk *parent)
1902 +{
1903 + int ret;
1904 +
1905 + if (!clk->ops->set_parent)
1906 + return -EINVAL;
1907 +
1908 + clk_disable(clk);
1909 + ret = clk->ops->set_parent(clk, parent);
1910 + clk_enable(clk);
1911 +
1912 + jz4740_clock_debugfs_update_parent(clk);
1913 +
1914 + return ret;
1915 +}
1916 +EXPORT_SYMBOL_GPL(clk_set_parent);
1917 +
1918 +struct clk *clk_get(struct device *dev, const char *name)
1919 +{
1920 + struct clk *clk;
1921 +
1922 + list_for_each_entry(clk, &jz_clocks, list) {
1923 + if (strcmp(clk->name, name) == 0)
1924 + return clk;
1925 + }
1926 + return ERR_PTR(-ENOENT);
1927 +}
1928 +EXPORT_SYMBOL_GPL(clk_get);
1929 +
1930 +void clk_put(struct clk *clk)
1931 +{
1932 +}
1933 +EXPORT_SYMBOL_GPL(clk_put);
1934 +
1935 +
1936 +static inline void clk_add(struct clk *clk)
1937 +{
1938 + list_add_tail(&clk->list, &jz_clocks);
1939 +
1940 + jz4740_clock_debugfs_add_clk(clk);
1941 +}
1942 +
1943 +static void clk_register_clks(void)
1944 +{
1945 + size_t i;
1946 +
1947 + clk_add(&jz_clk_ext.clk);
1948 + clk_add(&jz_clk_pll);
1949 + clk_add(&jz_clk_pll_half);
1950 + clk_add(&jz_clk_cpu.clk);
1951 + clk_add(&jz_clk_high_speed_peripheral.clk);
1952 + clk_add(&jz_clk_low_speed_peripheral.clk);
1953 + clk_add(&jz_clk_ko);
1954 + clk_add(&jz_clk_ld);
1955 + clk_add(&jz_clk_cim_mclk);
1956 + clk_add(&jz_clk_cim_pclk.clk);
1957 + clk_add(&jz_clk_rtc.clk);
1958 +
1959 + for (i = 0; i < ARRAY_SIZE(jz4740_clock_divided_clks); ++i)
1960 + clk_add(&jz4740_clock_divided_clks[i].clk);
1961 +
1962 + for (i = 0; i < ARRAY_SIZE(jz4740_clock_simple_clks); ++i)
1963 + clk_add(&jz4740_clock_simple_clks[i]);
1964 +}
1965 +
1966 +void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
1967 +{
1968 + switch (mode) {
1969 + case JZ4740_WAIT_MODE_IDLE:
1970 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
1971 + break;
1972 + case JZ4740_WAIT_MODE_SLEEP:
1973 + jz_clk_reg_set_bits(JZ_REG_CLOCK_LOW_POWER, JZ_CLOCK_LOW_POWER_MODE_SLEEP);
1974 + break;
1975 + }
1976 +}
1977 +
1978 +void jz4740_clock_udc_disable_auto_suspend(void)
1979 +{
1980 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
1981 +}
1982 +EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
1983 +
1984 +void jz4740_clock_udc_enable_auto_suspend(void)
1985 +{
1986 + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE, JZ_CLOCK_GATE_UDC);
1987 +}
1988 +EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
1989 +
1990 +void jz4740_clock_suspend(void)
1991 +{
1992 + jz_clk_reg_set_bits(JZ_REG_CLOCK_GATE,
1993 + JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
1994 +
1995 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
1996 +}
1997 +
1998 +void jz4740_clock_resume(void)
1999 +{
2000 + uint32_t pll;
2001 +
2002 + jz_clk_reg_set_bits(JZ_REG_CLOCK_PLL, JZ_CLOCK_PLL_ENABLED);
2003 +
2004 + do {
2005 + pll = jz_clk_reg_read(JZ_REG_CLOCK_PLL);
2006 + } while (!(pll & JZ_CLOCK_PLL_STABLE));
2007 +
2008 + jz_clk_reg_clear_bits(JZ_REG_CLOCK_GATE,
2009 + JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0);
2010 +}
2011 +
2012 +int jz4740_clock_init(void)
2013 +{
2014 + uint32_t val;
2015 +
2016 + jz_clock_base = ioremap(CPHYSADDR(JZ4740_CPM_BASE_ADDR), 0x100);
2017 + if (!jz_clock_base)
2018 + return -EBUSY;
2019 +
2020 + spin_lock_init(&jz_clock_lock);
2021 +
2022 + jz_clk_ext.rate = jz4740_clock_bdata.ext_rate;
2023 + jz_clk_rtc.rate = jz4740_clock_bdata.rtc_rate;
2024 +
2025 + val = jz_clk_reg_read(JZ_REG_CLOCK_SPI);
2026 +
2027 + if (val & JZ_CLOCK_SPI_SRC_PLL)
2028 + jz4740_clock_divided_clks[1].clk.parent = &jz_clk_pll_half;
2029 +
2030 + val = jz_clk_reg_read(JZ_REG_CLOCK_CTRL);
2031 +
2032 + if (val & JZ_CLOCK_CTRL_I2S_SRC_PLL)
2033 + jz4740_clock_divided_clks[0].clk.parent = &jz_clk_pll_half;
2034 +
2035 + if (val & JZ_CLOCK_CTRL_UDC_SRC_PLL)
2036 + jz4740_clock_simple_clks[0].parent = &jz_clk_pll_half;
2037 +
2038 + jz4740_clock_debugfs_init();
2039 +
2040 + clk_register_clks();
2041 +
2042 + return 0;
2043 +}
2044 diff --git a/arch/mips/jz4740/clock.h b/arch/mips/jz4740/clock.h
2045 new file mode 100644
2046 index 0000000..96010a4
2047 --- /dev/null
2048 +++ b/arch/mips/jz4740/clock.h
2049 @@ -0,0 +1,75 @@
2050 +/*
2051 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
2052 + * JZ4740 SoC clock support
2053 + *
2054 + * This program is free software; you can redistribute it and/or modify it
2055 + * under the terms of the GNU General Public License as published by the
2056 + * Free Software Foundation; either version 2 of the License, or (at your
2057 + * option) any later version.
2058 + *
2059 + * You should have received a copy of the GNU General Public License along
2060 + * with this program; if not, write to the Free Software Foundation, Inc.,
2061 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2062 + *
2063 + */
2064 +
2065 +#ifndef __JZ4740_CLOCK_H__
2066 +#define __JZ4740_CLOCK_H__
2067 +
2068 +struct jz4740_clock_board_data {
2069 + unsigned long ext_rate;
2070 + unsigned long rtc_rate;
2071 +};
2072 +
2073 +extern struct jz4740_clock_board_data jz4740_clock_bdata;
2074 +
2075 +int jz4740_clock_init(void);
2076 +void jz4740_clock_suspend(void);
2077 +void jz4740_clock_resume(void);
2078 +
2079 +struct clk;
2080 +
2081 +struct clk_ops {
2082 + unsigned long (*get_rate)(struct clk *clk);
2083 + unsigned long (*round_rate)(struct clk *clk, unsigned long rate);
2084 + int (*set_rate)(struct clk *clk, unsigned long rate);
2085 + int (*enable)(struct clk *clk);
2086 + int (*disable)(struct clk *clk);
2087 + int (*is_enabled)(struct clk *clk);
2088 +
2089 + int (*set_parent)(struct clk *clk, struct clk *parent);
2090 +
2091 +};
2092 +
2093 +struct clk {
2094 + const char *name;
2095 + struct clk *parent;
2096 +
2097 + uint32_t gate_bit;
2098 +
2099 + const struct clk_ops *ops;
2100 +
2101 + struct list_head list;
2102 +
2103 +#ifdef CONFIG_DEBUG_FS
2104 + struct dentry *debugfs_entry;
2105 + struct dentry *debugfs_parent_entry;
2106 +#endif
2107 +
2108 +};
2109 +
2110 +#define JZ4740_CLK_NOT_GATED ((uint32_t)-1)
2111 +
2112 +int clk_is_enabled(struct clk *clk);
2113 +
2114 +#ifdef CONFIG_DEBUG_FS
2115 +void jz4740_clock_debugfs_init(void);
2116 +void jz4740_clock_debugfs_add_clk(struct clk *clk);
2117 +void jz4740_clock_debugfs_update_parent(struct clk *clk);
2118 +#else
2119 +static inline void jz4740_clock_debugfs_init(void) {};
2120 +static inline void jz4740_clock_debugfs_add_clk(struct clk *clk) {};
2121 +static inline void jz4740_clock_debugfs_update_parent(struct clk *clk) {};
2122 +#endif
2123 +
2124 +#endif
2125 diff --git a/arch/mips/jz4740/dma.c b/arch/mips/jz4740/dma.c
2126 new file mode 100644
2127 index 0000000..b712afc
2128 --- /dev/null
2129 +++ b/arch/mips/jz4740/dma.c
2130 @@ -0,0 +1,336 @@
2131 +/*
2132 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
2133 + * JZ4740 SoC DMA support
2134 + *
2135 + * This program is free software; you can redistribute it and/or modify it
2136 + * under the terms of the GNU General Public License as published by the
2137 + * Free Software Foundation; either version 2 of the License, or (at your
2138 + * option) any later version.
2139 + *
2140 + * You should have received a copy of the GNU General Public License along
2141 + * with this program; if not, write to the Free Software Foundation, Inc.,
2142 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2143 + *
2144 + */
2145 +
2146 +#include <linux/kernel.h>
2147 +#include <linux/module.h>
2148 +#include <linux/spinlock.h>
2149 +#include <linux/interrupt.h>
2150 +
2151 +#include <linux/dma-mapping.h>
2152 +#include <asm/mach-jz4740/dma.h>
2153 +#include <asm/mach-jz4740/base.h>
2154 +
2155 +#define JZ_REG_DMA_SRC_ADDR(x) (0x00 + (x) * 0x20)
2156 +#define JZ_REG_DMA_DST_ADDR(x) (0x04 + (x) * 0x20)
2157 +#define JZ_REG_DMA_TRANSFER_COUNT(x) (0x08 + (x) * 0x20)
2158 +#define JZ_REG_DMA_REQ_TYPE(x) (0x0C + (x) * 0x20)
2159 +#define JZ_REG_DMA_STATUS_CTRL(x) (0x10 + (x) * 0x20)
2160 +#define JZ_REG_DMA_CMD(x) (0x14 + (x) * 0x20)
2161 +#define JZ_REG_DMA_DESC_ADDR(x) (0x18 + (x) * 0x20)
2162 +
2163 +#define JZ_REG_DMA_CTRL 0x300
2164 +#define JZ_REG_DMA_IRQ 0x304
2165 +#define JZ_REG_DMA_DOORBELL 0x308
2166 +#define JZ_REG_DMA_DOORBELL_SET 0x30C
2167 +
2168 +#define JZ_DMA_STATUS_CTRL_NO_DESC BIT(31)
2169 +#define JZ_DMA_STATUS_CTRL_DESC_INV BIT(6)
2170 +#define JZ_DMA_STATUS_CTRL_ADDR_ERR BIT(4)
2171 +#define JZ_DMA_STATUS_CTRL_TRANSFER_DONE BIT(3)
2172 +#define JZ_DMA_STATUS_CTRL_HALT BIT(2)
2173 +#define JZ_DMA_STATUS_CTRL_COUNT_TERMINATE BIT(1)
2174 +#define JZ_DMA_STATUS_CTRL_ENABLE BIT(0)
2175 +
2176 +#define JZ_DMA_CMD_SRC_INC BIT(23)
2177 +#define JZ_DMA_CMD_DST_INC BIT(22)
2178 +#define JZ_DMA_CMD_RDIL_MASK (0xf << 16)
2179 +#define JZ_DMA_CMD_SRC_WIDTH_MASK (0x3 << 14)
2180 +#define JZ_DMA_CMD_DST_WIDTH_MASK (0x3 << 12)
2181 +#define JZ_DMA_CMD_INTERVAL_LENGTH_MASK (0x7 << 8)
2182 +#define JZ_DMA_CMD_BLOCK_MODE BIT(7)
2183 +#define JZ_DMA_CMD_DESC_VALID BIT(4)
2184 +#define JZ_DMA_CMD_DESC_VALID_MODE BIT(3)
2185 +#define JZ_DMA_CMD_VALID_IRQ_ENABLE BIT(2)
2186 +#define JZ_DMA_CMD_TRANSFER_IRQ_ENABLE BIT(1)
2187 +#define JZ_DMA_CMD_LINK_ENABLE BIT(0)
2188 +
2189 +#define JZ_DMA_CMD_FLAGS_OFFSET 22
2190 +#define JZ_DMA_CMD_RDIL_OFFSET 16
2191 +#define JZ_DMA_CMD_SRC_WIDTH_OFFSET 14
2192 +#define JZ_DMA_CMD_DST_WIDTH_OFFSET 12
2193 +#define JZ_DMA_CMD_TRANSFER_SIZE_OFFSET 8
2194 +#define JZ_DMA_CMD_MODE_OFFSET 7
2195 +
2196 +#define JZ_DMA_CTRL_PRIORITY_MASK (0x3 << 8)
2197 +#define JZ_DMA_CTRL_HALT BIT(3)
2198 +#define JZ_DMA_CTRL_ADDRESS_ERROR BIT(2)
2199 +#define JZ_DMA_CTRL_ENABLE BIT(0)
2200 +
2201 +
2202 +static void __iomem *jz4740_dma_base;
2203 +static spinlock_t jz4740_dma_lock;
2204 +
2205 +static inline uint32_t jz4740_dma_read(size_t reg)
2206 +{
2207 + return readl(jz4740_dma_base + reg);
2208 +}
2209 +
2210 +static inline void jz4740_dma_write(size_t reg, uint32_t val)
2211 +{
2212 + writel(val, jz4740_dma_base + reg);
2213 +}
2214 +
2215 +static inline void jz4740_dma_write_mask(size_t reg, uint32_t val, uint32_t mask)
2216 +{
2217 + uint32_t val2;
2218 + val2 = jz4740_dma_read(reg);
2219 + val2 &= ~mask;
2220 + val2 |= val;
2221 + jz4740_dma_write(reg, val2);
2222 +}
2223 +
2224 +struct jz4740_dma_chan {
2225 + unsigned int id;
2226 + void *dev;
2227 + const char *name;
2228 +
2229 + enum jz4740_dma_flags flags;
2230 + uint32_t transfer_shift;
2231 +
2232 + jz4740_dma_complete_callback_t complete_cb;
2233 +
2234 + unsigned used:1;
2235 +};
2236 +
2237 +#define JZ4740_DMA_CHANNEL(_id) { .id = _id }
2238 +
2239 +struct jz4740_dma_chan jz4740_dma_channels[] = {
2240 + JZ4740_DMA_CHANNEL(0),
2241 + JZ4740_DMA_CHANNEL(1),
2242 + JZ4740_DMA_CHANNEL(2),
2243 + JZ4740_DMA_CHANNEL(3),
2244 + JZ4740_DMA_CHANNEL(4),
2245 + JZ4740_DMA_CHANNEL(5),
2246 +};
2247 +
2248 +struct jz4740_dma_chan *jz4740_dma_request(void *dev, const char *name)
2249 +{
2250 + unsigned int i;
2251 + struct jz4740_dma_chan *dma = NULL;
2252 +
2253 + spin_lock(&jz4740_dma_lock);
2254 +
2255 + for (i = 0; i < ARRAY_SIZE(jz4740_dma_channels); ++i) {
2256 + if (!jz4740_dma_channels[i].used) {
2257 + dma = &jz4740_dma_channels[i];
2258 + dma->used = 1;
2259 + break;
2260 + }
2261 + }
2262 +
2263 + spin_unlock(&jz4740_dma_lock);
2264 +
2265 + if (!dma)
2266 + return NULL;
2267 +
2268 + dma->dev = dev;
2269 + dma->name = name;
2270 +
2271 + return dma;
2272 +}
2273 +EXPORT_SYMBOL_GPL(jz4740_dma_request);
2274 +
2275 +void jz4740_dma_configure(struct jz4740_dma_chan *dma,
2276 + const struct jz4740_dma_config *config)
2277 +{
2278 + uint32_t cmd;
2279 +
2280 + switch (config->transfer_size) {
2281 + case JZ4740_DMA_TRANSFER_SIZE_2BYTE:
2282 + dma->transfer_shift = 1;
2283 + break;
2284 + case JZ4740_DMA_TRANSFER_SIZE_4BYTE:
2285 + dma->transfer_shift = 2;
2286 + break;
2287 + case JZ4740_DMA_TRANSFER_SIZE_16BYTE:
2288 + dma->transfer_shift = 4;
2289 + break;
2290 + case JZ4740_DMA_TRANSFER_SIZE_32BYTE:
2291 + dma->transfer_shift = 5;
2292 + break;
2293 + default:
2294 + dma->transfer_shift = 0;
2295 + break;
2296 + }
2297 +
2298 + cmd = config->flags << JZ_DMA_CMD_FLAGS_OFFSET;
2299 + cmd |= config->src_width << JZ_DMA_CMD_SRC_WIDTH_OFFSET;
2300 + cmd |= config->dst_width << JZ_DMA_CMD_DST_WIDTH_OFFSET;
2301 + cmd |= config->transfer_size << JZ_DMA_CMD_TRANSFER_SIZE_OFFSET;
2302 + cmd |= config->mode << JZ_DMA_CMD_MODE_OFFSET;
2303 + cmd |= JZ_DMA_CMD_TRANSFER_IRQ_ENABLE;
2304 +
2305 + jz4740_dma_write(JZ_REG_DMA_CMD(dma->id), cmd);
2306 + jz4740_dma_write(JZ_REG_DMA_STATUS_CTRL(dma->id), 0);
2307 + jz4740_dma_write(JZ_REG_DMA_REQ_TYPE(dma->id), config->request_type);
2308 +}
2309 +EXPORT_SYMBOL_GPL(jz4740_dma_configure);
2310 +
2311 +void jz4740_dma_set_src_addr(struct jz4740_dma_chan *dma, dma_addr_t src)
2312 +{
2313 + jz4740_dma_write(JZ_REG_DMA_SRC_ADDR(dma->id), src);
2314 +}
2315 +EXPORT_SYMBOL_GPL(jz4740_dma_set_src_addr);
2316 +
2317 +void jz4740_dma_set_dst_addr(struct jz4740_dma_chan *dma, dma_addr_t dst)
2318 +{
2319 + jz4740_dma_write(JZ_REG_DMA_DST_ADDR(dma->id), dst);
2320 +}
2321 +EXPORT_SYMBOL_GPL(jz4740_dma_set_dst_addr);
2322 +
2323 +void jz4740_dma_set_transfer_count(struct jz4740_dma_chan *dma, uint32_t count)
2324 +{
2325 + count >>= dma->transfer_shift;
2326 + jz4740_dma_write(JZ_REG_DMA_TRANSFER_COUNT(dma->id), count);
2327 +}
2328 +EXPORT_SYMBOL_GPL(jz4740_dma_set_transfer_count);
2329 +
2330 +void jz4740_dma_set_complete_cb(struct jz4740_dma_chan *dma,
2331 + jz4740_dma_complete_callback_t cb)
2332 +{
2333 + dma->complete_cb = cb;
2334 +}
2335 +EXPORT_SYMBOL_GPL(jz4740_dma_set_complete_cb);
2336 +
2337 +void jz4740_dma_free(struct jz4740_dma_chan *dma)
2338 +{
2339 + dma->dev = NULL;
2340 + dma->complete_cb = NULL;
2341 + dma->used = 0;
2342 +}
2343 +EXPORT_SYMBOL_GPL(jz4740_dma_free);
2344 +
2345 +void jz4740_dma_enable(struct jz4740_dma_chan *dma)
2346 +{
2347 + jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id),
2348 + JZ_DMA_STATUS_CTRL_NO_DESC | JZ_DMA_STATUS_CTRL_ENABLE,
2349 + JZ_DMA_STATUS_CTRL_HALT | JZ_DMA_STATUS_CTRL_NO_DESC |
2350 + JZ_DMA_STATUS_CTRL_ENABLE);
2351 +
2352 + jz4740_dma_write_mask(JZ_REG_DMA_CTRL,
2353 + JZ_DMA_CTRL_ENABLE,
2354 + JZ_DMA_CTRL_HALT | JZ_DMA_CTRL_ENABLE);
2355 +}
2356 +EXPORT_SYMBOL_GPL(jz4740_dma_enable);
2357 +
2358 +void jz4740_dma_disable(struct jz4740_dma_chan *dma)
2359 +{
2360 + jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
2361 + JZ_DMA_STATUS_CTRL_ENABLE);
2362 +}
2363 +EXPORT_SYMBOL_GPL(jz4740_dma_disable);
2364 +
2365 +uint32_t jz4740_dma_get_residue(const struct jz4740_dma_chan *dma)
2366 +{
2367 + uint32_t residue;
2368 + residue = jz4740_dma_read(JZ_REG_DMA_TRANSFER_COUNT(dma->id));
2369 + return residue << dma->transfer_shift;
2370 +}
2371 +EXPORT_SYMBOL_GPL(jz4740_dma_get_residue);
2372 +
2373 +static void jz4740_dma_chan_irq(struct jz4740_dma_chan *dma)
2374 +{
2375 + uint32_t status;
2376 +
2377 + status = jz4740_dma_read(JZ_REG_DMA_STATUS_CTRL(dma->id));
2378 +
2379 + jz4740_dma_write_mask(JZ_REG_DMA_STATUS_CTRL(dma->id), 0,
2380 + JZ_DMA_STATUS_CTRL_ENABLE | JZ_DMA_STATUS_CTRL_TRANSFER_DONE);
2381 +
2382 + if (dma->complete_cb)
2383 + dma->complete_cb(dma, 0, dma->dev);
2384 +}
2385 +
2386 +static irqreturn_t jz4740_dma_irq(int irq, void *dev_id)
2387 +{
2388 + uint32_t irq_status;
2389 + unsigned int i;
2390 +
2391 + irq_status = readl(jz4740_dma_base + JZ_REG_DMA_IRQ);
2392 +
2393 + for (i = 0; i < 6; ++i) {
2394 + if (irq_status & (1 << i))
2395 + jz4740_dma_chan_irq(&jz4740_dma_channels[i]);
2396 + }
2397 +
2398 + return IRQ_HANDLED;
2399 +}
2400 +
2401 +#if 0
2402 +static struct jz4740_dma_config dma_test_config = {
2403 + .src_width = JZ4740_DMA_WIDTH_32BIT,
2404 + .dst_width = JZ4740_DMA_WIDTH_32BIT,
2405 + .transfer_size = JZ4740_DMA_TRANSFER_SIZE_4BYTE,
2406 + .request_type = JZ4740_DMA_TYPE_AUTO_REQUEST,
2407 + .flags = JZ4740_DMA_SRC_AUTOINC | JZ4740_DMA_DST_AUTOINC,
2408 + .mode = JZ4740_DMA_MODE_BLOCK,
2409 +};
2410 +
2411 +static void jz4740_dma_test(void)
2412 +{
2413 + uint32_t *buf1, *buf2;
2414 + dma_addr_t addr1, addr2;
2415 + struct jz4740_dma_chan *dma = jz4740_dma_request(NULL, "dma test");
2416 + int i;
2417 +
2418 + printk("STARTING DMA TEST\n");
2419 +
2420 + buf1 = dma_alloc_coherent(NULL,
2421 + 0x1000,
2422 + &addr1, GFP_KERNEL);
2423 + buf2 = dma_alloc_coherent(NULL,
2424 + 0x1000,
2425 + &addr2, GFP_KERNEL);
2426 +
2427 + for (i = 0; i < 0x400; ++i)
2428 + buf1[i] = i;
2429 +
2430 +
2431 + jz4740_dma_configure(dma, &dma_test_config);
2432 + jz4740_dma_set_src_addr(dma, addr1);
2433 + jz4740_dma_set_dst_addr(dma, addr2);
2434 + jz4740_dma_set_transfer_count(dma, 0x1000);
2435 +
2436 + jz4740_dma_enable(dma);
2437 + mdelay(2000);
2438 +
2439 + for (i = 0; i < 0x400; ++i) {
2440 + if (buf2[i] != i)
2441 + printk("OH MY GOD: %x %x\n", i, buf2[i]);
2442 + }
2443 +
2444 + printk("DMA TEST DONE\n");
2445 +}
2446 +#endif
2447 +
2448 +static int jz4740_dma_init(void)
2449 +{
2450 + unsigned int ret;
2451 +
2452 + jz4740_dma_base = ioremap(CPHYSADDR(JZ4740_DMAC_BASE_ADDR), 0x400);
2453 +
2454 + if (!jz4740_dma_base)
2455 + return -EBUSY;
2456 +
2457 + spin_lock_init(&jz4740_dma_lock);
2458 +
2459 + ret = request_irq(JZ4740_IRQ_DMAC, jz4740_dma_irq, 0, "DMA", NULL);
2460 +
2461 + if (ret)
2462 + printk(KERN_ERR "JZ4740 DMA: Failed to request irq: %d\n", ret);
2463 +
2464 + return ret;
2465 +}
2466 +arch_initcall(jz4740_dma_init);
2467 diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
2468 new file mode 100644
2469 index 0000000..84f4ef9
2470 --- /dev/null
2471 +++ b/arch/mips/jz4740/gpio.c
2472 @@ -0,0 +1,598 @@
2473 +/*
2474 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
2475 + * JZ4740 platform GPIO support
2476 + *
2477 + * This program is free software; you can redistribute it and/or modify it
2478 + * under the terms of the GNU General Public License as published by the
2479 + * Free Software Foundation; either version 2 of the License, or (at your
2480 + * option) any later version.
2481 + *
2482 + * You should have received a copy of the GNU General Public License along
2483 + * with this program; if not, write to the Free Software Foundation, Inc.,
2484 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2485 + *
2486 + */
2487 +
2488 +#include <linux/kernel.h>
2489 +#include <linux/module.h>
2490 +#include <linux/init.h>
2491 +
2492 +#include <linux/spinlock.h>
2493 +#include <linux/sysdev.h>
2494 +#include <linux/io.h>
2495 +#include <linux/gpio.h>
2496 +#include <linux/delay.h>
2497 +#include <linux/interrupt.h>
2498 +#include <linux/bitops.h>
2499 +
2500 +#include <linux/debugfs.h>
2501 +#include <linux/seq_file.h>
2502 +
2503 +#include <asm/mach-jz4740/base.h>
2504 +
2505 +#define JZ4740_GPIO_BASE_A (32*0)
2506 +#define JZ4740_GPIO_BASE_B (32*1)
2507 +#define JZ4740_GPIO_BASE_C (32*2)
2508 +#define JZ4740_GPIO_BASE_D (32*3)
2509 +
2510 +#define JZ4740_GPIO_NUM_A 32
2511 +#define JZ4740_GPIO_NUM_B 32
2512 +#define JZ4740_GPIO_NUM_C 31
2513 +#define JZ4740_GPIO_NUM_D 32
2514 +
2515 +#define JZ4740_IRQ_GPIO_BASE_A (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_A)
2516 +#define JZ4740_IRQ_GPIO_BASE_B (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_B)
2517 +#define JZ4740_IRQ_GPIO_BASE_C (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_C)
2518 +#define JZ4740_IRQ_GPIO_BASE_D (JZ4740_IRQ_GPIO(0) + JZ4740_GPIO_BASE_D)
2519 +
2520 +#define JZ4740_IRQ_GPIO_A(num) (JZ4740_IRQ_GPIO_BASE_A + num)
2521 +#define JZ4740_IRQ_GPIO_B(num) (JZ4740_IRQ_GPIO_BASE_B + num)
2522 +#define JZ4740_IRQ_GPIO_C(num) (JZ4740_IRQ_GPIO_BASE_C + num)
2523 +#define JZ4740_IRQ_GPIO_D(num) (JZ4740_IRQ_GPIO_BASE_D + num)
2524 +
2525 +#define JZ_REG_GPIO_PIN 0x00
2526 +#define JZ_REG_GPIO_DATA 0x10
2527 +#define JZ_REG_GPIO_DATA_SET 0x14
2528 +#define JZ_REG_GPIO_DATA_CLEAR 0x18
2529 +#define JZ_REG_GPIO_MASK 0x20
2530 +#define JZ_REG_GPIO_MASK_SET 0x24
2531 +#define JZ_REG_GPIO_MASK_CLEAR 0x28
2532 +#define JZ_REG_GPIO_PULL 0x30
2533 +#define JZ_REG_GPIO_PULL_SET 0x34
2534 +#define JZ_REG_GPIO_PULL_CLEAR 0x38
2535 +#define JZ_REG_GPIO_FUNC 0x40
2536 +#define JZ_REG_GPIO_FUNC_SET 0x44
2537 +#define JZ_REG_GPIO_FUNC_CLEAR 0x48
2538 +#define JZ_REG_GPIO_SELECT 0x50
2539 +#define JZ_REG_GPIO_SELECT_SET 0x54
2540 +#define JZ_REG_GPIO_SELECT_CLEAR 0x58
2541 +#define JZ_REG_GPIO_DIRECTION 0x60
2542 +#define JZ_REG_GPIO_DIRECTION_SET 0x64
2543 +#define JZ_REG_GPIO_DIRECTION_CLEAR 0x68
2544 +#define JZ_REG_GPIO_TRIGGER 0x70
2545 +#define JZ_REG_GPIO_TRIGGER_SET 0x74
2546 +#define JZ_REG_GPIO_TRIGGER_CLEAR 0x78
2547 +#define JZ_REG_GPIO_FLAG 0x80
2548 +#define JZ_REG_GPIO_FLAG_CLEAR 0x14
2549 +
2550 +
2551 +#define GPIO_TO_BIT(gpio) BIT(gpio & 0x1f)
2552 +#define GPIO_TO_REG(gpio, reg) (gpio_to_jz_gpio_chip(gpio)->base + (reg))
2553 +#define CHIP_TO_REG(chip, reg) (gpio_chip_to_jz_gpio_chip(chip)->base + (reg))
2554 +
2555 +struct jz_gpio_chip {
2556 + unsigned int irq;
2557 + unsigned int irq_base;
2558 + uint32_t wakeup;
2559 + uint32_t suspend_mask;
2560 + uint32_t edge_trigger_both;
2561 +
2562 + void __iomem *base;
2563 +
2564 + spinlock_t lock;
2565 +
2566 + struct gpio_chip gpio_chip;
2567 + struct irq_chip irq_chip;
2568 + struct sys_device sysdev;
2569 +};
2570 +
2571 +
2572 +static struct jz_gpio_chip jz4740_gpio_chips[];
2573 +
2574 +static inline struct jz_gpio_chip *gpio_to_jz_gpio_chip(unsigned int gpio)
2575 +{
2576 + return &jz4740_gpio_chips[gpio >> 5];
2577 +}
2578 +
2579 +static inline struct jz_gpio_chip *gpio_chip_to_jz_gpio_chip(struct gpio_chip *gpio_chip)
2580 +{
2581 + return container_of(gpio_chip, struct jz_gpio_chip, gpio_chip);
2582 +}
2583 +
2584 +static inline struct jz_gpio_chip *irq_to_jz_gpio_chip(unsigned int irq)
2585 +{
2586 + return get_irq_chip_data(irq);
2587 +}
2588 +
2589 +static inline void jz_gpio_write_bit(unsigned int gpio, unsigned int reg)
2590 +{
2591 + writel(GPIO_TO_BIT(gpio), GPIO_TO_REG(gpio, reg));
2592 +}
2593 +
2594 +int jz_gpio_set_function(int gpio, enum jz_gpio_function function)
2595 +{
2596 + if (function == JZ_GPIO_FUNC_NONE) {
2597 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_CLEAR);
2598 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
2599 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
2600 + } else {
2601 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_FUNC_SET);
2602 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_CLEAR);
2603 + switch (function) {
2604 + case JZ_GPIO_FUNC1:
2605 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_CLEAR);
2606 + break;
2607 + case JZ_GPIO_FUNC3:
2608 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_TRIGGER_SET);
2609 + case JZ_GPIO_FUNC2: /* Falltrough */
2610 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_SELECT_SET);
2611 + break;
2612 + default:
2613 + BUG();
2614 + break;
2615 + }
2616 + }
2617 +
2618 + return 0;
2619 +}
2620 +EXPORT_SYMBOL_GPL(jz_gpio_set_function);
2621 +
2622 +int jz_gpio_bulk_request(const struct jz_gpio_bulk_request *request, size_t num)
2623 +{
2624 + size_t i;
2625 + int ret;
2626 +
2627 + for (i = 0; i < num; ++i, ++request) {
2628 + ret = gpio_request(request->gpio, request->name);
2629 + if (ret)
2630 + goto err;
2631 + jz_gpio_set_function(request->gpio, request->function);
2632 + }
2633 +
2634 + return 0;
2635 +
2636 +err:
2637 + for (--request; i > 0; --i, --request) {
2638 + gpio_free(request->gpio);
2639 + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
2640 + }
2641 +
2642 + return ret;
2643 +}
2644 +EXPORT_SYMBOL_GPL(jz_gpio_bulk_request);
2645 +
2646 +void jz_gpio_bulk_free(const struct jz_gpio_bulk_request *request, size_t num)
2647 +{
2648 + size_t i;
2649 +
2650 + for (i = 0; i < num; ++i, ++request) {
2651 + gpio_free(request->gpio);
2652 + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
2653 + }
2654 +
2655 +}
2656 +EXPORT_SYMBOL_GPL(jz_gpio_bulk_free);
2657 +
2658 +void jz_gpio_bulk_suspend(const struct jz_gpio_bulk_request *request, size_t num)
2659 +{
2660 + size_t i;
2661 +
2662 + for (i = 0; i < num; ++i, ++request) {
2663 + jz_gpio_set_function(request->gpio, JZ_GPIO_FUNC_NONE);
2664 + jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_DIRECTION_CLEAR);
2665 + jz_gpio_write_bit(request->gpio, JZ_REG_GPIO_PULL_SET);
2666 + }
2667 +}
2668 +EXPORT_SYMBOL_GPL(jz_gpio_bulk_suspend);
2669 +
2670 +void jz_gpio_bulk_resume(const struct jz_gpio_bulk_request *request, size_t num)
2671 +{
2672 + size_t i;
2673 +
2674 + for (i = 0; i < num; ++i, ++request)
2675 + jz_gpio_set_function(request->gpio, request->function);
2676 +}
2677 +EXPORT_SYMBOL_GPL(jz_gpio_bulk_resume);
2678 +
2679 +void jz_gpio_enable_pullup(unsigned gpio)
2680 +{
2681 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_CLEAR);
2682 +}
2683 +EXPORT_SYMBOL_GPL(jz_gpio_enable_pullup);
2684 +
2685 +void jz_gpio_disable_pullup(unsigned gpio)
2686 +{
2687 + jz_gpio_write_bit(gpio, JZ_REG_GPIO_PULL_SET);
2688 +}
2689 +EXPORT_SYMBOL_GPL(jz_gpio_disable_pullup);
2690 +
2691 +static int jz_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2692 +{
2693 + return !!(readl(CHIP_TO_REG(chip, JZ_REG_GPIO_PIN)) & BIT(gpio));
2694 +}
2695 +
2696 +static void jz_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2697 +{
2698 + uint32_t __iomem *reg = CHIP_TO_REG(chip, JZ_REG_GPIO_DATA_SET);
2699 + reg += !value;
2700 + writel(BIT(gpio), reg);
2701 +}
2702 +
2703 +static int jz_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
2704 + int value)
2705 +{
2706 + writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_SET));
2707 + jz_gpio_set_value(chip, gpio, value);
2708 +
2709 + return 0;
2710 +}
2711 +
2712 +static int jz_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2713 +{
2714 + writel(BIT(gpio), CHIP_TO_REG(chip, JZ_REG_GPIO_DIRECTION_CLEAR));
2715 +
2716 + return 0;
2717 +}
2718 +
2719 +int jz_gpio_port_direction_input(int port, uint32_t mask)
2720 +{
2721 + writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_CLEAR));
2722 +
2723 + return 0;
2724 +}
2725 +EXPORT_SYMBOL(jz_gpio_port_direction_input);
2726 +
2727 +int jz_gpio_port_direction_output(int port, uint32_t mask)
2728 +{
2729 + writel(mask, GPIO_TO_REG(port, JZ_REG_GPIO_DIRECTION_SET));
2730 +
2731 + return 0;
2732 +}
2733 +EXPORT_SYMBOL(jz_gpio_port_direction_output);
2734 +
2735 +void jz_gpio_port_set_value(int port, uint32_t value, uint32_t mask)
2736 +{
2737 + writel(~value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_CLEAR));
2738 + writel(value & mask, GPIO_TO_REG(port, JZ_REG_GPIO_DATA_SET));
2739 +}
2740 +EXPORT_SYMBOL(jz_gpio_port_set_value);
2741 +
2742 +uint32_t jz_gpio_port_get_value(int port, uint32_t mask)
2743 +{
2744 + uint32_t value = readl(GPIO_TO_REG(port, JZ_REG_GPIO_PIN));
2745 +
2746 + return value & mask;
2747 +}
2748 +EXPORT_SYMBOL(jz_gpio_port_get_value);
2749 +
2750 +
2751 +#define IRQ_TO_GPIO(irq) (irq - JZ4740_IRQ_GPIO(0))
2752 +#define IRQ_TO_BIT(irq) BIT(IRQ_TO_GPIO(irq) & 0x1f)
2753 +
2754 +#define IRQ_TO_REG(irq, reg) GPIO_TO_REG(IRQ_TO_GPIO(irq), reg)
2755 +
2756 +static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
2757 +{
2758 + uint32_t flag;
2759 + unsigned int gpio_irq;
2760 + unsigned int gpio_bank;
2761 + struct jz_gpio_chip *chip = get_irq_desc_data(desc);
2762 +
2763 + gpio_bank = JZ4740_IRQ_GPIO0 - irq;
2764 +
2765 + flag = readl(chip->base + JZ_REG_GPIO_FLAG);
2766 +
2767 + gpio_irq = ffs(flag) - 1;
2768 +
2769 + if (chip->edge_trigger_both & BIT(gpio_irq)) {
2770 + uint32_t value = readl(chip->base + JZ_REG_GPIO_PIN);
2771 + if (value & BIT(gpio_irq)) {
2772 + writel(BIT(gpio_irq),
2773 + chip->base + JZ_REG_GPIO_DIRECTION_CLEAR);
2774 + } else {
2775 + writel(BIT(gpio_irq),
2776 + chip->base + JZ_REG_GPIO_DIRECTION_SET);
2777 + }
2778 + }
2779 +
2780 + gpio_irq += (gpio_bank << 5) + JZ4740_IRQ_GPIO(0);
2781 +
2782 + generic_handle_irq(gpio_irq);
2783 +};
2784 +
2785 +static inline void jz_gpio_set_irq_bit(unsigned int irq, unsigned int reg)
2786 +{
2787 + writel(IRQ_TO_BIT(irq), IRQ_TO_REG(irq, reg));
2788 +}
2789 +
2790 +static void jz_gpio_irq_mask(unsigned int irq)
2791 +{
2792 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_SET);
2793 +};
2794 +
2795 +static void jz_gpio_irq_unmask(unsigned int irq)
2796 +{
2797 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_MASK_CLEAR);
2798 +};
2799 +
2800 +
2801 +/* TODO: Check if function is gpio */
2802 +static unsigned int jz_gpio_irq_startup(unsigned int irq)
2803 +{
2804 + struct irq_desc *desc = irq_to_desc(irq);
2805 +
2806 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_SET);
2807 +
2808 + desc->status &= ~IRQ_MASKED;
2809 + jz_gpio_irq_unmask(irq);
2810 +
2811 + return 0;
2812 +}
2813 +
2814 +static void jz_gpio_irq_shutdown(unsigned int irq)
2815 +{
2816 + struct irq_desc *desc = irq_to_desc(irq);
2817 +
2818 + jz_gpio_irq_mask(irq);
2819 + desc->status |= IRQ_MASKED;
2820 +
2821 + /* Set direction to input */
2822 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
2823 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_SELECT_CLEAR);
2824 +}
2825 +
2826 +static void jz_gpio_irq_ack(unsigned int irq)
2827 +{
2828 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_FLAG_CLEAR);
2829 +};
2830 +
2831 +static int jz_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
2832 +{
2833 + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
2834 + struct irq_desc *desc = irq_to_desc(irq);
2835 +
2836 + jz_gpio_irq_mask(irq);
2837 +
2838 + if (flow_type == IRQ_TYPE_EDGE_BOTH) {
2839 + uint32_t value = readl(IRQ_TO_REG(irq, JZ_REG_GPIO_PIN));
2840 + if (value & IRQ_TO_BIT(irq))
2841 + flow_type = IRQ_TYPE_EDGE_FALLING;
2842 + else
2843 + flow_type = IRQ_TYPE_EDGE_RISING;
2844 + chip->edge_trigger_both |= IRQ_TO_BIT(irq);
2845 + } else {
2846 + chip->edge_trigger_both &= ~IRQ_TO_BIT(irq);
2847 + }
2848 +
2849 + switch (flow_type) {
2850 + case IRQ_TYPE_EDGE_RISING:
2851 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
2852 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
2853 + break;
2854 + case IRQ_TYPE_EDGE_FALLING:
2855 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
2856 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_SET);
2857 + break;
2858 + case IRQ_TYPE_LEVEL_HIGH:
2859 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_SET);
2860 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
2861 + break;
2862 + case IRQ_TYPE_LEVEL_LOW:
2863 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_DIRECTION_CLEAR);
2864 + jz_gpio_set_irq_bit(irq, JZ_REG_GPIO_TRIGGER_CLEAR);
2865 + break;
2866 + default:
2867 + return -EINVAL;
2868 + }
2869 +
2870 + if (!(desc->status & IRQ_MASKED))
2871 + jz_gpio_irq_unmask(irq);
2872 +
2873 + return 0;
2874 +}
2875 +
2876 +static int jz_gpio_irq_set_wake(unsigned int irq, unsigned int on)
2877 +{
2878 + struct jz_gpio_chip *chip = irq_to_jz_gpio_chip(irq);
2879 + spin_lock(&chip->lock);
2880 + if (on)
2881 + chip->wakeup |= IRQ_TO_BIT(irq);
2882 + else
2883 + chip->wakeup &= ~IRQ_TO_BIT(irq);
2884 + spin_unlock(&chip->lock);
2885 +
2886 + set_irq_wake(chip->irq, on);
2887 + return 0;
2888 +}
2889 +
2890 +int gpio_to_irq(unsigned gpio)
2891 +{
2892 + return JZ4740_IRQ_GPIO(0) + gpio;
2893 +}
2894 +EXPORT_SYMBOL_GPL(gpio_to_irq);
2895 +
2896 +int irq_to_gpio(unsigned gpio)
2897 +{
2898 + return IRQ_TO_GPIO(gpio);
2899 +}
2900 +EXPORT_SYMBOL_GPL(irq_to_gpio);
2901 +
2902 +/*
2903 + * This lock class tells lockdep that GPIO irqs are in a different
2904 + * category than their parents, so it won't report false recursion.
2905 + */
2906 +static struct lock_class_key gpio_lock_class;
2907 +
2908 +#define JZ4740_GPIO_CHIP(_bank) { \
2909 + .irq_base = JZ4740_IRQ_GPIO_BASE_ ## _bank, \
2910 + .gpio_chip = { \
2911 + .label = "Bank " # _bank, \
2912 + .owner = THIS_MODULE, \
2913 + .set = jz_gpio_set_value, \
2914 + .get = jz_gpio_get_value, \
2915 + .direction_output = jz_gpio_direction_output, \
2916 + .direction_input = jz_gpio_direction_input, \
2917 + .base = JZ4740_GPIO_BASE_ ## _bank, \
2918 + .ngpio = JZ4740_GPIO_NUM_ ## _bank, \
2919 + }, \
2920 + .irq_chip = { \
2921 + .name = "GPIO Bank " # _bank, \
2922 + .mask = jz_gpio_irq_mask, \
2923 + .unmask = jz_gpio_irq_unmask, \
2924 + .ack = jz_gpio_irq_ack, \
2925 + .startup = jz_gpio_irq_startup, \
2926 + .shutdown = jz_gpio_irq_shutdown, \
2927 + .set_type = jz_gpio_irq_set_type, \
2928 + .set_wake = jz_gpio_irq_set_wake, \
2929 + }, \
2930 +}
2931 +
2932 +static struct jz_gpio_chip jz4740_gpio_chips[] = {
2933 + JZ4740_GPIO_CHIP(A),
2934 + JZ4740_GPIO_CHIP(B),
2935 + JZ4740_GPIO_CHIP(C),
2936 + JZ4740_GPIO_CHIP(D),
2937 +};
2938 +
2939 +static inline struct jz_gpio_chip *sysdev_to_chip(struct sys_device *dev)
2940 +{
2941 + return container_of(dev, struct jz_gpio_chip, sysdev);
2942 +}
2943 +
2944 +static int jz4740_gpio_suspend(struct sys_device *dev, pm_message_t state)
2945 +{
2946 + struct jz_gpio_chip *chip = sysdev_to_chip(dev);
2947 +
2948 + chip->suspend_mask = readl(chip->base + JZ_REG_GPIO_MASK);
2949 + writel(~(chip->wakeup), chip->base + JZ_REG_GPIO_MASK_SET);
2950 + writel(chip->wakeup, chip->base + JZ_REG_GPIO_MASK_CLEAR);
2951 +
2952 + return 0;
2953 +}
2954 +
2955 +static int jz4740_gpio_resume(struct sys_device *dev)
2956 +{
2957 + struct jz_gpio_chip *chip = sysdev_to_chip(dev);
2958 + uint32_t mask = chip->suspend_mask;
2959 +
2960 + writel(~mask, chip->base + JZ_REG_GPIO_MASK_CLEAR);
2961 + writel(mask, chip->base + JZ_REG_GPIO_MASK_SET);
2962 +
2963 + return 0;
2964 +}
2965 +
2966 +static struct sysdev_class jz4740_gpio_sysdev_class = {
2967 + .name = "gpio",
2968 + .suspend = jz4740_gpio_suspend,
2969 + .resume = jz4740_gpio_resume,
2970 +};
2971 +
2972 +static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
2973 +{
2974 + int ret, irq;
2975 +
2976 + chip->sysdev.id = id;
2977 + chip->sysdev.cls = &jz4740_gpio_sysdev_class;
2978 + ret = sysdev_register(&chip->sysdev);
2979 +
2980 + if (ret)
2981 + return ret;
2982 +
2983 + spin_lock_init(&chip->lock);
2984 +
2985 + chip->base = ioremap(CPHYSADDR(JZ4740_GPIO_BASE_ADDR) + (id * 0x100), 0x100);
2986 +
2987 + gpiochip_add(&chip->gpio_chip);
2988 +
2989 + chip->irq = JZ4740_IRQ_INTC_GPIO(id);
2990 + set_irq_data(chip->irq, chip);
2991 + set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
2992 +
2993 + for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
2994 + lockdep_set_class(&irq_desc[irq].lock, &gpio_lock_class);
2995 + set_irq_chip_and_handler(irq, &chip->irq_chip, handle_level_irq);
2996 + set_irq_chip_data(irq, chip);
2997 + }
2998 +
2999 + return 0;
3000 +}
3001 +
3002 +int __init jz_gpiolib_init(void)
3003 +{
3004 + unsigned int i;
3005 + int ret;
3006 +
3007 + ret = sysdev_class_register(&jz4740_gpio_sysdev_class);
3008 + if (ret)
3009 + return ret;
3010 +
3011 + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i) {
3012 + jz4740_gpio_chip_init(&jz4740_gpio_chips[i], i);
3013 + }
3014 +
3015 + printk(KERN_INFO "JZ4740 GPIO initalized\n");
3016 +
3017 + return 0;
3018 +}
3019 +
3020 +#ifdef CONFIG_DEBUG_FS
3021 +
3022 +static inline void gpio_seq_reg(struct seq_file *s, struct jz_gpio_chip *chip,
3023 + const char *name, unsigned int reg)
3024 +{
3025 + seq_printf(s, "\t%s: %08x\n", name, readl(chip->base + reg));
3026 +}
3027 +
3028 +
3029 +static int gpio_regs_show(struct seq_file *s, void *unused)
3030 +{
3031 + struct jz_gpio_chip *chip = jz4740_gpio_chips;
3032 + int i;
3033 +
3034 + for (i = 0; i < ARRAY_SIZE(jz4740_gpio_chips); ++i, ++chip) {
3035 + seq_printf(s, "GPIO %d: \n", i);
3036 + gpio_seq_reg(s, chip, "Pin", JZ_REG_GPIO_PIN);
3037 + gpio_seq_reg(s, chip, "Data", JZ_REG_GPIO_DATA);
3038 + gpio_seq_reg(s, chip, "Mask", JZ_REG_GPIO_MASK);
3039 + gpio_seq_reg(s, chip, "Pull", JZ_REG_GPIO_PULL);
3040 + gpio_seq_reg(s, chip, "Func", JZ_REG_GPIO_FUNC);
3041 + gpio_seq_reg(s, chip, "Select", JZ_REG_GPIO_SELECT);
3042 + gpio_seq_reg(s, chip, "Direction", JZ_REG_GPIO_DIRECTION);
3043 + gpio_seq_reg(s, chip, "Trigger", JZ_REG_GPIO_TRIGGER);
3044 + gpio_seq_reg(s, chip, "Flag", JZ_REG_GPIO_FLAG);
3045 + }
3046 +
3047 + return 0;
3048 +}
3049 +
3050 +static int gpio_regs_open(struct inode *inode, struct file *file)
3051 +{
3052 + return single_open(file, gpio_regs_show, NULL);
3053 +}
3054 +
3055 +static const struct file_operations gpio_regs_operations = {
3056 + .open = gpio_regs_open,
3057 + .read = seq_read,
3058 + .llseek = seq_lseek,
3059 + .release = single_release,
3060 +};
3061 +
3062 +static int __init gpio_debugfs_init(void)
3063 +{
3064 + (void) debugfs_create_file("jz_regs_gpio", S_IFREG | S_IRUGO,
3065 + NULL, NULL, &gpio_regs_operations);
3066 + return 0;
3067 +}
3068 +subsys_initcall(gpio_debugfs_init);
3069 +
3070 +#endif
3071 diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
3072 new file mode 100644
3073 index 0000000..46a03ee
3074 --- /dev/null
3075 +++ b/arch/mips/jz4740/irq.c
3076 @@ -0,0 +1,170 @@
3077 +/*
3078 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3079 + * JZ4740 platform IRQ support
3080 + *
3081 + * This program is free software; you can redistribute it and/or modify it
3082 + * under the terms of the GNU General Public License as published by the
3083 + * Free Software Foundation; either version 2 of the License, or (at your
3084 + * option) any later version.
3085 + *
3086 + * You should have received a copy of the GNU General Public License along
3087 + * with this program; if not, write to the Free Software Foundation, Inc.,
3088 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3089 + *
3090 + */
3091 +
3092 +#include <linux/errno.h>
3093 +#include <linux/init.h>
3094 +#include <linux/types.h>
3095 +#include <linux/interrupt.h>
3096 +#include <linux/ioport.h>
3097 +#include <linux/timex.h>
3098 +#include <linux/slab.h>
3099 +#include <linux/delay.h>
3100 +
3101 +#include <linux/debugfs.h>
3102 +#include <linux/seq_file.h>
3103 +
3104 +#include <asm/io.h>
3105 +#include <asm/mipsregs.h>
3106 +#include <asm/irq_cpu.h>
3107 +
3108 +#include <asm/mach-jz4740/base.h>
3109 +
3110 +static void __iomem *jz_intc_base;
3111 +static uint32_t jz_intc_wakeup;
3112 +static uint32_t jz_intc_saved;
3113 +
3114 +#define JZ_REG_INTC_STATUS 0x00
3115 +#define JZ_REG_INTC_MASK 0x04
3116 +#define JZ_REG_INTC_SET_MASK 0x08
3117 +#define JZ_REG_INTC_CLEAR_MASK 0x0c
3118 +#define JZ_REG_INTC_PENDING 0x10
3119 +
3120 +#define IRQ_BIT(x) BIT((x) - JZ4740_IRQ_BASE)
3121 +
3122 +static void intc_irq_unmask(unsigned int irq)
3123 +{
3124 + writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
3125 +}
3126 +
3127 +static void intc_irq_mask(unsigned int irq)
3128 +{
3129 + writel(IRQ_BIT(irq), jz_intc_base + JZ_REG_INTC_SET_MASK);
3130 +}
3131 +
3132 +static int intc_irq_set_wake(unsigned int irq, unsigned int on)
3133 +{
3134 + if (on)
3135 + jz_intc_wakeup |= IRQ_BIT(irq);
3136 + else
3137 + jz_intc_wakeup &= ~IRQ_BIT(irq);
3138 +
3139 + return 0;
3140 +}
3141 +
3142 +static struct irq_chip intc_irq_type = {
3143 + .name = "INTC",
3144 + .mask = intc_irq_mask,
3145 + .mask_ack = intc_irq_mask,
3146 + .unmask = intc_irq_unmask,
3147 + .set_wake = intc_irq_set_wake,
3148 +};
3149 +
3150 +static irqreturn_t jz4740_cascade(int irq, void *data)
3151 +{
3152 + uint32_t irq_reg;
3153 + int intc_irq;
3154 +
3155 + irq_reg = readl(jz_intc_base + JZ_REG_INTC_PENDING);
3156 +
3157 + intc_irq = ffs(irq_reg);
3158 + if (intc_irq)
3159 + generic_handle_irq(intc_irq - 1 + JZ4740_IRQ_BASE);
3160 +
3161 + return IRQ_HANDLED;
3162 +}
3163 +
3164 +static struct irqaction jz4740_cascade_action = {
3165 + .handler = jz4740_cascade,
3166 + .name = "JZ4740 cascade interrupt",
3167 + .flags = IRQF_DISABLED,
3168 +};
3169 +
3170 +void __init arch_init_irq(void)
3171 +{
3172 + int i;
3173 + mips_cpu_irq_init();
3174 +
3175 + jz_intc_base = ioremap(CPHYSADDR(JZ4740_INTC_BASE_ADDR), 0x14);
3176 +
3177 + for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
3178 + intc_irq_mask(i);
3179 + set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
3180 + }
3181 +
3182 + setup_irq(2, &jz4740_cascade_action);
3183 +}
3184 +
3185 +asmlinkage void plat_irq_dispatch(void)
3186 +{
3187 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
3188 + if (pending & STATUSF_IP2)
3189 + do_IRQ(2);
3190 + else if (pending & STATUSF_IP3)
3191 + do_IRQ(3);
3192 + else
3193 + spurious_interrupt();
3194 +}
3195 +
3196 +void jz4740_intc_suspend(void)
3197 +{
3198 + jz_intc_saved = readl(jz_intc_base + JZ_REG_INTC_MASK);
3199 + writel(~jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_SET_MASK);
3200 + writel(jz_intc_wakeup, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
3201 +}
3202 +
3203 +void jz4740_intc_resume(void)
3204 +{
3205 + writel(~jz_intc_saved, jz_intc_base + JZ_REG_INTC_CLEAR_MASK);
3206 + writel(jz_intc_saved, jz_intc_base + JZ_REG_INTC_SET_MASK);
3207 +}
3208 +
3209 +#ifdef CONFIG_DEBUG_FS
3210 +
3211 +static inline void intc_seq_reg(struct seq_file *s, const char *name,
3212 + unsigned int reg)
3213 +{
3214 + seq_printf(s, "%s:\t\t%08x\n", name, readl(jz_intc_base + reg));
3215 +}
3216 +
3217 +static int intc_regs_show(struct seq_file *s, void *unused)
3218 +{
3219 + intc_seq_reg(s, "Status", JZ_REG_INTC_STATUS);
3220 + intc_seq_reg(s, "Mask", JZ_REG_INTC_MASK);
3221 + intc_seq_reg(s, "Pending", JZ_REG_INTC_PENDING);
3222 +
3223 + return 0;
3224 +}
3225 +
3226 +static int intc_regs_open(struct inode *inode, struct file *file)
3227 +{
3228 + return single_open(file, intc_regs_show, NULL);
3229 +}
3230 +
3231 +static const struct file_operations intc_regs_operations = {
3232 + .open = intc_regs_open,
3233 + .read = seq_read,
3234 + .llseek = seq_lseek,
3235 + .release = single_release,
3236 +};
3237 +
3238 +static int __init intc_debugfs_init(void)
3239 +{
3240 + (void) debugfs_create_file("jz_regs_intc", S_IFREG | S_IRUGO,
3241 + NULL, NULL, &intc_regs_operations);
3242 + return 0;
3243 +}
3244 +subsys_initcall(intc_debugfs_init);
3245 +
3246 +#endif
3247 diff --git a/arch/mips/jz4740/irq.h b/arch/mips/jz4740/irq.h
3248 new file mode 100644
3249 index 0000000..dadbd5f
3250 --- /dev/null
3251 +++ b/arch/mips/jz4740/irq.h
3252 @@ -0,0 +1,21 @@
3253 +/*
3254 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3255 + *
3256 + * This program is free software; you can redistribute it and/or modify it
3257 + * under the terms of the GNU General Public License as published by the
3258 + * Free Software Foundation; either version 2 of the License, or (at your
3259 + * option) any later version.
3260 + *
3261 + * You should have received a copy of the GNU General Public License along
3262 + * with this program; if not, write to the Free Software Foundation, Inc.,
3263 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3264 + *
3265 + */
3266 +
3267 +#ifndef __MIPS_JZ4740_IRQ_H__
3268 +#define __MIPS_JZ4740_IRQ_H__
3269 +
3270 +extern void jz4740_intc_suspend(void);
3271 +extern void jz4740_intc_resume(void);
3272 +
3273 +#endif
3274 diff --git a/arch/mips/jz4740/platform.c b/arch/mips/jz4740/platform.c
3275 new file mode 100644
3276 index 0000000..6bb0778
3277 --- /dev/null
3278 +++ b/arch/mips/jz4740/platform.c
3279 @@ -0,0 +1,246 @@
3280 +/*
3281 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3282 + * JZ4740 platform devices
3283 + *
3284 + * This program is free software; you can redistribute it and/or modify it
3285 + * under the terms of the GNU General Public License as published by the
3286 + * Free Software Foundation; either version 2 of the License, or (at your
3287 + * option) any later version.
3288 + *
3289 + * You should have received a copy of the GNU General Public License along
3290 + * with this program; if not, write to the Free Software Foundation, Inc.,
3291 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3292 + *
3293 + */
3294 +
3295 +#include <linux/device.h>
3296 +#include <linux/platform_device.h>
3297 +#include <linux/kernel.h>
3298 +#include <linux/init.h>
3299 +#include <linux/resource.h>
3300 +
3301 +#include <asm/mach-jz4740/platform.h>
3302 +#include <asm/mach-jz4740/base.h>
3303 +#include <asm/mach-jz4740/irq.h>
3304 +
3305 +/* OHCI (USB full speed host controller) */
3306 +static struct resource jz4740_usb_ohci_resources[] = {
3307 + [0] = {
3308 + .start = CPHYSADDR(JZ4740_UHC_BASE_ADDR),
3309 + .end = CPHYSADDR(JZ4740_UHC_BASE_ADDR) + 0x10000 - 1,
3310 + .flags = IORESOURCE_MEM,
3311 + },
3312 + [1] = {
3313 + .start = JZ4740_IRQ_UHC,
3314 + .end = JZ4740_IRQ_UHC,
3315 + .flags = IORESOURCE_IRQ,
3316 + },
3317 +};
3318 +
3319 +/* The dmamask must be set for OHCI to work */
3320 +static u64 ohci_dmamask = ~(u32)0;
3321 +
3322 +struct platform_device jz4740_usb_ohci_device = {
3323 + .name = "jz4740-ohci",
3324 + .id = -1,
3325 + .dev = {
3326 + .dma_mask = &ohci_dmamask,
3327 + .coherent_dma_mask = 0xffffffff,
3328 + },
3329 + .num_resources = ARRAY_SIZE(jz4740_usb_ohci_resources),
3330 + .resource = jz4740_usb_ohci_resources,
3331 +};
3332 +
3333 +/* UDC (USB gadget controller) */
3334 +static struct resource jz4740_usb_gdt_resources[] = {
3335 + [0] = {
3336 + .start = CPHYSADDR(JZ4740_UDC_BASE_ADDR),
3337 + .end = CPHYSADDR(JZ4740_UDC_BASE_ADDR) + 0x10000 - 1,
3338 + .flags = IORESOURCE_MEM,
3339 + },
3340 + [1] = {
3341 + .start = JZ4740_IRQ_UDC,
3342 + .end = JZ4740_IRQ_UDC,
3343 + .flags = IORESOURCE_IRQ,
3344 + },
3345 +};
3346 +
3347 +static u64 jz4740_udc_dmamask = ~(u32)0;
3348 +
3349 +struct platform_device jz4740_usb_gdt_device = {
3350 + .name = "jz-udc",
3351 + .id = -1,
3352 + .dev = {
3353 + .dma_mask = &jz4740_udc_dmamask,
3354 + .coherent_dma_mask = 0xffffffff,
3355 + },
3356 + .num_resources = ARRAY_SIZE(jz4740_usb_gdt_resources),
3357 + .resource = jz4740_usb_gdt_resources,
3358 +};
3359 +
3360 +/** MMC/SD controller **/
3361 +static struct resource jz4740_mmc_resources[] = {
3362 + [0] = {
3363 + .start = CPHYSADDR(JZ4740_MSC_BASE_ADDR),
3364 + .end = CPHYSADDR(JZ4740_MSC_BASE_ADDR) + 0x10000 - 1,
3365 + .flags = IORESOURCE_MEM,
3366 + },
3367 + [1] = {
3368 + .start = JZ4740_IRQ_MSC,
3369 + .end = JZ4740_IRQ_MSC,
3370 + .flags = IORESOURCE_IRQ,
3371 + }
3372 +};
3373 +
3374 +static u64 jz4740_mmc_dmamask = ~(u32)0;
3375 +
3376 +struct platform_device jz4740_mmc_device = {
3377 + .name = "jz4740-mmc",
3378 + .id = 0,
3379 + .dev = {
3380 + .dma_mask = &jz4740_mmc_dmamask,
3381 + .coherent_dma_mask = 0xffffffff,
3382 + },
3383 + .num_resources = ARRAY_SIZE(jz4740_mmc_resources),
3384 + .resource = jz4740_mmc_resources,
3385 +};
3386 +
3387 +static struct resource jz4740_rtc_resources[] = {
3388 + [0] = {
3389 + .start = CPHYSADDR(JZ4740_RTC_BASE_ADDR),
3390 + .end = CPHYSADDR(JZ4740_RTC_BASE_ADDR) + 0x38 - 1,
3391 + .flags = IORESOURCE_MEM,
3392 + },
3393 + [1] = {
3394 + .start = JZ4740_IRQ_RTC,
3395 + .end = JZ4740_IRQ_RTC,
3396 + .flags = IORESOURCE_IRQ,
3397 + },
3398 +};
3399 +
3400 +struct platform_device jz4740_rtc_device = {
3401 + .name = "jz4740-rtc",
3402 + .id = -1,
3403 + .num_resources = ARRAY_SIZE(jz4740_rtc_resources),
3404 + .resource = jz4740_rtc_resources,
3405 +};
3406 +
3407 +/** I2C controller **/
3408 +static struct resource jz4740_i2c_resources[] = {
3409 + [0] = {
3410 + .start = CPHYSADDR(JZ4740_I2C_BASE_ADDR),
3411 + .end = CPHYSADDR(JZ4740_I2C_BASE_ADDR) + 0x10000 - 1,
3412 + .flags = IORESOURCE_MEM,
3413 + },
3414 + [1] = {
3415 + .start = JZ4740_IRQ_I2C,
3416 + .end = JZ4740_IRQ_I2C,
3417 + .flags = IORESOURCE_IRQ,
3418 + }
3419 +};
3420 +
3421 +static u64 jz4740_i2c_dmamask = ~(u32)0;
3422 +
3423 +struct platform_device jz4740_i2c_device = {
3424 + .name = "jz_i2c",
3425 + .id = 0,
3426 + .dev = {
3427 + .dma_mask = &jz4740_i2c_dmamask,
3428 + .coherent_dma_mask = 0xffffffff,
3429 + },
3430 + .num_resources = ARRAY_SIZE(jz4740_i2c_resources),
3431 + .resource = jz4740_i2c_resources,
3432 +};
3433 +
3434 +static struct resource jz4740_nand_resources[] = {
3435 + [0] = {
3436 + .start = CPHYSADDR(JZ4740_EMC_BASE_ADDR),
3437 + .end = CPHYSADDR(JZ4740_EMC_BASE_ADDR) + 0x10000 - 1,
3438 + .flags = IORESOURCE_MEM,
3439 + },
3440 +};
3441 +
3442 +struct platform_device jz4740_nand_device = {
3443 + .name = "jz4740-nand",
3444 + .num_resources = ARRAY_SIZE(jz4740_nand_resources),
3445 + .resource = jz4740_nand_resources,
3446 +};
3447 +
3448 +static struct resource jz4740_framebuffer_resources[] = {
3449 + [0] = {
3450 + .start = CPHYSADDR(JZ4740_LCD_BASE_ADDR),
3451 + .end = CPHYSADDR(JZ4740_LCD_BASE_ADDR) + 0x10000 - 1,
3452 + .flags = IORESOURCE_MEM,
3453 + },
3454 +};
3455 +
3456 +static u64 jz4740_fb_dmamask = ~(u32)0;
3457 +
3458 +struct platform_device jz4740_framebuffer_device = {
3459 + .name = "jz4740-fb",
3460 + .id = -1,
3461 + .num_resources = ARRAY_SIZE(jz4740_framebuffer_resources),
3462 + .resource = jz4740_framebuffer_resources,
3463 + .dev = {
3464 + .dma_mask = &jz4740_fb_dmamask,
3465 + .coherent_dma_mask = 0xffffffff,
3466 + },
3467 +};
3468 +
3469 +static struct resource jz4740_i2s_resources[] = {
3470 + [0] = {
3471 + .start = CPHYSADDR(JZ4740_AIC_BASE_ADDR),
3472 + .end = CPHYSADDR(JZ4740_AIC_BASE_ADDR) + 0x38 - 1,
3473 + .flags = IORESOURCE_MEM,
3474 + },
3475 +};
3476 +
3477 +struct platform_device jz4740_i2s_device = {
3478 + .name = "jz4740-i2s",
3479 + .id = -1,
3480 + .num_resources = ARRAY_SIZE(jz4740_i2s_resources),
3481 + .resource = jz4740_i2s_resources,
3482 +};
3483 +
3484 +static struct resource jz4740_codec_resources[] = {
3485 + [0] = {
3486 + .start = CPHYSADDR(JZ4740_AIC_BASE_ADDR) + 0x80,
3487 + .end = CPHYSADDR(JZ4740_AIC_BASE_ADDR) + 0x88 - 1,
3488 + .flags = IORESOURCE_MEM,
3489 + },
3490 +};
3491 +
3492 +struct platform_device jz4740_codec_device = {
3493 + .name = "jz4740-codec",
3494 + .id = -1,
3495 + .num_resources = ARRAY_SIZE(jz4740_codec_resources),
3496 + .resource = jz4740_codec_resources,
3497 +};
3498 +
3499 +static struct resource jz4740_adc_resources[] = {
3500 + [0] = {
3501 + .start = CPHYSADDR(JZ4740_SADC_BASE_ADDR),
3502 + .end = CPHYSADDR(JZ4740_SADC_BASE_ADDR) + 0x30,
3503 + .flags = IORESOURCE_MEM,
3504 + },
3505 + [1] = {
3506 + .start = JZ4740_IRQ_SADC,
3507 + .end = JZ4740_IRQ_SADC,
3508 + .flags = IORESOURCE_IRQ,
3509 + },
3510 +};
3511 +
3512 +struct platform_device jz4740_adc_device = {
3513 + .name = "jz4740-adc",
3514 + .id = -1,
3515 + .num_resources = ARRAY_SIZE(jz4740_adc_resources),
3516 + .resource = jz4740_adc_resources,
3517 +};
3518 +
3519 +struct platform_device jz4740_battery_device = {
3520 + .name = "jz4740-battery",
3521 + .id = -1,
3522 + .dev = {
3523 + .parent = &jz4740_adc_device.dev
3524 + },
3525 +};
3526 diff --git a/arch/mips/jz4740/pm.c b/arch/mips/jz4740/pm.c
3527 new file mode 100644
3528 index 0000000..4ca3156
3529 --- /dev/null
3530 +++ b/arch/mips/jz4740/pm.c
3531 @@ -0,0 +1,59 @@
3532 +/*
3533 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3534 + * JZ4740 SoC power management support
3535 + *
3536 + * This program is free software; you can redistribute it and/or modify it
3537 + * under the terms of the GNU General Public License as published by the
3538 + * Free Software Foundation; either version 2 of the License, or (at your
3539 + * option) any later version.
3540 + *
3541 + * You should have received a copy of the GNU General Public License along
3542 + * with this program; if not, write to the Free Software Foundation, Inc.,
3543 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3544 + *
3545 + */
3546 +
3547 +#include <linux/init.h>
3548 +#include <linux/pm.h>
3549 +#include <linux/delay.h>
3550 +#include <linux/suspend.h>
3551 +
3552 +#include <asm/mach-jz4740/clock.h>
3553 +
3554 +#include "clock.h"
3555 +#include "irq.h"
3556 +
3557 +static int jz_pm_enter(suspend_state_t state)
3558 +{
3559 + jz4740_intc_suspend();
3560 + jz4740_clock_suspend();
3561 +
3562 + jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_SLEEP);
3563 +
3564 + __asm__(".set\tmips3\n\t"
3565 + "wait\n\t"
3566 + ".set\tmips0");
3567 +
3568 + jz4740_clock_set_wait_mode(JZ4740_WAIT_MODE_IDLE);
3569 +
3570 + jz4740_clock_resume();
3571 + jz4740_intc_resume();
3572 +
3573 + return 0;
3574 +}
3575 +
3576 +static struct platform_suspend_ops jz_pm_ops = {
3577 + .valid = suspend_valid_only_mem,
3578 + .enter = jz_pm_enter,
3579 +};
3580 +
3581 +/*
3582 + * Initialize power interface
3583 + */
3584 +int __init jz_pm_init(void)
3585 +{
3586 + suspend_set_ops(&jz_pm_ops);
3587 + return 0;
3588 +
3589 +}
3590 +late_initcall(jz_pm_init);
3591 diff --git a/arch/mips/jz4740/prom.c b/arch/mips/jz4740/prom.c
3592 new file mode 100644
3593 index 0000000..4f99ea3
3594 --- /dev/null
3595 +++ b/arch/mips/jz4740/prom.c
3596 @@ -0,0 +1,69 @@
3597 +/*
3598 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3599 + * JZ4740 SoC prom code
3600 + *
3601 + * This program is free software; you can redistribute it and/or modify it
3602 + * under the terms of the GNU General Public License as published by the
3603 + * Free Software Foundation; either version 2 of the License, or (at your
3604 + * option) any later version.
3605 + *
3606 + * You should have received a copy of the GNU General Public License along
3607 + * with this program; if not, write to the Free Software Foundation, Inc.,
3608 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3609 + *
3610 + */
3611 +
3612 +
3613 +#include <linux/module.h>
3614 +#include <linux/kernel.h>
3615 +#include <linux/init.h>
3616 +#include <linux/string.h>
3617 +
3618 +#include <linux/serial_reg.h>
3619 +
3620 +#include <asm/bootinfo.h>
3621 +#include <asm/mach-jz4740/base.h>
3622 +
3623 +void jz4740_init_cmdline(int argc, char *argv[])
3624 +{
3625 + unsigned int count = COMMAND_LINE_SIZE - 1;
3626 + int i;
3627 + char *dst = &(arcs_cmdline[0]);
3628 + char *src;
3629 +
3630 + for (i = 1; i < argc && count; ++i) {
3631 + src = argv[i];
3632 + while (*src && count) {
3633 + *dst++ = *src++;
3634 + --count;
3635 + }
3636 + *dst++ = ' ';
3637 + }
3638 + if (i > 1)
3639 + --dst;
3640 +
3641 + *dst = 0;
3642 +}
3643 +
3644 +void __init prom_init(void)
3645 +{
3646 + jz4740_init_cmdline((int)fw_arg0, (char **)fw_arg1);
3647 + mips_machtype = MACH_INGENIC_JZ4740;
3648 +}
3649 +
3650 +void __init prom_free_prom_memory(void)
3651 +{
3652 +}
3653 +
3654 +#define UART_REG(offset) ((void __iomem*)(JZ4740_UART0_BASE_ADDR + (offset << 2)))
3655 +
3656 +void prom_putchar(char c)
3657 +{
3658 + uint8_t lsr;
3659 +
3660 + do {
3661 + lsr = readb(UART_REG(UART_LSR));
3662 + } while ((lsr & UART_LSR_TEMT) == 0);
3663 +
3664 + writeb(c, UART_REG(UART_TX));
3665 +}
3666 diff --git a/arch/mips/jz4740/pwm.c b/arch/mips/jz4740/pwm.c
3667 new file mode 100644
3668 index 0000000..0ff8c1d
3669 --- /dev/null
3670 +++ b/arch/mips/jz4740/pwm.c
3671 @@ -0,0 +1,167 @@
3672 +/*
3673 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3674 + * JZ4740 platform PWM support
3675 + *
3676 + * This program is free software; you can redistribute it and/or modify it
3677 + * under the terms of the GNU General Public License as published by the
3678 + * Free Software Foundation; either version 2 of the License, or (at your
3679 + * option) any later version.
3680 + *
3681 + * You should have received a copy of the GNU General Public License along
3682 + * with this program; if not, write to the Free Software Foundation, Inc.,
3683 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3684 + *
3685 + */
3686 +
3687 +
3688 +#include <linux/kernel.h>
3689 +
3690 +#include <linux/clk.h>
3691 +#include <linux/err.h>
3692 +#include <linux/pwm.h>
3693 +#include <linux/gpio.h>
3694 +
3695 +#include <asm/mach-jz4740/gpio.h>
3696 +#include "timer.h"
3697 +
3698 +static struct clk *jz4740_pwm_clk;
3699 +
3700 +DEFINE_MUTEX(jz4740_pwm_mutex);
3701 +
3702 +struct pwm_device {
3703 + unsigned int id;
3704 + unsigned int gpio;
3705 + bool used;
3706 +};
3707 +
3708 +static struct pwm_device jz4740_pwm_list[] = {
3709 + { 2, JZ_GPIO_PWM2, false },
3710 + { 3, JZ_GPIO_PWM3, false },
3711 + { 4, JZ_GPIO_PWM4, false },
3712 + { 5, JZ_GPIO_PWM5, false },
3713 + { 6, JZ_GPIO_PWM6, false },
3714 + { 7, JZ_GPIO_PWM7, false },
3715 +};
3716 +
3717 +struct pwm_device *pwm_request(int id, const char *label)
3718 +{
3719 + int ret = 0;
3720 + struct pwm_device *pwm;
3721 +
3722 + if (!jz4740_pwm_clk) {
3723 + jz4740_pwm_clk = clk_get(NULL, "pclk");
3724 +
3725 + if (IS_ERR(jz4740_pwm_clk))
3726 + return ERR_PTR(PTR_ERR(jz4740_pwm_clk));
3727 + }
3728 +
3729 + if (id < 2 || id > 7) {
3730 + return ERR_PTR(-ENOENT);
3731 + }
3732 +
3733 + mutex_lock(&jz4740_pwm_mutex);
3734 +
3735 + pwm = &jz4740_pwm_list[id - 2];
3736 + if (pwm->used)
3737 + ret = -EBUSY;
3738 + else
3739 + pwm->used = true;
3740 +
3741 + mutex_unlock(&jz4740_pwm_mutex);
3742 +
3743 + if (ret) {
3744 + return ERR_PTR(ret);
3745 + }
3746 +
3747 + ret = gpio_request(pwm->gpio, label);
3748 +
3749 + if (ret) {
3750 + printk("Failed to request pwm gpio: %d\n", ret);
3751 + pwm->used = false;
3752 + return ERR_PTR(ret);
3753 + }
3754 +
3755 + jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_PWM);
3756 +
3757 + jz4740_timer_start(id);
3758 +
3759 + return pwm;
3760 +}
3761 +
3762 +void pwm_free(struct pwm_device *pwm)
3763 +{
3764 + pwm_disable(pwm);
3765 + jz4740_timer_set_ctrl(pwm->id, 0);
3766 +
3767 + jz_gpio_set_function(pwm->gpio, JZ_GPIO_FUNC_NONE);
3768 + gpio_free(pwm->gpio);
3769 +
3770 + jz4740_timer_stop(pwm->id);
3771 +
3772 + pwm->used = false;
3773 +
3774 +}
3775 +
3776 +int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
3777 +{
3778 + unsigned long long tmp;
3779 + unsigned long period, duty;
3780 + unsigned int prescaler = 0;
3781 + unsigned int id = pwm->id;
3782 + uint16_t ctrl;
3783 + bool is_enabled;
3784 +
3785 + if (duty_ns < 0 || duty_ns > period_ns)
3786 + return -EINVAL;
3787 +
3788 + tmp = (unsigned long long)clk_get_rate(jz4740_pwm_clk) * period_ns;
3789 +
3790 + do_div(tmp, 1000000000);
3791 +
3792 + period = tmp;
3793 +
3794 + while (period > 0xffff && prescaler < 6) {
3795 + period >>= 2;
3796 + ++prescaler;
3797 + }
3798 +
3799 + if (prescaler == 6)
3800 + return -EINVAL;
3801 +
3802 +
3803 + tmp = (unsigned long long)period * duty_ns;
3804 + do_div(tmp, period_ns);
3805 + duty = tmp;
3806 +
3807 + if (duty >= period)
3808 + duty = period - 1;
3809 +
3810 + is_enabled = jz4740_timer_is_enabled(id);
3811 + jz4740_timer_disable(id);
3812 +
3813 + jz4740_timer_set_count(id, 0);
3814 + jz4740_timer_set_duty(id, duty);
3815 + jz4740_timer_set_period(id, period);
3816 +
3817 + ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_PWM_ENABLE |
3818 + JZ_TIMER_CTRL_SRC_PCLK;
3819 +
3820 + jz4740_timer_set_ctrl(id, ctrl);
3821 +
3822 + if (is_enabled)
3823 + jz4740_timer_enable(id);
3824 +
3825 + return 0;
3826 +}
3827 +
3828 +int pwm_enable(struct pwm_device *pwm)
3829 +{
3830 + jz4740_timer_enable(pwm->id);
3831 +
3832 + return 0;
3833 +}
3834 +
3835 +void pwm_disable(struct pwm_device *pwm)
3836 +{
3837 + jz4740_timer_disable(pwm->id);
3838 +}
3839 diff --git a/arch/mips/jz4740/reset.c b/arch/mips/jz4740/reset.c
3840 new file mode 100644
3841 index 0000000..448a7da
3842 --- /dev/null
3843 +++ b/arch/mips/jz4740/reset.c
3844 @@ -0,0 +1,81 @@
3845 +/*
3846 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3847 + *
3848 + * This program is free software; you can redistribute it and/or modify it
3849 + * under the terms of the GNU General Public License as published by the
3850 + * Free Software Foundation; either version 2 of the License, or (at your
3851 + * option) any later version.
3852 + *
3853 + * You should have received a copy of the GNU General Public License along
3854 + * with this program; if not, write to the Free Software Foundation, Inc.,
3855 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3856 + *
3857 + */
3858 +
3859 +#include <linux/io.h>
3860 +#include <linux/kernel.h>
3861 +#include <linux/pm.h>
3862 +
3863 +#include <linux/delay.h>
3864 +
3865 +#include <asm/reboot.h>
3866 +
3867 +#include <asm/mach-jz4740/base.h>
3868 +#include <asm/mach-jz4740/timer.h>
3869 +
3870 +static void jz4740_halt(void)
3871 +{
3872 + while (1) {
3873 + __asm__(".set push;\n"
3874 + ".set mips3;\n"
3875 + "wait;\n"
3876 + ".set pop;\n"
3877 + );
3878 + }
3879 +}
3880 +
3881 +#define JZ_REG_WDT_DATA 0x00
3882 +#define JZ_REG_WDT_COUNTER_ENABLE 0x04
3883 +#define JZ_REG_WDT_COUNTER 0x08
3884 +#define JZ_REG_WDT_CTRL 0x0c
3885 +
3886 +static void jz4740_restart(char *command)
3887 +{
3888 + void __iomem *wdt_base = ioremap(CPHYSADDR(JZ4740_WDT_BASE_ADDR), 0x0f);
3889 +
3890 + jz4740_timer_enable_watchdog();
3891 +
3892 + writeb(0, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
3893 +
3894 + writew(0, wdt_base + JZ_REG_WDT_COUNTER);
3895 + writew(0, wdt_base + JZ_REG_WDT_DATA);
3896 + writew(BIT(2), wdt_base + JZ_REG_WDT_CTRL);
3897 +
3898 + writeb(1, wdt_base + JZ_REG_WDT_COUNTER_ENABLE);
3899 + jz4740_halt();
3900 +}
3901 +
3902 +#define JZ_REG_RTC_CTRL 0x00
3903 +#define JZ_REG_RTC_HIBERNATE 0x20
3904 +
3905 +#define JZ_RTC_CTRL_WRDY BIT(7)
3906 +
3907 +static void jz4740_power_off(void)
3908 +{
3909 + void __iomem *rtc_base = ioremap(CPHYSADDR(JZ4740_RTC_BASE_ADDR), 0x24);
3910 + uint32_t ctrl;
3911 +
3912 + do {
3913 + ctrl = readl(rtc_base + JZ_REG_RTC_CTRL);
3914 + } while (!(ctrl & JZ_RTC_CTRL_WRDY));
3915 +
3916 + writel(1, rtc_base + JZ_REG_RTC_HIBERNATE);
3917 + jz4740_halt();
3918 +}
3919 +
3920 +void jz4740_reset_init(void)
3921 +{
3922 + _machine_restart = jz4740_restart;
3923 + _machine_halt = jz4740_halt;
3924 + pm_power_off = jz4740_power_off;
3925 +}
3926 diff --git a/arch/mips/jz4740/reset.h b/arch/mips/jz4740/reset.h
3927 new file mode 100644
3928 index 0000000..c57a829
3929 --- /dev/null
3930 +++ b/arch/mips/jz4740/reset.h
3931 @@ -0,0 +1,7 @@
3932 +#ifndef __MIPS_JZ4740_RESET_H__
3933 +#define __MIPS_JZ4740_RESET_H__
3934 +
3935 +extern void jz4740_reset_init(void);
3936 +
3937 +#endif
3938 +
3939 diff --git a/arch/mips/jz4740/setup.c b/arch/mips/jz4740/setup.c
3940 new file mode 100644
3941 index 0000000..a6628f4
3942 --- /dev/null
3943 +++ b/arch/mips/jz4740/setup.c
3944 @@ -0,0 +1,64 @@
3945 +/*
3946 + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3947 + * JZ4740 setup code
3948 + *
3949 + * This program is free software; you can redistribute it and/or modify it
3950 + * under the terms of the GNU General Public License as published by the
3951 + * Free Software Foundation; either version 2 of the License, or (at your
3952 + * option) any later version.
3953 + *
3954 + * You should have received a copy of the GNU General Public License along
3955 + * with this program; if not, write to the Free Software Foundation, Inc.,
3956 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3957 + *
3958 + */
3959 +
3960 +
3961 +#include <linux/init.h>
3962 +#include <linux/kernel.h>
3963 +#include <linux/serial.h>
3964 +#include <linux/serial_core.h>
3965 +#include <linux/serial_8250.h>
3966 +
3967 +#include <asm/mach-jz4740/base.h>
3968 +#include <asm/mach-jz4740/clock.h>
3969 +#include <asm/mach-jz4740/serial.h>
3970 +
3971 +#include "reset.h"
3972 +#include "clock.h"
3973 +
3974 +static void __init jz4740_serial_setup(void)
3975 +{
3976 +#ifdef CONFIG_SERIAL_8250
3977 + struct uart_port s;
3978 + memset(&s, 0, sizeof(s));
3979 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3980 + s.iotype = SERIAL_IO_MEM;
3981 + s.regshift = 2;
3982 + s.uartclk = jz4740_clock_bdata.ext_rate;
3983 +
3984 + s.line = 0;
3985 + s.membase = (u8 *)JZ4740_UART0_BASE_ADDR;
3986 + s.irq = JZ4740_IRQ_UART0;
3987 + if (early_serial_setup(&s) != 0) {
3988 + printk(KERN_ERR "Serial ttyS0 setup failed!\n");
3989 + }
3990 +
3991 + s.line = 1;
3992 + s.membase = (u8 *)JZ4740_UART1_BASE_ADDR;
3993 + s.irq = JZ4740_IRQ_UART1;
3994 + if (early_serial_setup(&s) != 0) {
3995 + printk(KERN_ERR "Serial ttyS1 setup failed!\n");
3996 + }
3997 +#endif
3998 +}
3999 +void __init plat_mem_setup(void)
4000 +{
4001 + jz4740_reset_init();
4002 + jz4740_serial_setup();
4003 +}
4004 +
4005 +const char *get_system_type(void)
4006 +{
4007 + return "JZ4740";
4008 +}
4009 diff --git a/arch/mips/jz4740/time.c b/arch/mips/jz4740/time.c
4010 new file mode 100644
4011 index 0000000..da8183f
4012 --- /dev/null
4013 +++ b/arch/mips/jz4740/time.c
4014 @@ -0,0 +1,144 @@
4015 +/*
4016 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4017 + * JZ4740 platform time support
4018 + *
4019 + * This program is free software; you can redistribute it and/or modify it
4020 + * under the terms of the GNU General Public License as published by the
4021 + * Free Software Foundation; either version 2 of the License, or (at your
4022 + * option) any later version.
4023 + *
4024 + * You should have received a copy of the GNU General Public License along
4025 + * with this program; if not, write to the Free Software Foundation, Inc.,
4026 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4027 + *
4028 + */
4029 +
4030 +#include <linux/interrupt.h>
4031 +#include <linux/kernel.h>
4032 +#include <linux/time.h>
4033 +
4034 +#include <linux/clockchips.h>
4035 +
4036 +#include <asm/mach-jz4740/irq.h>
4037 +#include <asm/time.h>
4038 +
4039 +#include "clock.h"
4040 +#include "timer.h"
4041 +
4042 +#define TIMER_CLOCKEVENT 0
4043 +#define TIMER_CLOCKSOURCE 1
4044 +
4045 +static uint16_t jz4740_jiffies_per_tick;
4046 +
4047 +static cycle_t jz4740_clocksource_read(struct clocksource *cs)
4048 +{
4049 + return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
4050 +}
4051 +
4052 +static struct clocksource jz4740_clocksource = {
4053 + .name = "jz4740-timer",
4054 + .rating = 200,
4055 + .read = jz4740_clocksource_read,
4056 + .mask = CLOCKSOURCE_MASK(16),
4057 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
4058 +};
4059 +
4060 +static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
4061 +{
4062 + struct clock_event_device *cd = devid;
4063 +
4064 + jz4740_timer_ack_full(TIMER_CLOCKEVENT);
4065 +
4066 + if (cd->mode != CLOCK_EVT_MODE_PERIODIC)
4067 + jz4740_timer_disable(TIMER_CLOCKEVENT);
4068 +
4069 + cd->event_handler(cd);
4070 +
4071 + return IRQ_HANDLED;
4072 +}
4073 +
4074 +static void jz4740_clockevent_set_mode(enum clock_event_mode mode,
4075 + struct clock_event_device *cd)
4076 +{
4077 + switch (mode) {
4078 + case CLOCK_EVT_MODE_PERIODIC:
4079 + jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
4080 + jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
4081 + case CLOCK_EVT_MODE_RESUME:
4082 + jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
4083 + jz4740_timer_enable(TIMER_CLOCKEVENT);
4084 + break;
4085 + case CLOCK_EVT_MODE_ONESHOT:
4086 + case CLOCK_EVT_MODE_SHUTDOWN:
4087 + jz4740_timer_disable(TIMER_CLOCKEVENT);
4088 + break;
4089 + default:
4090 + break;
4091 + }
4092 +}
4093 +
4094 +static int jz4740_clockevent_set_next(unsigned long evt,
4095 + struct clock_event_device *cd)
4096 +{
4097 + jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
4098 + jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
4099 + jz4740_timer_enable(TIMER_CLOCKEVENT);
4100 +
4101 + return 0;
4102 +}
4103 +
4104 +static struct clock_event_device jz4740_clockevent = {
4105 + .name = "jz4740-timer",
4106 + .features = CLOCK_EVT_FEAT_PERIODIC,
4107 + .set_next_event = jz4740_clockevent_set_next,
4108 + .set_mode = jz4740_clockevent_set_mode,
4109 + .rating = 200,
4110 + .irq = JZ4740_IRQ_TCU0,
4111 +};
4112 +
4113 +static struct irqaction timer_irqaction = {
4114 + .handler = jz4740_clockevent_irq,
4115 + .flags = IRQF_PERCPU | IRQF_TIMER | IRQF_DISABLED,
4116 + .name = "jz4740-timerirq",
4117 + .dev_id = &jz4740_clockevent,
4118 +};
4119 +
4120 +void __init plat_time_init(void)
4121 +{
4122 + int ret;
4123 + uint32_t clk_rate;
4124 + uint16_t ctrl;
4125 +
4126 + jz4740_timer_init();
4127 +
4128 + clk_rate = jz4740_clock_bdata.ext_rate >> 4;
4129 + jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
4130 +
4131 + clockevent_set_clock(&jz4740_clockevent, clk_rate);
4132 + jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
4133 + jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
4134 + jz4740_clockevent.cpumask = cpumask_of(0);
4135 +
4136 + clockevents_register_device(&jz4740_clockevent);
4137 +
4138 + clocksource_set_clock(&jz4740_clocksource, clk_rate);
4139 + ret = clocksource_register(&jz4740_clocksource);
4140 +
4141 + if (ret)
4142 + printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
4143 +
4144 + setup_irq(JZ4740_IRQ_TCU0, &timer_irqaction);
4145 +
4146 + ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
4147 +
4148 + jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
4149 + jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
4150 +
4151 + jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
4152 + jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
4153 +
4154 + jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
4155 +
4156 + jz4740_timer_enable(TIMER_CLOCKEVENT);
4157 + jz4740_timer_enable(TIMER_CLOCKSOURCE);
4158 +}
4159 diff --git a/arch/mips/jz4740/timer.c b/arch/mips/jz4740/timer.c
4160 new file mode 100644
4161 index 0000000..6e09cae
4162 --- /dev/null
4163 +++ b/arch/mips/jz4740/timer.c
4164 @@ -0,0 +1,48 @@
4165 +/*
4166 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4167 + * JZ4740 platform timer support
4168 + *
4169 + * This program is free software; you can redistribute it and/or modify it
4170 + * under the terms of the GNU General Public License as published by the
4171 + * Free Software Foundation; either version 2 of the License, or (at your
4172 + * option) any later version.
4173 + *
4174 + * You should have received a copy of the GNU General Public License along
4175 + * with this program; if not, write to the Free Software Foundation, Inc.,
4176 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4177 + *
4178 + */
4179 +
4180 +#include <linux/io.h>
4181 +#include <linux/kernel.h>
4182 +#include <linux/module.h>
4183 +
4184 +#include "timer.h"
4185 +
4186 +#include <asm/mach-jz4740/base.h>
4187 +
4188 +void __iomem *jz4740_timer_base;
4189 +
4190 +void jz4740_timer_enable_watchdog(void)
4191 +{
4192 + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
4193 +}
4194 +
4195 +void jz4740_timer_disable_watchdog(void)
4196 +{
4197 + writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
4198 +}
4199 +
4200 +void __init jz4740_timer_init(void)
4201 +{
4202 + jz4740_timer_base = ioremap(CPHYSADDR(JZ4740_TCU_BASE_ADDR), 0x100);
4203 +
4204 + if (!jz4740_timer_base)
4205 + panic("Failed to ioremap timer registers");
4206 +
4207 + /* Disable all timer clocks except for those used as system timers */
4208 + writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
4209 +
4210 + /* Timer irqs are unmasked by default, mask them */
4211 + writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
4212 +}
4213 diff --git a/arch/mips/jz4740/timer.h b/arch/mips/jz4740/timer.h
4214 new file mode 100644
4215 index 0000000..77d748c
4216 --- /dev/null
4217 +++ b/arch/mips/jz4740/timer.h
4218 @@ -0,0 +1,130 @@
4219 +/*
4220 + * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4221 + * JZ4740 platform timer support
4222 + *
4223 + * This program is free software; you can redistribute it and/or modify it
4224 + * under the terms of the GNU General Public License as published by the
4225 + * Free Software Foundation; either version 2 of the License, or (at your
4226 + * option) any later version.
4227 + *
4228 + * You should have received a copy of the GNU General Public License along
4229 + * with this program; if not, write to the Free Software Foundation, Inc.,
4230 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4231 + *
4232 + */
4233 +
4234 +#ifndef __MIPS_JZ4740_TIMER_H__
4235 +#define __MIPS_JZ4740_TIMER_H__
4236 +
4237 +#include <linux/module.h>
4238 +#include <linux/io.h>
4239 +
4240 +#define JZ_REG_TIMER_STOP 0x1C
4241 +#define JZ_REG_TIMER_STOP_SET 0x2C
4242 +#define JZ_REG_TIMER_STOP_CLEAR 0x3C
4243 +#define JZ_REG_TIMER_ENABLE 0x10
4244 +#define JZ_REG_TIMER_ENABLE_SET 0x14
4245 +#define JZ_REG_TIMER_ENABLE_CLEAR 0x18
4246 +#define JZ_REG_TIMER_FLAG 0x20
4247 +#define JZ_REG_TIMER_FLAG_SET 0x24
4248 +#define JZ_REG_TIMER_FLAG_CLEAR 0x28
4249 +#define JZ_REG_TIMER_MASK 0x30
4250 +#define JZ_REG_TIMER_MASK_SET 0x34
4251 +#define JZ_REG_TIMER_MASK_CLEAR 0x38
4252 +
4253 +#define JZ_REG_TIMER_DFR(x) (((x) * 0x10) + 0x40)
4254 +#define JZ_REG_TIMER_DHR(x) (((x) * 0x10) + 0x44)
4255 +#define JZ_REG_TIMER_CNT(x) (((x) * 0x10) + 0x48)
4256 +#define JZ_REG_TIMER_CTRL(x) (((x) * 0x10) + 0x4C)
4257 +
4258 +#define JZ_TIMER_IRQ_HALF(x) BIT((x) + 0x10)
4259 +#define JZ_TIMER_IRQ_FULL(x) BIT(x)
4260 +
4261 +#define JZ_TIMER_CTRL_PWM_ACTIVE_LOW BIT(8)
4262 +#define JZ_TIMER_CTRL_PWM_ENABLE BIT(7)
4263 +#define JZ_TIMER_CTRL_PRESCALE_MASK 0x1c
4264 +#define JZ_TIMER_CTRL_PRESCALE_OFFSET 0x3
4265 +#define JZ_TIMER_CTRL_PRESCALE_1 (0 << 3)
4266 +#define JZ_TIMER_CTRL_PRESCALE_4 (1 << 3)
4267 +#define JZ_TIMER_CTRL_PRESCALE_16 (2 << 3)
4268 +#define JZ_TIMER_CTRL_PRESCALE_64 (3 << 3)
4269 +#define JZ_TIMER_CTRL_PRESCALE_256 (4 << 3)
4270 +#define JZ_TIMER_CTRL_PRESCALE_1024 (5 << 3)
4271 +
4272 +#define JZ_TIMER_CTRL_PRESCALER(x) ((x) << JZ_TIMER_CTRL_PRESCALE_OFFSET)
4273 +
4274 +#define JZ_TIMER_CTRL_SRC_EXT BIT(2)
4275 +#define JZ_TIMER_CTRL_SRC_RTC BIT(1)
4276 +#define JZ_TIMER_CTRL_SRC_PCLK BIT(0)
4277 +
4278 +extern void __iomem *jz4740_timer_base;
4279 +void __init jz4740_timer_init(void);
4280 +
4281 +static inline void jz4740_timer_stop(unsigned int timer)
4282 +{
4283 + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET);
4284 +}
4285 +
4286 +static inline void jz4740_timer_start(unsigned int timer)
4287 +{
4288 + writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR);
4289 +}
4290 +
4291 +static inline bool jz4740_timer_is_enabled(unsigned int timer)
4292 +{
4293 + return readb(jz4740_timer_base + JZ_REG_TIMER_ENABLE) & BIT(timer);
4294 +}
4295 +
4296 +static inline void jz4740_timer_enable(unsigned int timer)
4297 +{
4298 + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_SET);
4299 +}
4300 +
4301 +static inline void jz4740_timer_disable(unsigned int timer)
4302 +{
4303 + writeb(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_ENABLE_CLEAR);
4304 +}
4305 +
4306 +
4307 +static inline void jz4740_timer_set_period(unsigned int timer, uint16_t period)
4308 +{
4309 + writew(period, jz4740_timer_base + JZ_REG_TIMER_DFR(timer));
4310 +}
4311 +
4312 +static inline void jz4740_timer_set_duty(unsigned int timer, uint16_t duty)
4313 +{
4314 + writew(duty, jz4740_timer_base + JZ_REG_TIMER_DHR(timer));
4315 +}
4316 +
4317 +static inline void jz4740_timer_set_count(unsigned int timer, uint16_t count)
4318 +{
4319 + writew(count, jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
4320 +}
4321 +
4322 +static inline uint16_t jz4740_timer_get_count(unsigned int timer)
4323 +{
4324 + return readw(jz4740_timer_base + JZ_REG_TIMER_CNT(timer));
4325 +}
4326 +
4327 +static inline void jz4740_timer_ack_full(unsigned int timer)
4328 +{
4329 + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
4330 +}
4331 +
4332 +static inline void jz4740_timer_irq_full_enable(unsigned int timer)
4333 +{
4334 + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR);
4335 + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR);
4336 +}
4337 +
4338 +static inline void jz4740_timer_irq_full_disable(unsigned int timer)
4339 +{
4340 + writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET);
4341 +}
4342 +
4343 +static inline void jz4740_timer_set_ctrl(unsigned int timer, uint16_t ctrl)
4344 +{
4345 + writew(ctrl, jz4740_timer_base + JZ_REG_TIMER_CTRL(timer));
4346 +}
4347 +
4348 +#endif
4349 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
4350 index be5bb16..926c260 100644
4351 --- a/arch/mips/kernel/cpu-probe.c
4352 +++ b/arch/mips/kernel/cpu-probe.c
4353 @@ -163,6 +163,7 @@ void __init check_wait(void)
4354 case CPU_BCM6358:
4355 case CPU_CAVIUM_OCTEON:
4356 case CPU_CAVIUM_OCTEON_PLUS:
4357 + case CPU_JZRISC:
4358 cpu_wait = r4k_wait;
4359 break;
4360
4361 @@ -932,6 +933,22 @@ platform:
4362 }
4363 }
4364
4365 +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
4366 +{
4367 + decode_configs(c);
4368 + /* JZRISC does not implement the CP0 counter. */
4369 + c->options &= ~MIPS_CPU_COUNTER;
4370 + switch (c->processor_id & 0xff00) {
4371 + case PRID_IMP_JZRISC:
4372 + c->cputype = CPU_JZRISC;
4373 + __cpu_name[cpu] = "Ingenic JZRISC";
4374 + break;
4375 + default:
4376 + panic("Unknown Ingenic Processor ID!");
4377 + break;
4378 + }
4379 +}
4380 +
4381 const char *__cpu_name[NR_CPUS];
4382 const char *__elf_platform;
4383
4384 @@ -970,6 +987,9 @@ __cpuinit void cpu_probe(void)
4385 case PRID_COMP_CAVIUM:
4386 cpu_probe_cavium(c, cpu);
4387 break;
4388 + case PRID_COMP_INGENIC:
4389 + cpu_probe_ingenic(c, cpu);
4390 + break;
4391 }
4392
4393 BUG_ON(!__cpu_name[cpu]);
4394 diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
4395 index 86f004d..4510e61 100644
4396 --- a/arch/mips/mm/tlbex.c
4397 +++ b/arch/mips/mm/tlbex.c
4398 @@ -409,6 +409,11 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
4399 tlbw(p);
4400 break;
4401
4402 + case CPU_JZRISC:
4403 + tlbw(p);
4404 + uasm_i_nop(p);
4405 + break;
4406 +
4407 default:
4408 panic("No TLB refill handler yet (CPU type: %d)",
4409 current_cpu_data.cputype);
4410 --
4411 1.5.6.5
4412
Personal OpenWRT clone
This page took 0.309404 seconds and 5 git commands to generate.