2 * Atheros AR71xx SoC platform devices
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
28 unsigned char ar71xx_mac_base
[ETH_ALEN
] __initdata
;
30 static struct resource ar71xx_uart_resources
[] = {
32 .start
= AR71XX_UART_BASE
,
33 .end
= AR71XX_UART_BASE
+ AR71XX_UART_SIZE
- 1,
34 .flags
= IORESOURCE_MEM
,
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data
[] = {
41 .mapbase
= AR71XX_UART_BASE
,
42 .irq
= AR71XX_MISC_IRQ_UART
,
43 .flags
= AR71XX_UART_FLAGS
,
47 /* terminating entry */
51 static struct platform_device ar71xx_uart_device
= {
53 .id
= PLAT8250_DEV_PLATFORM
,
54 .resource
= ar71xx_uart_resources
,
55 .num_resources
= ARRAY_SIZE(ar71xx_uart_resources
),
57 .platform_data
= ar71xx_uart_data
61 static struct resource ar933x_uart_resources
[] = {
63 .start
= AR933X_UART_BASE
,
64 .end
= AR933X_UART_BASE
+ AR71XX_UART_SIZE
- 1,
65 .flags
= IORESOURCE_MEM
,
68 .start
= AR71XX_MISC_IRQ_UART
,
69 .end
= AR71XX_MISC_IRQ_UART
,
70 .flags
= IORESOURCE_IRQ
,
74 static struct ar933x_uart_platform_data ar933x_uart_data
;
75 static struct platform_device ar933x_uart_device
= {
76 .name
= "ar933x-uart",
78 .resource
= ar933x_uart_resources
,
79 .num_resources
= ARRAY_SIZE(ar933x_uart_resources
),
81 .platform_data
= &ar933x_uart_data
,
85 void __init
ar71xx_add_device_uart(void)
87 struct platform_device
*pdev
;
90 case AR71XX_SOC_AR7130
:
91 case AR71XX_SOC_AR7141
:
92 case AR71XX_SOC_AR7161
:
93 case AR71XX_SOC_AR7240
:
94 case AR71XX_SOC_AR7241
:
95 case AR71XX_SOC_AR7242
:
96 case AR71XX_SOC_AR9130
:
97 case AR71XX_SOC_AR9132
:
98 pdev
= &ar71xx_uart_device
;
99 ar71xx_uart_data
[0].uartclk
= ar71xx_ahb_freq
;
102 case AR71XX_SOC_AR9330
:
103 case AR71XX_SOC_AR9331
:
104 pdev
= &ar933x_uart_device
;
105 ar933x_uart_data
.uartclk
= ar71xx_ref_freq
;
108 case AR71XX_SOC_AR9341
:
109 case AR71XX_SOC_AR9342
:
110 case AR71XX_SOC_AR9344
:
111 pdev
= &ar71xx_uart_device
;
112 ar71xx_uart_data
[0].uartclk
= ar71xx_ref_freq
;
119 platform_device_register(pdev
);
122 static struct resource ar71xx_mdio0_resources
[] = {
125 .flags
= IORESOURCE_MEM
,
126 .start
= AR71XX_GE0_BASE
,
127 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
131 static struct ag71xx_mdio_platform_data ar71xx_mdio0_data
;
133 struct platform_device ar71xx_mdio0_device
= {
134 .name
= "ag71xx-mdio",
136 .resource
= ar71xx_mdio0_resources
,
137 .num_resources
= ARRAY_SIZE(ar71xx_mdio0_resources
),
139 .platform_data
= &ar71xx_mdio0_data
,
143 static struct resource ar71xx_mdio1_resources
[] = {
146 .flags
= IORESOURCE_MEM
,
147 .start
= AR71XX_GE1_BASE
,
148 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
152 static struct ag71xx_mdio_platform_data ar71xx_mdio1_data
;
154 struct platform_device ar71xx_mdio1_device
= {
155 .name
= "ag71xx-mdio",
157 .resource
= ar71xx_mdio1_resources
,
158 .num_resources
= ARRAY_SIZE(ar71xx_mdio1_resources
),
160 .platform_data
= &ar71xx_mdio1_data
,
164 static void ar71xx_set_pll(u32 cfg_reg
, u32 pll_reg
, u32 pll_val
, u32 shift
)
169 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
171 t
= __raw_readl(base
+ cfg_reg
);
174 __raw_writel(t
, base
+ cfg_reg
);
177 __raw_writel(pll_val
, base
+ pll_reg
);
180 __raw_writel(t
, base
+ cfg_reg
);
184 __raw_writel(t
, base
+ cfg_reg
);
187 printk(KERN_DEBUG
"ar71xx: pll_reg %#x: %#x\n",
188 (unsigned int)(base
+ pll_reg
), __raw_readl(base
+ pll_reg
));
193 static void __init
ar71xx_mii_ctrl_set_if(unsigned int reg
,
199 base
= ioremap(AR71XX_MII_BASE
, AR71XX_MII_SIZE
);
201 t
= __raw_readl(base
+ reg
);
202 t
&= ~(MII_CTRL_IF_MASK
);
203 t
|= (mii_if
& MII_CTRL_IF_MASK
);
204 __raw_writel(t
, base
+ reg
);
209 void __init
ar71xx_add_device_mdio(unsigned int id
, u32 phy_mask
)
211 struct platform_device
*mdio_dev
;
212 struct ag71xx_mdio_platform_data
*mdio_data
;
215 if (ar71xx_soc
== AR71XX_SOC_AR9341
||
216 ar71xx_soc
== AR71XX_SOC_AR9342
||
217 ar71xx_soc
== AR71XX_SOC_AR9344
)
223 printk(KERN_ERR
"ar71xx: invalid MDIO id %u\n", id
);
227 switch (ar71xx_soc
) {
228 case AR71XX_SOC_AR7241
:
229 case AR71XX_SOC_AR9330
:
230 case AR71XX_SOC_AR9331
:
231 mdio_dev
= &ar71xx_mdio1_device
;
232 mdio_data
= &ar71xx_mdio1_data
;
235 case AR71XX_SOC_AR9341
:
236 case AR71XX_SOC_AR9342
:
237 case AR71XX_SOC_AR9344
:
239 mdio_dev
= &ar71xx_mdio0_device
;
240 mdio_data
= &ar71xx_mdio0_data
;
242 mdio_dev
= &ar71xx_mdio1_device
;
243 mdio_data
= &ar71xx_mdio1_data
;
247 case AR71XX_SOC_AR7242
:
248 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
,
249 AR7242_PLL_REG_ETH0_INT_CLOCK
, 0x62000000,
250 AR71XX_ETH0_PLL_SHIFT
);
253 mdio_dev
= &ar71xx_mdio0_device
;
254 mdio_data
= &ar71xx_mdio0_data
;
258 mdio_data
->phy_mask
= phy_mask
;
260 switch (ar71xx_soc
) {
261 case AR71XX_SOC_AR7240
:
262 case AR71XX_SOC_AR7241
:
263 case AR71XX_SOC_AR9330
:
264 case AR71XX_SOC_AR9331
:
265 mdio_data
->is_ar7240
= 1;
268 case AR71XX_SOC_AR9341
:
269 case AR71XX_SOC_AR9342
:
270 case AR71XX_SOC_AR9344
:
272 mdio_data
->is_ar7240
= 1;
279 platform_device_register(mdio_dev
);
282 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data
;
283 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data
;
285 static u32
ar71xx_get_eth_pll(unsigned int mac
, int speed
)
287 struct ar71xx_eth_pll_data
*pll_data
;
292 pll_data
= &ar71xx_eth0_pll_data
;
295 pll_data
= &ar71xx_eth1_pll_data
;
303 pll_val
= pll_data
->pll_10
;
306 pll_val
= pll_data
->pll_100
;
309 pll_val
= pll_data
->pll_1000
;
318 static void ar71xx_set_pll_ge0(int speed
)
320 u32 val
= ar71xx_get_eth_pll(0, speed
);
322 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH0_INT_CLOCK
,
323 val
, AR71XX_ETH0_PLL_SHIFT
);
326 static void ar71xx_set_pll_ge1(int speed
)
328 u32 val
= ar71xx_get_eth_pll(1, speed
);
330 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG
, AR71XX_PLL_REG_ETH1_INT_CLOCK
,
331 val
, AR71XX_ETH1_PLL_SHIFT
);
334 static void ar724x_set_pll_ge0(int speed
)
339 static void ar724x_set_pll_ge1(int speed
)
344 static void ar7242_set_pll_ge0(int speed
)
346 u32 val
= ar71xx_get_eth_pll(0, speed
);
349 base
= ioremap_nocache(AR71XX_PLL_BASE
, AR71XX_PLL_SIZE
);
350 __raw_writel(val
, base
+ AR7242_PLL_REG_ETH0_INT_CLOCK
);
354 static void ar91xx_set_pll_ge0(int speed
)
356 u32 val
= ar71xx_get_eth_pll(0, speed
);
358 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH0_INT_CLOCK
,
359 val
, AR91XX_ETH0_PLL_SHIFT
);
362 static void ar91xx_set_pll_ge1(int speed
)
364 u32 val
= ar71xx_get_eth_pll(1, speed
);
366 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG
, AR91XX_PLL_REG_ETH1_INT_CLOCK
,
367 val
, AR91XX_ETH1_PLL_SHIFT
);
370 static void ar933x_set_pll_ge0(int speed
)
375 static void ar933x_set_pll_ge1(int speed
)
380 static void ar934x_set_pll_ge0(int speed
)
385 static void ar934x_set_pll_ge1(int speed
)
390 static void ar71xx_ddr_flush_ge0(void)
392 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0
);
395 static void ar71xx_ddr_flush_ge1(void)
397 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1
);
400 static void ar724x_ddr_flush_ge0(void)
402 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0
);
405 static void ar724x_ddr_flush_ge1(void)
407 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1
);
410 static void ar91xx_ddr_flush_ge0(void)
412 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0
);
415 static void ar91xx_ddr_flush_ge1(void)
417 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1
);
420 static void ar933x_ddr_flush_ge0(void)
422 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0
);
425 static void ar933x_ddr_flush_ge1(void)
427 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1
);
430 static void ar934x_ddr_flush_ge0(void)
432 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0
);
435 static void ar934x_ddr_flush_ge1(void)
437 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1
);
440 static struct resource ar71xx_eth0_resources
[] = {
443 .flags
= IORESOURCE_MEM
,
444 .start
= AR71XX_GE0_BASE
,
445 .end
= AR71XX_GE0_BASE
+ 0x200 - 1,
448 .flags
= IORESOURCE_MEM
,
449 .start
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
,
450 .end
= AR71XX_MII_BASE
+ MII_REG_MII0_CTRL
+ 3,
453 .flags
= IORESOURCE_IRQ
,
454 .start
= AR71XX_CPU_IRQ_GE0
,
455 .end
= AR71XX_CPU_IRQ_GE0
,
459 struct ag71xx_platform_data ar71xx_eth0_data
= {
460 .reset_bit
= RESET_MODULE_GE0_MAC
,
463 struct platform_device ar71xx_eth0_device
= {
466 .resource
= ar71xx_eth0_resources
,
467 .num_resources
= ARRAY_SIZE(ar71xx_eth0_resources
),
469 .platform_data
= &ar71xx_eth0_data
,
473 static struct resource ar71xx_eth1_resources
[] = {
476 .flags
= IORESOURCE_MEM
,
477 .start
= AR71XX_GE1_BASE
,
478 .end
= AR71XX_GE1_BASE
+ 0x200 - 1,
481 .flags
= IORESOURCE_MEM
,
482 .start
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
,
483 .end
= AR71XX_MII_BASE
+ MII_REG_MII1_CTRL
+ 3,
486 .flags
= IORESOURCE_IRQ
,
487 .start
= AR71XX_CPU_IRQ_GE1
,
488 .end
= AR71XX_CPU_IRQ_GE1
,
492 struct ag71xx_platform_data ar71xx_eth1_data
= {
493 .reset_bit
= RESET_MODULE_GE1_MAC
,
496 struct platform_device ar71xx_eth1_device
= {
499 .resource
= ar71xx_eth1_resources
,
500 .num_resources
= ARRAY_SIZE(ar71xx_eth1_resources
),
502 .platform_data
= &ar71xx_eth1_data
,
506 #define AR71XX_PLL_VAL_1000 0x00110000
507 #define AR71XX_PLL_VAL_100 0x00001099
508 #define AR71XX_PLL_VAL_10 0x00991099
510 #define AR724X_PLL_VAL_1000 0x00110000
511 #define AR724X_PLL_VAL_100 0x00001099
512 #define AR724X_PLL_VAL_10 0x00991099
514 #define AR7242_PLL_VAL_1000 0x16000000
515 #define AR7242_PLL_VAL_100 0x00000101
516 #define AR7242_PLL_VAL_10 0x00001616
518 #define AR91XX_PLL_VAL_1000 0x1a000000
519 #define AR91XX_PLL_VAL_100 0x13000a44
520 #define AR91XX_PLL_VAL_10 0x00441099
522 #define AR933X_PLL_VAL_1000 0x00110000
523 #define AR933X_PLL_VAL_100 0x00001099
524 #define AR933X_PLL_VAL_10 0x00991099
526 #define AR934X_PLL_VAL_1000 0x00110000
527 #define AR934X_PLL_VAL_100 0x00001099
528 #define AR934X_PLL_VAL_10 0x00991099
530 static void __init
ar71xx_init_eth_pll_data(unsigned int id
)
532 struct ar71xx_eth_pll_data
*pll_data
;
533 u32 pll_10
, pll_100
, pll_1000
;
537 pll_data
= &ar71xx_eth0_pll_data
;
540 pll_data
= &ar71xx_eth1_pll_data
;
546 switch (ar71xx_soc
) {
547 case AR71XX_SOC_AR7130
:
548 case AR71XX_SOC_AR7141
:
549 case AR71XX_SOC_AR7161
:
550 pll_10
= AR71XX_PLL_VAL_10
;
551 pll_100
= AR71XX_PLL_VAL_100
;
552 pll_1000
= AR71XX_PLL_VAL_1000
;
555 case AR71XX_SOC_AR7240
:
556 case AR71XX_SOC_AR7241
:
557 pll_10
= AR724X_PLL_VAL_10
;
558 pll_100
= AR724X_PLL_VAL_100
;
559 pll_1000
= AR724X_PLL_VAL_1000
;
562 case AR71XX_SOC_AR7242
:
563 pll_10
= AR7242_PLL_VAL_10
;
564 pll_100
= AR7242_PLL_VAL_100
;
565 pll_1000
= AR7242_PLL_VAL_1000
;
568 case AR71XX_SOC_AR9130
:
569 case AR71XX_SOC_AR9132
:
570 pll_10
= AR91XX_PLL_VAL_10
;
571 pll_100
= AR91XX_PLL_VAL_100
;
572 pll_1000
= AR91XX_PLL_VAL_1000
;
575 case AR71XX_SOC_AR9330
:
576 case AR71XX_SOC_AR9331
:
577 pll_10
= AR933X_PLL_VAL_10
;
578 pll_100
= AR933X_PLL_VAL_100
;
579 pll_1000
= AR933X_PLL_VAL_1000
;
582 case AR71XX_SOC_AR9341
:
583 case AR71XX_SOC_AR9342
:
584 case AR71XX_SOC_AR9344
:
585 pll_10
= AR934X_PLL_VAL_10
;
586 pll_100
= AR934X_PLL_VAL_100
;
587 pll_1000
= AR934X_PLL_VAL_1000
;
594 if (!pll_data
->pll_10
)
595 pll_data
->pll_10
= pll_10
;
597 if (!pll_data
->pll_100
)
598 pll_data
->pll_100
= pll_100
;
600 if (!pll_data
->pll_1000
)
601 pll_data
->pll_1000
= pll_1000
;
604 static int __init
ar71xx_setup_phy_if_mode(unsigned int id
,
605 struct ag71xx_platform_data
*pdata
)
611 switch (ar71xx_soc
) {
612 case AR71XX_SOC_AR7130
:
613 case AR71XX_SOC_AR7141
:
614 case AR71XX_SOC_AR7161
:
615 case AR71XX_SOC_AR9130
:
616 case AR71XX_SOC_AR9132
:
617 switch (pdata
->phy_if_mode
) {
618 case PHY_INTERFACE_MODE_MII
:
619 mii_if
= MII0_CTRL_IF_MII
;
621 case PHY_INTERFACE_MODE_GMII
:
622 mii_if
= MII0_CTRL_IF_GMII
;
624 case PHY_INTERFACE_MODE_RGMII
:
625 mii_if
= MII0_CTRL_IF_RGMII
;
627 case PHY_INTERFACE_MODE_RMII
:
628 mii_if
= MII0_CTRL_IF_RMII
;
633 ar71xx_mii_ctrl_set_if(MII_REG_MII0_CTRL
, mii_if
);
636 case AR71XX_SOC_AR7240
:
637 case AR71XX_SOC_AR7241
:
638 case AR71XX_SOC_AR9330
:
639 case AR71XX_SOC_AR9331
:
640 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_MII
;
643 case AR71XX_SOC_AR7242
:
646 case AR71XX_SOC_AR9341
:
647 case AR71XX_SOC_AR9342
:
648 case AR71XX_SOC_AR9344
:
649 switch (pdata
->phy_if_mode
) {
650 case PHY_INTERFACE_MODE_MII
:
651 case PHY_INTERFACE_MODE_GMII
:
652 case PHY_INTERFACE_MODE_RGMII
:
653 case PHY_INTERFACE_MODE_RMII
:
665 switch (ar71xx_soc
) {
666 case AR71XX_SOC_AR7130
:
667 case AR71XX_SOC_AR7141
:
668 case AR71XX_SOC_AR7161
:
669 case AR71XX_SOC_AR9130
:
670 case AR71XX_SOC_AR9132
:
671 switch (pdata
->phy_if_mode
) {
672 case PHY_INTERFACE_MODE_RMII
:
673 mii_if
= MII1_CTRL_IF_RMII
;
675 case PHY_INTERFACE_MODE_RGMII
:
676 mii_if
= MII1_CTRL_IF_RGMII
;
681 ar71xx_mii_ctrl_set_if(MII_REG_MII1_CTRL
, mii_if
);
684 case AR71XX_SOC_AR7240
:
685 case AR71XX_SOC_AR7241
:
686 case AR71XX_SOC_AR9330
:
687 case AR71XX_SOC_AR9331
:
688 pdata
->phy_if_mode
= PHY_INTERFACE_MODE_GMII
;
691 case AR71XX_SOC_AR7242
:
694 case AR71XX_SOC_AR9341
:
695 case AR71XX_SOC_AR9342
:
696 case AR71XX_SOC_AR9344
:
697 switch (pdata
->phy_if_mode
) {
698 case PHY_INTERFACE_MODE_MII
:
699 case PHY_INTERFACE_MODE_GMII
:
715 static int ar71xx_eth_instance __initdata
;
716 void __init
ar71xx_add_device_eth(unsigned int id
)
718 struct platform_device
*pdev
;
719 struct ag71xx_platform_data
*pdata
;
723 printk(KERN_ERR
"ar71xx: invalid ethernet id %d\n", id
);
727 ar71xx_init_eth_pll_data(id
);
730 pdev
= &ar71xx_eth0_device
;
732 pdev
= &ar71xx_eth1_device
;
734 pdata
= pdev
->dev
.platform_data
;
736 err
= ar71xx_setup_phy_if_mode(id
, pdata
);
739 "ar71xx: invalid PHY interface mode for GE%u\n", id
);
743 switch (ar71xx_soc
) {
744 case AR71XX_SOC_AR7130
:
745 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
746 : ar71xx_ddr_flush_ge0
;
747 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
748 : ar71xx_set_pll_ge0
;
751 case AR71XX_SOC_AR7141
:
752 case AR71XX_SOC_AR7161
:
753 pdata
->ddr_flush
= id
? ar71xx_ddr_flush_ge1
754 : ar71xx_ddr_flush_ge0
;
755 pdata
->set_pll
= id
? ar71xx_set_pll_ge1
756 : ar71xx_set_pll_ge0
;
760 case AR71XX_SOC_AR7242
:
761 ar71xx_eth0_data
.reset_bit
|= AR724X_RESET_GE0_MDIO
|
762 RESET_MODULE_GE0_PHY
;
763 ar71xx_eth1_data
.reset_bit
|= AR724X_RESET_GE1_MDIO
|
764 RESET_MODULE_GE1_PHY
;
765 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
766 : ar724x_ddr_flush_ge0
;
767 pdata
->set_pll
= id
? ar724x_set_pll_ge1
768 : ar7242_set_pll_ge0
;
770 pdata
->is_ar724x
= 1;
772 if (!pdata
->fifo_cfg1
)
773 pdata
->fifo_cfg1
= 0x0010ffff;
774 if (!pdata
->fifo_cfg2
)
775 pdata
->fifo_cfg2
= 0x015500aa;
776 if (!pdata
->fifo_cfg3
)
777 pdata
->fifo_cfg3
= 0x01f00140;
780 case AR71XX_SOC_AR7241
:
781 ar71xx_eth0_data
.reset_bit
|= AR724X_RESET_GE0_MDIO
;
782 ar71xx_eth1_data
.reset_bit
|= AR724X_RESET_GE1_MDIO
;
784 case AR71XX_SOC_AR7240
:
785 ar71xx_eth0_data
.reset_bit
|= RESET_MODULE_GE0_PHY
;
786 ar71xx_eth1_data
.reset_bit
|= RESET_MODULE_GE1_PHY
;
787 pdata
->ddr_flush
= id
? ar724x_ddr_flush_ge1
788 : ar724x_ddr_flush_ge0
;
789 pdata
->set_pll
= id
? ar724x_set_pll_ge1
790 : ar724x_set_pll_ge0
;
791 pdata
->is_ar724x
= 1;
792 if (ar71xx_soc
== AR71XX_SOC_AR7240
)
793 pdata
->is_ar7240
= 1;
795 if (!pdata
->fifo_cfg1
)
796 pdata
->fifo_cfg1
= 0x0010ffff;
797 if (!pdata
->fifo_cfg2
)
798 pdata
->fifo_cfg2
= 0x015500aa;
799 if (!pdata
->fifo_cfg3
)
800 pdata
->fifo_cfg3
= 0x01f00140;
803 case AR71XX_SOC_AR9130
:
804 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
805 : ar91xx_ddr_flush_ge0
;
806 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
807 : ar91xx_set_pll_ge0
;
808 pdata
->is_ar91xx
= 1;
811 case AR71XX_SOC_AR9132
:
812 pdata
->ddr_flush
= id
? ar91xx_ddr_flush_ge1
813 : ar91xx_ddr_flush_ge0
;
814 pdata
->set_pll
= id
? ar91xx_set_pll_ge1
815 : ar91xx_set_pll_ge0
;
816 pdata
->is_ar91xx
= 1;
820 case AR71XX_SOC_AR9330
:
821 case AR71XX_SOC_AR9331
:
822 ar71xx_eth0_data
.reset_bit
= AR933X_RESET_GE0_MAC
|
823 AR933X_RESET_GE0_MDIO
;
824 ar71xx_eth1_data
.reset_bit
= AR933X_RESET_GE1_MAC
|
825 AR933X_RESET_GE1_MDIO
;
826 pdata
->ddr_flush
= id
? ar933x_ddr_flush_ge1
827 : ar933x_ddr_flush_ge0
;
828 pdata
->set_pll
= id
? ar933x_set_pll_ge1
829 : ar933x_set_pll_ge0
;
831 pdata
->is_ar724x
= 1;
833 if (!pdata
->fifo_cfg1
)
834 pdata
->fifo_cfg1
= 0x0010ffff;
835 if (!pdata
->fifo_cfg2
)
836 pdata
->fifo_cfg2
= 0x015500aa;
837 if (!pdata
->fifo_cfg3
)
838 pdata
->fifo_cfg3
= 0x01f00140;
841 case AR71XX_SOC_AR9341
:
842 case AR71XX_SOC_AR9342
:
843 case AR71XX_SOC_AR9344
:
844 ar71xx_eth0_data
.reset_bit
= AR934X_RESET_GE0_MAC
|
845 AR934X_RESET_GE0_MDIO
;
846 ar71xx_eth1_data
.reset_bit
= AR934X_RESET_GE1_MAC
|
847 AR934X_RESET_GE1_MDIO
;
848 pdata
->ddr_flush
= id
? ar934x_ddr_flush_ge1
849 : ar934x_ddr_flush_ge0
;
850 pdata
->set_pll
= id
? ar934x_set_pll_ge1
851 : ar934x_set_pll_ge0
;
853 pdata
->is_ar724x
= 1;
855 if (!pdata
->fifo_cfg1
)
856 pdata
->fifo_cfg1
= 0x0010ffff;
857 if (!pdata
->fifo_cfg2
)
858 pdata
->fifo_cfg2
= 0x015500aa;
859 if (!pdata
->fifo_cfg3
)
860 pdata
->fifo_cfg3
= 0x01f00140;
867 switch (pdata
->phy_if_mode
) {
868 case PHY_INTERFACE_MODE_GMII
:
869 case PHY_INTERFACE_MODE_RGMII
:
870 if (!pdata
->has_gbit
) {
871 printk(KERN_ERR
"ar71xx: no gbit available on eth%d\n",
880 if (!is_valid_ether_addr(pdata
->mac_addr
)) {
881 random_ether_addr(pdata
->mac_addr
);
883 "ar71xx: using random MAC address for eth%d\n",
884 ar71xx_eth_instance
);
887 if (pdata
->mii_bus_dev
== NULL
) {
888 switch (ar71xx_soc
) {
889 case AR71XX_SOC_AR9341
:
890 case AR71XX_SOC_AR9342
:
891 case AR71XX_SOC_AR9344
:
893 pdata
->mii_bus_dev
= &ar71xx_mdio0_device
.dev
;
895 pdata
->mii_bus_dev
= &ar71xx_mdio1_device
.dev
;
898 case AR71XX_SOC_AR7241
:
899 case AR71XX_SOC_AR9330
:
900 case AR71XX_SOC_AR9331
:
901 pdata
->mii_bus_dev
= &ar71xx_mdio1_device
.dev
;
905 pdata
->mii_bus_dev
= &ar71xx_mdio0_device
.dev
;
910 /* Reset the device */
911 ar71xx_device_stop(pdata
->reset_bit
);
914 ar71xx_device_start(pdata
->reset_bit
);
917 platform_device_register(pdev
);
918 ar71xx_eth_instance
++;
921 static struct resource ar71xx_spi_resources
[] = {
923 .start
= AR71XX_SPI_BASE
,
924 .end
= AR71XX_SPI_BASE
+ AR71XX_SPI_SIZE
- 1,
925 .flags
= IORESOURCE_MEM
,
929 static struct platform_device ar71xx_spi_device
= {
930 .name
= "ar71xx-spi",
932 .resource
= ar71xx_spi_resources
,
933 .num_resources
= ARRAY_SIZE(ar71xx_spi_resources
),
936 void __init
ar71xx_add_device_spi(struct ar71xx_spi_platform_data
*pdata
,
937 struct spi_board_info
const *info
,
940 spi_register_board_info(info
, n
);
941 ar71xx_spi_device
.dev
.platform_data
= pdata
;
942 platform_device_register(&ar71xx_spi_device
);
945 void __init
ar71xx_add_device_wdt(void)
947 platform_device_register_simple("ar71xx-wdt", -1, NULL
, 0);
950 void __init
ar71xx_set_mac_base(unsigned char *mac
)
952 memcpy(ar71xx_mac_base
, mac
, ETH_ALEN
);
955 void __init
ar71xx_parse_mac_addr(char *mac_str
)
960 t
= sscanf(mac_str
, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
961 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
964 t
= sscanf(mac_str
, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
965 &tmp
[0], &tmp
[1], &tmp
[2], &tmp
[3], &tmp
[4], &tmp
[5]);
968 ar71xx_set_mac_base(tmp
);
970 printk(KERN_DEBUG
"ar71xx: failed to parse mac address "
971 "\"%s\"\n", mac_str
);
974 static int __init
ar71xx_ethaddr_setup(char *str
)
976 ar71xx_parse_mac_addr(str
);
979 __setup("ethaddr=", ar71xx_ethaddr_setup
);
981 static int __init
ar71xx_kmac_setup(char *str
)
983 ar71xx_parse_mac_addr(str
);
986 __setup("kmac=", ar71xx_kmac_setup
);
988 void __init
ar71xx_init_mac(unsigned char *dst
, const unsigned char *src
,
993 if (!is_valid_ether_addr(src
)) {
994 memset(dst
, '\0', ETH_ALEN
);
998 t
= (((u32
) src
[3]) << 16) + (((u32
) src
[4]) << 8) + ((u32
) src
[5]);
1004 dst
[3] = (t
>> 16) & 0xff;
1005 dst
[4] = (t
>> 8) & 0xff;