target/linux/brcm47xx-2.6/patches/130-remove_scache.patch

   1 diff -urN linux-2.6.19.ref/arch/mips/Kconfig linux-2.6.19/arch/mips/Kconfig
   2 --- linux-2.6.19.ref/arch/mips/Kconfig  2006-12-04 21:33:48.000000000 +0100
   3 +++ linux-2.6.19/arch/mips/Kconfig      2006-12-04 21:34:04.000000000 +0100
   4 @@ -283,7 +283,6 @@
   5         select I8259
   6         select MIPS_BOARDS_GEN
   7         select MIPS_BONITO64
   8 -       select MIPS_CPU_SCACHE
   9         select MIPS_GT64120
  10         select MIPS_MSC
  11         select SWAP_IO_SPACE
  12 @@ -1434,13 +1433,6 @@
  13         bool
  14         select BOARD_SCACHE
  15
  16 -#
  17 -# Support for a MIPS32 / MIPS64 style S-caches
  18 -#
  19 -config MIPS_CPU_SCACHE
  20 -       bool
  21 -       select BOARD_SCACHE
  22 -
  23  config R5000_CPU_SCACHE
  24         bool
  25         select BOARD_SCACHE
  26 diff -urN linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c linux-2.6.19/arch/mips/kernel/cpu-probe.c
  27 --- linux-2.6.19.ref/arch/mips/kernel/cpu-probe.c       2006-12-04 21:33:48.000000000 +0100
  28 +++ linux-2.6.19/arch/mips/kernel/cpu-probe.c   2006-12-04 21:34:04.000000000 +0100
  29 @@ -631,6 +631,8 @@
  30                 break;
  31         case PRID_IMP_25KF:
  32                 c->cputype = CPU_25KF;
  33 +               /* Probe for L2 cache */
  34 +               c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  35                 break;
  36         case PRID_IMP_34K:
  37                 c->cputype = CPU_34K;
  38 diff -urN linux-2.6.19.ref/arch/mips/mm/c-r4k.c linux-2.6.19/arch/mips/mm/c-r4k.c
  39 --- linux-2.6.19.ref/arch/mips/mm/c-r4k.c       2006-11-29 22:57:37.000000000 +0100
  40 +++ linux-2.6.19/arch/mips/mm/c-r4k.c   2006-12-04 21:34:04.000000000 +0100
  41 @@ -1038,7 +1038,6 @@
  42
  43  extern int r5k_sc_init(void);
  44  extern int rm7k_sc_init(void);
  45 -extern int mips_sc_init(void);
  46
  47  static void __init setup_scache(void)
  48  {
  49 @@ -1086,29 +1085,17 @@
  50                 return;
  51
  52         default:
  53 -               if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
  54 -                   c->isa_level == MIPS_CPU_ISA_M32R2 ||
  55 -                   c->isa_level == MIPS_CPU_ISA_M64R1 ||
  56 -                   c->isa_level == MIPS_CPU_ISA_M64R2) {
  57 -#ifdef CONFIG_MIPS_CPU_SCACHE
  58 -                       if (mips_sc_init ()) {
  59 -                               scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
  60 -                               printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
  61 -                                      scache_size >> 10,
  62 -                                      way_string[c->scache.ways], c->scache.linesz);
  63 -                       }
  64 -#else
  65 -                       if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  66 -                               panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  67 -#endif
  68 -                       return;
  69 -               }
  70                 sc_present = 0;
  71         }
  72
  73         if (!sc_present)
  74                 return;
  75
  76 +       if ((c->isa_level == MIPS_CPU_ISA_M32R1 ||
  77 +            c->isa_level == MIPS_CPU_ISA_M64R1) &&
  78 +           !(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
  79 +               panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
  80 +
  81         /* compute a couple of other cache variables */
  82         c->scache.waysize = scache_size / c->scache.ways;
  83
  84 diff -urN linux-2.6.19.ref/arch/mips/mm/Makefile linux-2.6.19/arch/mips/mm/Makefile
  85 --- linux-2.6.19.ref/arch/mips/mm/Makefile      2006-11-29 22:57:37.000000000 +0100
  86 +++ linux-2.6.19/arch/mips/mm/Makefile  2006-12-04 21:34:04.000000000 +0100
  87 @@ -30,7 +30,6 @@
  88  obj-$(CONFIG_IP22_CPU_SCACHE)  += sc-ip22.o
  89  obj-$(CONFIG_R5000_CPU_SCACHE)  += sc-r5k.o
  90  obj-$(CONFIG_RM7000_CPU_SCACHE)        += sc-rm7k.o
  91 -obj-$(CONFIG_MIPS_CPU_SCACHE)  += sc-mips.o
  92
  93  #
  94  # Choose one DMA coherency model