target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 /*
   2  *  Ralink RT288x SoC PCI register definitions
   3  *
   4  *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
   5  *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  *  Parts of this file are based on Ralink's 2.6.21 BSP
   8  *
   9  *  This program is free software; you can redistribute it and/or modify it
  10  *  under the terms of the GNU General Public License version 2 as published
  11  *  by the Free Software Foundation.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/pci.h>
  16 #include <linux/io.h>
  17 #include <linux/init.h>
  18
  19 #include <asm/mach-ralink/rt288x.h>
  20 #include <asm/mach-ralink/rt288x_regs.h>
  21
  22 #define RT2880_PCI_MEM_BASE     0x20000000
  23 #define RT2880_PCI_MEM_SIZE     0x10000000
  24 #define RT2880_PCI_IO_BASE      0x00460000
  25 #define RT2880_PCI_IO_SIZE      0x00010000
  26
  27 #define RT2880_PCI_REG_PCICFG_ADDR      0x00
  28 #define RT2880_PCI_REG_PCIMSK_ADDR      0x0c
  29 #define RT2880_PCI_REG_BAR0SETUP_ADDR   0x10
  30 #define RT2880_PCI_REG_IMBASEBAR0_ADDR  0x18
  31 #define RT2880_PCI_REG_CONFIG_ADDR      0x20
  32 #define RT2880_PCI_REG_CONFIG_DATA      0x24
  33 #define RT2880_PCI_REG_MEMBASE          0x28
  34 #define RT2880_PCI_REG_IOBASE           0x2c
  35 #define RT2880_PCI_REG_ID               0x30
  36 #define RT2880_PCI_REG_CLASS            0x34
  37 #define RT2880_PCI_REG_SUBID            0x38
  38 #define RT2880_PCI_REG_ARBCTL           0x80
  39
  40 #define PCI_ACCESS_READ  0
  41 #define PCI_ACCESS_WRITE 1
  42
  43 static void __iomem *rt2880_pci_base;
  44 static DEFINE_SPINLOCK(rt2880_pci_lock);
  45
  46 static u32 rt2880_pci_reg_read(u32 reg)
  47 {
  48         return readl(rt2880_pci_base + reg);
  49 }
  50
  51 static void rt2880_pci_reg_write(u32 val, u32 reg)
  52 {
  53         writel(val, rt2880_pci_base + reg);
  54 }
  55
  56 static void config_access(unsigned char access_type, struct pci_bus *bus,
  57                           unsigned int devfn, unsigned char where, u32 *data)
  58 {
  59         unsigned int slot = PCI_SLOT(devfn);
  60         unsigned int address;
  61         u8 func = PCI_FUNC(devfn);
  62
  63         address = (bus->number << 16) | (slot << 11) | (func << 8) |
  64                   (where & 0xfc) | 0x80000000;
  65
  66         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
  67         if (access_type == PCI_ACCESS_WRITE)
  68                 rt2880_pci_reg_write(*data, RT2880_PCI_REG_CONFIG_DATA);
  69         else
  70                 *data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
  71 }
  72
  73 static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
  74                                   int where, int size, u32 *val)
  75 {
  76         unsigned long flags;
  77         u32 data = 0;
  78
  79         spin_lock_irqsave(&rt2880_pci_lock, flags);
  80         config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
  81         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
  82
  83         if (size == 1)
  84                 *val = (data >> ((where & 3) << 3)) & 0xff;
  85         else if (size == 2)
  86                 *val = (data >> ((where & 3) << 3)) & 0xffff;
  87         else
  88                 *val = data;
  89
  90         return PCIBIOS_SUCCESSFUL;
  91 }
  92
  93 static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
  94                                    int where, int size, u32 val)
  95 {
  96         unsigned long flags;
  97         u32 data = 0;
  98
  99         spin_lock_irqsave(&rt2880_pci_lock, flags);
 100         if (size == 4) {
 101                 data = val;
 102         } else {
 103                 config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 104                 if (size == 1)
 105                         data = (data & ~(0xff << ((where & 3) << 3))) |
 106                                (val << ((where & 3) << 3));
 107                 else if (size == 2)
 108                         data = (data & ~(0xffff << ((where & 3) << 3))) |
 109                                (val << ((where & 3) << 3));
 110         }
 111
 112         config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data);
 113         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 114
 115         return PCIBIOS_SUCCESSFUL;
 116 }
 117
 118 static struct pci_ops rt2880_pci_ops = {
 119         .read   = rt2880_pci_config_read,
 120         .write  = rt2880_pci_config_write,
 121 };
 122
 123 static struct resource rt2880_pci_io_resource = {
 124         .name   = "PCI MEM space",
 125         .start  = RT2880_PCI_MEM_BASE,
 126         .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
 127         .flags  = IORESOURCE_MEM,
 128 };
 129
 130 static struct resource rt2880_pci_mem_resource = {
 131         .name   = "PCI IO space",
 132         .start  = RT2880_PCI_IO_BASE,
 133         .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
 134         .flags  = IORESOURCE_IO,
 135 };
 136
 137 static struct pci_controller rt2880_pci_controller = {
 138         .pci_ops        = &rt2880_pci_ops,
 139         .mem_resource   = &rt2880_pci_io_resource,
 140         .io_resource    = &rt2880_pci_mem_resource,
 141 };
 142
 143 static inline void read_config(unsigned long bus, unsigned long dev,
 144                                unsigned long func, unsigned long reg,
 145                                unsigned long *val)
 146 {
 147         unsigned long address;
 148         unsigned long flags;
 149
 150         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 151                   0x80000000;
 152
 153         spin_lock_irqsave(&rt2880_pci_lock, flags);
 154         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 155         *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 156         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 157 }
 158
 159 static inline void write_config(unsigned long bus, unsigned long dev,
 160                                 unsigned long func, unsigned long reg,
 161                                 unsigned long val)
 162 {
 163         unsigned long address;
 164         unsigned long flags;
 165
 166         address = (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) |
 167                   0x80000000;
 168
 169         spin_lock_irqsave(&rt2880_pci_lock, flags);
 170         rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
 171         rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
 172         spin_unlock_irqrestore(&rt2880_pci_lock, flags);
 173 }
 174
 175 int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 176 {
 177         u16 cmd;
 178         unsigned long val;
 179         int irq = -1;
 180
 181         if (dev->bus->number != 0)
 182                 return 0;
 183
 184         switch (PCI_SLOT(dev->devfn)) {
 185         case 0x00:
 186                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 187                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 188                 break;
 189         case 0x11:
 190                 irq = RT288X_CPU_IRQ_PCI;
 191                 break;
 192         default:
 193                 printk("%s:%s[%d] trying to alloc unknown pci irq\n",
 194                        __FILE__, __func__, __LINE__);
 195                 BUG();
 196                 break;
 197         }
 198
 199         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
 200         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
 201         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
 202         cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
 203                PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
 204                PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
 205         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
 206         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
 207                               dev->irq);
 208         return irq;
 209 }
 210
 211 static int __init rt2880_pci_init(void)
 212 {
 213         unsigned long val = 0;
 214         int i;
 215
 216         rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
 217
 218         rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
 219         for(i = 0; i < 0xfffff; i++) {}
 220
 221         rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
 222         rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
 223         rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
 224         rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
 225         rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
 226         rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
 227         rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
 228         rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
 229         rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
 230         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 231         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 232
 233         register_pci_controller(&rt2880_pci_controller);
 234         return 0;
 235 }
 236
 237 int pcibios_plat_dev_init(struct pci_dev *dev)
 238 {
 239         return 0;
 240 }
 241
 242 struct pci_fixup pcibios_fixups[] = {
 243         {0}
 244 };
 245
 246 arch_initcall(rt2880_pci_init);