projects / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
revert the module exports patch on 2.6.28 until it is fixed
[openwrt.git] / target / linux / ppc40x / patches / 006-magicboxv2.patch
1 --- /dev/null
2 +++ b/arch/powerpc/boot/cuboot-magicboxv2.c
3 @@ -0,0 +1,69 @@
4 +/*
5 + * Old U-boot compatibility for Magicbox v2
6 + *
7 + * Author: Imre Kaloz <kaloz@openwrt.org>
8 + * Gabor Juhos <juhosg@openwrt.org>
9 + *
10 + * This program is free software; you can redistribute it and/or modify it
11 + * under the terms of the GNU General Public License version 2 as published
12 + * by the Free Software Foundation.
13 + */
14 +
15 +#include "ops.h"
16 +#include "io.h"
17 +#include "dcr.h"
18 +#include "stdio.h"
19 +#include "4xx.h"
20 +#include "44x.h"
21 +#include "cuboot.h"
22 +
23 +#define TARGET_4xx
24 +#define TARGET_405EP
25 +#include "ppcboot.h"
26 +
27 +static bd_t bd;
28 +
29 +static void fixup_cf_card(void)
30 +{
31 +#define DCRN_CPC0_PCI_BASE 0xf9
32 +#define CF_CS0_BASE 0xff100000
33 +#define CF_CS1_BASE 0xff200000
34 +
35 + /* Turn on PerWE instead of PCIsomething */
36 + mtdcr(DCRN_CPC0_PCI_BASE,
37 + mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
38 +
39 + /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
40 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
41 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
42 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
43 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
44 +
45 + /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
46 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
47 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
48 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
49 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
50 +
51 +#undef DCRN_CPC0_PCI_BASE
52 +#undef CF_CS0_BASE
53 +#undef CF_CS1_BASE
54 +}
55 +
56 +static void magicboxv2_fixups(void)
57 +{
58 + fixup_cf_card();
59 + ibm405ep_fixup_clocks(25000000);
60 + ibm4xx_sdram_fixup_memsize();
61 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
62 +}
63 +
64 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
65 + unsigned long r6, unsigned long r7)
66 +{
67 + CUBOOT_INIT();
68 + platform_ops.fixups = magicboxv2_fixups;
69 + platform_ops.exit = ibm40x_dbcr_reset;
70 + fdt_init(_dtb_start);
71 + serial_console_init();
72 +}
73 --- /dev/null
74 +++ b/arch/powerpc/boot/dts/magicboxv2.dts
75 @@ -0,0 +1,281 @@
76 +/*
77 + * Device Tree Source for Magicbox v2
78 + *
79 + * Copyright 2008 Imre Kaloz <kaloz@openwrt.org>
80 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
81 + *
82 + * Based on walnut.dts
83 + *
84 + * This file is licensed under the terms of the GNU General Public
85 + * License version 2. This program is licensed "as is" without
86 + * any warranty of any kind, whether express or implied.
87 + */
88 +
89 +/dts-v1/;
90 +
91 +/ {
92 + #address-cells = <1>;
93 + #size-cells = <1>;
94 + model = "magicboxv2";
95 + compatible = "magicboxv2";
96 + dcr-parent = <&{/cpus/cpu@0}>;
97 +
98 + aliases {
99 + ethernet0 = &EMAC0;
100 + ethernet1 = &EMAC1;
101 + serial0 = &UART0;
102 + serial1 = &UART1;
103 + };
104 +
105 + cpus {
106 + #address-cells = <1>;
107 + #size-cells = <0>;
108 +
109 + cpu@0 {
110 + device_type = "cpu";
111 + model = "PowerPC,405EP";
112 + reg = <0x00000000>;
113 + clock-frequency = <0xbebc200>; /* Filled in by zImage */
114 + timebase-frequency = <0>; /* Filled in by zImage */
115 + i-cache-line-size = <20>;
116 + d-cache-line-size = <20>;
117 + i-cache-size = <4000>;
118 + d-cache-size = <4000>;
119 + dcr-controller;
120 + dcr-access-method = "native";
121 + };
122 + };
123 +
124 + memory {
125 + device_type = "memory";
126 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
127 + };
128 +
129 + UIC0: interrupt-controller {
130 + compatible = "ibm,uic";
131 + interrupt-controller;
132 + cell-index = <0>;
133 + dcr-reg = <0x0c0 0x009>;
134 + #address-cells = <0>;
135 + #size-cells = <0>;
136 + #interrupt-cells = <2>;
137 + };
138 +
139 + plb {
140 + compatible = "ibm,plb3";
141 + #address-cells = <1>;
142 + #size-cells = <1>;
143 + ranges;
144 + clock-frequency = <0>; /* Filled in by zImage */
145 +
146 + SDRAM0: memory-controller {
147 + compatible = "ibm,sdram-405ep";
148 + dcr-reg = <0x010 0x002>;
149 + };
150 +
151 + MAL: mcmal {
152 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
153 + dcr-reg = <0x180 0x062>;
154 + num-tx-chans = <4>;
155 + num-rx-chans = <2>;
156 + interrupt-parent = <&UIC0>;
157 + interrupts = <
158 + 0xb 0x4 /* TXEOB */
159 + 0xc 0x4 /* RXEOB */
160 + 0xa 0x4 /* SERR */
161 + 0xd 0x4 /* TXDE */
162 + 0xe 0x4 /* RXDE */>;
163 + };
164 +
165 + POB0: opb {
166 + compatible = "ibm,opb-405ep", "ibm,opb";
167 + #address-cells = <1>;
168 + #size-cells = <1>;
169 + ranges = <0xef600000 0xef600000 0x00a00000>;
170 + dcr-reg = <0x0a0 0x005>;
171 + clock-frequency = <0>; /* Filled in by zImage */
172 +
173 + UART0: serial@ef600300 {
174 + device_type = "serial";
175 + compatible = "ns16550";
176 + reg = <0xef600300 0x00000008>;
177 + virtual-reg = <0xef600300>;
178 + clock-frequency = <0>; /* Filled in by zImage */
179 + current-speed = <115200>;
180 + interrupt-parent = <&UIC0>;
181 + interrupts = <0x0 0x4>;
182 + };
183 +
184 + UART1: serial@ef600400 {
185 + device_type = "serial";
186 + compatible = "ns16550";
187 + reg = <0xef600400 0x00000008>;
188 + virtual-reg = <0xef600400>;
189 + clock-frequency = <0>; /* Filled in by zImage */
190 + current-speed = <115200>;
191 + interrupt-parent = <&UIC0>;
192 + interrupts = <0x1 0x4>;
193 + };
194 +
195 + IIC: i2c@ef600500 {
196 + compatible = "ibm,iic-405ep", "ibm,iic";
197 + #address-cells = <1>;
198 + #size-cells = <0>;
199 + reg = <0xef600500 0x00000011>;
200 + interrupt-parent = <&UIC0>;
201 + interrupts = <0x2 0x4>;
202 +
203 + dtt@48 {
204 + compatible = "national,lm75";
205 + reg = <0x48>;
206 + };
207 +
208 + eeprom@50 {
209 + compatible = "at24,24c16";
210 + reg = <0x50>;
211 + };
212 + };
213 +
214 + GPIO0: gpio-controller@ef600700 {
215 + compatible = "ibm,ppc4xx-gpio";
216 + reg = <0xef600700 0x00000020>;
217 + #gpio-cells = <2>;
218 + gpio-controller;
219 + };
220 +
221 + EMAC0: ethernet@ef600800 {
222 + linux,network-index = <0x0>;
223 + device_type = "network";
224 + compatible = "ibm,emac-405ep", "ibm,emac";
225 + interrupt-parent = <&UIC0>;
226 + interrupts = <
227 + 0xf 0x4 /* Ethernet */
228 + 0x9 0x4 /* Ethernet Wake Up */>;
229 + local-mac-address = [000000000000]; /* Filled in by zImage */
230 + reg = <0xef600800 0x00000070>;
231 + mal-device = <&MAL>;
232 + mal-tx-channel = <0>;
233 + mal-rx-channel = <0>;
234 + cell-index = <0>;
235 + max-frame-size = <0x5dc>;
236 + rx-fifo-size = <0x1000>;
237 + tx-fifo-size = <0x800>;
238 + phy-mode = "mii";
239 + phy-map = <0x00000000>;
240 + };
241 +
242 + EMAC1: ethernet@ef600900 {
243 + linux,network-index = <0x1>;
244 + device_type = "network";
245 + compatible = "ibm,emac-405ep", "ibm,emac";
246 + interrupt-parent = <&UIC0>;
247 + interrupts = <
248 + 0x11 0x4 /* Ethernet */
249 + 0x09 0x4 /* Ethernet Wake Up */>;
250 + local-mac-address = [000000000000]; /* Filled in by zImage */
251 + reg = <0xef600900 0x00000070>;
252 + mal-device = <&MAL>;
253 + mal-tx-channel = <2>;
254 + mal-rx-channel = <1>;
255 + cell-index = <1>;
256 + max-frame-size = <0x5dc>;
257 + rx-fifo-size = <0x1000>;
258 + tx-fifo-size = <0x800>;
259 + mdio-device = <&EMAC0>;
260 + phy-mode = "mii";
261 + phy-map = <0x00000001>;
262 + };
263 +
264 + leds {
265 + compatible = "gpio-leds";
266 + user {
267 + label = "magicbox:red:user";
268 + gpios = <&GPIO0 2 1>;
269 + };
270 + };
271 + };
272 +
273 + EBC0: ebc {
274 + compatible = "ibm,ebc-405ep", "ibm,ebc";
275 + dcr-reg = <0x012 0x002>;
276 + #address-cells = <2>;
277 + #size-cells = <1>;
278 + /* The ranges property is supplied by the bootwrapper
279 + * and is based on the firmware's configuration of the
280 + * EBC bridge
281 + */
282 + clock-frequency = <0>; /* Filled in by zImage */
283 +
284 + cf_card@ff100000 {
285 + compatible = "magicbox-cf", "pata-magicbox-cf";
286 + reg = <0x00000000 0xff100000 0x00001000
287 + 0x00000000 0xff200000 0x00001000>;
288 + interrupt-parent = <&UIC0>;
289 + interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
290 + };
291 +
292 + nor_flash@ffc00000 {
293 + compatible = "cfi-flash";
294 + bank-width = <2>;
295 + reg = <0x00000000 0xffc00000 0x00400000>;
296 + #address-cells = <1>;
297 + #size-cells = <1>;
298 + partition@0 {
299 + label = "linux";
300 + reg = <0x0 0x120000>;
301 + };
302 + partition@120000 {
303 + label = "rootfs";
304 + reg = <0x120000 0x2a0000>;
305 + };
306 + partition@3c0000 {
307 + label = "u-boot";
308 + reg = <0x3c0000 0x30000>;
309 + read-only;
310 + };
311 + };
312 + };
313 +
314 + PCI0: pci@ec000000 {
315 + device_type = "pci";
316 + #interrupt-cells = <1>;
317 + #size-cells = <2>;
318 + #address-cells = <3>;
319 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
320 + primary;
321 + reg = <0xeec00000 0x00000008 /* Config space access */
322 + 0xeed80000 0x00000004 /* IACK */
323 + 0xeed80000 0x00000004 /* Special cycle */
324 + 0xef480000 0x00000040>; /* Internal registers */
325 +
326 + /* Outbound ranges, one memory and one IO,
327 + * later cannot be changed. Chip supports a second
328 + * IO range but we don't use it for now
329 + */
330 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
331 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
332 +
333 + /* Inbound 2GB range starting at 0 */
334 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
335 +
336 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
337 + interrupt-map = <
338 + /* IDSEL 1 */
339 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
340 +
341 + /* IDSEL 2 */
342 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
343 +
344 + /* IDSEL 3 */
345 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
346 +
347 + /* IDSEL 4 */
348 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
349 + >;
350 + };
351 + };
352 +
353 + chosen {
354 + linux,stdout-path = "/plb/opb/serial@ef600300";
355 + };
356 +};
357 --- a/arch/powerpc/boot/Makefile
358 +++ b/arch/powerpc/boot/Makefile
359 @@ -70,7 +70,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
360 cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
361 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
362 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
363 - cuboot-acadia.c cuboot-magicboxv1.c
364 + cuboot-acadia.c cuboot-magicboxv1.c cuboot-magicboxv2.c
365 src-boot := $(src-wlib) $(src-plat) empty.c
366
367 src-boot := $(addprefix $(obj)/, $(src-boot))
368 @@ -215,6 +215,7 @@ image-$(CONFIG_EP405) += dtbImage.ep40
369 image-$(CONFIG_WALNUT) += treeImage.walnut
370 image-$(CONFIG_ACADIA) += cuImage.acadia
371 image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
372 +image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
373
374 # Board ports in arch/powerpc/platform/44x/Kconfig
375 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
376 --- a/arch/powerpc/platforms/40x/Kconfig
377 +++ b/arch/powerpc/platforms/40x/Kconfig
378 @@ -59,6 +59,16 @@ config MAGICBOXV1
379 help
380 This option enables support for the Magicbox v1 board.
381
382 +config MAGICBOXV2
383 + bool "Magicbox v2"
384 + depends on 40x
385 + default n
386 + select PPC40x_SIMPLE
387 + select 405EP
388 + select PCI
389 + help
390 + This option enables support for the Magicbox v2 board.
391 +
392 config MAKALU
393 bool "Makalu"
394 depends on 40x
395 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
396 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
397 @@ -52,7 +52,8 @@ machine_device_initcall(ppc40x_simple, p
398 */
399 static char *board[] __initdata = {
400 "amcc,acadia",
401 - "magicboxv1"
402 + "magicboxv1",
403 + "magicboxv2",
404 };
405
406 static int __init ppc40x_probe(void)
Personal OpenWRT clone
This page took 0.075852 seconds and 5 git commands to generate.