target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.h

   1 #ifndef __GLAMO_CORE_H
   2 #define __GLAMO_CORE_H
   3
   4 #include <asm/system.h>
   5
   6 /* for the time being, we put the on-screen framebuffer into the lowest
   7  * VRAM space.  This should make the code easily compatible with the various
   8  * 2MB/4MB/8MB variants of the Smedia chips */
   9 #define GLAMO_OFFSET_VRAM       0x800000
  10 #define GLAMO_OFFSET_FB (GLAMO_OFFSET_VRAM)
  11
  12 /* we only allocate the minimum possible size for the framebuffer to make
  13  * sure we have sufficient memory for other functions of the chip */
  14 //#define GLAMO_FB_SIZE (640*480*4)     /* == 0x12c000 */
  15 #define GLAMO_INTERNAL_RAM_SIZE 0x800000
  16 #define GLAMO_MMC_BUFFER_SIZE (64 * 1024)
  17 #define GLAMO_FB_SIZE   (GLAMO_INTERNAL_RAM_SIZE - GLAMO_MMC_BUFFER_SIZE)
  18
  19 struct glamo_core {
  20         int irq;
  21         int irq_works; /* 0 means PCB does not support Glamo IRQ */
  22         struct resource *mem;
  23         struct resource *mem_core;
  24         void __iomem *base;
  25         struct platform_device *pdev;
  26         struct glamofb_platform_data *pdata;
  27         u_int16_t type;
  28         u_int16_t revision;
  29         spinlock_t lock;
  30         u32 engine_enabled_bitfield;
  31         u32 engine_enabled_bitfield_suspend;
  32         int suspending;
  33 };
  34
  35 struct glamo_script {
  36         u_int16_t reg;
  37         u_int16_t val;
  38 };
  39
  40 int glamo_run_script(struct glamo_core *glamo,
  41                      struct glamo_script *script, int len, int may_sleep);
  42
  43 enum glamo_engine {
  44         GLAMO_ENGINE_CAPTURE,
  45         GLAMO_ENGINE_ISP,
  46         GLAMO_ENGINE_JPEG,
  47         GLAMO_ENGINE_MPEG_ENC,
  48         GLAMO_ENGINE_MPEG_DEC,
  49         GLAMO_ENGINE_LCD,
  50         GLAMO_ENGINE_CMDQ,
  51         GLAMO_ENGINE_2D,
  52         GLAMO_ENGINE_3D,
  53         GLAMO_ENGINE_MMC,
  54         GLAMO_ENGINE_MICROP0,
  55         GLAMO_ENGINE_RISC,
  56         GLAMO_ENGINE_MICROP1_MPEG_ENC,
  57         GLAMO_ENGINE_MICROP1_MPEG_DEC,
  58 #if 0
  59         GLAMO_ENGINE_H264_DEC,
  60         GLAMO_ENGINE_RISC1,
  61         GLAMO_ENGINE_SPI,
  62 #endif
  63         __NUM_GLAMO_ENGINES
  64 };
  65
  66 struct glamo_mci_pdata {
  67         struct glamo_core * pglamo;
  68         unsigned int    gpio_detect;
  69         unsigned int    gpio_wprotect;
  70         unsigned long   ocr_avail;
  71         int             (*glamo_can_set_mci_power)(void);
  72         /* glamo-mci asking if it should use the slow clock to card */
  73         int             (*glamo_mci_use_slow)(void);
  74         int             (*glamo_irq_is_wired)(void);
  75         void            (*mci_suspending)(struct platform_device *dev);
  76         int             (*mci_all_dependencies_resumed)(struct platform_device *dev);
  77
  78 };
  79
  80 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine);
  81 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine);
  82 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine);
  83 int glamo_engine_reclock(struct glamo_core *glamo,
  84                          enum glamo_engine engine, int ps);
  85
  86 void glamo_engine_clkreg_set(struct glamo_core *glamo,
  87                              enum glamo_engine engine,
  88                              u_int16_t mask, u_int16_t val);
  89
  90 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
  91                                   enum glamo_engine engine);
  92 #endif /* __GLAMO_CORE_H */